JP2001352762A - Method for compensating output voltage of pwm inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress distortion of the output voltage waveform from a PWM inverter and to compensate the dead time and the forward voltage drop of an element. SOLUTION: In order to compensate for the error voltage of an inverter output voltage caused by a dead time held between the PWM pulse of a PWM inverter and the drive pulse of the semiconductor switching element in each phase arm, a PWM command pulse is corrected using the value of pulse accumulated between edge variation of the PWM command pulse and edge variation of an ON detection pulse of the semiconductor switching element as an error amount. In such a method for compensating the output voltage of the PWM inverter, a compensation amount is operated based on the forward voltage drop of the semiconductor element constituting the PWM inverter depending on the phase current polarity thereof and superposed on a voltage signal corresponding to the error amount thus correcting the PWM command pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for compensating an output voltage of a PWM inverter which obtains an AC voltage from a DC voltage, and more particularly, to a dead time provided for preventing simultaneous upper and lower arms of each phase of the PWM inverter. The error voltage caused by the error between the PWM command pulse and the actual drive pulse (ON detection pulse) of each phase upper and lower arm,
A semiconductor switching element and a freewheeling diode (hereinafter referred to as FW) constituting a main circuit of a PWM inverter.
D), the output voltage compensating method for suppressing the distortion of the inverter output voltage caused by the loss voltage due to the forward voltage drop.

[0002]

2. Description of the Related Art An error voltage (an error between an output voltage command value and an output voltage detection value) generated by an error between a PWM command pulse of a PWM inverter and an ON detection pulse obtained from an ON detection circuit of a semiconductor switching element of each phase upper and lower arm. error)
Compensation method (hereinafter referred to as pulse width compensation method)
Will be described based on the prior art shown in FIG.

In FIG. 16, 1 is a DC power supply and 2 is a PW
M inverters, T1 to T6 are switching units composed of semiconductor switching elements and FWD, U, V, W are AC output terminals, 3A, 3B, 3C are for correcting U-phase, V-phase, and W-phase gate signals, respectively. Is a correction circuit having the same configuration.

[0004] The configuration of the above correction circuit, U-phase correction circuit 3A
Will be described as an example. In the U-phase correction circuit 3A, 6
Are the PWM command pulse PWM _U ^* and the data selector 14,
Pulse difference detection circuit to which 16 output signals are input, 7A
Is an up / down counter for integrating error pulses for counting the output signal of the pulse difference detection circuit 6, 8 is a flip-flop set / reset by the output signal of the up / down counter 7, and 9 is the output of the flip-flop 8 after correction. An on-delay circuit for generating the timing of the upper and lower arm gate signals from the PWM command pulse
0 is a gate drive circuit that generates actual gate signals for the upper and lower arms of the U phase based on the output signal of the on-delay circuit 9, 11 is an upper arm ON detection circuit that detects the ON state of the upper arm semiconductor switching element, and 12 is a lower arm A lower arm ON detection circuit 13 for detecting the ON state of the semiconductor switching element of the arm 13 is an inversion of the ON detection pulse output from each of the ON detection circuits 11 and 12, the PWM command pulse PWM _U ^*, and the PWM command pulse via the inverter 26. A data selector to which a pulse is input, and each of the on-detection circuits 11, 1
An off / off section detection circuit for detecting the off section of both the upper and lower semiconductor switching elements based on the on detection pulse from 2; 14 turns on the output signal of the data selector 13 and the inverted pulse of the PWM command pulse PWM _U ^*. A data selector 16 for selecting an output signal of the oscillator 17 and an output signal of the 分 frequency divider 18 in accordance with the off / off section detection signal;

Here, a pulse difference detection circuit 6, an up / down counter 7A, a flip-flop 8, an upper arm on detection circuit 11, a lower arm on detection circuit 12, data selectors 13, 14, 16, an off / off section detection circuit 15, and an inversion circuit The compensator 26 constitutes a correction operation unit 33A for compensating an error voltage caused by the dead time.

In the correction operation section 33A, the data selector 13 selects and outputs an upper arm ON detection signal when the PWM command pulse PWM _U ^* is an upper arm ON command (High level). The data selector 14 selects the PWM command pulse PWM _U ^* of the inverted signal at the output of the off-off period detection signal, when either one of the upper and lower arms are turned on selects the output signal of the data selector 13 Output. The data selector 16 outputs the output signal of the 分 frequency divider 18 during the off / off period based on the off / off period detection signal, and outputs the output signal of the oscillator 17 when one of the upper and lower arms is on. Select and output.

In the pulse difference detection circuit 6, the PWM command pulse PW
The inverted signal of M _U ^* is selected and the data selector 16
When the output signal of the 分 frequency divider 18 is selected, the output signal of the 分 frequency divider 18 (the half frequency of the output signal (carrier) of the oscillator 17 which is a regular clock) is And an inverted signal of the PWM command pulse PWM _U ^* to obtain a clock of an amount corresponding to the error voltage, and when one of the upper and lower arms is turned on (the output signal of the data selector 13 is output by the data selector 14). Is selected and the output signal of the oscillator 17 is selected by the data selector 16), the amount of error voltage corresponding to the error voltage is determined from the output signal (regular clock) of the oscillator 17 and the ON detection signal of the own arm. Get the clock. And
These clocks are integrated by the up / down counter 7A. Further, the flip-flop 8 is set / reset based on the integration result of the up / down counter 7A, and a PWM command pulse in which an error voltage caused by dead time is corrected is obtained.

That is, the up / down counter 7A
Error pulses from the edge change of the PWM command pulse PWM _U ^{* to} the edge change of the upper arm on detection pulse and the lower arm on detection pulse are integrated, and then the PWM command pulse PW
When an edge change of M _U ^* occurs, an operation is performed in which the output pulse is not changed by the time width (hereinafter, referred to as an error amount) of the error pulse integrated up to that time. Therefore, the operation is performed to correct the output voltage by the voltage signal corresponding to the error amount due to the dead time, and the forward voltage drop amount of the constituent elements of the semiconductor switching units T1 to T6 constituting the upper and lower arms cannot be corrected.

Here, the constituent elements of the upper and lower arms are IGBT
(Insulated gate bipolar transistor), BJT (bipolar junction transistor), switching element such as MOSFET (MOS field effect transistor), and FWD
In order to compensate for the forward voltage drop of these elements, the pulse width correction method is performed by superposing the element forward voltage drop calculated from the inverter phase current on the inverter output voltage command value. Was.

[0010]

As described above, in order to correct the forward voltage drop of the element in the conventional compensation method, the output voltage command value of the inverter must always be manipulated. There was a problem that the distortion of the waveform could not be suppressed. Accordingly, the present invention corrects the PWM command pulse by superimposing a compensation amount for compensating the element forward voltage drop amount on a voltage signal corresponding to the error amount without manipulating the output voltage command value of the inverter, thereby achieving a high-speed PWM command pulse. It is an object of the present invention to provide an output voltage compensation method which enables compensation and suppresses waveform distortion of an output voltage of a PWM inverter.

[0011]

First, a method of correcting a PWM command pulse by superimposing a compensation amount for compensating an element forward voltage drop amount on a voltage signal corresponding to an error amount is shown in FIG. At the timing after the error pulse integrating up / down counter 7A integrates the error pulse and before the counter starts the compensation operation (the operation that does not change the output pulse), the compensation amount is added to the error pulse integrated value. What is necessary is just to reset the superimposed value in this counter.

First, the amount of element forward voltage drop to be compensated will be described. FIG. 17A is a connection diagram for one arm of the main circuit, and the switching unit includes an IGBT as a semiconductor switching element and an FWD connected in anti-parallel to the IGBT. FIG. 17B shows IGBT and FWD.
, The phase voltage in an ideal element assuming that the forward voltage drop amount is zero, FIG. 17C shows the phase voltage when the phase current i> 0,
(D) shows the phase voltage when i <0. here,
As shown in FIGS. 17C and 17D, the actual phase voltage is a value obtained by superimposing a forward voltage drop amount of an element forming an arm according to a current polarity on a phase voltage of an ideal element. Therefore, the average value v ₀ of the phase voltage within one cycle T _{c of the} carrier wave shown in FIG. 17B is expressed by the following equation (1) for an ideal element, the equation (2) for i> 0, and i <0 as shown below. Is represented by Equation 3.

[0013]

(Equation 1)

[0014]

(Equation 2)

[0015]

(Equation 3)

In the above equations, E _dc is the voltage of the DC power supply 1, v _{ce (sat)} is the forward voltage drop of the IGBT, and v _d is the FW
D is the forward voltage drop amount. Also, t _on = t ₁ + t ₃ , t
It is _off = t _2.

The second term on the right side of Expressions 2 and 3 is IGB
Since these are errors with respect to ideal phase voltage values caused by forward voltage drops of T and FWD, these voltages may be compensated as compensation amounts. Then, as each value required for the calculation of the second term on the right side of Expressions 2 and 3, a preset value or a detected value may be used. As means for calculating the amount of compensation, there are the following means. First, the variables required for the operation are v
_{ce (sat)} , v _d , t _on , t _off , T _c and the polarity of the current i. Since _Tc is the period of the carrier wave, the set value is used, and the current polarity uses the polarity detection result of the phase current. Assuming that a set value or a detected value is used for the remaining four variables, there are the following five cases.

(1) First compensation amount calculating means: v_{ce (sat)}
= V_dAnd v_{ce (sat)}, V_d, T_on, T _offSet all to
Calculate using values. Before the second term on the right side of Equations 2 and 3
With the above conditions, the compensation amount is given by Equation 4 when i> 0.
When i <0, Expression 5 is obtained. In other words, compensation
The amount will depend on the polarity of the phase current.

[0019]

(Equation 4)

[0020]

(Equation 5)

(2) Second compensation amount calculating means:
_{v ce (sat), v d} , t on, is calculated using all the t _off the set value. (3) Third compensation amount calculation means: Calculation is performed using set values for v _{ce (sat)} and v _d and detection values for t _on and t _off . (4) Fourth compensation amount calculating means: v _{ce (sat),} v detection value is _d, t _on, the t _off calculates with the set value. (5) Fifth compensation amount calculating _{means: v ce (sat), v} d, t on,
For _toff , calculations are performed using the detected values.

Next, the means for detecting the polarity of the phase current will be described. (1) First polarity detection means: a phase current is detected by a current detector and compared with zero by a comparator (that is, the polarity is detected by the polarity of the phase current).

The correction operation unit 33A shown in FIG. 16 is an operation unit for correcting the pulse width of the gate signal.
The "ON detection signal of each arm" is generated. Therefore,
Means for detecting the polarity of the phase current from these ON detection signals will be described below. Note that the following current polarity detecting means are referred to as a second polarity detecting means and a third polarity detecting means.

(2) Second polarity detecting means: FIG. 18 shows the principle of operation of the second polarity detecting means. In this figure, (a) shows a circuit diagram for one arm of the main circuit, and (b) shows the behavior of the phase current polarity and the arm voltage. In these figures, if the direction in which the phase current flows from the upper arm to the load is defined as positive, the arm voltage v at the rising point of the upper arm gate signal (hereinafter referred to as the ON signal) is negative when the phase current is positive. (FIG. 18B). This is because, if the arm voltage v in the dead time t _d is FWD of the upper arm is on, because determined by either FWD in the lower arm is turned on, depending on the current polarity. In other words, if it is possible to detect whether the upper arm or the lower arm FWD is on at the time of turning on the gate signal of the own arm (arm of interest) and determine the sign of the voltage v of the own arm, the phase current The polarity can be determined.

(3) Third polarity detecting means: FIG. 19 shows the principle of operation of the third polarity detecting means. In this figure, (a) shows the behavior of the phase current and the arm voltage, (b) shows the relationship between the phase current and the error amount, and (c) shows the equivalent circuit of the FWD. The behavior of the phase current and the arm voltage during the dead time will be described with reference to FIG. The arm voltage v during the dead time depends on the polarity of the phase current i, as described in the section on the second polarity detection means. Further, the arm voltage v also depends on the magnitude of the phase current.

Here, the equivalent circuit of the FWD is shown in FIG.
As shown in (c), since the circuit is a parallel circuit of the on-resistance R _on and the junction capacitance C _j , a voltage change during the dead time (hereinafter, referred to as “c”).
dv / dt) is determined by the speed at which the junction capacitance _Cj is charged with the phase current i. That is, when the current i is small, dv / dt is small because the charging speed is low. Conversely, when the current i is large, the charging speed increases, and dv /
dt increases. Further, the arm voltage v depends on the current polarity.
Changes. Therefore, as shown in FIG. 19A, the change of the arm voltage v during the dead time depends on the polarity and the magnitude of the current i. That is, the fact that the arm voltage v during the dead time depends on the phase current i is shown in FIG.
Means that the error amount ε _r during the dead time depends on the phase current i. In other words, the error amount ε
The polarity of the phase current i is known from _r .

[0027] Therefore, explaining the method of detecting the amount of error ε _r. In FIG. 19 (a), the change arm voltage v during dead-time becomes constant and the junction capacitance C _j of the FWD is constant-current charging, the size is proportional to the current i. Therefore, it is possible to the on-state of the upper and lower arms to detect individually detecting the amount of error epsilon _r by measuring the time difference between these on the detection pulse by the counter. FIG.
According to principle diagram of (b), by the magnitude of the amount of error determined the magnitude of the detected error amount epsilon _r at half the dead time t _d / 2 time and comparing, determining the polarity of the phase current i be able to.

Finally, means for resetting the value obtained by superimposing the compensation amount on the voltage signal corresponding to the error amount in the up / down counter will be described. FIG. 20 shows a method of resetting the up / down counter. (A) of this figure shows the case where i> 0 (current polarity is positive), and (b) shows the case where i <0 (current polarity is negative).
In FIGS. 20A and 20B, the error amount due to the dead time is the time from the change of the PWM command pulse until the polarity of the gate signal of the corresponding arm becomes the same as the polarity of the PWM command pulse. The detection end timing of the error amount can be determined from the fact that the polarity of the PWM command pulse and the polarity of the corresponding arm gate signal match. Therefore, after detecting the coincidence between the polarity of the PWM command pulse and the polarity of the corresponding arm gate signal, the compensation amount is superimposed on the voltage signal corresponding to the error amount. May be reset as the initial value of.

That is, the present invention provides an inverter output voltage error caused by a dead time held between a PWM command pulse of a PWM inverter and a drive pulse of a semiconductor switching element of each phase arm. In order to compensate for the voltage, the integrated value of the pulse from the edge change of the PWM command pulse to the edge change of the ON detection pulse of the semiconductor switching element is used as an error amount, and the PWM command pulse is corrected using this error amount. In the output voltage compensation method for a PWM inverter, a compensation amount based on a forward voltage drop amount of a semiconductor element forming the PWM inverter is calculated according to a phase current polarity of the PWM inverter, and the compensation amount is calculated as a voltage signal corresponding to the error amount. Superimposed on PW
It is characterized in that the M command pulse is corrected. The first to third polarity detection means are included as phase current polarity detection means, and the first to fifth compensation amount calculation means are included as compensation amount calculation means. According to the present invention configured as described above, a high-speed forward voltage drop compensation is performed by superimposing a compensation amount for compensating the element forward voltage drop amount on a voltage signal corresponding to an error amount during a dead time in a cycle of a carrier wave. Becomes possible.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, a first embodiment corresponding to claims 1 and 2 is shown in FIG. In FIG. 1, a DC power supply 1 is connected to a DC side of a three-phase PWM inverter 2 including switching units T1 to T6, and the inverter 2 includes a U-phase gate signal output from a U-phase correction circuit 3 and a V-phase correction circuit 4. Is driven by the V-phase gate signal output from the W-phase correction circuit 5 and converts the voltage of the DC power supply 1 into an AC voltage. Outputs of the current detectors 29, 30, and 31 provided on the AC output side of the inverter 2 are input to the corresponding phase correction circuits 3 to 5, respectively. here,
For convenience, the configuration and operation of the U-phase correction circuit 3 will be described below focusing on the U-phase correction circuit 3. The same components as those in FIG. 16 are denoted by the same reference numerals.

The correction circuit 3 includes a correction calculation unit 33, a current polarity detection unit 27A, an edge detection circuit 19A, and a switch 2.
3, a multiplier 24, an adder 25, an on-delay circuit 9, and a gate drive circuit 10. The current polarity detecting means 27A corresponds to the above-described first polarity detecting means, and outputs the phase current detected by the current detector 29 to the comparator 28A.
To detect the polarity of the phase current in comparison with zero.

First, the operation of the correction calculator 33 will be described.
The U-phase arm voltage of inverter 2 is the upper arm ON detector
11 and the lower arm-on detector 12
Upper arm on detection signal T that goes high when on₁ ^ist
And lower arm on detection signal T _Four ^istGet. These on
Detection signal is off / off for both upper arm and lower arm
An off / off section detection circuit 15 for detecting a section
Data selector 13. Data selector 13
Then, PWM command pulse PWM_U ^*Is upper arm ON command
(High level), upper arm ON detection signal T₁ ^istChoose
Lower arm when lower arm ON command (Low level)
ON detection signal T_Four ^istSelect and output. And the day
The output signal of the data selector 13 is input to the data selector 14.
The off / off section from the off / off section detection circuit 15
The inter-detection signal is transmitted between the data selector 14 and the data selector 1.
6 has been entered.

The data selector 14 selects an inverted signal of the PWM command pulse PWM _U ^* during the off / off period of the upper and lower arms, and outputs the output signal of the data selector 13 when one of the upper and lower arms is on. select. On the other hand, the output signal (carrier) of the oscillator 17 is input to the 分 frequency divider 18 and the data selector 16, and the output signal of the 分 frequency divider 18 is input to the data selector 16. The data selector 16 selects the output signal of the 1/2 frequency divider 18 during the off / off section based on the off / off section detection signal, and outputs the oscillator 17 when one of the upper and lower arms is on. And outputs the selected signal.

The output signal of the data selector 14 and the output signal of the data selector 16 are input to the pulse difference detection circuit 6. In the pulse difference detection circuit 6, during the OFF / OFF period (that is, the inverted signal of the PWM command pulse PWM _U ^* is selected and output by the data selector 14, and
When the output signal of the 分 frequency divider 18 is selected and output by the data selector 16), the output signal of the 分 frequency divider 18 (a signal having a half frequency of a normal clock) And an inverted signal of the PWM command pulse PWM _U ^* , an amount of clock corresponding to the error voltage is obtained, and when one of the upper and lower arms is on (that is, the output signal of the data selector 13 is (When the output signal of the oscillator 17 is selected and output by the data selector 16) and the output signal (regular clock) of the oscillator 17 and the ON detection signal of the own arm, the error amount is determined. The number of clocks corresponding to is obtained. Then, these clocks are integrated by the load type up / down counter 7. Furthermore, the flip-flop 8 is calculated based on the integration result of the up / down counter 7.
Is set / reset to obtain a PWM command pulse in which the error amount due to the dead time is corrected within the period of the carrier wave.

On the other hand, the phase current detected by the current detector 29 is input to the current polarity detecting means 27A, and is compared with zero by the comparator 28 to detect the phase current polarity. As described above as the first compensation amount calculating means, according to Expressions 4 and 5, the compensation amount is v _{ce (sat)} or −v according to the current polarity.
_{ce (sat)} . Therefore, the switch 23 is switched to “1” or “−1” according to the current polarity output from the comparator 28, and the multiplier 24 multiplies the forward voltage drop (v _{ce (sat)} ) of the element (IGBT). , And its result (v _{ce (sat)} or −v _{ce (sat)} ) as the compensation amount. This compensation amount is superimposed by the adder 25 on the error amount integrated by the load type up / down counter 7.

The output signal of the adder 25 is reset in the load type up / down counter 7 by the timing signal output from the edge detector 19A. In addition,
The edge detector 19A detects that the polarity of the PWM command pulse PWM _U ^* matches the polarity of the output signal of the data selector 14 (the ON detection signal of the upper arm or the lower arm, that is, the gate signal), and detects an error amount. It recognizes the end and outputs a timing signal. In response to the reset timing signal, the up / down counter 7 resets the “error amount + compensation amount” that is the output signal of the adder 25 as an initial value.

By these operations, the corrected arithmetic operation unit 33 outputs a corrected PWM command pulse including the element forward voltage drop amount. This command pulse is input to the on-delay circuit 9 to generate a gate signal for the semiconductor switching elements of the upper and lower arms. These gate signals are input to the gate drive circuit 10 and become gate signals for driving the U-phase of the inverter 2.

Next, a second embodiment of the present invention corresponding to claims 1 and 3 is shown in FIG. Parts overlapping with those in the first embodiment will be omitted, and only different parts will be described. The different parts are in the current polarity detecting means in the correction circuits 3 to 5. In the U-phase correction circuit 3, the current polarity detecting means 27B
Corresponds to the above-described second polarity detection means, and determines whether the voltage of the own arm is positive or negative based on the ON signal of the own arm, and determines the current polarity.

Specifically, the upper arm ON detection circuit 11,
The upper arm ON detection signal and the lower arm ON detection signal output from the lower arm ON detection circuit 12 are input to the FWD mode detector 20 based on the upper arm and the FWD mode detector 21 based on the lower arm. The gate signals of the corresponding arm are also input to the FWD mode detectors 20 and 21, and the upper arm on detection signal and the lower arm on detection signal are latched at the rise of these gate signals. That is, the FWD mode detector 20 based on the upper arm is
By latching the upper arm ON detection signal at the rising edge of the upper arm gate signal, the ON / OFF state of the upper arm FWD is detected, and the FWD mode detector 2 based on the lower arm is used.
1 detects the on / off state of the lower arm FWD by latching the lower arm on detection signal at the rise of the lower arm gate signal.

The on / off state of the upper arm or lower arm FWD corresponds to the arm voltage level during the dead time, and the current polarity can be determined from the arm voltage level as shown in FIG. The flip-flop 22 detects the U-phase current polarity from the ON / OFF state (arm voltage level) of the upper arm or lower arm FWD latched by the FWD mode detectors 20 and 21. The method of determining the compensation amount according to the current polarity is the same as that of the first embodiment, and the compensation amount v _{ce (sat)} or −v _{ce ( sat)} is calculated, and performs compensation operation by superimposing the error amount from the load type up-down counter 7 by the adder 25.

Next, a third embodiment of the present invention corresponding to claims 1 and 4 is shown in FIG. Parts overlapping with those in the first embodiment will be omitted, and only different parts will be described. Also in this embodiment, the current polarity detecting means in the correction circuits 3 to 5 is different. In the U-phase correction circuit 3, the current polarity detection means 27C corresponds to the above-described third polarity detection means.
The timing signal output from the 9B a data latch 32 for latching the output signal of the load type up-down counter 7, 1 of the output signal and the dead time t _d
And a comparator 28 to which the output signal of the flip-flop 8 and the period signal t _d / 2, which is the period of / 2, are input.

The error amount accumulated by the up / down counter 7 is used as an edge detection circuit 19 for detecting the end of error amount detection.
The data is latched by the data latch 32 in response to the output signal of B. The comparator 28 compares the latched error amount with the error amount at t _d / 2 (calculated from the period signal t _d / 2 and the output signal of the flip-flop 8), and further performs PWM.
To determine the current polarity with reference to the polarity of the command pulse PWM _U ^*. The method of determining the compensation amount according to the current polarity is the same as that of the first embodiment, and the compensation amount v _{ce (sat)} or −v _{ce ( sat)} is calculated, and the adder 25 superimposes the error amount from the up / down counter 7 to perform a compensation operation. The load signal generator 36 generates and outputs a reset timing signal for the up / down counter 7 based on the timing signal from the edge detection circuit 19B and the phase current polarity from the comparator 28.

FIG. 4 shows a fourth embodiment of the present invention corresponding to claims 5 and 6. This embodiment differs from the first embodiment in that a compensation amount calculating means 34 is provided.
The calculation means 34 corresponds to the above-described second compensation amount calculation means, and calculates the compensation amount using all the set values for v _{ce (sat)} , v _d , t _on , and t _off . The compensation quantity operation means 34 includes a U-phase voltage set value v _U ^*, a DC voltage E _dc detected by the DC voltage detector 37, a carrier wave period setting value T _c ^*, the forward voltage of the semiconductor switching element (IGBT) Set amount of descent _vce
^* , The forward voltage drop setting value v _d ^{* of} the FWD, and the current polarity from the current polarity detection means 27A (comparator 28) are input.

Here, the second term on the right side of Equations 2 and 3 is represented by v _{ce (sat)} = v _ce ^* , v _d = v _d ^* , T _c = T _c ^* , t
_on = v ^* / E _dc, as ^{_{t off = T c * -t on}} , the compensation amount calculation means 34 calculates the amount of compensation. In ^{_{addition, t on = v * / E}} dc
The reason is that v ^* is the output voltage command value at the specified DC voltage E _dc ^*, so that the fluctuation of the DC voltage is compensated. The compensation amount calculated by the compensation amount calculating means 34 is input to the multiplier 24, and the switch 2 is switched according to the current polarity.
Multiplied by “1” or “−1” selected by 3 and input to the adder 25. The subsequent operation is the same as in the first to third embodiments.

According to the fifth and seventh aspects of the present invention,
Five embodiments are shown in FIG. This embodiment is a second implementation
Circuit 3 in Embodiment and Compensation Amount in Fourth Embodiment
Combined with arithmetic means 34 and DC voltage detector 37
Things. That is, as the current polarity detecting means 27B,
Uses the second polarity detection means and outputs
The polarity of the current is determined by determining whether the voltage of the
You. The compensation amount calculating means is a second compensation amount calculating means.
Using the steps, v_{ce (sat)}, V_d, T _on, T_offAll set values
Is used to calculate the compensation amount.

FIG. 6 shows a sixth embodiment of the present invention corresponding to claims 5 and 8. This embodiment combines the correction circuit 3 of the third embodiment with the compensation amount calculating means 34 and the DC voltage detector 37 of the fourth embodiment. That is, as the current polarity detecting means, the third
The current polarity detecting means 27C is composed of a data latch 32 and a comparator 28. The comparator 28 detects the integrated error amount of the latched load type up / down counter 7 and The error amount at t _d / 2 is compared with the PWM command pulse PWM.
_The current polarity is determined with reference to the polarity of _U ^* . Further, the second compensation amount calculating means is used as the compensation amount calculating means,
Compensation amounts are calculated using set values for _{ce (sat)} , v _d , t _on , and t _off .

FIG. 7 shows a seventh embodiment of the present invention corresponding to claims 9 and 10. The parts overlapping with the fourth embodiment will be omitted, and only the different parts will be described. In this embodiment, the compensation amount calculating means 35 is different. The calculation means 35 corresponds to the third compensation amount calculation means described above, and calculates a compensation amount using a set value for v _{ce (sat)} and v _d and a detected value for t _on and t _off. . The current polarity detector 27A is a first polarity detector, and the comparator 28 compares the detected phase current with zero to detect the current polarity.

In the compensation amount calculating means 35, equations 2 and 3
The second term of the right side _{v ce (sat) = v ce} *, v d = v d *, T c = T
_c ^*, and t _on and t _off are the upper arm on detection circuit 1
1. The upper arm ON detection signal and the lower arm ON detection signal output from the lower arm ON detection circuit 12 are input to an internal counter or the like (not shown) to measure the ON width and the OFF width. These v _{ce (sat)} , v _d , T _c ,
Expressions 2 and 3 are used according to the current polarity using t _on and t _off.
The amount of compensation is calculated by the second term on the right side of. Subsequent operations are the same as in the fourth embodiment.

FIG. 8 shows an eighth embodiment of the present invention corresponding to the ninth and eleventh aspects. A part different from the seventh embodiment is a current polarity detecting means 27B. The FWD mode detectors 20, 21 and the flip-flop 22 determine whether the voltage of the own arm is positive or negative based on the ON signal of the own arm, and determine the current polarity. This detecting means is a second polarity detecting means 2
Corresponds to. Note that the compensation amount calculating means 35 corresponds to the above-described third compensation amount calculating means, similarly to the seventh embodiment.

FIG. 9 shows a ninth embodiment of the present invention corresponding to the ninth and twelfth aspects. The difference from the seventh embodiment is the current polarity detecting means 27C,
And the comparator 28 constitute a third polarity detecting means. In the current polarity detection means 27C, the integrated error amount of the load type up / down counter 7 latched by the data latch 32 and the error amount at t _d / 2 are compared by the comparator 28, and further, the PWM command pulse PWM
_The current polarity is determined with reference to the polarity of _U ^* . The compensation amount calculating means 35 corresponds to the third compensation amount calculating means as in the seventh embodiment, where v _{ce (sat)} and v _d are set values, t _on and t
_off calculates the compensation amount using the detected value.

FIG. 10 shows a tenth embodiment of the present invention corresponding to claim 13 or claim 14. The difference from the seventh embodiment lies in the compensation amount calculating means 38. This calculation means 3
8 corresponds to the above-described fourth compensation amount calculating means,
_{ce (sat),} v _d is the detection value, t _on, t _off calculates the compensation amount with the set value. In FIG. 10, reference numeral 39 denotes an arm-on voltage detector, which is connected between both ends of the DC power supply 1 and the interconnection point of the upper and lower arms of each phase, and turns on the upper arm on-voltage v _u- when each arm is on. U, v _v -U, v
_w- U, the lower arm on-voltages v _u -D, v _v -D, and v _w -D are input to the correction circuits 3 to 5 of each phase. The compensation amount calculating means 38 uses the detection values v _u -U and v _u -D of the arm-on voltage detector 37 as v _{ce (sat)} and v _d in the second term on the right side of Expressions 2 and 3, and for other than these. calculating a compensation amount corresponding to the current polarity by using the ^{_{T c = T c *, t}} on = v * / E dc, both as referred t _off = T _c ^* -t _on the set value. The compensation amount is input to the multiplier 24. The subsequent operation is the same as in the first to ninth embodiments.

FIG. 11 shows an eleventh embodiment of the present invention corresponding to the thirteenth and fifteenth aspects. The difference from the tenth embodiment is the current polarity detection means. In the present embodiment, the current polarity detection means 2 corresponds to the second polarity detection means.
7B determines whether the voltage of the own arm is positive or negative based on the ON signal of the own arm, and determines the current polarity.

The invention according to claims 13 and 16
FIG. 12 shows a twelfth embodiment of the present invention. 10th embodiment and
The different part is the current polarity detecting means, and in this embodiment,
Is current polarity detecting means 2 corresponding to the third polarity detecting means.
7C, the row latched by the data latch 32
Error amount of the tally type up / down counter 7 and t_d
/ 2 by the comparator 28, and
PWM command pulse PWM _U ^*Current polarity with reference to the polarity of
Determine.

The present invention according to claims 17 and 18
13th Embodiment is shown in FIG. 10th embodiment and
Overlapping parts are omitted, and only different parts are described. Strange
Is a compensation amount calculating means 35.
Corresponds to the above-mentioned fifth compensation amount calculating means. That is,
The compensation calculation means 35 calculates_{ce (sat)}, V_d, T_on, T_offTo
The compensation amount is calculated using all the detected values. Explain concretely
Then, in the compensation amount calculating means 35, the right-hand side of Expressions 2 and 3
V in the second term_{ce (sat)}, V_dAs arm-on voltage detection
Value v by the detector 37_u-U, v _uUsing -D,
T_c= T_c ^*And t_on, T_offAbout the upper arm
Detection circuit 11 and lower arm on detection circuit 12
Each of the ON detection signals obtained is converted into a counter or the like in the arithmetic means 35 (see FIG.
(Not shown) to measure the ON width and OFF width.
Request. These v_{ce (sat)}, V_d, T_c, T_on, T_off
And the second term on the right side of Equations 2 and 3 according to the current polarity
To calculate the compensation amount.

FIG. 14 shows a fourteenth embodiment of the present invention corresponding to claim 17 and claim 19. The difference from the thirteenth embodiment is the current polarity detection means 27B corresponding to the second polarity detection means, and the other configuration is clear from the previous embodiment, and therefore the description is omitted.

FIG. 15 shows a fifteenth embodiment of the present invention corresponding to claim 17 and claim 20. The part different from the thirteenth embodiment is a current polarity detection unit 27C corresponding to the third polarity detection unit. The other configuration is clear from the previous embodiment, and thus the description is omitted.

[0057]

As described above, according to the present invention, generally,
By superimposing the compensation amount for compensating the element forward voltage drop amount on the error amount due to the dead time in the cycle of the carrier wave, high-speed compensation becomes possible, and the distortion of the output voltage waveform of the PWM inverter can be suppressed. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing an eighth embodiment of the present invention.

FIG. 9 is a block diagram showing a ninth embodiment of the present invention.

FIG. 10 is a block diagram showing a tenth embodiment of the present invention.

FIG. 11 is a block diagram showing an eleventh embodiment of the present invention.

FIG. 12 is a block diagram showing a twelfth embodiment of the present invention.

FIG. 13 is a block diagram showing a thirteenth embodiment of the present invention.

FIG. 14 is a block diagram showing a fourteenth embodiment of the present invention.

FIG. 15 is a block diagram showing a fifteenth embodiment of the present invention.

FIG. 16 is a block diagram showing a conventional technique.

FIG. 17 is a diagram for explaining an element forward voltage drop amount to be compensated in the present invention.

FIG. 18 is a diagram for explaining the operation principle of the current polarity detection means in the present invention.

FIG. 19 is a diagram for explaining the operation principle of the current polarity detection means in the present invention.

FIG. 20 is a diagram for explaining a method of resetting an up / down counter according to the present invention.

[Explanation of symbols]

 Reference Signs List 1 DC power supply 2 PWM inverter T1 to T6 Switching unit U, V, W AC output terminal 3 U-phase correction circuit 4 V-phase correction circuit 5 W-phase correction circuit 6 Pulse difference detection circuit 7 Load type up / down counter 8 Flip-flop 9 ON Delay circuit 10 Gate drive circuit 11 Upper arm on detection circuit 12 Lower arm on detection circuit 13, 14, 16 Data selector 15 Off / off section detection circuit 17 Oscillator 18 1/2 frequency divider 19A, 19B Edge detection circuit 20 Upper arm reference FWD Mode detector 21 Lower arm reference FWD mode detector 22 Flip-flop 23 Switch 24 Multiplier 25 Adder 26 Inverter 27A, 27B, 27C Current polarity detection means 28 Comparator 29, 30, 31 Current detector 32 Data latch 33 Correction Arithmetic unit 34, 3 , 38 compensation amount calculating means 36 load signal generator 37 DC voltage detector 39 arm ON voltage detector

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideyuki Ito 1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. No. 1 Fuji Electric Co., Ltd. F term (reference) 5H007 AA04 AA07 CA01 CB05 DB02 DC02 DC05 DC05 EA02 FA06 FA13

Claims (20)

[Claims] In order to compensate for an error voltage of an inverter output voltage caused by a dead time held between a PWM command pulse of a PWM inverter and a drive pulse of a semiconductor switching element of each phase arm, a PWM command pulse is generated. An output voltage compensation method for a PWM inverter in which an integrated value of a pulse from an edge change to an edge change of an ON detection pulse of a semiconductor switching element is used as an error amount, and the PWM command pulse is corrected using the error amount. Calculating a compensation amount based on the forward voltage drop amount of the semiconductor element constituting the PWM inverter in accordance with the phase current polarity of the PWM inverter, and superimposing the compensation amount on a voltage signal corresponding to the error amount to correct the PWM command pulse. A method for compensating an output voltage of a PWM inverter, characterized in that: 2. The output voltage compensation method for a PWM inverter according to claim 1, wherein the phase current polarity is detected from a positive or negative value of a phase current detection value of the PWM inverter. 3. The output voltage compensation method for a PWM inverter according to claim 1, wherein the phase current polarity is detected based on an on / off state of the semiconductor element of the phase held at a timing of turning on a semiconductor switching element of the phase. PWM characterized by doing
Inverter output voltage compensation method. 4. The PWM inverter output voltage compensation method according to claim 1, wherein said phase current polarity is detected based on a magnitude of said error amount and a polarity of a PWM command pulse.
Output voltage compensation method for M inverter. 5. The output voltage compensation method for a PWM inverter according to claim 1, wherein the compensation amount includes a detected value of a phase current polarity, a set value of a forward voltage drop amount of a semiconductor element of the phase, and a carrier wave period. PWM
A method for compensating an output voltage of a PWM inverter, wherein the output voltage is calculated from a set value of an ON time and an OFF time of a command pulse. 6. The output voltage compensation method for a PWM inverter according to claim 5, wherein the phase current polarity is detected from a positive or negative phase current detection value of the PWM inverter. 7. The output voltage compensation method for a PWM inverter according to claim 5, wherein the phase current polarity is detected based on an on / off state of the semiconductor element of the phase held at a timing of turning on a semiconductor switching element of the phase. PWM characterized by doing
Inverter output voltage compensation method. 8. The PWM inverter output voltage compensation method according to claim 5, wherein the phase current polarity is detected based on the magnitude of the error amount and the polarity of a PWM command pulse.
Output voltage compensation method for M inverter. 9. The output voltage compensation method for a PWM inverter according to claim 1, wherein the compensation amount includes a detection value of a phase current polarity, a set value of a forward voltage drop amount of a semiconductor element of the phase, and a carrier wave period. PWM
A method for compensating an output voltage of a PWM inverter, wherein the method is calculated from detection values of an ON time and an OFF time of a command pulse. 10. The PWM inverter output voltage compensation method according to claim 9, wherein the phase current polarity is detected from the positive or negative of a phase current detection value of the PWM inverter. 11. The output voltage compensation method for a PWM inverter according to claim 9, wherein the phase current polarity is detected based on an on / off state of the semiconductor element of the phase held at a timing of turning on a semiconductor switching element of the phase. PWM characterized by doing
Inverter output voltage compensation method. 12. The method of claim 9, wherein the polarity of the phase current is detected based on the magnitude of the error amount and the polarity of a PWM command pulse.
Output voltage compensation method for M inverter. 13. The output voltage compensation method for a PWM inverter according to claim 1, wherein the compensation amount includes a detected value of a phase current polarity, a detected value of a forward voltage drop amount of a semiconductor device of the phase, and a carrier wave period. PWM
A method for compensating an output voltage of a PWM inverter, wherein the output voltage is calculated from a set value of an ON time and an OFF time of a command pulse. 14. The PWM inverter output voltage compensation method according to claim 13, wherein the phase current polarity is detected from a positive or negative phase current detection value of the PWM inverter. 15. The output voltage compensation method for a PWM inverter according to claim 13, wherein the phase current polarity is detected based on an on / off state of the semiconductor element of the phase held at a timing of turning on a semiconductor switching element of the phase. PWM characterized by doing
Inverter output voltage compensation method. 16. The PWM inverter output voltage compensation method according to claim 13, wherein the phase current polarity is detected based on the magnitude of the error amount and the polarity of a PWM command pulse.
Output voltage compensation method for M inverter. 17. The output voltage compensation method for a PWM inverter according to claim 1, wherein the compensation amount includes a detected value of a phase current polarity, a detected value of a forward voltage drop of a semiconductor element of the phase, and a carrier wave period. PWM
A method for compensating an output voltage of a PWM inverter, wherein the method is calculated from detection values of an ON time and an OFF time of a command pulse. 18. The PWM inverter output voltage compensation method according to claim 17, wherein the phase current polarity is detected from the positive or negative of a phase current detection value of the PWM inverter. 19. The output voltage compensation method for a PWM inverter according to claim 17, wherein the phase current polarity is detected based on an on / off state of the semiconductor element of the phase held at a timing of turning on the semiconductor switching element of the phase. PWM characterized by doing
Inverter output voltage compensation method. 20. The method of claim 17, wherein the phase current polarity is detected based on the magnitude of the error amount and the polarity of a PWM command pulse.
Output voltage compensation method for M inverter.