JP3792244B2 - Waveform equalizer and recorded information reproducing apparatus - Google Patents

Description

  The present invention relates to a waveform equalizer and a recorded information reproducing apparatus in a recorded information reproducing apparatus that reproduces recorded information from a recording medium.

  In order to improve the S / N ratio of a read signal read from a recording medium on which digital data is recorded at high density, a technique for performing waveform equalization by performing a filtering process that emphasizes the high frequency band on the read signal is known. ing. At this time, the improvement ratio of the S / N ratio can be increased as the degree of emphasis on the high frequency with respect to the read signal is increased. was there.

  The present invention has been made to solve such a problem, and provides a waveform equalizer and a recorded information reproducing apparatus capable of improving the S / N ratio without causing jitter in a read signal read from a recording medium. The purpose is to provide.

The waveform equalizer according to claim 1 performs equalization correction reading by performing waveform equalization on a read signal obtained by reading an RLL (Run Length Limited) encoded signal recorded on a recording medium. a waveform equalizer for obtaining a signal, at sample points after just before and straight zero crossing point of the read signal, and the amplitude limit value generating means for generating an amplitude limit value based on the amplitude of the read signal, the Amplitude limiting means for limiting the amplitude level of the read signal with the amplitude limit value to obtain an amplitude limited read signal, and a filter for outputting the filtered signal of the amplitude limited read signal as the equalization correction read signal. Prepare.

The recorded information reproducing apparatus according to claim 8 is a recorded information reproducing apparatus for reproducing recorded information from a recording medium, the pickup for reading the recorded information from the recording medium to obtain a read signal, and the read signal A waveform equalizer that obtains an equalized correction read signal by performing waveform equalization, and a demodulating unit that demodulates the equalized correction read signal and outputs a reproduction signal. , at sample points after just before and straight zero crossing point of the read signal, the reading and the amplitude limit value generating means for generating an amplitude limit value based on the amplitude of the signal, the reading the amplitude limit value the amplitude level of the signal And an amplitude limiting unit that obtains an amplitude limited read signal by limiting the signal, and a filter that outputs a signal obtained by filtering the amplitude limited read signal as the equalized correction read signal.

  An amplitude limit value having a value corresponding to the amplitude of the read signal at a sample point before and after the zero crossing point of the read signal read from the recording medium is generated, and the amplitude limit process is performed on the read signal with the amplitude limit value. Waveform equalization is performed by subjecting the amplitude limited read signal obtained by applying filtering processing to the signal.

  Examples of the present invention will be described below.

  FIG. 1 is a diagram showing a configuration of a recorded information reproducing apparatus including a waveform equalizer according to the present invention.

  In FIG. 1, a pickup 1 reads recorded information recorded on a recording disk 3 rotated by a spindle motor 2 and supplies a read signal obtained at this time to an amplifier 4. The amplifier 4 supplies the read signal R obtained by amplifying the read signal as desired to the waveform equalizer 5.

The amplitude limiting circuit 51 in the waveform equalizer 5 converts the signal level of the read signal R according to the input / output characteristics as shown in FIG. 2A or FIG. Amplitude restriction is applied to the signal, and the amplitude restriction read signal R _LIM obtained at this time is supplied to the high-frequency emphasis filter 52. At this time, as long as the amplitude limiting circuit 51 having although such characteristics as shown in FIG. 2 (a), the signal level of the read signal R is smaller than a predetermined amplitude limitation value T _h, and the amplitude limit value If it is greater than -T _h, the signal level of this read signal R is output as it is as an amplitude limited read signal R _LIM . On the other hand, when the signal level of the read signal R is greater than the amplitude limit value T _h outputs the amplitude limiting value T _h itself as the amplitude limited read signal R _LIM. When the signal level of the read signal R is smaller than the amplitude limit value −T _h , the amplitude limit value −T _h itself is output as the amplitude limit read signal R _LIM .

On the other hand, if the amplitude limiting circuit 51 has but such characteristics are shown in FIG. 2 (b), the amplitude of the amplitude limit value T _h and -T _h the read signal by the nonlinear saturation characteristics saturated with R Limit. The high frequency emphasis filter 52 emphasizes the level of the high frequency component of the amplitude limited read signal R _LIM supplied from the amplitude limit circuit 51 and supplies this to the binary decision circuit 6 as an equalized correction read signal _RH. . Based on the signal level of the equalization correction read signal _RH , the binary determination circuit 6 determines whether this is a logical level “1” or “0”, and reproduces the determination result. Output as data.

Next, the operation of the waveform equalizer 5 will be described. The reproduction characteristics of the recorded information reproduction system as shown in FIG.
λ / 2 ・ NA
λ: wavelength of light source in pickup 1
NA: LPF (low pass filter) characteristic determined by the numerical aperture of the objective lens in the pickup 1. For example, in DVD, in order to increase the recording density, a signal corresponding to the shortest recording wavelength, that is, a signal corresponding to run length 3T in 8/16 modulation (T indicates the bit interval of the information data series) is cut off in the reproduction characteristics. Since it is set in the vicinity of the wavelength, the level of the read signal corresponding to this run length 3T decreases.

  Therefore, in order to improve the S / N ratio for the run-length 3T signal, the high-frequency emphasis filter 52 raises the high-frequency component corresponding to the run-length 3T signal. At this time, if excessive high-frequency emphasis is performed by the high-frequency emphasis filter 52, intersymbol interference occurs and, conversely, jitter occurs. In the waveform equalizer according to the present invention, An amplitude limiting circuit 51 is provided to prevent the occurrence of jitter.

FIG. 3 shows an operation principle for preventing the occurrence of jitter by the amplitude limiting circuit 51. Data recorded using an RLL (Run Length Limited) code having a minimum inversion interval of 3T, such as 8/16 modulation used in a DVD. FIG. Since the minimum inversion interval of the recording data is 3T, the recording data “1” or “−1” is always continuously three or more. Therefore, when data is inverted from “1” to “−1” between D ₋₁ and D ₁ , D ₋₂ and D ₋₃ are “1”, and D ₂ and D ₃ are “−”. 1 ”. Indicated by X, D _-4 previous data and D ₄ subsequent data show that 1, may be either case of -1.

The waveform of the read signal obtained when reading such record data is the record data pattern of the periphery (data before D _-4 and data after D ₄ are either "1" or "-1"). There are an infinite number of patterns depending on the combination of ()), but the value y ₀ at the zero cross point of the waveform in any case converges to 0 (that is, the intersymbol interference (jitter) is zero). To do.

  Here, it is assumed that the high-frequency emphasis filter 52 is an FIR (Finite Impulse Resnponse) filter as shown in FIG.

Note that the FIR filter shown in FIG. 4A includes unit delay elements FD _{1 to} FD ₄ , coefficient multipliers M _{1 to} M ₃ each having a multiplication coefficient {−k, 1, −k}, a coefficient This is a so-called cosine equalizer including an adder AD that outputs the sum of the outputs of the multipliers M _{1 to} M ₃ as an equalization correction read signal _RH .

At this time, the signal z0 obtained when the FIR filter performs high frequency emphasis at the zero cross point is as follows.
z ₀ = (− k) · y ₋₂ + y ₀ + (− k) · y ₂
y _-2 : Read signal level at the second most distant position immediately after the zero cross point
y ₀ : Read signal level at the zero cross point
y ₂ : The read signal level at the second most distant position immediately before the zero cross point.

However, as shown in various waveforms of the read signal R in FIG. 3, the values that y ₋₂ and y ₂ can take vary depending on the peripheral recording data pattern. When high frequency emphasis is performed, the influence of the variation in these y _-2 and y ₂ appears as intersymbol interference as it is. Therefore, the amplitude limiting circuit 51, by multiplying the amplitude limit by the amplitude limit value T _h and -T _h to the reading signal R, as a variation of the y _-2 and y ₂ y 'of _-2 and y' ₂ Forced down. Using these signals y ′ ₋₂ and y ′ ₂ ,
z ₀ '= (− k) · y ′ ₋₂ + y ₀ + (− k) · y ′ ₂
By performing this calculation, it is possible to prevent the occurrence of variation (jitter) in z ₀ ′. With this operation, sufficient high frequency emphasis can be performed by the high frequency emphasizing filter 52 without causing intersymbol interference. Incidentally, the absolute value T _h in the amplitude limiting values T _h and -T _h is larger in than the read signal level of the run-length 3T as the shortest wavelength, and also shorter than 4T of the read signal levels of the run-length to the next Set to a smaller value.

The high-frequency emphasis filter 52 actually uses a FIR filter with tap coefficients (−k, k, 1, k, −k) as shown in FIG. Note that the FIR filter shown in FIG. 4B has unit delay elements FD _{1 to} FD ₄ and coefficient multipliers M _{1 to} M each having multiplication coefficients {−k, k, 1, k, −k}. _This is a so-called cosine equalizer including 5 and an adder AD that outputs the sum of the outputs of the coefficient multipliers M _{1 to} M ₅ as an equalization correction read signal _RH .

According to the high-frequency emphasis filter 52 having such a configuration, the equalization correction read signal _RH output at the time of zero crossing is
R _H = (− k) · y ′ ₋₂ + k · (y ′ ₋₁ ) + y ′ ₀ + k · (y ′ ₁ ) + (− k) · y ′ ₂ = y ′ ₀ + k (y ′ ₋₁ − y ′ ₋₂ ) + k (y ′ ₁ −y ′ ₂ )
If the conditions y ′ ₋₁ = y ′ ₋₂ and y ′ ₁ = y ′ ₂ are satisfied, no intersymbol interference occurs regardless of the value of the coefficient k, that is, the amount of enhancement in the high frequency range.

  As described above, the waveform equalizer 5 is configured to perform the filtering process by the high-frequency emphasis filter 52 after limiting the amplitude of the read signal R with a predetermined amplitude limit value. At this time, the amplitude limit value is larger than the signal level of the shortest recording wavelength obtained when reading the recording data with the shortest run length (recording data with the run length 3T), and the recording with the next shortest run length. It is set smaller than the read signal level obtained when reading data (run length 4T recording data).

  Therefore, according to such a configuration, the variation in the read signal level before and after the zero cross in the read signal, which causes intersymbol interference when high frequency emphasis is performed, is forcibly suppressed. Even if sufficient high frequency emphasis is performed, intersymbol interference does not occur. The internal configuration of the waveform equalizer 5 is not limited to that shown in FIG.

  FIG. 5 is a diagram showing another configuration of the waveform equalizer 5.

  In FIG. 5, signal processing by the amplitude limiting circuit 51 and the high frequency emphasis filter 52 is the same as that shown in FIG. However, the waveform equalizer shown in FIG. 5 further includes a second high-frequency emphasis filter 53 that applies high-frequency emphasis to the read signal R supplied from the amplifier 4. A signal obtained by adding the high frequency emphasized read signals output from the high frequency emphasized filters 52 and 53 by the adder 54 is supplied to the binary decision circuit 6 as an equalized corrected read signal RH.

  FIG. 6 is a diagram showing a specific example of the waveform equalizer 5 shown in FIG.

In FIG. 6, the high-frequency emphasis filter 52 includes coefficient multipliers M ₁ , M ₂ , and M ₄ each having unit delay elements FD _{1 to} FD ₄ and multiplication coefficients {−k, k, k, −k}. And M ₅ and an adder AD that outputs the sum of the outputs of these coefficient multipliers, and is realized by an FIR filter with tap coefficients (−k, k, 0, k, −k).

Here, the principle of preventing jitter generation is to forcibly suppress variations in y ₋₂ and y ₂ in FIG. 3 by limiting the amplitude of the read signal by the amplitude limiting circuit 51. At this time, since the signal level y ₀ at the zero cross point is substantially 0, the signal level does not change before and after the amplitude limitation. Therefore, the coefficient multiplication performed in the coefficient multiplier M ₃ in FIG. 4B is performed in the high frequency emphasis filter 53 as shown in FIG. 6, and the result is used as the output of the high frequency emphasis filter 52. Even if the addition (adder 54) is performed, the effect of preventing the occurrence of jitter by the amplitude limiting circuit 51 is exhibited.

In the description of FIG. 3, the case where the read signal R has no intersymbol interference and y ₀ converges to 0 has been described. However, when there is intersymbol interference, the high frequency shown in FIG. The enhancement filter 53 may perform moderate high-frequency enhancement to remove intersymbol interference to generate a signal in which y ₀ converges to 0, and this may be added to the output of the high-frequency enhancement filter 52.

  On the other hand, in the configuration of the waveform equalizer 5 shown in FIG. 1, the low-frequency signal level is limited by the amplitude limiting circuit 51. May become low. However, in the configuration shown in FIG. 6, since the signal level of the low frequency is not lowered by the amplitude limiting circuit 51, the information reproduction accuracy is higher than that shown in FIG.

  Here, the waveform equalizer 5 performs high-frequency emphasis on the read signal R in advance of the amplitude limiting circuit 51 shown in FIG. A configuration as shown in FIG. 7 in which a high frequency emphasis filter 55 to be applied is provided may be employed.

  Further, as shown in FIG. 8, the waveform equalizer 5 may have a configuration in which the high-frequency emphasis filter 55 is provided in front of the waveform equalizer 5 in FIG. 5. At this time, the high-frequency emphasis filter 55 is used to lift the read signal corresponding to the run length 3T, that is, when the level of the shortest wavelength signal is extremely lowered.

Further, in the above embodiment has been described with reference to the amplitude limit value T _h and -T _h in the amplitude limiting circuit 51 as a predetermined fixed value, so as to automatically generated according to the amplitude limit value of the level of the read signal R May be.

  FIG. 9 is a diagram showing an internal configuration of the amplitude limiting circuit 51 made in view of such points.

9, the amplitude limit value generating circuit 511, the average of the absolute value of the reading signal level at the sample point nearest the zero crossing point in the read signal R, and supplies to the limiter 510 so as amplitude limitation value T _h. Limiter 510 to obtain the amplitude limited read signal R _LIM performs amplitude limitation for the read signal R based on this amplitude limiting value T _h.

Here, the amplitude limit value generation circuit 511 includes an absolute value conversion circuit 512, a zero level detection circuit 513, a low-pass filter 514, flip-flops D1 to D3, an OR gate OR, and a switch SW. An example of an internal operation waveform of the amplitude limit value generation circuit 511 having such a configuration is shown in FIG. The absolute value converting circuit 512 in the amplitude limit value generating circuit 511 obtains the absolute value of the read signal R and supplies it to the flip-flop D1 as the read signal absolute value Rb. Flip-flop D1 is such a read signal supplied to the switch SW as the absolute value R _b delays that delayed by one sampling period of the read signal absolute value R _c. The zero level detection circuit 513 generates a pulse signal R _d having a logic level “1” only when the read signal R becomes zero level. Flip-flops D 2 and D 3 supplies to the OR gate OR to which such pulse signal R _d is delayed by 2 sampling periods as a delay pulse signal R _e. OR gate OR is the pulse signal R _d or delay pulse signal one of R _e generates a switch-on signal R _f of logical level "1" only during the period of the logic level "1", this switch SW To supply. The switch SW is turned on only while the switch-on signal R _f having the logic level “1” is supplied, and supplies the delayed read signal absolute value R _c to the low-pass filter 514. Low pass filter 514 is supplied to a limiter 510 so the average value of such delayed read signal absolute value R _c as the amplitude limit value T _h.

With such a configuration, the amplitude limit value generation circuit 511 has the sample values {r ₂ , r ₄ , r closest to the zero crossing point among the sample values {r _{1 to} r ₁₁ } in the read signal R shown in FIG. _6, r _8, the absolute value of _{r 10} {-r 2, r} 4, r 6, -r 8, the average of -r _10} is taken as the amplitude limit value T _h. The amplitude limiting circuit 51 is not limited to that shown in FIG. 9, but may be configured as shown in FIG.

The amplitude limiting circuit 51 shown in FIG. 11, similarly to the configuration shown in FIG. 9, even while executing an amplitude limitation to the read signal by the amplitude limit value T _h determined by the amplitude limit value generating circuit 511, such amplitude limit value T _h is performing feedback control so as to converge to a predetermined target amplitude limitation value T _hm. That is, the subtractor 516 and the loop filter 517 calculates an error value between the amplitude limit value T _h and the target amplitude limitation value T _hm, amplifies for reading signal by a gain based on such error values. That is, instead of the amplifier 4 shown in FIG. 1, a variable gain amplifier 4 ′ as shown in FIG. 11 is used.

Figure 12 is a diagram showing an internal operation waveform when the amplitude limit value T _h obtained by the amplitude limit value generating circuit 511 is less than the target amplitude limit value T _hm, shortage gain of the gain variable amplifier 4 ' Is in a state. Therefore, at this time, the loop filter 517 outputs a positive error value, and feedback control is performed in a direction in which the gain of the gain variable amplifier 4 ′ increases. As a result, the amplitude level of the read signal R increases overall.

On the other hand, FIG. 13, the amplitude limit value T _h obtained by the amplitude limit value generating circuit 511 is a diagram showing an internal operation waveforms in the case where it exceeds the target amplitude limitation value T _hm, the gain variable amplifier 4 ' The gain is overstated. Therefore, at this time, the loop filter 517 outputs a negative error value, and feedback control is performed in a direction in which the gain of the gain variable amplifier 4 ′ decreases. Thereby, the amplitude level of the read signal R becomes small as a whole.

In the embodiment shown in FIG. 11, the limiter 510 has a configuration using the amplitude limiting value T _h determined by the amplitude limit value generating circuit 511, instead the target amplitude limited to such an amplitude limitation value T _h The value T _hm may be used. Further, the internal configuration of the amplitude limit value generation circuit 511 is not limited to that shown in FIG. 9, and for example, the configuration shown in FIG. 14 may be adopted.

The amplitude limit value generation circuit 511 shown in FIG. 14 detects the amplitude level of the read signal R (amplitude detection circuit 518) and multiplies the detected amplitude level by a predetermined value k (multiplier 519). and outputs as a limiting value T _h. Further, as the limiter 510 shown in FIGS. 9 and 11, an analog limiter as shown in FIG. 15 may be used.

In the analog limiter shown in FIG. 15, the level of the input signal IN is
| (R2 / R1) · IN | <| V _d |
When V _d is the forward voltage of the diodes D1 and D2, the diodes D1 and D2 are both turned off, so that the operation of the inverting amplifier including the resistors R1 and R2 and the operational amplifier OP is substantially performed. That is, the output signal OUT is
OUT =-(R2 / R1) ・ IN
It becomes.

On the other hand, the level of the input signal IN is
− (R2 / R1) · IN> V _d
If it is, the diode D2 becomes conductive is forward biased, this time, the output signal OUT will be limited to its maximum level at a forward voltage V _d of the diode D2.

Also, the level of the input signal IN is
− (R2 / R1) · IN <−V _d
If it is, the diode D1 becomes conductive is forward biased, this time, the output signal OUT will be limited to the minimum level at -V _d.

  By the operation as described above, the analog limiter shown in FIG. 15 realizes the amplitude limitation on the read signal with the input / output characteristics as shown in FIG.

  Further, as the limiter 510 shown in FIGS. 9 and 11, a configuration as shown in FIG. 17 may be adopted.

17, the comparator CM1 is an input signal IN, performs comparison between the amplitude limit value T _h, a logic level "1" if towards the input signal IN is large, the direction of the input signal IN If it is small, a comparison result signal GT of logic level “0” is generated and supplied to the selector SEL1. Selector SEL1, supplied from among the input signal IN and the amplitude limit value T _h, it alternatively selects by a person in accordance with the logic level of the comparison result signal GT to the selector SEL2. That is, the selector SEL1 the comparison result signal GT is a logic level "1", that is, of the input signal IN and the amplitude limit value T _h, select the amplitude limit value T _h in the case towards the input signal IN is larger This is supplied to the selector SEL2. On the other hand, when the comparison result signal GT is the logic level “0”, that is, when the input signal IN is smaller, the input signal IN is selected and supplied to the selector SEL2.

The multiplier MU calculates the amplitude limit value -T _h obtained by inverting the polarity of the amplitude limit value T _h by multiplying "-1" to the amplitude limiting value T _h, and supplies it to the selector SEL2 and the comparator CMP2 . Comparator CM2 includes the input signal IN, performs comparison between the amplitude limit value -T _h, the logic level "1" if towards the input signal IN is small, the large direction of the input signal IN If it is, the comparison result signal LT of the logic level “0” is generated and supplied to the selector SEL2. The selector SEL2 from among the supplied values and the amplitude limit value -T _h from the selector SEL1, alternatively select the person according to the logic level of the comparison result signal LT, and outputs this as an output signal OUT . That is, the selector SEL2 the comparison result signal LT is a logic level "1", that is, when towards the input signal IN among the input signal IN and the amplitude limit value T _h is smaller output amplitude limit value -T _h On the other hand, if the comparison result signal LT is at the logic level “0”, that is, the input signal IN is larger, the value supplied from the selector SEL1 is output.

With the above configuration, in the limiter shown in FIG.
| IN | in the case of <T _h is, OUT = IN
In the case of the IN> T _h is, OUT = T _h
In the case of IN <-T _h is, OUT = -T _h
The amplitude limitation on the read signal R is realized with the input / output characteristics.

  As another implementation method of the amplitude limiting circuit 51, a memory table in which the nonlinear input / output characteristics as shown in FIG. 2A or 2B are replaced with the address-read data relationship is used. There is a method using a ROM having the same.

  FIG. 18A is a diagram showing a configuration example of the amplitude limiting circuit 51 implemented using such a ROM, and FIG. 18B is a diagram showing an example of a memory table of this ROM.

Further, as a method for realizing the amplitude limiting circuit 51, there is a method using an A / D converter. At this time, a flash type is used as such an A / D converter, and a change as shown in FIG. 18B is added to the conversion table of the encoding circuit provided in the A / D converter. . That is, for the output beyond the range of the amplitude limiting values T _h ~-T _h, which is to use a conversion table to convert the amplitude limit value T _h or -T _h becomes a fixed value.

  In the above embodiment, the FIR filter is used as the high frequency emphasis filter 52. However, an analog high frequency emphasis filter may be used. Furthermore, in the above-described embodiment, the method for preventing the occurrence of jitter due to excessive high frequency emphasis has been described. However, the present invention can also be applied to the case of preventing the occurrence of jitter due to excessive attenuation of the high frequency. In that case, the high frequency emphasis filter 52 may be a low pass filter that cuts the high frequency from the shortest wavelength signal (run length 3T).

It is a figure which shows the structure of the recorded information reproducing | regenerating apparatus provided with the waveform equalizer by this invention. It is a figure which shows the input / output characteristic in the amplitude limiting circuit 51. It is a figure which shows the operation | movement which prevents the jitter generation by the amplitude limiting circuit 51. 5 is a diagram illustrating an example of an FIR filter as a high frequency emphasis filter 52. FIG. It is a figure which shows another example of the internal structure of the waveform equalizer 5. FIG. It is a figure which shows the specific structure of the waveform equalizer 5 shown by FIG. It is a figure which shows another example of the internal structure of the waveform equalizer 5. FIG. It is a figure which shows another example of the internal structure of the waveform equalizer 5. FIG. 2 is a diagram illustrating an example of an internal configuration of an amplitude limiting circuit 51. FIG. FIG. 10 is a diagram illustrating an example of operation waveforms in the amplitude limit value generation circuit 511 illustrated in FIG. 9. 6 is a diagram illustrating another example of the internal configuration of the amplitude limiting circuit 51. FIG. It is a figure which shows an example of the operation waveform in the amplitude limiting circuit 51 shown by FIG. It is a figure which shows an example of the operation waveform in the amplitude limiting circuit 51 shown by FIG. 6 is a diagram illustrating another example of the internal configuration of the amplitude limit value generation circuit 511. FIG. It is a figure which shows the structure of the limiter 510. FIG. It is a figure which shows the input / output characteristic of the limiter shown by FIG. It is a figure which shows the other structure of the limiter 510. FIG. It is a figure which shows the other structure of the limiter 510. FIG.

Explanation of symbols

5 Waveform equalizer 51 Amplitude limiting circuit 52 High-frequency emphasis filter

Claims (8)

A waveform equalizer that obtains an equalized corrected read signal by performing waveform equalization on a read signal obtained by reading an RLL (Run Length Limited) encoded signal recorded on a recording medium,
At the sample point after straight before and linear zero-cross point of the read signal, and the amplitude limit value generating means for generating an amplitude limit value based on the amplitude of the read signal,
Amplitude limiting means for limiting the amplitude level of the read signal with the amplitude limit value to obtain an amplitude limited read signal;
A waveform equalizer comprising: a filter that outputs a signal obtained by filtering the amplitude limited read signal as the equalization correction read signal.   The waveform equalizer according to claim 1, wherein the amplitude limit value generating unit generates the amplitude limit value by averaging absolute values of amplitudes of the read signals at the sample points.   2. The waveform equalizer according to claim 1, wherein the amplitude limit value is smaller than an amplitude value of the read signal corresponding to recording data that is next shortest after a minimum inversion interval.   2. The waveform equalizer according to claim 1, wherein the amplitude limit value is a value equal to or larger than an amplitude value of the read signal corresponding to the recording data of the minimum inversion interval.   2. The waveform equalizer according to claim 1, further comprising a variable gain amplifier that adjusts an amplitude of the read signal so that the amplitude limit value becomes equal to a predetermined value.   The waveform equalizer according to claim 1, wherein the filter is a filter that emphasizes a signal corresponding to the recording data of the minimum inversion interval.   The waveform equalizer according to claim 1, wherein the filter is an FIR filter having a tap coefficient of (−k, k, 1, k, −k). A recorded information reproducing apparatus for reproducing recorded information from a recording medium,
A pickup that reads the recording information from the recording medium to obtain a read signal, a waveform equalizer that performs waveform equalization on the read signal to obtain an equalized corrected read signal, and demodulates the equalized corrected read signal And a demodulating means for outputting a reproduction signal.
Said waveform equalizer at the sample point after straight before and linear zero-cross point of the read signal, and the amplitude limit value generating means for generating an amplitude limit value based on the amplitude of the read signal,
Amplitude limiting means for limiting the amplitude level of the read signal with the amplitude limit value to obtain an amplitude limited read signal;
And a filter that outputs a signal obtained by filtering the amplitude limited read signal as the equalized correction read signal.

Images