JP3788699B2 - Integrated optical circuit element and manufacturing method thereof - Google Patents

Description

【００５１】
で表される。
【００５２】
このとき、半導体レーザ部１０の活性層１０８と光導波路部３０の光導波層１０２とは、それらの間の間隙の中心線が、埋め込み部１１４の基板１００の表面からの高さ方向の中心線に一致するように、設置される。また、活性層１０８と光導波層１０２との間の間隔Ｔは、以下の式２、
【００５３】
【数２】

【００５４】
で表されるように設計する。
【００５５】
このような構造にすることにより、多モード干渉領域２０（より正確にはその埋め込み部１１４）を伝搬する光は、以下に述べるように、半導体レーザ部１０から光導波路部３０へ平行移動する。
【００５６】
上記で説明した本実施形態の構成では、電極１１２及び１１３の間に電流注入することにより、半導体レーザ部１０がレーザ発振を起こす。このときの発振波長は、約８５０ｎｍである。半導体レーザ部１０の活性層１０８からの出射光は、多モード干渉領域２０に入射する。多モード干渉領域２０における伝搬時には、横モードはほぼ入射時の光分布を保つが、多モード干渉領域２０（より正確にはその埋め込み部１１４）が縦方向で多モード導波路構造を有していることから、縦方向には多モードとなる。
【００５７】
図２には、図１のＡ−Ａ’断面における光分布を、模式的に示している。なお、図２において、図１と同じ構成要素を同じ参照番号で示しており、それらの説明はここでは省略する。
【００５８】
半導体レーザ部１０より出射した縦方向の光分布は、全幅で約０．９μｍである。多モード干渉領域２０では、入射した光は多モード導波路の固有モードの和として与えられるが、個々の固有モードの伝搬速度に差が生じるため、ある距難の多モード干渉領域を形成しておくと、その距離に応じて入射光の分割や平行移動などが発生する。本実施形態における集積型光結合素子では、多モード干渉領域２０の長さＬを、式１より約６７０μｍに作製することにより、活性層１０８より出射した光の多モード干渉領域への入射時の光分布が、光導波層１０２まで維持される。従って、本実施形態の構成では、半導体レーザ部１０からの出射光の光分布がほぼそのまま光導波路部３０の光導波層１０２へ入射される。光導波路部３０においては、そこに形成されているリッジ１３１が光導波路部３０に屈折率分布を与え、その光導波特性を有利にする。
【００５９】
光導波路部３０における光分布は、全幅が２．８μｍになり、モード不一致による放射損失が存在する。また、光導波路部３０はキャリアドービングされていて光吸収があるが、これは、光導波路部３０の長さを十分に短くしておけば、問題ない程度に抑えられる。
【００６０】
上記のように本実施形態では、光導波路部３０の光導波層１０２と半導体レーザ部１０の光導波層１０２とを同一の結晶成長プロセスにより作製することで、双方の光導波層の間の位置ずれなどに起因する損失が無い、良好なモード変換レーザ素子が得られる。また、多モード干渉領域２０の埋め込み部１１４をアルミニウム混晶比が０．３以下であるＡｌＧａＡｓで形成することにより、マスクの上に結晶が析出することなく、良好な素子作製が実現される。
【００６１】
なお、上述のようなＡｌＧａＡｓ系材料に限らず、これ以外の半導体材料の使用も可能である。
【００６２】
（第２の実施形態）
本発明の集積型光回路素子の第２の実施形態を、図３を参照して詳細に説明する。具体的には、本実施形態の集積型光変換素子はモード変換型レーザ素子であって、さらに低損失での光結合を実現する光回路素子の集積化に適した構成を有している。
【００６３】
なお、図３において、図１と同じ構成要素は、同じ参照番号で示している。
【００６４】
まず、作製方法を説明すると、第１の実施形態においてと同様に、ＧａＡｓ基板１００の上に通常のＭＯＣＶＤ法を用いて、光導波路を形成するため、Ａｌ_0.22Ｇａ_0.78Ａｓ第１光ガイド層１０１、厚さ２μｍのＡｌ_0.20Ｇａ_0.80Ａｓ光導波層１０２、Ａｌ_0.22Ｇａ_0.78Ａｓ第２光ガイド層１０３、Ａｌ_0.8Ｇａ_0.2Ａｓエッチング停止層１０４、及びＡｌ_0.22Ｇａ_0.78Ａｓ第３光ガイド層１０５を、順次積層する。これらの層は、ノンドープ層として形成する。これによって、半導体レーザ部１０及び光導波路部３０の双方に、光導波路が形成される。
【００６５】
次に、ｎ型ＧａＡｓ電極層１０６を形成した後に、その上に、半導体レーザ素子の発光部を形成するため、ｎ型Ａｌ_0.7Ｇａ_0.3Ａｓ第１クラッド層１０７、厚さ０．１μｍのｉ型ＧａＡｓ活性層１０８、ｐ型Ａｌ_0.7Ｇａ_0.3Ａｓ第２クラッド層１０９、ｐ型ＧａＡｓエッチング停止層１１０、及びｐ型第３クラッド層１１１を、順次積層する。この結果、半導体レーザ部１０には、主として光導波作用を奏する第１の素子領域３１０と、主として発光作用を有する第２の素子領域３２０とが、層厚方向に積層された状態で含まれることになる。
【００６６】
次に、多モード干渉領域２０を、第１の実施形態と同じ作製方法で形成する（その説明は、ここでは省略する）。但し、本実施形態では、多モード干渉領域２０の長さを６５８μｍに設定する。
【００６７】
次に、引き続いて行われる半導体レーザ部１０及び光導波路部３０の作製プロセスを説明すると、新たなＳｉＯ₂マスク（不図示）をパターニングし、このマスクを用いて、光導波路部３０において、硫酸系のエッチャントによって第１クラッド層１０７の途中までエッチングし、その後にフッ酸系のエッチャントによるエッチングを行う。このエッチングは、ｎ型ＧａＡｓ電極形成層１０６で自動的に停止する。このとき、適切なマスクパターンの使用によって、光導波路部３０のエッチングに加えて、半導体レーザ部１０の下部電極１１３の形成箇所にエッチング穴を同時に形成する。
【００６８】
その後に、第１の実施形態と同様のプロセスで、半導体レーザ部１０のリッジ１１１と光導波路部３０のリッジ１３１とを形成する。この場合のリッジ１３１は、電極形成層１０６及び第３光ガイド層１０５から構成されている。最後に、半導体レーザ部１０のリッジ１１１の上面と先のエッチングプロセスで形成された穴部とに、上部電極１１２及び下部電極１１３をそれぞれ形成する。
【００６９】
本実施形態の集積型光回路素子の機能を、以下に説明する。
【００７０】
本素子では、半導体レーザ部１０及び光導波路部３０の屈折率や寸法などは、第１の実施形態と同様である。本実施形態の構成では、電極形成層１０６より電流を注入できるので、電流損失を少なくしてレーザ発振を行うことができる。半導体レーザ部１０からの出射光は多モード干渉領域２０に入射し、光導波路部３０に至る。
【００７１】
多モード干渉領域２０は、第１の実施形態と同様に、半導体レーザ部１０との界面から６７０μｍの位置で、レーザ出射端面においてと同一の光分布を再現するが、本実施形態では、多モード干渉領城２０の長さ（Ｌ＝６５８μｍ）を上記の値に一致させていない。この点を図４（ａ）及び（ｂ）を参照して更に説明する。図４（ａ）は、先述の第１の実施形態の素子構成を示し、図４（ｂ）は、本実施形態の素子構成を示す。但し、個々の層の参照番号は省略している。
【００７２】
図４（ａ）に示す第１の実施形態の構成では、多モード干渉領城２０の長さを、多モード干渉領城２０と光導波路部３０との界面で、半導体レーザ部１０の活性層１０８の出射端面と同一光分布が得られる長さに一致させている。これに対して、図４（ｂ）に示す本実施形態の構成では、そのような長さに設定する代わりに、多モード干渉領城２０と光導波路部３０との間の結合効率が最大になるような長さに設定している。これにより、図４（ｂ）に示すように、多モード干渉領城２０と光導波路部３０との界面での光分布の縦方向の幅が、光導波路部３０の光導波層１０２における光分布の縦方向の幅に一致させられる。この結果、モード不一致による放射モードの低減が、実現される。
【００７３】
本願発明者らは、多モード干渉領域２０の長さＬを様々に変化させた幾つかの素子を作製して、多モード干渉領城２０と光導波路部３０との間の結合効率を測定した。図５には、その測定結果を示す。これより、０．６０以上の結合効率を得るためには、多モード干渉領域２０の長さＬは約６５１〜６６３μｍの範囲にその最適値がある。このことは、半導体レーザ部１０と光導波路部３０との間で縦方向に光分布の幅が異なることによって初めて有効となる方法であり、本発明だけの独特の効果である。
【００７４】
更に、本実施形態の素子では、光導波路部３０をノンドープとすることにより、光導波路部３０での光吸収を無くすことができる。
【００７５】
また、電極形成層１０６を設けることにより、電極１１３から活性層１０８までの距離が短くなり、電流損失を小さくすることができる。この電極形成層１０６は、光導波路部３０のリッジ１３１の上面まで延びているが、光導波層１０２を伝搬する光はこの電極形成層１０６にまで広がらないので、大きな損失を引き引き起こすことはない。
【００７６】
以上に説明したように、本実施形態の集積型光回路素子では、多モード干渉領域２０の長さを実際の光分布と光導波層１０２の固有モードとの関係を考慮して調節することで、放射モードを抑制した良好な光結合が実現される。また、光導波路部３０をノンドープとすることで、光導波路部３０での光吸収を無くして、その長さを長くすることができる。これによって、光導波路部３０にＹ分岐光回路などを作製することが可能になる。
【００７７】
（第３の実施形態）
本発明の集積型光回路素子の第３の実施形態を、図６を参照して詳細に説明する。具体的には、本実施形態の集積型光変換素子はモード変換型レーザ素子であって、第１及び第２の実施形態における縦方向の光分布変換に加えて、横方向での光分布変換も実現する構成を有している。
【００７８】
図６において、図３と同じ構成要素は同じ参照番号で示しており、それらの詳細な説明はここでは省略する。なお、本実施形態の素子の製造プロセスは、基本的に第２の実施形態におけるプロセスと同様である。
【００７９】
本実施形態の構成では、多モード干渉領域２０は、深さ４．７５μｍ及び長さ２００μｍとし、その埋め込み部１１４の幅は、半導体レーザ部１０に近い端面で２μｍ、光導波路部３０に近い端面で０．５μｍとして、その間で連続的に変化させる。
【００８０】
また、図６に示すように、半導体レーザ部１０と多モード干渉領域２０との境界部分に、薄い境界層１１６を、発振レーザ光の進行方向に対して垂直方向に形成する。この薄い境界層１１６の形成は、多モード干渉領域２０の埋め込み部１１４の形成のためのエッチング及び埋め込みプロセスにて、同時に行われる。
【００８１】
具体的には、このエッチングでは、ｎ型第１光ガイド層１０１が０．２５μｍの厚さだけ残るように行う。その後に、２回目のＭＯＣＶＤ工程によって、薄い境界層１１６と多モード干渉領域２０の埋め込み部１１４の全体とを、ｉ型Ａｌ_0.15Ｇａ_0.85Ａｓで埋め込む。第１及び第２の実施形態では、多モード干渉領域２０の埋め込み部１１４の最下部及び最上部の厚さ０．２５μｍの部分をＡｌ_0.20Ｇａ_0.80Ａｓで埋め込んでいるが、本実施形態では、上記のようにＡｌ_0.15Ｇａ_0.85Ａｓで全体を一様に埋め込む。
【００８２】
光導波路部３０のリッジ１３１の幅は、第１及び第２の実施形態では２μｍであったが、この実施形態では４μｍにする。第３光ガイド層１０５の厚さは、幅４μｍでシングルモード導波路になるように設定する。本実施形態の場合、多モード干渉領域２０の埋め込み部１１４は非対称閉じ込め構造となるために、埋め込み部１１４の長さＬ、及び活性層１０８と光導波層１０２との間隔Ｔは、先述の式１及び式２で表されない。本願出願人らは、式１及び式２に基づく計算機シミュレーションなどによって最適構造を検討した上で、その有効性を実際の素子作製によって確認した。
【００８３】
本実施形態の集積型光回路素子の機能について説明する。
【００８４】
半導体レーザ部１０から出射した光は、多モード干渉領域２０に入射する。多モード干渉領域２０では、その下側のみにアルミニウム混晶比が０．２０の光ガイド層１０１が形成されており、上側には特別な層が形成されずに空気に直接に接触している。従って、縦方向の屈折率分布が非対称である多モード導波構造が得られる。多モード干渉領域２０の長さを最適に設計すれば、第１及び第２の実施形態と同様に、縦方向に光分布が平行移動して、半導体レーザ部１０から出射した光が光導波路部３０の光導波層１０２へ導かれる。一方、横方向の光分布は、多モード干渉領域２０の埋め込み部１１４の幅が連続的に狭くなるに応じて光が埋め込み部１１４の外側へはみ出し、多モード干渉領域２０の終端では光分布の全幅が５．５μｍまで広がって、光導波路部３０における横方向の光分布と一致する。
【００８５】
薄い境界層１１６は、充分に薄く形成しているため、横方向の光の広がりには寄与しないが、電極１１２から注入された電流が、多モード干渉領域２０の埋め込み部１１４の端部から、活性層１０８並びに第１及び第２クラッド層１０７及び１０９を経て半導体レーザ部１０から漏れ出ることを防止する電気的絶緑層としての機能を有する。薄い境界層１１６は、光の広がりに影響なく且つ電流阻止を行うことができる厚さであれば、薄いほど良い。典型的には０．１〜１０μｍに設定され、好ましくは５μｍ以下であり、より好ましくは２μｍ以下である。
【００８６】
本実施形態の素子では、マスクパターンの変化のみで、横方向の光結合が高効率で実現できる。なお、以上の説明では、多モード干渉領域２０の埋め込み部１１４の幅をレーザ光の進行方向に連続的に小さくなるよう変化させているが、段階的に変化させても、同様の効果が得られる。また、その変化は、直線状であっても曲線状であってもよい。また、多モード干渉領域２０の埋め込み部１１４の厚さをレーザ光の進行方向に連続的或いは段階的に広くすることによっても、上記と同様の効果が得られる。
【００８７】
また、半導体レーザ部１０と多モード干渉領域２０との間にｉ型の薄い境界層１１６を形成することにより、効率的な電流注入が実現されて、レーザの発振閾値の低下が実現される。
【００８８】
（第４の実施形態）
本発明の集積型光回路素子の第４の実施形態を、図７を参照して詳細に説明する。
【００８９】
図７において、図３と同じ構成要素は同じ参照番号で示しており、それらの詳細な説明はここでは省略する。なお、本実施形態の素子の製造プロセスは、基本的に第２の実施形態におけるプロセスと同様である。但し、本実施形態の構成では、多モード干渉領域２０の埋め込み部１１４の幅を、１５μｍと大きく形成する。また、半導体レーザ部１０のリッジ１１１の中心線と光導波路部３０のリッジ１３１の中心線とを幅方向に６．３μｍずれて設けて、多モード干渉領域２０の埋め込み部１１４の横方向の中心に対して線対称に位置するように設計されている。
【００９０】
本実施形態の集積型光回路素子の機能について説明する。
【００９１】
第１〜第３の実施形態では、多モード干渉領域２０の埋め込み部１１４の幅が０．５〜２μｍと狭いため、図８に模式的に示すように、多モード干渉領域２０の表面において、埋め込み部１１４と非埋め込み部との境界に凹状又は凸状の形状が生じて、平坦にならないことがある。このような場合には、多モード干渉領域２０の埋め込み部１１４での固有モードの分布に若干の変化が生じて、結合効率に劣化が生じる。これに対して本実施形態の構成では、縦及び横方向に広がった埋め込み部１１４を設けることによって、実効的に光の分布する領域は平坦な埋め込みがなされる。
【００９２】
図９は、本実施形態の構成における多モード干渉領域２０（より厳密にはその埋め込み部１１４）の内部での光分布を、上面から示したものでる。
【００９３】
光は、半導体レーザ部１０から出射した直後、或いは光導波路部３０へ入射する直前に、半導体レーザ部１０と多モード干渉領域２０との間の境界領域、及び多モード干渉領域２０と光導波路部３０との間の境界領域に存在する、平坦に埋め込まれていない領域３１を通過する。しかし、この領域３１の距離が短いので、光分布は影響されない。また、図８の場合と比較して、多モード干渉領域２０の光は、平坦に埋め込まれていない領域３１の直下には分布せず、平坦に埋め込まれた領域３２のみに分布するので、光分布に対する好ましくない影響は発生しない。
【００９４】
このように、本実施形態では、多モード干渉領域２０の埋め込み部１１４の形成のための結晶成長時に埋め込み部１１４の上面が平坦化しない間題を回避して、その点に起因していた結合効率の低下を防ぐとともに、埋め込み部１１４の平坦化のためのプロセスを省略することができる。
【００９５】
なお、上記の説明では、半導体レーザ部１０と光導波路部３０とで横方向の光分布の幅がほば等しいが、この幅が等しくなくても、多モード干渉領域２０の長さを最適に設定することにより、良好な光結合が実現される。
【００９６】
（第５の実施形態）
本発明の集積型光回路素子の第５の実施形態を、図１０を参照して詳細に説明する。具体的には、本実施形態の集積型光変換素子は、モード変換型レーザ素子である。
【００９７】
なお、図１０において、これまでの実施形態においてと同じ構成要素は、同じ参照番号で示している。
【００９８】
まず、作製方法を説明すると、第１の実施形態においてと同様に、ＧａＡｓ基板１００の上に通常のＭＯＣＶＤ法を用いて、光導波路を形成するため、Ａｌ_{0. 22}Ｇａ_0.78Ａｓ第１光ガイド層１０１、厚さ２μｍのＡｌ_0.20Ｇａ_0.80Ａｓ光導波層１０２、及びＡｌ_0.22Ｇａ_0.78Ａｓ第２光ガイド層１０３を、順次積層する。これらの層は、ノンドープ層として形成する。これによって、半導体レーザ部１０及び光導波路部３０の双方に、光導波路が形成される。
【００９９】
次に、ｎ型ＧａＡｓ電極層１０６を形成した後に、その上に、半導体レーザ素子の発光部を形成するため、ｎ型Ａｌ_0.7Ｇａ_0.3Ａｓ第１クラッド層１０７、厚さ０．１μｍのｉ型ＧａＡｓ活性層１０８、ｐ型Ａｌ_0.7Ｇａ_0.3Ａｓ第２クラッド層１０９、ｐ型ＧａＡｓエッチング停止層１１０、及びｐ型第３クラッド層１１１を、順次積層する。この結果、半導体レーザ部１０には、主として光導波作用を奏する第１の素子領域３１０と、主として発光作用を有する第２の素子領域３２０とが、層厚方向に積層された状態で含まれることになる。
【０１００】
次に、多モード干渉領域２０を形成するためのＲＩＢＥエッチングを行うが、このときのエッチングマスクパターンは、光導波路部３０の両端部１２１もエッチングして、その後の工程で半導体レーザ部１０のリッジ１１１及び多モード干渉領域２０の埋め込み部１１４と一直線上に並ぶメサ構造が形成されるように、設定する。また、好ましくは、第２の実施形態と同様に、半導体レーザ部１０に下部電極１１３を形成するためのエッチング穴を、更に同時に形成する。
【０１０１】
ＲＩＢＥエッチングは、第１の実施形態と同様にＧａＡｓ基板１００に達するまで行う。その後に、得られたエッチング溝をＡｌＧａＡｓで埋め込んで、埋め込み部１１４を形成する。なお、埋め込み部１１４のうちで、最下部及び最上部のそれぞれ厚さ０．２５μｍの部分ではＡｌＧａＡｓのＡｌ混晶比を０．２９とし、残りの部分では、ＡｌＧａＡｓのＡｌ混晶比を０．２４とする。光導波路部３０のメサ構造の端部１２１も、埋め込み部１１４と同じ上記のプロセスで埋め込まれる。
【０１０２】
多モード干渉領域２０の埋め込み部１１４は、図１０に示すように、その幅が連続的に変化するように設定し、且つ特に幅が狭い領域で、その幅の変化が緩やかになるようにした。これにより、埋め込み部１１４の幅が直線的に変化する場合に比べて、多モード干渉領域２０の長さが同一であってもモード変換効率が向上する。
【０１０３】
多モード干渉領域２０の埋め込み部１１４のＡｌ混晶比が、光導波層１０２のＡｌ混晶比よりも高く設定されている。このため、横方向の光閉じ込めがアンチガイドになって、この領城での漏れ光波による損失が存在するが、この損失量は０．１ｄＢ／１００μｍ程度であり、問題とはならない。なお、光導波路部３０では、縦及び横の両方向ともにガイド構造となって、シングルモード導波路が形成される。
【０１０４】
この様に本実施形態では、半導体レーザ部１０から光導波路部３０への高効率な光結合が達成されると共に、光導波路部３０でのリッジ形成が不要な素子が実現される。また、光導波路部３０の長さが十分に短い場合には、多モード干渉領域２０の埋め込み部１１４のＡｌ混晶比を光導波層１０２のＡｌ混晶比よりも低く設定することによって、光導波路部３０をアンチカイドとして用いることも可能である。この場合にも、漏れ光波による導波損失は０．１ｄＢ／１００μｍ程度であり、問題とはならない。
【０１０５】
また、多モード干渉領域２０の埋め込み部１１４と光導波路部３０におけるメサ構造の両端部１２１とを、お互いに異なるＡｌ混晶比を有する半導体材料で埋め込めば、多モード干渉領域２０及び光導波路領域３０の何れにおいてもガイド構造を実現することが可能になって、低損失で且つ他の光素子と一体集積可能な集積型半導体レーザ素子が得られる。本発明は、横方向の光閉じ込め方法に限定されるものではなく、このような構造も本発明の範疇である。
【０１０６】
（第６の実施形態）
以下に、本発明の集積型光回路素子の第６の実施形態を説明する。具体的には、本実施形態の集積型光変換素子は、モード変換型レーザ素子である。
【０１０７】
図１１（ａ）は、本実施形態の集積型光回路素子の、多モード干渉領域２０の埋め込み部１１４を通る断面（図１の線Ａ−Ａ’に相当する）での断面図である。本実施形態の素子は、従来技術によるプロセスや本発明の第１〜第５の実施形態にて説明したプロセスを用いて形成することができる。但し、本実施形態では、半導体レーザ部１０と光導波路部３０との中間に、更に光バッファ部４０を設けている。光バッファ部４０と半導体レーザ部１０との間、及び光バッファ部４０と光導波路部３０との間は、それぞれ多モード干渉領域２０１及び２０２で接続される。多モード干渉領域２０１及び２０２を用いた接続では、従来の様な導波層間の位置ずれや不要層の存在がなく、多段接続による結合効率の劣化が生じない。
【０１０８】
本実施形態の構成の効果について説明する。
【０１０９】
半導体レーザ部１０及び光導波路部３０における光分布幅をそれぞれｗ₁及びｗ₃とすると、光バツファ部４０が設けられていない場合の結合効率η₁は、ほぼ以下の式３、
【０１１０】
【数３】

【０１１１】
で表される。
【０１１２】
これに対して、本実施形態のように光バッファ部４０が設けられている場合の結合効率η₂は、光バッファ部４０における光分布幅をｗ₂とすると、以下の式４、
【０１１３】
【数４】

【０１１４】
で表される。
【０１１５】
これより、半導体レーザ部１０と光導波路部３０との光分布幅が大きく異なるとき（ｗ₃≫ｗ₁）には、ｗ₂の値を以下の式５、
【０１１６】
【数５】

【０１１７】
に従って設定することによって、式４で表される本実施形態での結合効率η₂を、式３で表される光バッファ層４０が設けられていない場合の結合効率η₁の約２倍にまで向上させることができる。
【０１１８】
本実施形態のように光バッファ部４０を設けることで、第１の実施形態と同一の光分布幅を持つ半導体レーザ部１０及び光導波路部３０を有する構成において、結合効率が光バッファ部４０を有さない場合の約１．４倍に向上した。これにより、光導波路部３０を半導体レーザ部１０と同一プロセスで形成することができ、再成長による結晶品質の低下を招くことなく、良好な光結合が実現される。この多段接続の効果はテーパ接続によって得られるものであり、従来技術においてよりも信頼性の高い集積型光回路素子が実現される。
【０１１９】
図１１（ｂ）は、本実施形態の改変された素子構成であり、２つの多モード干渉領域２０１及び２０２が同一の深さで作製されている。この場合にも、２つの多モード干渉領域２０１及び２０２の長さを最適化することによって、上記と同様の効果が得られる。なお、図１１（ｂ）の構成では、２つの多モード干渉領域２０１及び２０２のエッチングプロセス及び埋め込みプロセスを同時に行えるという利点がある。
【０１２０】
なお、上記では、半導体レーザ部１０と光導波路部３０との間を光バッファ部４０を用いて多段接続する構成を説明しているが、本実施形態の構成の適用は上記に限られるものではない。例えば、厚さの異なる光導波路間の結合に対しても適用可能であって、そのような構造も本発明に含まれる。
【０１２１】
（第７の実施形態）
本発明の実施形態を、以下に説明する。具体的には、本実施形態は、先に説明した第１の実施形態における集積型光変換素子の異なる製造方法を説明するものであり、得られる素子は第１の実施形態における場合よりも向上した特性を有している。
【０１２２】
なお、以下の説明で、これまでの実施形態においてと同じ構成要素は、同じ参照番号で示している。
【０１２３】
まず、作製方法を説明すると、第１の実施形態においてと同様に、ＧａＡｓ基板１００の上に通常のＭＯＣＶＤ法を用いて、光導波路を形成する層１０１〜１０５を順次積層する。これによって、半導体レーザ部１０及び光導波路部３０の双方に、光導波路が形成される。次に、上記で得られた積層構造の上に、半導体レーザ素子の発光部を形成する層１０７〜１１１を順次積層する。
【０１２４】
続いて、図１２Ａに示すようにＳｉＯ₂マスク１１７を層１１１の上にパターニングし、これを用いて多モード干渉領域２０を形成するためのＲＩＢＥエッチングを、ＧａＡｓ基板１００に達するまで行う。ＲＩＢＥエッチングの後に、更にウェットエッチングなどを行うことによって、ＲＩＢＥエッチングで得られたエッチング溝の底面を更に平坦化しても良い。その後に、ＭＯＣＶＤによる選択成長を行って、ＲＩＢＥエッチングで得られたエッチング溝に、多モード干渉領域２０の埋め込み部１１４（図１２Ｂ参照）を形成することになる３層のＡｌＧａＡｓ成長層を埋め込む（但し、図１２Ｂでは層を区別して図示していない）。埋め込み部１１４を構成する３つのＡｌＧａＡｓ層のそれぞれの厚さ及び組成は、第１の実施形態と同じにする。
【０１２５】
更に、図１２Ｂを参照すると、埋め込まれたＡｌＧａＡｓ層の上部に、半導体レーザ部１０と光導波路部３０とを接続するようにＳｉＯ₂膜パターン１１８を形成する。そして、先に形成されていたＳｉＯ₂マスク１１７とこのＳｉＯ₂膜パターン１１８とを使用して、多モード干渉領域２０の埋め込み部１１４に相当する箇所のみが残存するように、埋め込まれたＡｌＧａＡｓ層に対するＲＩＢＥエッチングを行う。これによって、多モード干渉領域２０における横方向の光閉じ込め構造を、図１２Ｂのように形成する。
【０１２６】
この後、第１の実施形態においてと同様のプロセスによって、半導体レーザ部１０及び光導波路部３０にそれぞれリッジ１１１及び１３１を形成する。なお、このリッジ形成時のウェットエッチングによって、多モード干渉領域２０の埋め込み部１１４や半導体レーザ部１０及び光導波路部３０の露出した側面１１９にサイドエッチングが行われることを避けるためには、エッチングの実施前に、露出面の１１９を覆うような保護膜（例えばＳｉＯ₂膜）を形成するか、或いは半導体材料やポリイミドなどの適切な材料によって、埋め込み部１１４の側部１２８（図１２Ｃ参照）を埋め込んでおけば良い。但し、このような埋め込みを行う場合には、多モード干渉領域２０での横方向モードの安定のために、埋め込み部１１４の側部１２８を埋め込むために使用される材料の種類に応じて、埋め込み部１１４の幅を適切に設計する必要がある。本実施形態では、半導体材料、具体的にはＡｌ_0.18Ｇａ_0.82Ａｓによって、埋め込み部１１４の側部１２８を埋め込んでいる。
【０１２７】
最後に、半導体レーザ部１０のリッジ１１１の上面に上部電極１１２を形成し、基板の下面に下部電極（不図示）を形成して、図１２Ｃに示す構成を得る。
【０１２８】
上記のような選択成長を用いる場合には、図１２Ｃ或いは図１２Ｄに模式的に示しているように、成長領域と非成長領域（マスクされた領域）との境界付近では平坦な埋め込みが実現されずに、成長層が厚くなることが知られている。しかし、本実施形態の上記の製造プロセスでは、多モード干渉領域２０の埋め込み部１１４の形成時には、横方向での埋め込み幅が十分に広いために、図１２Ｃ或いは図１２Ｄより、平坦な埋め込みが実現されない領域は半導体レーザ部１０或いは光導波路部３０と多モード干渉領域２０との界面の極く近傍に限られており、多モード干渉領域２０の埋め込み部１１４の横方向での厚さの実質的な変化が生じない。
【０１２９】
この場合、図１２Ｄに示すように、半導体レーザ部１０から出射した光は、多モード干渉領域２０に放射した後に上下の層で反射されるが、この反射は、実際には多モード干渉領域２０の中央部で生じる。本実施形態の構成では、多モード干渉領域２０の中央部が実質的に平坦に埋め込まれているので、望ましい反射状態が実現されて、半導体レーザ部１０から出射した光は効率的に光導波路部３０に結合される。
【０１３０】
（第８の実施形態）
本発明の第８の実施形態を、以下に説明する。具体的には、本実施形態は、先に説明した第１の実施形態における集積型光変換素子の異なる製造方法を説明するものであり、得られる素子は第１の実施形態における場合よりも向上した特性を有している。なお、以下の説明で、これまでの実施形態においてと同じ構成要素は、同じ参照番号で示している。
【０１３１】
第７の実施形態に関連して説明したように、多モード干渉領域２０の埋め込み部１１４を平坦に作製すれば、素子特性が向上する。本実施形態では、更に平坦化された埋め込み部１１４を得ることができるプロセスを説明する。
【０１３２】
まず、ＧａＡｓ基板１００の上に通常のＭＯＣＶＤ法を用いて、３つのＡｌＧａＡｓ層２１〜２３を順次積層する。これら３つのＡｌＧａＡｓ層２１〜２３のそれぞれの厚さ及び組成は、第１の実施形態と同じにする。この時点で、多モード干渉領域２０の埋め込み部１１４の上面及び下面は平坦な面である。
【０１３３】
次に、多モード干渉領域２０の長さ（図１３Ａの面内方向の長さ）が第２の実施形態における素子構成と同じ６５８μｍになるように、適切な形状のＳｉＯ₂マスク１１７を、最上部のＡｌＧａＡｓ層２３の上にパターニングする。そして、このＳｉＯ₂マスク１１７を用いて、多モード干渉領域２０以外の部分をＧａＡｓ基板１００に達するまで、ほぼ垂直にＲＩＢＥエッチングする。
【０１３４】
次に、半導体レーザ部１０及び光導波路部３０の形成プロセスの実施のために、多モード干渉領域２０の側面を囲むＳｉＯ₂膜１１７ａを、バイアススパッタ法によって形成する。最適なバイアス電圧を基板１００に印加した状態で実施するこのバイアススパッタ法により、エッチングされた領域の底面では、イオン照射によるＳｉＯ₂膜の脱離と形成とが競合して、ＳｉＯ₂膜が実質的に形成されない。従って、多モード干渉領域２０の側面のみに、ＳｉＯ₂膜１１７ａが形成される。
【０１３５】
なお、先のＲＩＢＥエッチングで使用して残存しているＳｉＯ₂マスク１１７に対しても、このバイアススパッタプロセスにおいて、同様の脱離と形成との競合が発生するが、その厚さはむしろ減少する傾向にあるので、その点を考慮して、あらかじめ厚く形成しておくことが好ましい。
【０１３６】
次に、上記によって露出した基板１００の表面に、ＭＯＣＶＤ選択成長法を用いて、第１の実施形態においてと同様の光導波路を形成する層１０１〜１０５を順次積層する。これによって、半導体レーザ部１０及び光導波路部３０の双方に、光導波路が形成される。次に、上記で得られた積層構造の上に、半導体レーザ素子の発光部を形成する層１０７〜１１１を順次積層する。この結果、これまでの実施形態においてと同様に、半導体レーザ部１０には、主として光導波作用を奏する第１の素子領域３１０と、主として発光作用を有する第２の素子領域３２０とが、層厚方向に積層された状態で含まれることになる。
【０１３７】
なお、上記の選択成長においては、ＳｉＯ₂層１１７の上では結晶成長は起こらず、結果的に、図１３Ａに示すように各層１０１〜１０５及び１０７〜１１１は実質的に水平に形成される。
【０１３８】
この後には、第７の実施形態として説明したように、多モード干渉領域２０における横方向での光閉じ込めのために、３つのＡｌＧａＡｓ層２１〜２３からなる積層構造の一部をエッチングで除去し、その後に、それによって除去された部分をポリイミドなどの適切な材料で埋め込む。さらにその後で、既に説明したリッジ形成プロセスを行って、半導体レーザ部１０及び光導波路部３０の最終構造を形成する。
【０１３９】
本実施形態の製造プロセスによれば、多モード干渉領域２０の埋め込み層１１４を構成する各ＡｌＧａＡｓ層２１〜２３は、平坦なＧａＡｓ基板１００の表面に平坦に形成される。これにより、多モード干渉領域２０の特性が向上する。
【０１４０】
なお、上記の説明では、集積される光素子としての半導体レーザ素子を形成するために、選択成長法を使用して実質的に平行な成長層１０７〜１１１を得ている。しかし、多モード干渉領域２０と集積される光素子との間の結合において、高い結合効率が要求されない場合には、選択成長法に代えて、バイアススパッタ法などの他の成長プロセスで必要な成長層を形成しても良い。
【０１４１】
また、上記の説明では、多モード干渉領域２０の埋め込み部１１４の側部をポリイミドで埋め込んでいるが、その代わりに半導体材料によって埋め込むことも可能である。その場合には、３つのＡｌＧａＡｓ層２１〜２３の積層構造の形成後に、適切なパターンのマスク１１７を使用して、多モード干渉領域２０の埋め込み部１１４に相当する箇所の周囲の部分を、図１３Ｂに示すようにエッチングで除去する。そして、露出した埋め込み部１１４の側面に、バイアススパッタ法によってＳｉＯ₂膜１１７ａを形成する。その後に、図１３Ｃに示されるように、半導体レーザ部１０及び光導波路部３０の最終構造を形成する。
【０１４２】
このようにすれば、半導体レーザ部１０及び光導波路部３０の形成と多モード干渉領域２０の埋め込み部１１４の側部の埋め込みとを、同一のプロセスで実施することが可能になる。
【０１４３】
【発明の効果】
本発明によれば、層厚方向に光分布幅の異なる複数の光素子の間での高効率な光結合を実現して、ー体集積化が可能な集積型光回路素子を得ることができる。
【０１４４】
また、多モード干渉領域の長さ及び幅を最適に設定することにより、ある光素子から他の光素子への結合の際に生じる縦方向モードの不一致に関する放射損失の低減、横モードの変換、及び多モード干渉領域の作製時の不完全な埋め込み（不完全な平坦化）による結合損失の低減が、実現される。また、多モード干渉領域の埋め込み部をアルミニウム混晶比が０．３以下の材料で形成することによって、マスク上への埋め込み材料の析出がない良好な素子作製が実施される。
【０１４５】
また、本発明による集積型光回路素子は、従来の素子構造に比べて簡単化されたプロセスで形成可能である。具体的には、２回のＭＯＣＶＤ成長によって作製が可能であり、更に２回目のＭＯＣＶＤ成長では多モード干渉領域での埋め込み部を形成するのみであるので、素子の動作特性に影響を及ぼすような再成長に伴う結晶品質の低下が、発生しない。
【０１４６】
集積される光素子（光素子部）として半導体レーザ素子（半導体レーザ部）及び光導波路素子（光導波路部）を用いる場合、多モード干渉領域と半導体レーザ部との間に薄い境界層をｉ型材料で埋め込むことにより、半導体レーザ部からの漏れ電流の無い集積型光回路素子が得られる。また、本発明では、半導体レーザ部の下部電極の形成時に、光導波路部におけるリッジ形成プロセスを同時に行うことが可能である。更に、光導波路部のメサ構造の形成と多モード干渉領域のエッチングとを同時に行ったり、多モード干渉領域における埋め込み部の形成と光導波路部のメサ構造の両端部の埋め込みとを同時に行ったりすることも、可能である。これらによって、作製プロセスの簡略化や効率化を図ることができる。
【０１４７】
多モード干渉領域の形成時のエッチングによって溝形状を形成すれば、溝部への埋め込みが溝部の長手方向に対してほぼ平坦に行われるので、多モード干渉領域の特性が向上する。
【０１４８】
更に好ましくは、多モード干渉領域の積層を、半導体レーザ素子（半導体レーザ部）の発光部として機能する層や半導体レーザ素子（半導体レーザ部）及び光導波路素子（光導波路部）の光導波層として機能する層の積層に先立って行い、その後にエッチングによって半導体レーザ素子（半導体レーザ部）及び光導波路素子（光導波路部）の作製領域を確保した上でこれらの素子を形成し、集積型光回路素子を得る。これにより、更に平坦性の高い多モード干渉領域が得られて、素子特性が向上する。
【０１４９】
また、複教の多モード干渉領域及び光バッファ層を設けた多段接続構成とすれば、結合効率の更なる向上が図れる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態における集積型光回路素子として、モード変換型半導体レーザ素子の構成を模式的に示す斜視図である。
【図２】図１の第１の実施形態の素子の動作を説明する断面図である。
【図３】本発明の第２の実施形態における集積型光回路素子として、モード変換型半導体レーザ素子の構成を模式的に示す斜視図である。
【図４】（ａ）は、図１に示す第１の実施形態の素子の動作を説明する断面図であり、（ｂ）は、図３に示す第２の実施形態の素子の動作を説明する断面図である。
【図５】図３に示す第２の実施形態の効果を説明する図である。
【図６】本発明の第３の実施形態における集積型光回路素子として、モード変換型半導体レーザ素子の構成を模式的に示す斜視図である。
【図７】本発明の第４の実施形態における集積型光回路素子として、モード変換型半導体レーザ素子の構成を模式的に示す斜視図である。
【図８】図７に示す第４の実施形態の構成に関連した課題を説明する図である。
【図９】図７に示す第４の実施形態の素子の動作を説明する断面図である。
【図１０】本発明の第５の実施形態における集積型光回路素子として、モード変換型半導体レーザ素子の構成を模式的に示す斜視図である。
【図１１】（ａ）は、本発明の第６の実施形態における集積型光回路素子として、モード変換型半導体レーザ素子のある構成を模式的に示す断面図であり、（ｂ）は、その改変された構成を模式的に示す断面図である。
【図１２Ａ】本発明の第７の実施形態における集積型光回路素子の製造方法のあるステップを説明するための模式的な斜視図である。
【図１２Ｂ】本発明の第７の実施形態における集積型光回路素子の製造方法の他のステップを説明するための模式的な斜視図である。
【図１２Ｃ】本発明の第７の実施形態における集積型光回路素子の製造方法の更に他のステップを説明するための模式的な斜視図である。
【図１２Ｄ】本発明の第７の実施形態に従って形成される素子の動作を説明する断面図である。
【図１３Ａ】本発明の第８の実施形態における集積型光回路素子の製造方法のあるステップを説明するための模式的な斜視図である。
【図１３Ｂ】本発明の第８の実施形態における集積型光回路素子の他の製造方法のあるステップを説明するための模式的な斜視図である。
【図１３Ｃ】図１３Ｂに引き続くある製造ステップを説明するための模式的な斜視図である。
【図１４】従来技術におけるある集積型光回路素子の構成を模式的に示す断面図である。
【図１５】従来技術における他の集積型光回路素子の構成を模式的に示す断面図である。
【符号の説明】
１０ 半導体レーザ部
２０ 多モード干渉領域
３０ 光導波路部
４０ 光バッファ部
１００ ＧａＡｓ基板
１０１ 第１光ガイド層
１０２ 光導波層
１０３ 第２光ガイド層
１０４ エッチング停止層
１０５ 第３光ガイド層
１０６ 電極形成層
１０７ 第１クラツド層
１０８ 活性層
１０９ 第２クラヅド層
１１０ エッチング停止層
１１１ 第３クラッド層
１１２ 電極
１１３ 電極
１１４ 埋め込み部
１１５ バッファ導波層
１１６ 薄い境界層
２０１、２０２ 多モード干渉領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated optical circuit element and a manufacturing method thereof, and more particularly, to an optical coupling method between a plurality of optical circuit elements. More specifically, the present invention relates to an integrated optical circuit element in which a semiconductor laser part and an optical waveguide part having different near fields are integrated, and a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in manufacturing an integrated optical circuit element in which a semiconductor laser element (also referred to as a “semiconductor laser part”) and an optical waveguide element (also referred to as an “optical waveguide part”) having different near fields are integrated, A hybrid system is generally used in which the optical waveguide element and the optical waveguide element are combined and then combined. However, in practice, since the alignment accuracy is severe, it is difficult to industrially use the hybrid system.
[0003]
In order to eliminate this difficulty, a method has been proposed in which a semiconductor laser element and an optical waveguide element are integrated on the same substrate.
[0004]
For example, in Japanese Patent Laid-Open No. 63-182882, as schematically shown in FIG. 14, after the active layer 2 and the cladding layer 3 are deposited on the InP substrate 1, the active layer 2 and the cladding layer 3 are formed. A structure is disclosed in which an optical waveguide portion is formed by removing a part by etching and depositing a buffer layer 5, an optical waveguide layer 6, and a protective layer 7 on the removed portion. An electrode 8 is formed on the remaining portions of the active layer 2 and the cladding layer 3 to function as a semiconductor laser portion.
[0005]
On the other hand, on page 88 (February 1990) of Volume 2, Issue 2, of IEEE PHOTOTONICS TECHNOLOGY LETTERS, as schematically shown in FIG. A configuration has been proposed in which a tapered portion 12 whose distribution changes stepwise is provided and the semiconductor laser portion 13 and the optical waveguide portion 11 are integrated.
[0006]
[The linework to be solved by the invention]
However, in the configuration of FIG. 14, there is no structure for confining light in the vertical direction in the region 9 between the active layer 2 and the optical waveguide layer 6. For this reason, radiation of light not directed to the optical waveguide layer 6 is generated in the region 9, and the coupling efficiency to the optical waveguide layer 6 is deteriorated.
[0007]
Furthermore, since the active layer 2 and the optical waveguide layer 6 are formed by separate growth processes, it is difficult to match the heights of the active layer 2 and the optical waveguide layer 6 within the controllability of the crystal growth technique. It is. For example, when the optical waveguide layer 6 is formed using a normal metal organic chemical vapor deposition (MOCVD) technique, the layer thickness and the formation position in the height direction are generally deviated by about 5 to 10% from the set values. In general, it is desirable that the optical waveguide layer be formed to have a thickness of about several μm in consideration of connection with an external element (for example, an optical fiber). At this time, the thickness of the buffer layer provided below the optical waveguide layer is generally several μm. In such a case, a positional deviation of about 0.1 to 0.5 μm occurs in the height direction, and the thickness of the region 9 between the active layer 2 and the optical waveguide layer 6 reaches several μm. The coupling loss due to causes other than the mode mismatch is about 1 dB. In particular, in the case of an optical element having a small light distribution width such as a semiconductor laser, the above-described positional deviation and light emission in a region without a light confinement structure are remarkably generated.
[0008]
On the other hand, in the example shown in FIG. 15, since the semiconductor laser part 13 and the optical waveguide part 11 are connected by the tapered part 12 having a light distribution that changes stepwise, there is almost no light emission between them. Highly efficient optical coupling is expected. However, in order to form the tapered portion 12, it is necessary to perform an etching process and a regrowth process a plurality of times (three or more times in the configuration shown in the drawing). It is difficult to obtain the expected operating characteristics due to a decrease in crystal quality of the portion 12 and the optical waveguide portion 11. For this reason, an example in which the configuration of FIG. 15 has been put to practical use in the industry has not been reported.
[0009]
In the structure of FIG. 15, since the optical waveguide layer of the optical waveguide unit 11 and the active layer of the semiconductor laser unit 13 are formed of the same material, the waveguide loss due to free carrier loss in the optical waveguide unit 11 is achieved. And good characteristics of the optical waveguide portion 11 cannot be expected.
[0010]
The present invention has been made in view of the above-described problems. The object of the present invention is (1) a plurality of optical element portions such as a semiconductor laser and an optical waveguide are manufactured by the same crystal growth process, and It is to provide an integrated optical circuit element having a configuration in which there is no layer that prevents optical coupling between them, and (2) to provide a method for manufacturing such an integrated optical circuit element.
[0011]
[Means for Solving the Problems]
The integrated optical circuit element of the present invention is formed at a position apart from the first optical element part including the first and second element regions stacked in the layer thickness direction, and the first optical element part. A second optical element portion, and a multimode interference region having a buried portion formed in the light propagation direction, which is located between the first optical element portion and the second optical element portion. The first optical element portion and the second optical element portion are optically coupled via the multimode interference region, thereby achieving the above object.
[0012]
The embedding part of the multimode interference region causes the light emitted from the first optical element part to translate while maintaining the light distribution shape at the time of emission from the first optical element part. It is possible to set the length to reach the optical element portion.
[0013]
The width in the direction perpendicular to the light propagation direction of the embedded portion of the multimode interference region may change continuously or stepwise.
[0014]
A thin boundary layer may be formed between the first optical element portion and the multimode interference region.
[0015]
Another integrated optical circuit element of the present invention includes a first optical element unit including first and second element regions stacked in the layer thickness direction and having different light distribution widths, and the first optical element unit. A multimode interference region having a buried portion having a multimode waveguide structure in each of the layer thickness direction and an in-plane direction perpendicular to the layer thickness direction, formed in the propagation direction of light emitted from the optical element portion And a second optical element portion formed at a position away from the first optical element portion via the multimode interference region, and the light emitted from the first optical element portion However, by propagating through the multimode interference region to the second optical element unit, the first optical element unit and the second optical element unit are optically coupled, and thereby, The aforementioned objective is achieved.
[0016]
In the configuration of the integrated optical circuit element, the second optical element unit has a mesa structure that is aligned with the first optical element unit and the embedded portion of the multimode interference region. May be.
[0017]
The embedded portion of the multimode interference region may be configured by stacking two or more subregions.
[0018]
The method for manufacturing an integrated optical circuit element according to the present invention includes a first optical element unit having first and second element regions stacked in a layer thickness direction, and a position away from the first optical element unit. A step of simultaneously forming a second optical element portion to be disposed; and a first step of etching an area between the first optical element portion and the second optical element portion to form an etching groove An etching step and an embedding step for forming an embedding portion of the multimode interference region in the etching groove, whereby the aforementioned object is achieved.
[0019]
In one embodiment, in the first etching step, all of the formation positions of the multimode interference region are etched to form the etching groove, and the embedding step includes the entire etching groove in the multimode interference region. A step of forming a first buried layer by embedding with the constituent material of the buried portion, and removing a predetermined portion of the first buried layer by etching, and a portion corresponding to the buried portion of the multimode interference region The method further includes a second etching step for remaining, and a step of forming a thin film or a second buried layer so as to cover a side portion of the buried portion of the remaining multimode interference region.
[0020]
In one embodiment, in the first etching step, a mesa structure for lateral confinement in the second optical element portion is simultaneously formed.
[0021]
According to another method of manufacturing an integrated optical circuit element of the present invention, there is provided a step of forming a multimode interference region having a buried portion, and etching a predetermined region around the multimode interference region to provide at least two removal regions. At a position sandwiching the embedded portion of the multi-mode interference region, and a first element region and a second element region are stacked in one layer thickness direction on one of the at least two removal regions. Forming one optical element portion and the second optical element portion on the other at the same time, whereby the aforementioned object is achieved.
[0022]
In one embodiment, an etching step for forming the multimode interference region and an etching step for forming a mesa structure for lateral confinement in the second optical element portion are simultaneously performed.
[0023]
In the above manufacturing method, the formation hole of the upper electrode of the first optical element portion and the ridge of the second optical element portion may be simultaneously formed by the same etching process.
[0024]
In the integrated optical circuit element of the present invention having the above-described features, an optical waveguide layer and an active layer of a semiconductor laser part are sequentially stacked on a semiconductor substrate, and then a part thereof is etched to etch the optical waveguide layer. And to a level below the active layer. Next, an embedded portion of the multimode interference region is embedded in the removed region as a layer having a refractive index that becomes a multimode waveguide in the vertical direction. This embedded portion is a narrow-mode multimode interference region.
[0025]
The multimode interference region (more precisely, the buried portion) acts to guide the light emitted from the semiconductor laser part to the optical waveguide part away from the semiconductor laser part, and thereby, the integrated light with high efficiency coupling. A circuit element is obtained. In addition, since the semiconductor laser part and the optical waveguide layer of the optical waveguide part are separated in the vertical direction (layer thickness direction), the optical waveguide part can be produced non-doped, and an optical waveguide part with little light absorption can be produced. realizable.
[0026]
If the length of the multimode interference castle is optimized, the coupling efficiency between optical elements having different light distribution widths in the layer thickness direction can be further improved.
[0027]
When a semiconductor laser element (semiconductor laser part) and an optical waveguide element (optical waveguide part) are used as the optical element part, the light distribution width differs greatly between them, so that the effects of the present invention can be obtained more remarkably.
[0028]
Furthermore, if the multimode interference region is made multistage using the optical buffer layer, further high-efficiency coupling can be realized.
[0029]
If the width of the embedded portion of the multimode interference region is changed continuously or stepwise, optical coupling between optical elements having different light distribution widths in the lateral direction can be performed more efficiently. Further, a smaller effect can be obtained by reducing the rate of change in the light distribution width in the lateral direction in the narrower region.
[0030]
Furthermore, if a multimode interference region that functions as a multimode waveguide is provided in both the layer thickness direction and the lateral direction, optical coupling efficiency that is not affected by the fabrication accuracy of the multimode interference region can be obtained. Further, if the bidirectional multi-mode interference region is multi-staged by using an optical buffer layer, high efficiency can be realized without being affected by manufacturing accuracy.
[0031]
When a semiconductor laser element (semiconductor laser part) is used as the optical element part, an insulating layer is provided between the semiconductor laser element (semiconductor laser part) and the multimode interference region in order to prevent current injection into the multimode interference region. Thus, an integrated optical circuit element that realizes a low threshold operation can be obtained.
[0032]
Furthermore, in the present invention, since all the optical element portions are manufactured by the same process, positioning between the optical elements is easily performed, no height deviation occurs, and the coupling efficiency is in accordance with the process accuracy. Does not deteriorate.
[0033]
In the fabrication of the integrated optical circuit device of the present invention, the formation of the lower electrode of the semiconductor laser portion and the formation of the ridge of the optical waveguide portion can be performed by the same process, thereby simplifying the manufacturing process. Also, the embedding of the mesa side for lateral light confinement in the optical waveguide portion and the embedding of the multimode interference region can be performed in the same process, which also simplifies the manufacturing process.
[0034]
In addition, if the multimode interference region is formed not by embedding the hole portion but by embedding in the groove portion, a multimode interference region having high flatness can be obtained and the characteristics thereof are improved.
[0035]
More preferably, a layer for forming a multimode interference region is laminated on a flat substrate, a part of the layer is left to function as the multimode interference region, and the remaining part is removed by etching, and then a plurality of layers are formed. When the optical element is formed, a multimode interference region having a substantially flat upper surface and lower surface is formed.
[0036]
In the constituent material of the multimode interference region (for example, GaAlAs), if the mixed crystal ratio of aluminum is set to 0.3 or less, good selective embedding can be achieved without causing precipitation of aluminum on the mask. It can function well as a multimode interference region.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of an integrated optical circuit element of the present invention will be described in detail with reference to FIG. Specifically, the integrated light conversion element of the present embodiment is a mode conversion type laser element that includes an AlGaAs semiconductor laser element and converts its emission mode. Below, after explaining a manufacturing method first, the function is demonstrated.
[0038]
Specifically, first, an optical waveguide is formed on an n-type GaAs substrate 100 using a normal MOCVD method._0.22Ga_0.78As first light guide layer 101, n-type Al having a thickness of 2 μm_0.20Ga_0.80As optical waveguide layer 102, n-type Al_0.22Ga_0.78As second light guide layer 103, n-type Al_0.8Ga_0.2As etching stop layer 104 and n-type Al_0.22Ga_0.78The As third light guide layer 105 is sequentially stacked. Thereby, an optical waveguide is formed in both the semiconductor laser unit 10 and the optical waveguide unit 30.
[0039]
Furthermore, in order to form a light emitting part of the semiconductor laser element thereon, an n-type Al_0.7Ga_0.3As first cladding layer 107, 0.1 μm thick i-type GaAs active layer 108, p-type Al_0.7Ga_0.3An As second cladding layer 109, a p-type GaAs etching stop layer 110, and a p-type third cladding layer 111 are sequentially stacked. As a result, the semiconductor laser portion 10 includes the first element region 310 mainly having an optical waveguide effect and the second element region 320 mainly having a light emitting effect in a state of being stacked in the layer thickness direction. become.
[0040]
The thickness of each layer can be changed in the element design. However, in the configuration of this embodiment, the center of the optical waveguide layer 102 is 1.45 μm from the upper surface of the GaAs substrate 100 and the active layer 108 of the semiconductor laser unit 10 is It is designed to be located at a distance of 3.55 μm from the upper surface of the GaAs substrate 100.
[0041]
Next, a method for manufacturing the multimode interference region 20, specifically, the embedded portion 114 will be described. The buried portion 114 of the multimode interference region 20 is a narrowly defined multimode interference region, and is a multimode waveguide 114 having a width of 2 μm and a length of 670 μm formed between the semiconductor laser portion 10 and the optical waveguide portion 30. It is.
[0042]
First, on the surface of the multilayer structure including the layers 101 to 111 formed by the above-described process in a region other than the formation region of the embedded portion 114, SiO 2₂A film (not shown) is patterned. Next, SiO₂In a portion where the film is not formed, vertical etching with a depth of 5 μm is performed using reactive ion beam etching (RIBE). This vertical etching is performed until the n-type GaAs substrate 100 is reached by controlling the etching time. More preferably, the remaining film thickness is monitored during the etching.
[0043]
Thereafter, a second MOCVD growth is performed, and a buried portion 114 is formed of AlGaAs in the multimode interference region 20. At this time, as shown in FIG. 2, a portion having a thickness of 0.25 μm at the bottom and a portion having a thickness of 0.25 μm at the top of the embedded portion 114 are made of_0.20Ga_0.80The As layers 21 and 23 are filled with the remaining 4.5 μm thick parts._0.195Ga_0.805Embed in the As layer 22. Thereby, the embedded portion 114 functions as a single mode waveguide having a width of 2 μm in the horizontal direction and functions as a multimode waveguide having a thickness of 4.5 μm in the vertical direction. If the mixed crystal ratio of aluminum in the material for embedding the embedding portion 114 is 0.3 or less, SiO 2₂Crystal precipitation on the mask hardly occurs.
[0044]
The produced embedded portion 114 has a center line in the height direction positioned approximately in the middle between the active layer 108 and the optical waveguide layer 102.
[0045]
Next, a manufacturing process of the semiconductor laser unit 10 and the optical waveguide unit 30 performed subsequently will be described.
[0046]
First, the previously formed SiO₂The mask is removed using buffered hydrofluoric acid, and then a new SiO 2 film is used to selectively etch only the optical waveguide section 30.₂A mask (not shown) is patterned. Using this mask, the optical waveguide section 30 is etched flatly to the middle of the first cladding layer 107 with a sulfuric acid-based etchant, and then etched directly above the third light guide layer 105 with a hydrofluoric acid-based etchant. Next, a ridge 131 having a width of 2 μm is formed in the extension line direction between the semiconductor laser section 10 and the multimode interference region 20 by etching with an ammonia-based etchant using an appropriate mask pattern. This etching is automatically stopped at the etching stop layer 104. Further, in order to form a ridge 111 having a width of 2 μm in the semiconductor laser portion 10, etching with a hydrofluoric acid-based etchant using a new mask pattern is performed to etch the etching stop layer 110. By this series of etching processes, the ridge 111 of the semiconductor laser unit 10 and the ridge 131 of the optical waveguide unit 30 are formed on a straight line. In this case, the ridge 131 includes the third light guide layer 105.
[0047]
Finally, an upper electrode 112 and a lower electrode 113 are formed on the upper surface of the ridge 111 of the semiconductor laser unit 10 and the back surface of the substrate 100, respectively.
[0048]
A method for designing the embedded portion 114 of the multimode interference region 20 formed as described above will be described below.
[0049]
Considering only the TE mode of the laser beam for simplicity, the oscillation wavelength λ of the laser, the thickness W of the embedded portion 114, and the refractive index n_r, And the refractive index n of the layers positioned above and below the embedded portion 114_cOn the other hand, the length L of the embedded portion 114 is expressed by the following formula 1,
[0050]
[Expression 1]

[0051]
It is represented by
[0052]
At this time, the active layer 108 of the semiconductor laser unit 10 and the optical waveguide layer 102 of the optical waveguide unit 30 are such that the center line of the gap between them is the center line in the height direction from the surface of the substrate 100 of the embedded unit 114. It is installed to match. Further, the interval T between the active layer 108 and the optical waveguide layer 102 is expressed by the following formula 2,
[0053]
[Expression 2]

[0054]
Design as shown in
[0055]
With this structure, light propagating through the multimode interference region 20 (more precisely, the embedded portion 114) moves in parallel from the semiconductor laser portion 10 to the optical waveguide portion 30 as described below.
[0056]
In the configuration of the present embodiment described above, by injecting a current between the electrodes 112 and 113, the semiconductor laser unit 10 causes laser oscillation. The oscillation wavelength at this time is about 850 nm. Light emitted from the active layer 108 of the semiconductor laser unit 10 enters the multimode interference region 20. When propagating in the multimode interference region 20, the transverse mode substantially maintains the light distribution at the time of incidence, but the multimode interference region 20 (more precisely, the embedded portion 114) has a multimode waveguide structure in the vertical direction. Therefore, there are multiple modes in the vertical direction.
[0057]
FIG. 2 schematically shows the light distribution in the A-A ′ cross section of FIG. 1. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here.
[0058]
The vertical light distribution emitted from the semiconductor laser section 10 is about 0.9 μm in total width. In the multimode interference region 20, the incident light is given as the sum of the eigenmodes of the multimode waveguide. However, since the propagation speeds of the individual eigenmodes are different, a multimode interference region having a certain distance is formed. In other words, incident light splits or translates depending on the distance. In the integrated optical coupling element according to the present embodiment, the length L of the multimode interference region 20 is made to be about 670 μm from Equation 1, so that the light emitted from the active layer 108 is incident on the multimode interference region. The light distribution is maintained up to the optical waveguide layer 102. Therefore, in the configuration of the present embodiment, the light distribution of the light emitted from the semiconductor laser unit 10 is incident on the optical waveguide layer 102 of the optical waveguide unit 30 almost as it is. In the optical waveguide section 30, the ridge 131 formed therein gives a refractive index distribution to the optical waveguide section 30, making the optical waveguide characteristics advantageous.
[0059]
The light distribution in the optical waveguide section 30 has a total width of 2.8 μm, and there is radiation loss due to mode mismatch. The optical waveguide 30 is carrier-doped and absorbs light, but this can be suppressed to an extent that there is no problem if the length of the optical waveguide 30 is sufficiently shortened.
[0060]
As described above, in the present embodiment, the optical waveguide layer 102 of the optical waveguide unit 30 and the optical waveguide layer 102 of the semiconductor laser unit 10 are manufactured by the same crystal growth process, so that the position between both optical waveguide layers is increased. A good mode conversion laser element free from loss due to deviation or the like can be obtained. Further, by forming the buried portion 114 of the multimode interference region 20 with AlGaAs having an aluminum mixed crystal ratio of 0.3 or less, good device fabrication can be realized without crystal precipitation on the mask.
[0061]
Note that not only the AlGaAs-based material as described above, but also other semiconductor materials can be used.
[0062]
(Second Embodiment)
A second embodiment of the integrated optical circuit element of the present invention will be described in detail with reference to FIG. Specifically, the integrated optical conversion element of this embodiment is a mode conversion type laser element, and has a configuration suitable for integration of an optical circuit element that realizes optical coupling with low loss.
[0063]
In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals.
[0064]
First, the fabrication method will be described. As in the first embodiment, since an optical waveguide is formed on the GaAs substrate 100 using a normal MOCVD method, Al is used._0.22Ga_0.78As first light guide layer 101, 2 μm thick Al_0.20Ga_0.80As optical waveguide layer 102, Al_0.22Ga_0.78As second light guide layer 103, Al_0.8Ga_0.2As etch stop layer 104 and Al_0.22Ga_0.78The As third light guide layer 105 is sequentially stacked. These layers are formed as non-doped layers. Thereby, an optical waveguide is formed in both the semiconductor laser unit 10 and the optical waveguide unit 30.
[0065]
Next, after the n-type GaAs electrode layer 106 is formed, an n-type Al is formed thereon to form a light emitting portion of the semiconductor laser element._0.7Ga_0.3As first cladding layer 107, 0.1 μm thick i-type GaAs active layer 108, p-type Al_0.7Ga_0.3An As second cladding layer 109, a p-type GaAs etching stop layer 110, and a p-type third cladding layer 111 are sequentially stacked. As a result, the semiconductor laser portion 10 includes the first element region 310 mainly having an optical waveguide effect and the second element region 320 mainly having a light emitting effect in a state of being stacked in the layer thickness direction. become.
[0066]
Next, the multimode interference region 20 is formed by the same manufacturing method as in the first embodiment (the description thereof is omitted here). However, in the present embodiment, the length of the multimode interference region 20 is set to 658 μm.
[0067]
Next, the manufacturing process of the semiconductor laser part 10 and the optical waveguide part 30 performed subsequently will be described.₂A mask (not shown) is patterned, and using this mask, etching is performed to the middle of the first clad layer 107 with a sulfuric acid-based etchant in the optical waveguide section 30, and then etching with a hydrofluoric acid-based etchant is performed. This etching automatically stops at the n-type GaAs electrode formation layer 106. At this time, by using an appropriate mask pattern, in addition to the etching of the optical waveguide portion 30, an etching hole is simultaneously formed at the formation position of the lower electrode 113 of the semiconductor laser portion 10.
[0068]
Thereafter, the ridge 111 of the semiconductor laser unit 10 and the ridge 131 of the optical waveguide unit 30 are formed by the same process as in the first embodiment. In this case, the ridge 131 includes the electrode forming layer 106 and the third light guide layer 105. Finally, the upper electrode 112 and the lower electrode 113 are respectively formed on the upper surface of the ridge 111 of the semiconductor laser unit 10 and the hole formed by the previous etching process.
[0069]
The function of the integrated optical circuit element of this embodiment will be described below.
[0070]
In this element, the refractive indexes and dimensions of the semiconductor laser unit 10 and the optical waveguide unit 30 are the same as those in the first embodiment. In the configuration of this embodiment, since current can be injected from the electrode formation layer 106, laser oscillation can be performed with reduced current loss. Light emitted from the semiconductor laser unit 10 enters the multimode interference region 20 and reaches the optical waveguide unit 30.
[0071]
Similar to the first embodiment, the multimode interference region 20 reproduces the same light distribution as that at the laser emission end face at a position of 670 μm from the interface with the semiconductor laser unit 10. The length of the interference castle 20 (L = 658 μm) is not matched with the above value. This point will be further described with reference to FIGS. 4 (a) and 4 (b). 4A shows the element configuration of the first embodiment described above, and FIG. 4B shows the element configuration of the present embodiment. However, the reference numbers of the individual layers are omitted.
[0072]
In the configuration of the first embodiment shown in FIG. 4A, the length of the multimode interference castle 20 is the active layer of the semiconductor laser unit 10 at the interface between the multimode interference castle 20 and the optical waveguide unit 30. It is made to correspond to the length which can obtain the same light distribution as the 108 output end face. On the other hand, in the configuration of the present embodiment shown in FIG. 4B, instead of setting such a length, the coupling efficiency between the multimode interference castle 20 and the optical waveguide portion 30 is maximized. It is set to such a length. Accordingly, as shown in FIG. 4B, the vertical width of the light distribution at the interface between the multimode interference castle 20 and the optical waveguide portion 30 is the light distribution in the optical waveguide layer 102 of the optical waveguide portion 30. To match the vertical width of. As a result, reduction of the radiation mode due to mode mismatch is realized.
[0073]
The inventors of the present application manufactured several elements in which the length L of the multimode interference region 20 was variously changed, and measured the coupling efficiency between the multimode interference region 20 and the optical waveguide portion 30. . FIG. 5 shows the measurement results. Accordingly, in order to obtain a coupling efficiency of 0.60 or more, the length L of the multimode interference region 20 has an optimum value in a range of about 651 to 663 μm. This is a method that is effective only when the width of the light distribution differs in the vertical direction between the semiconductor laser portion 10 and the optical waveguide portion 30, and is a unique effect only in the present invention.
[0074]
Furthermore, in the element of the present embodiment, light absorption in the optical waveguide portion 30 can be eliminated by making the optical waveguide portion 30 non-doped.
[0075]
Further, by providing the electrode formation layer 106, the distance from the electrode 113 to the active layer 108 is shortened, and current loss can be reduced. The electrode forming layer 106 extends to the upper surface of the ridge 131 of the optical waveguide portion 30, but the light propagating through the optical waveguide layer 102 does not spread to the electrode forming layer 106, so that no large loss is caused. .
[0076]
As described above, in the integrated optical circuit element of the present embodiment, the length of the multimode interference region 20 is adjusted in consideration of the relationship between the actual light distribution and the natural mode of the optical waveguide layer 102. Thus, good optical coupling with suppressed radiation mode is realized. Further, by making the optical waveguide portion 30 non-doped, light absorption in the optical waveguide portion 30 can be eliminated and the length thereof can be increased. This makes it possible to produce a Y-branch optical circuit or the like in the optical waveguide portion 30.
[0077]
(Third embodiment)
A third embodiment of the integrated optical circuit element of the present invention will be described in detail with reference to FIG. Specifically, the integrated light conversion element of this embodiment is a mode conversion laser element, and in addition to the light distribution conversion in the vertical direction in the first and second embodiments, the light distribution conversion in the horizontal direction. Is also realized.
[0078]
6, the same components as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted here. Note that the manufacturing process of the element of this embodiment is basically the same as the process in the second embodiment.
[0079]
In the configuration of this embodiment, the multimode interference region 20 has a depth of 4.75 μm and a length of 200 μm, and the embedded portion 114 has a width of 2 μm at the end surface close to the semiconductor laser portion 10 and an end surface near the optical waveguide portion 30. The thickness is changed to 0.5 μm continuously.
[0080]
Further, as shown in FIG. 6, a thin boundary layer 116 is formed in a direction perpendicular to the traveling direction of the oscillation laser light at the boundary portion between the semiconductor laser unit 10 and the multimode interference region 20. The thin boundary layer 116 is formed at the same time in the etching and filling process for forming the buried portion 114 of the multimode interference region 20.
[0081]
Specifically, this etching is performed so that the n-type first light guide layer 101 remains with a thickness of 0.25 μm. Thereafter, in the second MOCVD process, the thin boundary layer 116 and the entire embedded portion 114 of the multimode interference region 20 are formed into i-type Al._0.15Ga_0.85Embed with As. In the first and second embodiments, the lowermost and uppermost 0.25 μm thick portions of the buried portion 114 of the multimode interference region 20 are made of Al._0.20Ga_0.80Although embedded in As, in this embodiment, as described above, Al_0.15Ga_0.85The whole is uniformly embedded with As.
[0082]
The width of the ridge 131 of the optical waveguide portion 30 is 2 μm in the first and second embodiments, but is 4 μm in this embodiment. The thickness of the third light guide layer 105 is set to be a single mode waveguide with a width of 4 μm. In the case of the present embodiment, since the buried portion 114 of the multimode interference region 20 has an asymmetric confinement structure, the length L of the buried portion 114 and the interval T between the active layer 108 and the optical waveguide layer 102 are expressed by the above formula. Not represented by 1 or Equation 2. The applicants of the present application have examined the optimum structure by computer simulation based on the formulas 1 and 2, and confirmed the effectiveness by actual device fabrication.
[0083]
The function of the integrated optical circuit element of this embodiment will be described.
[0084]
The light emitted from the semiconductor laser unit 10 enters the multimode interference region 20. In the multimode interference region 20, the light guide layer 101 having an aluminum mixed crystal ratio of 0.20 is formed only on the lower side, and a special layer is not formed on the upper side and is in direct contact with air. . Therefore, a multimode waveguide structure having an asymmetric refractive index distribution in the vertical direction can be obtained. If the length of the multi-mode interference region 20 is optimally designed, the light distribution is translated in the vertical direction and the light emitted from the semiconductor laser unit 10 is converted into the optical waveguide unit as in the first and second embodiments. 30 optical waveguide layers 102 are guided. On the other hand, the light distribution in the lateral direction is such that the light protrudes outside the embedding portion 114 as the width of the embedding portion 114 of the multimode interference region 20 becomes continuously narrower, and the light distribution at the end of the multimode interference region 20 The total width is expanded to 5.5 μm and coincides with the lateral light distribution in the optical waveguide section 30.
[0085]
Since the thin boundary layer 116 is formed to be sufficiently thin, it does not contribute to the spread of light in the lateral direction, but the current injected from the electrode 112 flows from the end of the embedded portion 114 of the multimode interference region 20. It has a function as an electrically green layer that prevents leakage from the semiconductor laser portion 10 through the active layer 108 and the first and second cladding layers 107 and 109. The thinner boundary layer 116 is better if it has a thickness that does not affect the spread of light and can block current. Typically, the thickness is set to 0.1 to 10 μm, preferably 5 μm or less, and more preferably 2 μm or less.
[0086]
In the element of this embodiment, lateral optical coupling can be realized with high efficiency only by changing the mask pattern. In the above description, the width of the embedding portion 114 of the multimode interference region 20 is changed so as to be continuously reduced in the traveling direction of the laser beam. However, the same effect can be obtained even if the width is changed stepwise. It is done. The change may be linear or curved. Also, the same effect as described above can be obtained by increasing the thickness of the embedding portion 114 in the multimode interference region 20 continuously or stepwise in the traveling direction of the laser beam.
[0087]
Further, by forming an i-type thin boundary layer 116 between the semiconductor laser unit 10 and the multimode interference region 20, efficient current injection is realized, and a laser oscillation threshold value is reduced.
[0088]
(Fourth embodiment)
A fourth embodiment of the integrated optical circuit element of the present invention will be described in detail with reference to FIG.
[0089]
7, the same components as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted here. Note that the manufacturing process of the element of this embodiment is basically the same as the process in the second embodiment. However, in the configuration of the present embodiment, the width of the embedded portion 114 of the multimode interference region 20 is formed as large as 15 μm. Further, the center line of the ridge 111 of the semiconductor laser section 10 and the center line of the ridge 131 of the optical waveguide section 30 are provided by being shifted by 6.3 μm in the width direction so that the lateral center of the buried section 114 of the multimode interference region 20 is provided. It is designed to be positioned symmetrically with respect to.
[0090]
The function of the integrated optical circuit element of this embodiment will be described.
[0091]
In the first to third embodiments, since the width of the embedded portion 114 of the multimode interference region 20 is as narrow as 0.5 to 2 μm, as schematically shown in FIG. A concave or convex shape may occur at the boundary between the embedded portion 114 and the non-embedded portion, and it may not be flat. In such a case, the eigenmode distribution in the embedding part 114 of the multimode interference region 20 is slightly changed, and the coupling efficiency is deteriorated. On the other hand, in the configuration of the present embodiment, by providing the embedded portion 114 that spreads in the vertical and horizontal directions, the region where light is effectively distributed is embedded flat.
[0092]
FIG. 9 shows the light distribution inside the multimode interference region 20 (more precisely, the embedded portion 114) in the configuration of the present embodiment from the top.
[0093]
Immediately after being emitted from the semiconductor laser unit 10 or immediately before entering the optical waveguide unit 30, the boundary region between the semiconductor laser unit 10 and the multimode interference region 20, and the multimode interference region 20 and the optical waveguide unit are used. It passes through a region 31 that is not flatly embedded and exists in a boundary region between the two. However, since the distance of the region 31 is short, the light distribution is not affected. Compared with the case of FIG. 8, the light in the multimode interference region 20 is not distributed directly below the region 31 that is not flatly embedded, but is distributed only in the region 32 that is flatly embedded. There is no undesirable effect on the distribution.
[0094]
As described above, in this embodiment, the problem that the upper surface of the buried portion 114 is not flattened during crystal growth for forming the buried portion 114 in the multimode interference region 20 is avoided, and the coupling caused by that point is avoided. In addition to preventing a reduction in efficiency, a process for planarizing the embedded portion 114 can be omitted.
[0095]
In the above description, the width of the light distribution in the lateral direction is almost equal between the semiconductor laser unit 10 and the optical waveguide unit 30, but the length of the multimode interference region 20 is optimized even if the widths are not equal. By setting, good optical coupling is realized.
[0096]
(Fifth embodiment)
A fifth embodiment of the integrated optical circuit element of the present invention will be described in detail with reference to FIG. Specifically, the integrated optical conversion element of this embodiment is a mode conversion type laser element.
[0097]
In FIG. 10, the same constituent elements as those in the previous embodiments are denoted by the same reference numerals.
[0098]
First, the fabrication method will be described. As in the first embodiment, since an optical waveguide is formed on the GaAs substrate 100 using a normal MOCVD method, Al is used._{0. twenty two}Ga_0.78As first light guide layer 101, 2 μm thick Al_0.20Ga_0.80As optical waveguide layer 102 and Al_0.22Ga_0.78The As second light guide layer 103 is sequentially stacked. These layers are formed as non-doped layers. Thereby, an optical waveguide is formed in both the semiconductor laser unit 10 and the optical waveguide unit 30.
[0099]
Next, after the n-type GaAs electrode layer 106 is formed, an n-type Al is formed thereon to form a light emitting portion of the semiconductor laser element._0.7Ga_0.3As first cladding layer 107, 0.1 μm thick i-type GaAs active layer 108, p-type Al_0.7Ga_0.3An As second cladding layer 109, a p-type GaAs etching stop layer 110, and a p-type third cladding layer 111 are sequentially stacked. As a result, the semiconductor laser portion 10 includes the first element region 310 mainly having an optical waveguide effect and the second element region 320 mainly having a light emitting effect in a state of being stacked in the layer thickness direction. become.
[0100]
Next, RIBE etching for forming the multimode interference region 20 is performed. At this time, the etching mask pattern also etches both ends 121 of the optical waveguide portion 30, and the ridge of the semiconductor laser portion 10 in the subsequent process. 111 and a mesa structure aligned with the embedded portion 114 of the multimode interference region 20 are set. Preferably, similarly to the second embodiment, an etching hole for forming the lower electrode 113 in the semiconductor laser portion 10 is further formed at the same time.
[0101]
The RIBE etching is performed until reaching the GaAs substrate 100 as in the first embodiment. Thereafter, the obtained etching groove is filled with AlGaAs to form a buried portion 114. In the embedded portion 114, the Al mixed crystal ratio of AlGaAs is 0.29 in the lowermost portion and the uppermost portion of 0.25 μm in thickness, and the Al mixed crystal ratio of AlGaAs is 0.2 in the remaining portion. 24. The mesa structure end portion 121 of the optical waveguide section 30 is also embedded by the same process as the embedded section 114.
[0102]
As shown in FIG. 10, the embedding part 114 of the multimode interference region 20 is set so that the width thereof changes continuously, and the change of the width is made gentle especially in a narrow region. . Thereby, compared with the case where the width | variety of the embedding part 114 changes linearly, even if the length of the multimode interference area | region 20 is the same, mode conversion efficiency improves.
[0103]
The Al mixed crystal ratio of the buried portion 114 in the multimode interference region 20 is set to be higher than the Al mixed crystal ratio of the optical waveguide layer 102. For this reason, lateral light confinement becomes an anti-guide, and there is a loss due to the leaked light wave in this castle, but this loss amount is about 0.1 dB / 100 μm, which is not a problem. In addition, in the optical waveguide part 30, it becomes a guide structure in both the vertical and horizontal directions, and a single mode waveguide is formed.
[0104]
Thus, in this embodiment, highly efficient optical coupling from the semiconductor laser unit 10 to the optical waveguide unit 30 is achieved, and an element that does not require ridge formation in the optical waveguide unit 30 is realized. In addition, when the length of the optical waveguide portion 30 is sufficiently short, the Al mixed crystal ratio of the buried portion 114 of the multimode interference region 20 is set lower than the Al mixed crystal ratio of the optical waveguide layer 102, so that It is also possible to use the waveguide part 30 as an anti-cide. Also in this case, the waveguide loss due to the leaked light wave is about 0.1 dB / 100 μm, which is not a problem.
[0105]
Further, if the embedded portion 114 of the multimode interference region 20 and both end portions 121 of the mesa structure in the optical waveguide portion 30 are embedded with semiconductor materials having different Al mixed crystal ratios, the multimode interference region 20 and the optical waveguide region In any of 30, a guide structure can be realized, and an integrated semiconductor laser element that can be integrated with other optical elements with low loss can be obtained. The present invention is not limited to the lateral light confinement method, and such a structure is also included in the scope of the present invention.
[0106]
(Sixth embodiment)
The sixth embodiment of the integrated optical circuit element of the present invention will be described below. Specifically, the integrated optical conversion element of this embodiment is a mode conversion type laser element.
[0107]
FIG. 11A is a cross-sectional view (corresponding to the line A-A ′ in FIG. 1) through the embedded portion 114 of the multimode interference region 20 of the integrated optical circuit element of this embodiment. The element of the present embodiment can be formed by using a process according to a conventional technique or the processes described in the first to fifth embodiments of the present invention. However, in this embodiment, an optical buffer unit 40 is further provided between the semiconductor laser unit 10 and the optical waveguide unit 30. The multi-mode interference regions 201 and 202 are connected between the optical buffer unit 40 and the semiconductor laser unit 10 and between the optical buffer unit 40 and the optical waveguide unit 30, respectively. In the connection using the multimode interference regions 201 and 202, there is no positional shift between the waveguide layers and the presence of unnecessary layers as in the conventional case, and the coupling efficiency is not deteriorated due to the multistage connection.
[0108]
The effect of the configuration of the present embodiment will be described.
[0109]
The light distribution widths in the semiconductor laser part 10 and the optical waveguide part 30 are respectively represented by w₁And w_ThreeThen, the coupling efficiency η when the optical buffer unit 40 is not provided₁Is approximately the following Equation 3,
[0110]
[Equation 3]

[0111]
It is represented by
[0112]
On the other hand, the coupling efficiency η when the optical buffer unit 40 is provided as in the present embodiment.₂Is the light distribution width in the optical buffer unit 40 w₂Then, the following formula 4,
[0113]
[Expression 4]

[0114]
It is represented by
[0115]
Accordingly, when the light distribution widths of the semiconductor laser unit 10 and the optical waveguide unit 30 are greatly different (w_Three>> w₁) W₂The value of
[0116]
[Equation 5]

[0117]
In this embodiment, the coupling efficiency η represented by Equation 4 is set by₂Is the coupling efficiency η when the optical buffer layer 40 represented by Formula 3 is not provided.₁It is possible to improve it to about twice as much.
[0118]
By providing the optical buffer unit 40 as in the present embodiment, in the configuration including the semiconductor laser unit 10 and the optical waveguide unit 30 having the same light distribution width as in the first embodiment, the coupling efficiency of the optical buffer unit 40 is reduced. It improved about 1.4 times when not having. Thereby, the optical waveguide part 30 can be formed by the same process as that of the semiconductor laser part 10, and good optical coupling is realized without causing deterioration of crystal quality due to regrowth. The effect of this multi-stage connection is obtained by taper connection, and an integrated optical circuit element with higher reliability than in the prior art is realized.
[0119]
FIG. 11B shows a modified element configuration of the present embodiment, in which two multimode interference regions 201 and 202 are produced with the same depth. Also in this case, the same effect as described above can be obtained by optimizing the lengths of the two multimode interference regions 201 and 202. 11B has an advantage that the etching process and the embedding process of the two multimode interference regions 201 and 202 can be performed simultaneously.
[0120]
In the above description, the configuration in which the semiconductor laser unit 10 and the optical waveguide unit 30 are connected in multiple stages using the optical buffer unit 40 has been described. However, the application of the configuration of the present embodiment is not limited to the above. Absent. For example, the present invention can be applied to coupling between optical waveguides having different thicknesses, and such a structure is also included in the present invention.
[0121]
(Seventh embodiment)
Embodiments of the present invention will be described below. Specifically, this embodiment describes a different manufacturing method of the integrated optical conversion element in the first embodiment described above, and the obtained element is improved compared to the case in the first embodiment. It has the characteristics.
[0122]
In the following description, the same components as those in the previous embodiments are denoted by the same reference numerals.
[0123]
First, the manufacturing method will be described. As in the first embodiment, the layers 101 to 105 for forming the optical waveguide are sequentially laminated on the GaAs substrate 100 by using a normal MOCVD method. Thereby, an optical waveguide is formed in both the semiconductor laser unit 10 and the optical waveguide unit 30. Next, layers 107 to 111 for forming a light emitting portion of the semiconductor laser element are sequentially stacked on the stacked structure obtained above.
[0124]
Subsequently, as shown in FIG.₂The mask 117 is patterned on the layer 111 and is used to perform RIBE etching for forming the multimode interference region 20 until the GaAs substrate 100 is reached. The bottom surface of the etching groove obtained by the RIBE etching may be further flattened by performing wet etching or the like after the RIBE etching. Thereafter, selective growth by MOCVD is performed to embed a three-layer AlGaAs growth layer that will form the buried portion 114 (see FIG. 12B) of the multimode interference region 20 in the etching groove obtained by the RIBE etching (see FIG. 12B). However, in FIG. 12B, the layers are not shown separately. The thicknesses and compositions of the three AlGaAs layers constituting the embedded portion 114 are the same as those in the first embodiment.
[0125]
Further, referring to FIG. 12B, SiO 2 is connected to the upper part of the buried AlGaAs layer so that the semiconductor laser part 10 and the optical waveguide part 30 are connected.₂A film pattern 118 is formed. And the previously formed SiO₂Mask 117 and this SiO₂Using the film pattern 118, RIBE etching is performed on the buried AlGaAs layer so that only the portion corresponding to the buried portion 114 of the multimode interference region 20 remains. Thus, a lateral light confinement structure in the multimode interference region 20 is formed as shown in FIG. 12B.
[0126]
Thereafter, ridges 111 and 131 are formed in the semiconductor laser unit 10 and the optical waveguide unit 30 by the same process as in the first embodiment. In order to prevent side etching from being performed on the buried portion 114 of the multimode interference region 20 and the exposed side surface 119 of the semiconductor laser portion 10 and the optical waveguide portion 30 by wet etching at the time of forming the ridge, etching is not performed. Prior to implementation, a protective film (eg SiO 2) covering the exposed surface 119₂The side portion 128 (see FIG. 12C) of the embedded portion 114 may be embedded with an appropriate material such as a semiconductor material or polyimide. However, in the case where such embedding is performed, in order to stabilize the transverse mode in the multimode interference region 20, the embedding is performed depending on the type of material used for embedding the side portion 128 of the embedding portion 114. It is necessary to design the width of the portion 114 appropriately. In this embodiment, a semiconductor material, specifically, Al_0.18Ga_0.82The side part 128 of the embedding part 114 is embedded by As.
[0127]
Finally, the upper electrode 112 is formed on the upper surface of the ridge 111 of the semiconductor laser section 10, and the lower electrode (not shown) is formed on the lower surface of the substrate, thereby obtaining the configuration shown in FIG. 12C.
[0128]
When the selective growth as described above is used, flat embedding is realized in the vicinity of the boundary between the growth region and the non-growth region (masked region) as schematically shown in FIG. 12C or 12D. It is known that the growth layer becomes thicker. However, in the above-described manufacturing process of the present embodiment, when the embedded portion 114 of the multimode interference region 20 is formed, the embedded width in the lateral direction is sufficiently wide. The region that is not limited is limited to the very vicinity of the interface between the semiconductor laser unit 10 or the optical waveguide unit 30 and the multimode interference region 20, and the thickness of the buried portion 114 of the multimode interference region 20 in the lateral direction is substantially reduced. No change occurs.
[0129]
In this case, as shown in FIG. 12D, the light emitted from the semiconductor laser unit 10 is reflected by the upper and lower layers after being emitted to the multimode interference region 20, but this reflection is actually the multimode interference region 20. Occurs in the middle of In the configuration of the present embodiment, since the central portion of the multimode interference region 20 is embedded substantially flat, a desired reflection state is realized, and the light emitted from the semiconductor laser portion 10 is efficiently reflected by the optical waveguide portion. 30.
[0130]
(Eighth embodiment)
The eighth embodiment of the present invention will be described below. Specifically, this embodiment describes a different manufacturing method of the integrated optical conversion element in the first embodiment described above, and the obtained element is improved compared to the case in the first embodiment. It has the characteristics. In the following description, the same components as those in the previous embodiments are denoted by the same reference numerals.
[0131]
As described in relation to the seventh embodiment, if the embedded portion 114 of the multimode interference region 20 is formed flat, the element characteristics are improved. In the present embodiment, a process capable of obtaining the buried portion 114 that is further planarized will be described.
[0132]
First, three AlGaAs layers 21 to 23 are sequentially stacked on the GaAs substrate 100 using a normal MOCVD method. The thickness and composition of each of these three AlGaAs layers 21 to 23 are the same as those in the first embodiment. At this time, the upper surface and the lower surface of the embedded portion 114 of the multimode interference region 20 are flat surfaces.
[0133]
Next, the SiO2 having an appropriate shape is formed so that the length of the multimode interference region 20 (length in the in-plane direction of FIG. 13A) is 658 μm, which is the same as the element configuration in the second embodiment.₂A mask 117 is patterned on the uppermost AlGaAs layer 23. And this SiO₂Using the mask 117, RIBE etching is performed substantially vertically until a portion other than the multimode interference region 20 reaches the GaAs substrate 100.
[0134]
Next, in order to carry out the formation process of the semiconductor laser part 10 and the optical waveguide part 30, SiO surrounding the side surface of the multimode interference region 20 is formed.₂The film 117a is formed by bias sputtering. By this bias sputtering method, which is performed with an optimum bias voltage applied to the substrate 100, SiO 2 by ion irradiation is formed on the bottom surface of the etched region.₂The desorption and formation of the film compete with each other, and SiO₂A film is not substantially formed. Therefore, only the side surface of the multi-mode interference region 20 has SiO 2₂A film 117a is formed.
[0135]
Note that the remaining SiO used in the previous RIBE etching.₂In the bias sputtering process, a similar competition between desorption and formation also occurs with respect to the mask 117, but the thickness tends to decrease. It is preferable to keep it.
[0136]
Next, on the surface of the substrate 100 exposed as described above, layers 101 to 105 for forming optical waveguides similar to those in the first embodiment are sequentially laminated using the MOCVD selective growth method. Thereby, an optical waveguide is formed in both the semiconductor laser unit 10 and the optical waveguide unit 30. Next, the layers 107 to 111 that form the light emitting portion of the semiconductor laser element are sequentially stacked on the stacked structure obtained above. As a result, as in the previous embodiments, the semiconductor laser unit 10 has a first element region 310 mainly having an optical waveguide effect and a second element region 320 mainly having a light emitting effect. It will be included in a stacked state in the direction.
[0137]
In the above selective growth, SiO₂Crystal growth does not occur on the layer 117. As a result, as shown in FIG. 13A, the layers 101 to 105 and 107 to 111 are formed substantially horizontally.
[0138]
Thereafter, as described in the seventh embodiment, for the optical confinement in the lateral direction in the multimode interference region 20, a part of the laminated structure including the three AlGaAs layers 21 to 23 is removed by etching. Then, the portion removed thereby is embedded with a suitable material such as polyimide. Thereafter, the ridge formation process already described is performed to form the final structures of the semiconductor laser portion 10 and the optical waveguide portion 30.
[0139]
According to the manufacturing process of the present embodiment, the AlGaAs layers 21 to 23 constituting the buried layer 114 of the multimode interference region 20 are formed flat on the surface of the flat GaAs substrate 100. Thereby, the characteristics of the multimode interference region 20 are improved.
[0140]
In the above description, the substantially parallel growth layers 107 to 111 are obtained by using the selective growth method in order to form a semiconductor laser device as an integrated optical device. However, when high coupling efficiency is not required in the coupling between the multimode interference region 20 and the integrated optical device, the growth required in another growth process such as a bias sputtering method is used instead of the selective growth method. A layer may be formed.
[0141]
Further, in the above description, the side portion of the embedded portion 114 of the multimode interference region 20 is embedded with polyimide, but instead, it may be embedded with a semiconductor material. In that case, after the formation of the laminated structure of the three AlGaAs layers 21 to 23, a portion around the portion corresponding to the embedded portion 114 of the multimode interference region 20 is illustrated using a mask 117 having an appropriate pattern. It is removed by etching as shown in 13B. Then, the exposed side surface of the buried portion 114 is SiO 2 by bias sputtering.₂A film 117a is formed. Thereafter, as shown in FIG. 13C, final structures of the semiconductor laser part 10 and the optical waveguide part 30 are formed.
[0142]
In this way, the formation of the semiconductor laser part 10 and the optical waveguide part 30 and the embedding of the side part of the embedding part 114 in the multimode interference region 20 can be performed by the same process.
[0143]
【The invention's effect】
According to the present invention, it is possible to achieve an efficient optical coupling between a plurality of optical elements having different light distribution widths in the layer thickness direction, thereby obtaining an integrated optical circuit element that can be integrated. .
[0144]
In addition, by optimally setting the length and width of the multimode interference region, it is possible to reduce the radiation loss related to the mismatch of the longitudinal mode that occurs when coupling from one optical element to another optical element, to convert the transverse mode, In addition, a reduction in coupling loss due to incomplete embedding (incomplete planarization) during fabrication of the multimode interference region is realized. In addition, by forming the buried portion of the multimode interference region with a material having an aluminum mixed crystal ratio of 0.3 or less, a favorable device without the deposition of the buried material on the mask is implemented.
[0145]
Also, the integrated optical circuit element according to the present invention can be formed by a simplified process compared to the conventional element structure. Specifically, it can be manufactured by two MOCVD growths, and the second MOCVD growth only forms a buried portion in a multimode interference region, so that the operation characteristics of the element are affected. There is no reduction in crystal quality due to regrowth.
[0146]
When a semiconductor laser element (semiconductor laser part) and an optical waveguide element (optical waveguide part) are used as an integrated optical element (optical element part), a thin boundary layer is i-type between the multimode interference region and the semiconductor laser part. By embedding with the material, an integrated optical circuit element free from leakage current from the semiconductor laser portion can be obtained. In the present invention, the ridge formation process in the optical waveguide portion can be performed simultaneously with the formation of the lower electrode of the semiconductor laser portion. Furthermore, the formation of the mesa structure of the optical waveguide portion and the etching of the multimode interference region are performed simultaneously, or the formation of the buried portion in the multimode interference region and the embedding of both ends of the mesa structure of the optical waveguide portion are performed simultaneously. It is also possible. By these, the manufacturing process can be simplified and efficient.
[0147]
If the groove shape is formed by etching at the time of forming the multimode interference region, the embedding in the groove portion is performed almost flat with respect to the longitudinal direction of the groove portion, so that the characteristics of the multimode interference region are improved.
[0148]
More preferably, the multimode interference region stack is used as a layer functioning as a light emitting part of a semiconductor laser element (semiconductor laser part) or as an optical waveguide layer of a semiconductor laser element (semiconductor laser part) and an optical waveguide element (optical waveguide part). An integrated optical circuit is formed prior to the stacking of the functional layers, and after that, the semiconductor laser element (semiconductor laser part) and the optical waveguide element (optical waveguide part) are prepared by etching to secure these regions. Get the element. As a result, a multimode interference region with higher flatness is obtained, and the element characteristics are improved.
[0149]
Further, the coupling efficiency can be further improved by adopting a multistage connection configuration provided with a multi-teaching multimode interference region and an optical buffer layer.
[Brief description of the drawings]
FIG. 1 is a perspective view schematically showing a configuration of a mode conversion type semiconductor laser device as an integrated optical circuit device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view for explaining the operation of the element of the first embodiment shown in FIG.
FIG. 3 is a perspective view schematically showing a configuration of a mode conversion type semiconductor laser device as an integrated optical circuit device according to a second embodiment of the present invention.
4A is a cross-sectional view for explaining the operation of the element of the first embodiment shown in FIG. 1, and FIG. 4B is for explaining the operation of the element of the second embodiment shown in FIG. FIG.
FIG. 5 is a diagram for explaining the effect of the second embodiment shown in FIG. 3;
FIG. 6 is a perspective view schematically showing a configuration of a mode conversion type semiconductor laser device as an integrated optical circuit device according to a third embodiment of the present invention.
FIG. 7 is a perspective view schematically showing a configuration of a mode conversion type semiconductor laser device as an integrated optical circuit device according to a fourth embodiment of the present invention.
FIG. 8 is a diagram for explaining a problem related to the configuration of the fourth embodiment shown in FIG. 7;
FIG. 9 is a cross-sectional view illustrating the operation of the element of the fourth embodiment shown in FIG.
FIG. 10 is a perspective view schematically showing a configuration of a mode conversion type semiconductor laser device as an integrated optical circuit device according to a fifth embodiment of the present invention.
FIG. 11A is a cross-sectional view schematically showing a configuration of a mode conversion type semiconductor laser device as an integrated optical circuit device according to a sixth embodiment of the present invention, and FIG. It is sectional drawing which shows the modified structure typically.
FIG. 12A is a schematic perspective view for explaining a step in the method of manufacturing an integrated optical circuit element in the seventh embodiment of the present invention.
FIG. 12B is a schematic perspective view for explaining another step of the method of manufacturing the integrated optical circuit element in the seventh embodiment of the present invention.
FIG. 12C is a schematic perspective view for explaining still another step of the integrated optical circuit device manufacturing method according to the seventh embodiment of the present invention.
FIG. 12D is a cross-sectional view illustrating the operation of an element formed according to the seventh embodiment of the present invention.
FIG. 13A is a schematic perspective view for explaining a step in the method of manufacturing an integrated optical circuit element in the eighth embodiment of the present invention.
FIG. 13B is a schematic perspective view for explaining a step in another method for manufacturing the integrated optical circuit element in the eighth embodiment of the present invention.
FIG. 13C is a schematic perspective view for explaining a manufacturing step subsequent to FIG. 13B.
FIG. 14 is a cross-sectional view schematically showing the configuration of a certain integrated optical circuit element in the prior art.
FIG. 15 is a cross-sectional view schematically showing a configuration of another integrated optical circuit element in the prior art.
[Explanation of symbols]
10 Semiconductor laser section
20 Multimode interference area
30 Optical waveguide
40 Optical buffer
100 GaAs substrate
101 1st light guide layer
102 Optical waveguide layer
103 2nd light guide layer
104 Etching stop layer
105 Third light guide layer
106 Electrode forming layer
107 First cladding layer
108 Active layer
109 Second clad layer
110 Etch stop layer
111 Third cladding layer
112 electrodes
113 electrodes
114 Embedded part
115 Buffer Waveguide Layer
116 Thin boundary layer
201, 202 Multimode interference region

Claims (14)

A single-mode optical waveguide formed by laminating a plurality of semiconductor layers on a substrate in the layer thickness direction;
A semiconductor laser device formed by laminating a plurality of semiconductor layers in the layer thickness direction on the first region of the single mode optical waveguide;
Multimode interference having a buried portion formed on the substrate adjacent to the semiconductor laser portion so that light emitted from the semiconductor laser element is incident and formed so that the incident light propagates in a predetermined direction With areas,
The single mode optical waveguide has a second region facing the first region with the embedded portion interposed therebetween so that light propagated through the embedded portion of the multimode interference region is incident thereon,
Integrated light characterized in that light emitted from the semiconductor laser element is translated and coupled to the second region of the single mode optical waveguide while propagating through the buried portion of the multimode interference region Circuit element.   The embedded portion of the multimode interference region is configured such that the light emitted from the semiconductor laser element is translated while maintaining the light distribution shape at the time of emission from the semiconductor laser element. The integrated optical circuit element according to claim 1, wherein a length of the light propagation direction is set so as to reach two regions.   The buried portion of the multimode interference region has a length in the propagation direction of the light so that light emitted from the semiconductor laser element has a maximum coupling efficiency in the second region of the single mode optical waveguide. The integrated optical circuit element according to claim 1, wherein the integrated optical circuit element is set.   2. The integrated optical circuit element according to claim 1, wherein a width of the multimode interference region in a direction perpendicular to a light propagation direction of the embedded portion changes continuously or stepwise.   The integrated optical circuit element according to claim 1, wherein a thin boundary layer functioning as an electrically insulating layer is formed between the semiconductor laser element and the multimode interference region.   The single mode optical waveguide has a mesa structure aligned in a straight line with respect to the semiconductor laser element and the embedded portion of the multimode interference region. Integrated optical circuit element.   2. The integrated type according to claim 1, wherein the buried portion of the multimode interference region has a multimode waveguide structure in each of a layer thickness direction of the semiconductor laser element and an in-plane direction perpendicular to the layer thickness direction. Optical circuit element.   The embedded portion of the multimode interference region has a lowermost layer and an uppermost layer, and an intermediate layer sandwiched between the lowermost layer and the uppermost layer. Integrated optical circuit element.   2. The integrated light according to claim 1, wherein the embedded portion of the multimode interference region is provided with a buffer layer for propagating light along the light propagation direction at an intermediate portion of the light propagation direction. Circuit element. A method of manufacturing an integrated optical circuit element according to claim 1,
A single mode optical waveguide is formed by laminating a plurality of semiconductor layers on a substrate in the layer thickness direction, and a semiconductor is laminated by laminating a plurality of semiconductor layers on the first region of the single mode optical waveguide Forming a laser element;
Said first region in said single mode optical waveguide, a first etching step of forming the etching groove region between the second region remote from the first region by etching,
A burying step of forming a buried portion of a multimode interference region in the etching groove;
For manufacturing an integrated optical circuit device including: In the first etching step, all the formation portions of the multi-mode interference region are etched to form the etching groove,
The embedding step includes
Filling the entire etching groove with the constituent material of the buried portion of the multimode interference region to form a first buried layer;
A second etching step of removing a predetermined portion of the first buried layer by etching and leaving a portion corresponding to the buried portion of the multimode interference region;
Forming a thin film or a second buried layer so as to cover the side of the buried portion of the remaining multi-mode interference region;
The method for manufacturing an integrated optical circuit element according to claim 10, further comprising: The method of manufacturing an integrated optical circuit element according to claim 10 , wherein in the first etching step, a mesa structure for lateral confinement in the second region of the single mode optical waveguide is simultaneously formed. A method of manufacturing an integrated optical circuit element according to claim 1,
Forming a layer constituting a buried portion of the multimode interference region on the substrate;
Etching a predetermined region of the layer to form the buried portion of the multimode interference region, and forming a first region and a second region with the substrate surface exposed on both sides of the buried portion; ,
A plurality of semiconductor layers are stacked in the thickness direction in each of the first region and the second region to form a single mode optical waveguide, and a plurality of semiconductors are formed on the single mode optical waveguide in the first region . Laminating layers in the layer thickness direction to form a semiconductor laser element;
A method for manufacturing an integrated optical circuit element, comprising: The portion where the lower electrode of the semiconductor laser device is formed on the single mode optical waveguide and the ridge on the single mode optical waveguide in the second region are simultaneously formed by the same etching process. 14. A method for manufacturing an integrated optical circuit element according to any one of items 1 to 13.

Images