JP3777610B2 - Data reproducing apparatus and data reproducing method - Google Patents

Description

  The present invention relates to a data reproduction apparatus and a data reproduction method suitable for use when, for example, video data and audio data recorded by time division multiplexing on an optical disc are reproduced, separated, decoded and output.

  FIG. 31 is a block diagram showing a configuration of an example of a conventional data reproducing apparatus. The drive 1 reproduces data recorded on the built-in optical disk. On this optical disc, video data and audio data are time-division multiplexed and recorded. The reproduction data output from the drive 1 is supplied to the demodulator 2 and demodulated. The ECC circuit 3 performs error detection and correction of data output from the demodulator 2 and supplies the data to the ring buffer 4 and the address extraction circuit 31. The ring buffer 4 accumulates the supplied data in a predetermined amount, and then outputs it to the multiplexed data separator 5.

  The multiplexed data separation device 5 separates video data and audio data from the data supplied from the ring buffer 4, and at the same time, SCR (System Clock Reference) as timing data, video (DTSV), and audio ( The data separation circuit 21 separates the DTS (Decoding Time Stamp) of the DTSA).

  The format of data supplied to the multiplexed data separator 5 is defined as shown in FIG. 32, for example. This format is specified as a multiplexed bit stream of MPEG (ISO 11172). As shown in the figure, the multiplexed bit stream is composed of one or more packs (PACK). Each pack is composed of one or more packets (PACKET). A pack header (PACK HEADER) is arranged at the head of the pack, and a pack start code (PACK START CODE), SCR, and MUX_RATE indicating the start point of the pack are arranged in the pack header. The SCR represents the time when the last byte is input to the multiplexed data separator 5 (the time when demultiplexing is started). MUX_RATE indicates a transfer rate.

  In the example of FIG. 32, a video packet (VIDEO PACKET) and an audio packet (AUDIO PACKET) are sequentially arranged after the pack header. A packet header (PACKET HEADER) is arranged at the head of these packets, and in this packet header, a video packet start code (VIDEO PACKET START CODE) or an audio packet start code (Audio packet start code) indicating the start point of a video or audio packet is placed. AUDIO PACKET START CODE) and DTSV or DTSA indicating the start time of video or audio data decoding. Next to each packet header, video data (VIDEO DATA) or audio data (AUDIO DATA) is arranged.

  The timing data (time information) such as SCR, DTS (DTSV or DTSA) is represented by a count value of a clock having a frequency of 90 kHz, and has 33-bit significant digits.

  The video data separated by the data separation circuit 21 is supplied to the video code buffer 6 (FIFO). The audio data is supplied to the audio code buffer 8 (FIFO). The SCR is supplied to the STC register 26 and stored therein. The STC register 26 counts a clock having a frequency of 90 kHz output from the clock generation circuit 27, increments the stored value, and generates an STC (System Time Clock).

  The DTSV and DTSA separated by the data separation circuit 21 are supplied to and stored in the DTSV register 22 and the DTSA register 24, respectively. The data stored in the DTSV register 22 and the DTSA register 24 are supplied to the comparators 23 and 25, respectively, and compared with the STC output from the STC register 26. The control circuit 28 is constituted by, for example, a CPU and controls the reproduction operation based on a command input from the input unit 29 in response to a user operation. The address storage circuit 30 stores the reproduction start address and reproduction end address input from the input unit 29.

  The video data stored in the video code buffer 6 is read and supplied to the video decoder 7. The video signal decoded and generated by the video decoder 7 is output to a circuit (not shown). The video decoder 7 is supplied with a video decode start signal output from the comparator 23.

  Similarly, data output from the audio code buffer 8 is supplied to the audio decoder 9 and decoded. The audio decoder 9 is supplied with the output of the comparator 25 as an audio decoding start signal.

  Next, the operation will be described with reference to the timing chart of FIG. The input unit 29 is operated to instruct the control circuit 28 to start a reproduction start address, a reproduction end address, and reproduction. The reproduction start address and the reproduction end address are stored in the address storage circuit 30.

  At this time, the control circuit 28 issues a command to the drive 1 to reproduce the data recorded on the optical disk built in the drive 1. The reproduction data output from the drive 1 is supplied to the demodulator 2, demodulated, and then supplied to the ECC circuit 3 for error detection and correction processing.

  The data that has been subjected to error correction by the ECC circuit 3 is supplied to the address extraction circuit 31, and an address arranged at a predetermined position in the data is read and supplied to the control circuit 28. The control circuit 28 waits until the supplied read address matches the reproduction start address obtained from the address storage circuit 30, and generates an accumulation start command for the ring buffer 4 when both addresses match. As a result, the reproduction data output from the drive 1 is accumulated in the ring buffer 4. The data stored in the ring buffer 4 is read from there and supplied to the data separation circuit 21 of the multiplexed data separation device 5.

  The data separation circuit 21 is controlled by the control circuit 28 and separates the video data and the audio data from the data supplied from the ring buffer 4 and supplies them to the video code buffer 6 and the audio code buffer 8, respectively. In addition, SCR, DTSV, and DTSA are separated and supplied to STC register 26, DTSV register 22, and DTSA register 24, respectively, and stored therein.

  The STC register 26 stores the SCR, counts the clock output from the clock generation circuit 27 thereafter, and increments the stored value (SCR) corresponding to the clock. The stored value of the STC register 26 is supplied to the comparators 23 and 25 as the internal time (STC).

  The DTSV register 22 holds the DTSV supplied first after the reproduction is started by the drive 1. This is separated by the data separation circuit 21, supplied to the video code buffer 6, and corresponds to the decoding start time of the data of the first picture among the stored video data.

  Similarly, the DTSA register 24 holds the DTSA supplied first after the reproduction is started. This corresponds to the decoding start time of the first decoding unit of the audio data stored in the audio code buffer 8.

  The SCR corresponds to the time when the data is supplied from the ring buffer 4 to the multiplexed data separator 5 and the demultiplexing is started (the time of the input data at that time). That is, it corresponds to time t1 in the timing chart of FIG. The STC register 26 outputs the time data (current time) from this time t1 to one input of the comparators 23 and 25.

  The DTSV register 22 supplies the time DTSV at which the video decoder 7 starts decoding to the other input of the comparator 23. The comparator 23 outputs a video decode start signal to the video decoder 7 when the current time (STC) output from the STC register 26 coincides with the decode start time output from the DTSV register 22 (at time t2 in FIG. 33). To do. When this video decode start signal is input, the video decoder 7 reads the video data written in the video code buffer 6 for one frame and starts decoding.

  In FIG. 33, a straight line A indicates a state of writing data to the video code buffer 6 (the inclination indicates a write transfer rate), and a broken line B indicates a video decoder from the video code buffer 6. Reference numeral 7 denotes a state of reading data. Therefore, data remains in the video code buffer 6 in the shaded range in the figure. The storage capacity of the video code buffer 6 is represented by the distance between the straight line A and the straight line C in the vertical direction.

  When the video decoder 7 is supplied with the video decode start signal, the video decoder 7 starts decoding. At the time when the decoding is completed, that is, at the timing when the video decode delay (VIDEO_DECODE_DELAY) has elapsed, The video signal is output following this. Accordingly, when the video decoding delay time has elapsed after the start of decoding, the display is started.

  Similarly, the comparator 25 outputs an audio decoding start signal when the current time (STC) output from the STC register 26 matches the decoding start time (DTSA) of the audio data output from the DTSA register 24. When this audio decoding start signal is input, the audio decoder 9 reads data from the audio code buffer 8 by the decoding unit and starts the decoding process. As a result of the decoding process, the generated audio signal is output to a circuit (not shown).

  When the reproducing operation is performed by the drive 1, the address extraction circuit 31 always supplies the address being read to the control circuit 28. The control circuit 28 compares the supplied address of the data being read with the reproduction end address stored in the address storage circuit 30 and ends the reading from the drive 1 when they match.

  Since data remains in the ring buffer 4 and the code buffers 6 and 8, the actual reproduction ends when the data input to the video decoder 7 and the audio decoder 9 is exhausted. When the control circuit 28 detects that there is no more data input to the video decoder 7 and the audio decoder 9, the control circuit 28 ends the reproduction operation.

  Here, it is considered that two arbitrary discontinuous points on an optical disk on which a video signal compressed by the MPEG system is recorded are reproduced continuously. In other words, consider editing the playback operation. FIG. 34 is a timing chart when a predetermined range on the optical disk is continuously reproduced. Here, the dividing points for editing are G, H, and I, and the pictures before and after the points are [a, b], [c, d], and (e, f), respectively.

  In FIG. 34, a straight line D indicates a state of writing data to the video code buffer 6, and a slope indicates a write transfer rate. A broken line E indicates a state in which the video decoder 7 reads data from the video code buffer 6. Therefore, data remains in the video code buffer 6 in the shaded range in the figure. The storage capacity of the video code buffer 6 is represented by the distance between the straight line D and the straight line F in the vertical direction.

  For example, assume that the playback point jumps from point G to point H in FIG. When continuous playback is performed without jumping, picture b is played after picture a, but as a result of jumping, picture d is played after picture a. . Assuming that the time required for the jump from the point G to the point H is 0, the data writing and reading of the video code buffer 6 when such a jump is performed is performed as shown in FIG.

  That is, when no jump is performed at the point G, the picture b and the subsequent picture are written into the video code buffer 6 from time t11, and this writing is performed until time t12. At time t12, the data of the picture b is read from the video code buffer 6, supplied to the video decoder 7, and decoded. The reading of the data of the picture b at time t12 is performed at a time just after the time corresponding to one frame from the reading of the data of the previous picture a.

  Time Tb from time t11 to time t12 is a startup delay of picture b. This startup delay is the time from when picture data is input to the video code buffer 6 until it is decoded. In the MPEG system, image compression processing is performed in accordance with the complexity of the image of each picture. Therefore, the more complex the image, the more data, and the simpler the image, the less data. For this reason, in the MPEG system, the startup delay basically differs for each picture.

  In this example, when the jump is not performed at the point G, the startup delay Tb of the picture b to be reproduced next to the picture a is reproduced next to the picture a as a result of the jump from the point G to the point H. The value is smaller than the startup delay Td of the picture d to be displayed.

  Accordingly, as shown in FIG. 35, the video decoder 7 decodes the data of the picture a written in the video code buffer 6 immediately before the jump at the point G, and then the time for one frame has elapsed since then. At this timing, the data of the next picture b is read from the video code buffer 6 and is to be decoded. However, in this case, since the jump is performed, the writing of the data of the picture d to the video code buffer 6 is started from the time t11.

  Since the start-up delay Td of the picture d is larger than the start-up delay Tb of the picture b, the video decoder 7 reads and decodes the data of the next picture at the time t12 when the time corresponding to the start-up delay Tb of the picture b has elapsed from the time t11. When trying to do so, one frame of data of picture d has not yet been written in the video code buffer 6. As a result, when the video decoder 7 reads data for one frame from the video code buffer 6 at time t12, the video code buffer 6 underflows.

  On the other hand, when jumping from point H to point I in FIG. 34, when no jump is performed at point H, the startup delay Td of picture d reproduced next to picture c jumps from point H to point I. As a result, the startup delay Tf of the picture f reproduced next to the picture c is larger. As a result, as in the case described above, assuming that the time required for the jump is 0, the operation of the video decoder 7 when jumping from point H to point I is as shown in FIG.

  That is, as a result of jumping from point H to point I at time t13, writing of data of picture f to the video code buffer 6 is started from time t13. However, since the start-up delay Tf of this picture f is shorter than the start-up delay Td of the picture d that would have been reproduced if no jump was made at the point H, the data of the picture f is longer than the original start-up delay Tf. Is stored in the video code buffer 6.

  That is, the video decoder 7 receives a time t32 when a time corresponding to one frame has elapsed from the time when the data of the picture c is read (this time corresponds to the time when the startup delay Td of the picture d ends). Until decoding of the data of picture f cannot be started. As a result, the decoding timing of data after the picture f (reading timing from the video code buffer 6) is delayed by the difference (Td-Tf) between the startup delay Td of the picture d and the startup delay Tf of the picture f. Become. As a result, as shown in FIG. 36, data after the picture f may be accumulated, and the video code buffer 6 may overflow.

  In order to prevent the underflow as described above, it is necessary to delay the decoding timing in the video decoder 7 from the time t12 in FIG.

  Similarly, in order to prevent overflow, for example, as shown in FIG. 37, when a jump is made at a point H, the data from the point I is written to the video code buffer 6 and the startup delay of the picture d and the picture f is changed. It is necessary to delay by the difference (Td−Tf).

  However, the conventional apparatus does not have a configuration for adjusting the startup delay before and after the editing point. For this reason, when the editing operation is commanded, all the playback operations are once ended at the playback point where the jump is commanded. Then, the playback operation is started again from the playback point of the jump destination.

  As a result, when jumping from point G to point H, for example, as shown in FIG. 38, the playback operation of the drive 1 is temporarily stopped at point G (time t11). However, since the data of the picture a is already written in the video code buffer 6, the video decoder 7 reads out the data of the picture a at time t41, and decodes and outputs it. Then, after the decoding process of the data of picture a is completed, the control circuit 28 controls the drive 1 again and starts reproduction from the point H (time t42). Thus, data is read from the video code buffer 6 at time t43 when the start-up delay Td of the picture d has elapsed from time t42, and the video decoder 7 performs decoding.

  In the case of jumping from point H to point I, as shown in FIG. 39, when the point H is reached at time t13, all the reproduction operations of the drive 1 are once ended. Then, the video decoder 7 decodes the data already written in the video code buffer 6. This decoding process is completed at time t51.

  As described above, when the decoding of the data already stored in the video code buffer 6 is completed, the drive 1 is controlled again, and reproduction is started from the point I at time t52, and the data is written into the video code buffer 6. It is. Then, decoding of picture f is started at time t53 when the startup delay Tf of picture f has elapsed from time t52.

  In the conventional apparatus, when the reproduction point is moved discontinuously in this way, the reproduction operation is once ended at a predetermined reproduction point, and then the reproduction operation is started again from the reproduction point of the movement destination. . As a result, there is a problem that the time during which reproduction data is lost (the time from time t41 to time t43 in FIG. 38, or the time from time t51 to time t53 in FIG. 39) becomes long.

  The present invention has been made in view of such a situation, and makes it possible to shorten the time during which the reproduction tether is lost even when the reproduction point is moved discontinuously.

According to a first aspect of the present invention, there is provided a data reproducing apparatus for reproducing data recorded on a recording medium, first storage means for storing data reproduced from the recording medium, and reading from the first storage means. Separating means for separating the output data into a plurality of data; second storage means for storing data separated by the separating means; decoding means for decoding data read from the second storage means; When the detecting means for detecting the data storage amount of the second storage means and the reproducing means discontinuously move the reproduction point on the recording medium , the second means corresponding to the data storage amount detected by the detecting means Data amount control means for controlling the storage amount of data stored in the storage means, and when the detection means detects an underflow of the second storage means, the data amount control means decodes the decoding means To stop the work, when the detecting means detects the overflow of the second storage means and stopping the supply of data to the second storage means.

  The data amount control means restarts the decoding operation of the decoder means when the storage amount of the data stored in the second storage means reaches the optimum value after stopping the decoding operation of the decoding means, or After the supply of data to the second storage means is stopped, when the storage amount of the data stored in the second storage means reaches the optimum value, the supply of data to the second storage means is resumed. Can be.

A first data reproduction method of the present invention includes a reproduction step of reproducing data recorded on a recording medium, a first storage step of storing data reproduced from the recording medium in a first storage means, A separation step for separating data read from one storage means into a plurality of data, a second storage step for storing the data separated by the processing of the separation step in the second storage means, and a second storage When the reproduction point on the recording medium is moved discontinuously by the processing of the decoding step for decoding the data read from the means, the detection step for detecting the storage amount of the data in the second storage means, and the reproduction step , corresponding to the storage amount of data detected by the processing of the detection step, and a data amount control step of controlling storage of data stored in the second storage means When the underflow of the second storage means is detected by the detection step processing, the decoding operation by the decoding step processing is stopped by the data amount control step processing, and the second storage means is executed by the detection step processing. If the overflow is detected, the processing of the data amount control step, the supply of data to the second storing means is equal to or that will be stopped.

The second data reproducing apparatus of the present invention includes a reproducing means for reproducing data recorded on a recording medium, a first storage means for storing data reproduced from the recording medium, and a read from the first storage means. Separating means for separating the output data into a plurality of data; second storage means for storing data separated by the separating means; decoding means for decoding data read from the second storage means; When the detecting means for detecting the data storage amount of the second storage means and the reproducing means discontinuously move the reproduction point on the recording medium , the second means corresponding to the data storage amount detected by the detecting means Data amount control means for controlling the storage amount of data stored in the storage means, and when the detection means detects an underflow of the second storage means, the data amount control means decodes the decoding means The work is stopped, when the detecting means detects the overflow of the second memory means and thereby skipping the data output from the second storage means to be decoded subject decoding means.

A second data reproducing method of the present invention includes a reproducing step for reproducing data recorded on a recording medium, a first storing step for storing data reproduced from the recording medium in a first storage means, A separation step for separating data read from one storage means into a plurality of data, a second storage step for storing the data separated by the processing of the separation step in the second storage means, and a second storage When the reproduction point on the recording medium is moved discontinuously by the processing of the decoding step for decoding the data read from the means, the detection step for detecting the storage amount of the data in the second storage means, and the reproduction step , corresponding to the storage amount of data detected by the processing of the detection step, and a data amount control step of controlling storage of data stored in the second storage means When the underflow of the second storage means is detected by the detection step processing, the decoding operation by the decoding step processing is stopped by the data amount control step processing, and the second storage means is executed by the detection step processing. If the overflow is detected, the processing of the data amount control step, data output from the second storage device providing the decoding target of the processing of the decoding step and wherein the that will be skipped.

In the data reproducing apparatus and data reproducing method of the first aspect of the present invention, when the underflow of the second storage means is detected when the reproduction point on the recording medium is moved discontinuously, the decoding operation of the decoding means Is stopped and the supply of data to the second storage means is stopped when overflow of the second storage means is detected.

In the data reproducing apparatus and data reproducing method of the second aspect of the present invention, when the underflow of the second storage means is detected when the reproduction point on the recording medium is moved discontinuously, the decoding operation of the decoding means There is stopped, when the overflow of the second storing means is detected, the decoding means the data to be decoded is skipped.

  According to the data reproducing apparatus and the data reproducing method of the first aspect of the present invention and the data reproducing apparatus and the data reproducing method of the second aspect of the present invention, it is possible to reduce the reproduction data missing period when the data reproduction point is moved discontinuously. Can be shortened.

  FIG. 1 is a block diagram showing the configuration of an embodiment of the data reproducing apparatus of the present invention. The same reference numerals are given to the parts corresponding to those in FIG. In this embodiment, a discontinuous point storage circuit 50 is connected to the control circuit 28. The discontinuous point storage circuit 50 is composed of, for example, a RAM, and can also be used as the address storage circuit 30 by distinguishing addresses for storing data as necessary. Other configurations in FIG. 1 are the same as those in FIG.

  Next, the operation of the embodiment of FIG. 1 will be described with reference to the flowcharts of FIGS. First, in step S1, the input unit 29 is operated to reproduce the reproduction start address, reproduction end address, edit points G and H (or H and I) (these points correspond to the points shown in FIG. ) And start editing. These addresses and edit points are designated as addresses of an optical disk (not shown) driven by the drive 1.

  In step S2, the control circuit 28 supplies the address start circuit, the playback end address, and the edit point address input from the input unit 29 to the address storage circuit 30 for storage. In step S3, the control circuit 28 controls the drive 1 to start a reproduction operation. At this time, the drive 1 irradiates a built-in optical disk (not shown) with laser light, and reproduces data recorded on the optical disk from the reflected light. This reproduced signal is supplied to the demodulator 2. The demodulator 2 demodulates the signal supplied from the drive 1 and supplies the demodulation result to the ECC circuit 3. The ECC circuit 3 detects and corrects an error in the data supplied from the demodulator 2 and outputs it to the ring buffer 4 and the address extraction circuit 31.

  The address extraction circuit 31 extracts an address component from the data input from the ECC circuit 3 and outputs the extraction result to the control circuit 28. The control circuit 28 can know the reproduction point of the drive 1 from the address input from the address extraction circuit 31.

  In step S 4, the control circuit 28 waits until the read address supplied from the address extraction circuit 31 matches the reproduction start address stored in the address storage circuit 30. When both addresses match, that is, when the reproduction point reaches the reproduction start address designated in step S1, the process proceeds to step S5, where the control circuit 28 controls the ring buffer 4 and is supplied from the ECC circuit 3. Start writing data. That is, as a result, data after the reproduction start address designated in step S1 is sequentially written in the ring buffer 4.

  In step S6, the control circuit 28 waits until the read address output from the address extraction circuit 31 matches the address of the editing point (jumping point) G stored in the address storage circuit 30. When the reproduction point reaches the edit point G, the process proceeds to step S7, where the control circuit 28 stops writing data in the ring buffer 4. As a result, the data up to the editing point G is stored in the ring buffer 4. In step S 8, the writing position (writing point) WP at that point in the ring buffer 4 is read out and stored in the discontinuous point storage circuit 50 as a data discontinuous point WPR in the ring buffer 4.

  In step S9, the control circuit 28 controls the drive 1 to jump (discontinuously move) the reproduction point to the edit point (jump destination point) H. That is, the pickup of the drive 1 is jumped from the point G to the point H. The read address output from the address extraction circuit 31 is monitored, and the process waits at step S10 until the read address matches the address of the editing point H stored at step S2. When the addresses match, the process goes to step S11. Then, the writing of data to the ring buffer 4 is resumed. As a result, the data after the edit point H is written to the ring buffer 4 following the data up to the edit point G. As a result, on the ring buffer 4, the data of the edit point G and the edit point H are continuous.

  In this way, the data written in the ring buffer 4 is read out and supplied to the multiplexed data separator 5. During a period in which discontinuous data is stored in the ring buffer 4, the control circuit 28 monitors the reading position (reading point) RP of the ring buffer 4. Then, the process waits in step S12 until the leading point RP matches the discontinuous point WPR stored in step S8. When the leading point RP matches the discontinuous point WPR, the process proceeds to step S13 to read out the ring buffer 4. To cancel.

  That is, data up to the editing point G stored in the ring buffer 4 is read from the ring buffer 4 and input to the data separation circuit 21 to be separated into video data and audio data. The video data is supplied to the video code buffer 6 and the audio data is supplied to the audio code buffer 8. In addition, the data separation circuit 21 separates the DTSV signal, the DTSA signal, and the SCR signal from the input data, and supplies them to the DTSV register 22, the DTSA register 24, and the STC register 26. Each time a new signal is input, the DTSV register 22, the DTSA register 24, and the STC register 26 latch the signal.

  After storing the SCR signal supplied from the data separation circuit 21, the STC register 26 counts the clock output from the clock generation circuit 27, adds it to the stored SCR value, and increments the value. As a result, the STC register 26 outputs an STC signal representing the current time. This STC signal is supplied to the comparator 23 and the comparator 25. The comparator 23 and the comparator 25 compare the current time (STC signal) with the DTSV signal or DTSA signal output from the DTSV register 22 or DTSA register 24, and when they match, the video decode start signal or audio A decode start signal is generated and output to the video decoder 7 or the audio decoder 9.

  When a video decode start signal is input from the comparator 23, the video decoder 7 reads out one frame of video data stored in the video code buffer 6, decodes it, and outputs it to a circuit (not shown). Further, when an audio decode start signal is input, the audio decoder 9 reads out audio data for one unit from the audio code buffer 8, decodes it, and outputs it to a circuit (not shown).

  Actually, since DTS is not added to all frames, a decode start signal is input from the comparator 23 and the comparator 25 to the video decoder 7 and the audio decoder 9, respectively, at every decoding start timing. I don't mean. Therefore, each of the video decoder 7 and the audio decoder 9 has an internal timing generation function, and even when the decoding start signal is not input even when the decoding start time of the next frame comes, the next frame is automatically read. Start decoding.

  As described above, the video signal and the audio signal up to the editing point G are sequentially output from the video decoder 7 and the audio decoder 9.

  In step S13, when reading of the ring buffer 4 is stopped, the process proceeds to step S14, where the control circuit 28 ends the decoding operation of the video decoder 7 and the audio decoder 9, and the video data and audio data up to the editing point G are reached. Wait until the decoding process is completely completed.

  When the decoding process of the video data and the audio data up to the editing point G is completed, the process proceeds to step S15, and the reading process of the ring buffer 4 is started again. As described above, in the ring buffer 4, data up to the point G and data from the point H are continuously stored. Accordingly, since the data can be read immediately from the ring buffer 4 after the decoding in the video decoder 7 and the audio decoder 9 is completed, the time between them can be extremely short. The data after the editing point H read from the ring buffer 4 is decoded and output by the video decoder 7 and the audio decoder 9 in the same manner as described above.

  Next, the process proceeds to step S16, and the control circuit 28 waits until the read address output from the address extraction circuit 31 matches the reproduction end address stored in the address storage circuit 30, and when both addresses match, the control circuit 28 proceeds to step S17. Then, the writing of data to the ring buffer 4 is stopped and the reproduction operation of the drive 1 is stopped. In step S18, all the data in the video code buffer 6 and the audio code buffer 8 are read by the video decoder 7 or the audio decoder 9 and wait until the decoding is completed. When the decoding is completed, the process proceeds to step S19. End the playback operation.

  FIG. 4 and FIG. 5 respectively show the writing of data in the video code buffer 6 when the playback point jumps from point G to point H shown in FIG. 34 or when the playback point jumps from point H to point I. And read.

  As shown in FIG. 4, at time t11, a jump from point G to point H is performed. The data of picture a written up to point G is read from the video code buffer 6 to the video decoder 7 and decoded at time t42. Then, at time t61, writing of data from the point H is started, and at time t62, data of picture d is read from the video code buffer 6 to the video decoder 7 and decoded.

  In FIG. 5, a jump from the point H to the point I is performed at the time t13, and the data written in the video code buffer 6 until the time t13 is read by the video decoder 7 during the period until the time t14. Issued and decoded. At time t71, data from point I is written to the video code buffer 6, and at time t72, data of picture f is read from the video code buffer 6 to the video decoder 7 and decoded.

  As is apparent from comparison between FIGS. 4 and 38 and FIGS. 5 and 39, the operation of the video code buffer 6 in this embodiment is basically the same as in the conventional case. However, as described above, the data up to the point G and the data from the point H, or the data up to the point H and the data from the point I are continuously stored in the ring buffer 4. The period during which data is lost can be shortened compared to the conventional case.

  That is, the time from the time t11 to the time t42 in FIG. 38 or the time from the time t13 to the time t52 in FIG. 39 is temporarily stopped at the point G or the point H in the drive 1, respectively. This is the time required to start the reproduction operation from point H or point I again.

  On the other hand, in the case shown in FIG. 4 or FIG. 5, the operation is merely to jump the pickup from the point G to the point H or from the point H to the point I, and the reproduction operation is not terminated there. Therefore, in the case shown in FIGS. 4 and 5, the time between time t42 and time t61 and the time between time t14 and time t71 are set to the time in FIG. The time between t41 and time t42, or the time between time t51 and time t52 in FIG.

  FIG. 6 shows another embodiment. In this embodiment, the write address and read address of the video code buffer 6 are supplied to the control circuit 28. Other configurations are the same as those in FIG.

  Next, the operation of the embodiment of FIG. 6 will be described with reference to the flowcharts of FIGS. The processes in steps S31 to S42 in FIG. 7 are the same as the processes in steps S1 to S12 shown in FIG. That is, by these processes, the data up to the point G and the data from the point H are continuously written in the ring buffer 4. Then, the discontinuous point storage circuit 50 stores the address WPR of the discontinuous point in the ring buffer 4. Further, when reading data from the ring buffer 4, when the leading point RP reaches the discontinuous point WPR stored in the discontinuous point storage circuit 50, this is detected.

  When it is determined in step S42 that the reading point RP of the ring buffer 4 has reached the discontinuity point WPR, the process proceeds to step S43, and the writing point WPV of the video code buffer 6 at that time is set as the discontinuity point WPVR. The data is stored in the continuous point storage circuit 50.

  The data including the discontinuity is sequentially input and written to the video code buffer 6 from the ring buffer 4 via the data separation circuit 21. During a period in which the discontinuity point WPVR exists in the video code buffer 6, the control circuit 28 monitors the leading point RPV of the video code buffer 6. In step S44, the process waits until the leading point RPV becomes equal to the discontinuous point WPVR stored in step S43.

  If it is determined in step S44 that both addresses are equal, the process proceeds to step S45, where buffer fullness adjustment processing is executed. The details of the buffer fullness adjustment process will be described later with reference to FIGS. 23 and 26. In this step, the adjustment process is performed so that the data storage amount of the video code buffer 6 becomes an appropriate value. Done. As a result, it is possible to further shorten the reproduction data missing period during the jump operation.

  Next, the process proceeds to step S46, and waits until the read address extracted by the address extraction circuit 31 matches the reproduction end address stored in the address storage circuit 30, and when both addresses match, the process proceeds to step S47, where the ring buffer The data writing to 4 and the playback operation of the drive 1 are stopped. Then, the process proceeds to step S48, waiting until the data respectively stored in the video code buffer 6 and the audio code buffer 8 are decoded by the video decoder 7 or the audio decoder 9, and the decoding of these data is completed. Then, the process proceeds to step S49, and the reproduction operation is terminated. The processes in steps S46 to S49 are the same as the processes in steps S16 to S19 in FIG.

  In this embodiment, the data storage amount (buffer fullness) of the video code buffer 6 is investigated and adjusted immediately before the data at the discontinuity point is input to the video decoder 7, so that the discontinuity point is reached. The response can be made even faster.

  FIG. 9 shows still another embodiment. In this embodiment, a DTSV extraction circuit 51 is provided between the video code buffer 6 and the video decoder 7. The DTSV extraction circuit 51 extracts a DTSV signal from the data read from the video code buffer 6 and supplies the extracted result to the control circuit 28.

  Therefore, in this embodiment, the data separation circuit 21 supplies the video data to the video code buffer 6 in a state including the DTSV signal. Specifically, video data is output from the data separation circuit 21 to the video code buffer 6 in a state including a packet header. Since the packet start code (see FIG. 32) in the packet header is unique data in the video data, it can be easily extracted.

  In this embodiment, the DTSV stored in the DTSV register 22 is supplied to the control circuit 28 and stored in the discontinuous point storage circuit 50. Other configurations are the same as those in FIG.

  Next, the operation of the embodiment of FIG. 9 will be described with reference to the flowcharts shown in FIGS. The processing in steps S61 to S72 in FIG. 10 is the same as that in steps S1 to S12 in FIG.

  In step S72, when it is determined that the reading point RP of the ring buffer 4 is equal to the discontinuous point WPR stored in the discontinuous point storage circuit 50, the process proceeds to step S73. The DTSV input to the DTSV register 22 is read and supplied to the discontinuous point storage circuit 50 as DTSVR for storage.

  This DTSVR corresponds to the start time at which the video decoder 7 decodes data including discontinuous points.

  During a period in which discontinuous points exist in the data read from the video code buffer 6, the control circuit 28 monitors the DTSV output from the DTSV extraction circuit 51 and compares it with the DTSVR stored in step S73. In step S74, the process waits until the DTSV matches the DTSVR. When the DTSV matches, it is determined that data including a discontinuous point is input to the video decoder 7.

  In step S75, buffer fullness adjustment processing is executed. In steps S76 to S79, the reproduction process is continued until the reproduction end address is detected. The processes in steps S75 to S79 are the same as the processes in steps S45 to S49 in FIG.

  As described above, in this embodiment, when a discontinuous point is input to the demultiplexer 5, the value of the DTSV separated immediately after that is held as the DTSVR, and the same DTSV as that value is stored. Is detected by the DTSV extraction circuit 51 as a time when the data of the discontinuous point is input to the video decoder 7. For this reason, the missing period of the reproduction data at the time of discontinuous point reproduction can be shortened.

  In the above example, DTS is used as time information. However, the same applies even when a time code or temporal reference defined in MPEG1 video is used.

  FIG. 12 shows still another embodiment. In this embodiment, a DTSV extraction circuit 51 is provided between the video code buffer 6 and the video decoder 7 as in the case of FIG. The output of the DTSV extraction circuit 51 is supplied to the control circuit 28. Each time the video decoder 7 decodes one picture, a picture decode signal is output to the control circuit 28. However, in this embodiment, the output of the DTSV register 22 is not supplied to the control circuit 28. Other configurations are the same as those in FIG.

  Next, the operation of the embodiment of FIG. 12 will be described with reference to FIGS. 13, 14 and the flowchart of FIG. The processes in steps S91 to S104 in FIGS. 13 and 14 are basically the same as the processes in steps S61 to S79 in FIGS. 10 and 11, but the processes in steps S68 and S72 to S75 in FIGS. Is omitted. The process shown in FIG. 15 is always performed in parallel with the processes shown in FIGS. 13 and 14.

  That is, in the processing of FIG. 13 and FIG. 14, when the data after the reproduction start address is written in the ring buffer 4 in step S95 and the jump point G is detected in step S96, the ring is detected in step S97. Writing of data to the buffer 4 is stopped. Then, the storage process of the writing point WP in the ring buffer 4 is not performed, and the process proceeds to step S98, where access to the jump destination point H is immediately executed. When the point H is detected in step S99, the process proceeds to step S100, and writing of data to the ring buffer 4 is resumed from that point. Thereby, the data up to the point G and the data from the point H are continuously stored in the ring buffer 4.

  Next, the process proceeds to step S101 and waits until the read address extracted by the address extraction circuit 31 matches the reproduction end address stored in the address storage circuit 30 in step S92. When both addresses match, the process proceeds to step S102. The writing of data into the ring buffer 4 and the reproduction operation of the drive 1 are stopped. Then, the process proceeds to step S103, waiting for the data stored in the video code buffer 6 and the audio code buffer 8 to be decoded by the video decoder 7 or the audio decoder 9, respectively, and when the decoding of these data is completed. Then, the process proceeds to step S104, and the reproduction operation is terminated.

  As described above, the processing shown in FIG. 15 is performed in parallel during the period in which the operation from the reproduction start address to the reproduction end address is performed.

  First, in step S111, when the DTSV extraction circuit 51 detects DTSV from the data supplied from the video code buffer 6 to the video decoder 7, it outputs this to the control circuit 28. Further, when the video decoder 7 decodes the video data supplied from the video code buffer 6 via the DTSV extraction circuit 51, the video decoder 7 sends the picture decoding signal to the control circuit 28 every time one picture (decoding unit) is decoded. To supply. In step S112, the control circuit 28 counts the number of picture decode signals supplied from the video decoder 7 (of course, the audio data decode unit may be counted).

In step S113, the control circuit 28 obtains the expected value DTSVS of DTSV by calculation as follows.
DTSVS = DTSV + picture cycle × number of picture decode signals
= DTSV + (1 / 29.97Hz) × 90kHz × P
Here, 29.97 Hz is the time for one frame of the NTSC system, and P is the number of picture decode signals.

Further, the control circuit 28 can receive the picture decode signal, measure the time from the last DTSV, and obtain the DTSVS. In other words, when DTSV is received, the elapsed time from the immediately preceding DTSV is measured, and the result obtained by adding the elapsed time to the last DTSV is represented as DTSVS, as shown in the following equation.
DTSVS = (Previous DTSV) + Elapsed time

  In step S114, the newly detected DTSV is compared with the expected value DTSVS of DTSV. When the difference between the two is within the range of a predetermined reference value set in advance, it is determined that the data is continuous, the process returns to step S111, and the subsequent processing is repeatedly executed.

  In step S114, when it is determined that the difference between the DTSV and the expected value DTSVS exceeds the range of the reference value, it can be determined that a data discontinuity point has been detected. Therefore, in this case, the process proceeds to step S115, the buffer fullness adjustment is performed, and then the process returns to step S111 again.

  FIG. 16 shows the relationship between the input DTSV and the expected value DTSVS. In the video decoder 7, the pictures are sequentially decoded as shown by an ellipse in FIG. 16. It is assumed that DTSV is detected at the timings indicated by L, M, and N in the figure.

  The control circuit 28 detects DTSV = 10000 at the point L from the DTSV extraction circuit 51. Since the decoding time (picture cycle) per picture is 3003 (= (1 / 29.97 Hz) × 90 kHz) in the NTSC system, it is detected at point L every time a picture is decoded. The expected value DTSVS changes from DTSV = 10000 to 13003, 16006, 19209,. Since the DTSV detected at the point M is 19009, it is equal to the expected value. On the other hand, since the DTSV detected at the point N is 50000, it is greatly different from the expected value 28018 at that time. Therefore, at this point, it can be determined that the data has changed discontinuously.

  In this way, in the embodiment of FIG. 12, a DTSV discontinuity is detected and used as a data discontinuity. Immediately before the data discontinuity point is input to the video decoder 7, the buffer fullness of the video code buffer 6 is investigated, and the data amount is adjusted so that the discontinuity point can be dealt with quickly. Is possible.

  In the above example, DTS is used as time information. However, the same applies even when a time code or temporal reference defined in MPEG1 video is used.

  FIG. 17 shows still another embodiment. In this embodiment, every time the video decoder 7 decodes one picture, a picture decode signal is output to the control circuit 28, and a signal indicating the type of picture such as an I picture, B picture, P picture, etc. The data is output to the control circuit 28. The SCR separated and output by the data separation circuit 21 is supplied to the STC register 26 and also to the control circuit 28. Other configurations are the same as those in FIG.

  Next, the operation will be described with reference to the flowcharts of FIGS. Also in this embodiment, in steps S121 to S134, the same processing as in steps S91 to S104 of FIGS. 13 and 14 is performed. That is, the data up to the point G and the data from the point H are continuously written in the ring buffer 4 by the processing of steps S121 to S134. The data written to the ring buffer 4 is separated by the data separation circuit 21 and supplied to each circuit. Then, the reproduction is continued until the reproduction end address is detected. When the reproduction end address is detected, the reproduction process is terminated.

  In this way, the process shown in FIG. 20 is executed in parallel with the processes shown in FIGS. First, in step S <b> 141, the control circuit 28 detects the DTSV extracted from the data supplied from the video code buffer 6 to the video decoder 7 by the DTSV extraction circuit 51. Further, the control circuit 28 detects the SCR separated by the data separation circuit 21. In step S142, the DTSV detected in step S141 is compared with the SCR to determine whether or not the data storage amount of the video code buffer 6 is appropriate.

  If the difference between the DTSV and the SCR exceeds the preset reference value, it is determined that the data storage amount (buffer fullness) of the video code buffer 6 needs to be adjusted, and the process proceeds to step S143, where the buffer fullness Adjustment processing is executed. On the other hand, when the difference between DTSV and SCR is within the range of the preset reference value, it is determined that the data storage amount of the video code buffer 6 is appropriate, and the buffer fullness adjustment process is skipped. .

  In the case of this embodiment, it is possible to cope with the case where an error occurs on the data supply side and the supply of data to the video code buffer 6 is delayed. For example, when a vibration (disturbance) is applied to the drive 1 during the reproduction operation and an error that cannot be corrected by the ECC circuit 3 occurs in the reproduction data, the control circuit 28 controls the drive 1 and the same Command to replay the location again. When a command for reproducing the same portion is issued again, the pickup is jumped to a predetermined position, and data at the predetermined position is reproduced again. At this time, supply (writing) of reproduction data to the ring buffer 4 is temporarily interrupted. Moreover, since the decoding in the video decoder 7 is continued as it is, as a result, the amount of data stored in the video code buffer 6 decreases.

  Thereafter, even if the reproduction from the drive 1 is started again and the data supply to the video code buffer 6 is resumed, immediately after that, only a relatively small amount of data is stored in the video code buffer 6.

  In such a case, DTSV (the value is large) of the data read from the video code buffer 6 and supplied to the video decoder 7 to be decoded is separated by the data separation circuit 21 and supplied to the video code buffer 6 from now on. The difference from the SCR (the value is small) included in the data to be processed becomes large. Therefore, in such a case, the amount of data stored in the video code buffer 6 is reduced, so that the data amount is increased to the optimum value by adjusting the buffer fullness.

  The determination process in step S142 in FIG. 20 is a determination as to whether or not the DTSV is smaller than the SCR when the buffer fullness adjustment in step S143 is performed by the maximum rate full buffer method (MRFB method) shown in FIG. can do. If DTSV is smaller than SCR, it can be determined that the buffer fullness of the video code buffer 6 is appropriate.

  In this embodiment, the process shown in FIG. 21 or FIG. 22 may be executed instead of the process shown in FIG.

  In the case of the embodiment shown in FIG. 21, the DTSV extracted by the DTSV extraction circuit 51 is detected in step S151. Further, the control circuit 28 determines from the picture type signal supplied from the video decoder 7 whether the picture decoded by the video decoder 7 is an I picture.

  When it is determined that the picture is an I picture, the process proceeds to step S153 to determine whether or not the difference between DTSV and SCR is within the range of the reference value. When the difference exceeds the reference range, the process proceeds to step S154, and buffer fullness adjustment processing is executed. If it is determined in step S152 that a P picture or B picture other than an I picture has been decoded, and if it is determined in step S153 that the difference between DTSV and SCR is within the reference value range, the buffer full The process returns to step S151 without executing the tone adjustment process.

  That is, in this embodiment, when the DTSV is detected and the decoded picture is an I picture, the buffer fullness adjustment is executed. In the MPEG system, I pictures are inserted at a constant period (one for one group of pictures). Therefore, in this embodiment, the buffer fullness adjustment is performed at a predetermined cycle.

  In the embodiment of FIG. 22, in steps S161 to S164, basically the same processing as in steps S151 to S154 in FIG. 21 is performed, but the determination processing in step S162 is performed in step S152. It is different from the judgment process. That is, in step S152, it is determined whether or not it is an I picture, but in step S162, it is determined whether or not DTSV has been detected ten times. Other processes are the same as those in FIG.

  Therefore, in this embodiment, buffer fullness adjustment is performed every time DTSV is detected ten times.

  As described above, in the embodiment shown in FIGS. 17 to 22, the buffer fullness adjustment is periodically performed regardless of the editing point, as in the case of the embodiment shown in FIGS. Therefore, on the data consuming side, that is, on the video decoder 7 and audio decoder 9 side, the operation can be performed without being aware of the editing point, and the cost of the system can be reduced. Further, even when a trouble occurs on the data supply side and the data supply is interrupted, it is possible to shorten the period during which the reproduction data is lost.

  Next, examples of the buffer fullness adjustment process shown in step S45 of FIG. 8, step S75 of FIG. 11, step S115 of FIG. 15, step S143 of FIG. 20, step S154 of FIG. 21, and step S164 of FIG. Will be described. FIG. 23 shows a first embodiment of the buffer fullness adjustment process. For example, when this buffer fullness adjustment process is performed in the embodiment of FIG. 12, the SCR signal separated and output by the data separation circuit 21 is supplied to the control circuit 28 as shown in FIG. To do.

  When this buffer fullness adjustment process is performed, for example, in step S114 of FIG. 15, DTSV discontinuity is detected. Therefore, first, in step S201, the decoding operations of the video decoder 7 and the audio decoder 9 are stopped. In step S202, the DTSV extracted by the DTSV extraction circuit 51 is compared with the SCR separated by the data separation circuit 21. If the DTSV is larger than the SCR, it is determined that sufficient data is not yet stored in the video code buffer 6 or the audio code buffer 8, and the process returns to step S201 to stop the decoding operations of the video decoder 7 and the audio decoder 9. Keep it.

  If it is determined in step S202 that the SCR has become larger than DTSV, it is determined that appropriate data has been stored in the video code buffer 6 and the audio code buffer 8, and the process proceeds to step S203, where the video decoder 7 and the audio decoder 9 Resume decoding.

  The above processing will be further described with reference to FIG. 25 as follows. That is, it is assumed that a jump is now made from point G to point H. At time t81, writing of data after point H to the video code buffer 6 is started. The DTSV of the picture d written in the video code buffer 6 in this way corresponds to the time t83 when the video decoder 7 starts decoding.

  On the other hand, since the SCR corresponds to the time of the timing input from the ring buffer 4 to the data separation circuit 21 and hence to the video code buffer 6, the input until the time near the time t83 is reached. The SCR representing the time corresponding to the timing is smaller than the DTSV representing the decoding start time. In this case, the control device 28 determines that sufficient data is not stored in the video code buffer 6, and prohibits the video decoder 7 from performing a decoding operation.

  When the time is near or later than time t83, the SCR value is equal to or greater than the DTSV of picture d. At this time, the control circuit 28 determines that sufficient data has been stored in the video code buffer 6 and causes the video decoder 7 to resume the decoding operation.

  FIG. 26 shows a second embodiment of the buffer fullness adjustment process. In order to realize this embodiment, for example, as shown in FIG. 27 described later, a buffer fullness signal indicating the data accumulation amount of the video code buffer 6 is supplied to the control circuit 28.

  In step S221, the decoding operations of the video decoder 7 and the audio decoder 9 are stopped. Next, proceeding to step S222, it is determined whether or not the buffer fullness signal of the video code buffer 6 or the audio code buffer 8 indicates data full (a state in which the data is stored to the full capacity). If the data full is not indicated, the process returns to step S221 to keep the decoding operation stopped. In step S222, when the buffer fullness signals output from the video code buffer 6 and the audio code buffer 8 indicate data full, the process proceeds to step S223, and the decoding operation stopped in step S221 is resumed again.

  FIG. 27 shows still another embodiment of the data reproducing apparatus of the present invention. In this embodiment, a buffer fullness signal indicating whether or not these buffers have overflowed or underflowed is supplied from the video code buffer 6 and the audio code buffer 8 to the control circuit 28. Other configurations are the same as those in FIG.

  Next, the operation will be described with reference to the flowcharts of FIGS. The processes in steps S241 to S254 in FIGS. 28 and 29 are the same as the processes in steps S91 to S104 shown in FIGS. That is, by the processing from step S241 to S254, the data up to the point G before the jump and the data from the point H as the jump destination are successively written in the ring buffer 4. Then, reproduction is performed up to the reproduction end address.

  In parallel with the processing of FIGS. 28 and 29, the processing shown in FIG. 30 is executed. First, in step S <b> 261, the control circuit 28 acquires buffer fullness information from the video code buffer 6 and the audio code buffer 8. Then, in steps S262 and S266, it is determined whether or not these buffers are underflowing or overflowing.

  If it is determined in step S262 that an underflow has occurred, the process proceeds to step S263, where the video decoder 7 and the audio decoder 9 stop the decoding process. In step S264, the buffer fullness signals of the video code buffer 6 and the audio code buffer 8 are monitored, and the process waits until it is determined that the data accumulation amounts of the video code buffer 6 and the audio code buffer 8 have become optimum values. When it is determined that the data storage amount has reached the optimum value, the process proceeds to step S265, and the video decoder 7 and the audio decoder 9 are made to restart the decoding operation.

  On the other hand, when it is determined in step S266 that an overflow has occurred, the process proceeds to step S267, where the ring buffer 4 is controlled and the supply of data to the video code buffer 6 is stopped. Since the decoding operation by the video decoder 7 or the audio decoder 9 is continued as it is, the amount of data stored in the video code buffer 6 or the audio code buffer 8 gradually decreases. Therefore, the process proceeds to step S268 and waits until the data accumulation amount of the video code buffer 6 or the audio code buffer 8 reaches an optimum value. When the optimum value is reached, the process proceeds to step S269, and the data supply from the ring buffer 4 is performed. Is resumed again.

  If an overflow is detected, the video decoder 7 or audio decoder 9 is made to skip data to be decoded instead of stopping the data supply to the video code buffer 6 or the audio code buffer 8 in step S267. It is also possible.

  When neither underflow nor overflow is detected in step S262 and step S266, when the decoding operation is resumed in step S265, and when the data supply operation is resumed in step S269, the process returns to step S261, and the above-described processing repeat.

  As described above, in this embodiment, the amount of data stored in the video code buffer 6 and the audio code buffer 8 is constantly monitored, and when either one of them underflows or overflows, the data storage amount is reduced. Since the adjustment is made, it is possible to shorten the reproduction data missing period during the jump.

  In each of the above embodiments, the optical disk is reproduced in the drive 1 to obtain the reproduced data. However, the present invention can also be applied to the case where the data is reproduced from the solid-state memory. is there.

It is a block diagram which shows the structure of one Example of the data reproduction apparatus of this invention. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart following FIG. It is a figure explaining operation | movement of the video code buffer 6 of FIG. It is a figure explaining operation | movement of the video code buffer 6 of FIG. It is a block diagram which shows the structure of the other Example of the data reproduction apparatus of this invention. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart following FIG. It is a block diagram which shows the structure of the other Example of the data reproduction apparatus of this invention. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart following FIG. It is a block diagram which shows the structure of the other Example of the data reproduction apparatus of this invention. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart following FIG. It is a flowchart explaining the operation | movement of the Example of FIG. 13 is a timing chart for explaining the operation of the embodiment of FIG. It is a block diagram which shows the structure of the other Example of the data reproduction apparatus of this invention. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart following FIG. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart explaining a buffer fullness adjustment process. FIG. 24 is a block diagram illustrating a configuration of a data reproduction device that executes the process of FIG. 23. It is a timing chart explaining operation | movement of the video code buffer 6 of FIG. It is a flowchart which shows the 2nd Example of a buffer fullness adjustment process. It is a block diagram which shows the structure of the further another Example of the data reproduction apparatus of this invention. It is a flowchart explaining the operation | movement of the Example of FIG. It is a flowchart following FIG. It is a flowchart explaining the operation | movement of the Example of FIG. It is a block diagram which shows the structure of the conventional data reproduction apparatus. It is a figure explaining the data format of an MPEG system. 32 is a timing chart for explaining the operation of the video code buffer 6 of FIG. 31. 32 is a timing chart for explaining the operation of the video code buffer 6 of FIG. 31. 32 is a timing chart for explaining the operation of the video code buffer 6 of FIG. 31. 32 is a timing chart for explaining the operation of the video code buffer 6 of FIG. 31. 32 is a timing chart for explaining the operation of the video code buffer 6 of FIG. 31. 32 is a timing chart for explaining the operation of the video code buffer 6 of FIG. 31. 32 is a timing chart for explaining the operation of the video code buffer 6 of FIG. 31.

Explanation of symbols

1 drive, 2 demodulator, 3 ECC circuit, 4 ring buffer, 5 multiplexed data separator, 6 video code buffer, 7 video decoder, 8 audio code buffer, 9 audio decoder, 21 data separator, 22 DTSV register, 23 Comparator, 24 DTSA register, 25 comparator, 26 STC register, 27 clock generation circuit, 28 control circuit, 29 input unit, 30 address storage circuit, 50 discontinuous point storage circuit, 51 DTSV extraction circuit

Claims (5)

Reproducing means for reproducing data recorded on the recording medium;
First storage means for storing data reproduced from the recording medium;
Separating means for separating data read from the first storage means into a plurality of data;
Second storage means for storing data separated by the separation means;
Decoding means for decoding data read from the second storage means;
Detection means for detecting the amount of data stored in the second storage means;
When the reproduction means discontinuously moves the reproduction point on the recording medium, the storage amount of data stored in the second storage means is controlled in accordance with the storage amount of data detected by the detection means. Data amount control means for
The data amount control means stops the decoding operation of the decoding means when the detection means detects an underflow of the second storage means, and the detection means detects an overflow of the second storage means In this case, the data reproduction apparatus is characterized in that the supply of data to the second storage means is stopped. The data amount control means includes:
After the decoding operation of the decoding means is stopped, when the storage amount of data stored in the second storage means reaches an optimum value, the decoding operation of the decoder means is resumed,
Alternatively, when the amount of data stored in the second storage means reaches an optimum value after stopping the supply of data to the second storage means, the data to the second storage means The data reproducing apparatus according to claim 1, wherein the supply of data is resumed. A reproduction step of reproducing data recorded on the recording medium;
A first storage step of storing data reproduced from the recording medium in a first storage means;
A separation step of separating data read from the first storage means into a plurality of data;
A second storage step of storing the data separated by the process of the separation step in a second storage means;
A decoding step of decoding data read from the second storage means;
A detection step of detecting a data storage amount of the second storage means;
When the reproduction point on the recording medium is moved discontinuously by the process of the reproduction step, the reproduction point is stored in the second storage unit corresponding to the storage amount of the data detected by the process of the detection step. A data amount control step for controlling the storage amount of data, and
When an underflow of the second storage means is detected by the processing of the detection step, the decoding operation by the processing of the decoding step is stopped by the processing of the data amount control step, and the first operation is performed by the processing of the detection step. If an overflow of the second storage means is detected by the processing of the data amount control step, the data reproducing method of supplying the data to said second storage means and wherein the that will be stopped. Reproducing means for reproducing data recorded on the recording medium;
First storage means for storing data reproduced from the recording medium;
Separating means for separating data read from the first storage means into a plurality of data;
Second storage means for storing data separated by the separation means;
Decoding means for decoding data read from the second storage means;
Detection means for detecting the amount of data stored in the second storage means;
When the reproduction means discontinuously moves the reproduction point on the recording medium, the storage amount of data stored in the second storage means is controlled in accordance with the storage amount of data detected by the detection means. Data amount control means for
The data amount control means stops the decoding operation of the decoding means when the detection means detects an underflow of the second storage means, and the detection means detects an overflow of the second storage means case, the data reproducing apparatus, characterized in that to skip the data output from the second storage device providing the decoding target of the decoding means. A reproduction step of reproducing data recorded on the recording medium;
A first storage step of storing data reproduced from the recording medium in a first storage means;
A separation step of separating data read from the first storage means into a plurality of data;
A second storage step of storing the data separated by the process of the separation step in a second storage means;
A decoding step of decoding data read from the second storage means;
A detection step of detecting a data storage amount of the second storage means;
When the reproduction point on the recording medium is moved discontinuously by the process of the reproduction step, the reproduction point is stored in the second storage unit corresponding to the data storage amount detected by the process of the detection step. A data amount control step for controlling the amount of data stored, and
When an underflow of the second storage means is detected by the processing of the detection step, the decoding operation by the processing of the decoding step is stopped by the processing of the data amount control step, and the first operation is performed by the processing of the detection step. If an overflow of the second storage means is detected, and wherein the processing of the data amount control step, Ru is data skipped output from the second storage device providing the decoding target of the processing of the decoding step Data playback method.

Images