JP3692356B2 - Multiplexed data separation apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multiplexed data separation apparatus and method, for example, a multiplexed data separation apparatus and method suitable for use in reproducing and separating video data and audio data recorded by time division multiplexing on an optical disc, for example. About.
[0002]
[Prior art]
FIG. 5 is a block diagram showing a configuration of an example of a conventional multiplexed data separator. The drive 1 reproduces data recorded on the built-in optical disk. On this optical disc, video data and audio data are time-division multiplexed and recorded. The reproduction data output from the drive 1 is supplied to the demodulator 2 and demodulated. The ECC circuit 3 performs error detection and correction on the data output from the demodulator 2 and supplies it to the ring buffer 4. The ring buffer 4 accumulates the supplied data in a predetermined amount, and then outputs it to the multiplexed data separator 5.
[0003]
The multiplexed data separation device 5 separates video data and audio data from the data supplied from the ring buffer 4, and at the same time, SCR (System Clock Reference) as timing data, video (DTSV), and audio ( The data separation circuit 21 separates the DTS (Decoding Time Stamp) of the DTSA).
[0004]
The format of data supplied to the multiplexed data separator 5 is defined as shown in FIG. 6, for example. This format is specified as a multiplexed bit stream of MPEG (ISO 11172). As shown in the figure, the multiplexed bit stream is composed of one or more packs (PACK). Each pack is composed of one or more packets (PACKET). A pack header (PACK HEADER) is arranged at the head of the pack, and a pack start code (PACK START CODE), SCR, and MUX_RATE indicating the start point of the pack are arranged in the pack header. The SCR represents the time when the last byte is input to the multiplexed data separator 5 (the time when demultiplexing is started). MUX_RATE indicates a transfer rate.
[0005]
In the example of FIG. 6, a video packet (VIDEO PACKET) and an audio packet (AUDIO PACKET) are arranged next to the pack header. A packet header is arranged at the head of these packets. The packet header includes a video packet start code (VIDEO PACKET START CODE) or an audio packet start code (AUDIO PACKET START CODE) indicating a start point of a video or audio packet. DTSV or DTSA indicating the start time of video or audio data decoding is arranged. Next to each packet header, video data or audio data is arranged. However, since the video data has a larger data amount per unit time than the audio data, the DTSV is arranged at a rate of once in a plurality of packs.
[0006]
The timing data such as SCR and DTS (DTSV or DTSA) is represented by a count value of a clock having a frequency of 90 kHz, and has 33-bit significant digits.
[0007]
The video data is supplied to the video code buffer 6 (FIFO). The audio data is supplied to the audio code buffer 8 (FIFO). The SCR is supplied to the STC register 26 and stored therein. The STC register 26 counts the clock with a frequency of 90 kHz output from the clock generation circuit 27 and increments the stored value to generate an STC (System Time Clock).
[0008]
DTSV and DTSA are supplied to and stored in the DTSV register 22 and the DTSA register 24, respectively. The data stored in the DTSV register 22 and the DTSA register 24 are supplied to the comparators 23 and 25, respectively, and compared with the STC output from the STC register 26. The control circuit 28 is constituted by a CPU, for example, and controls the data separation circuit 21 based on a command input from the input unit 29 in response to a user operation.
[0009]
The video data stored in the video code buffer 6 is read and supplied to the video decoder 7. The video signal decoded and generated by the video decoder 7 is output to a circuit (not shown). The video decoder 7 is supplied with a video decode start signal output from the comparator 23.
[0010]
Similarly, the data output from the audio code buffer 8 is supplied to the audio decoder 9 and decoded. The audio decoder 9 is supplied with the output of the comparator 25 as an audio decoding start signal.
[0011]
Next, the operation will be described with reference to the timing chart of FIG. The input unit 29 is operated to instruct the control circuit 28 to start reproduction. The control circuit 28 issues a command to the drive 1 to reproduce the data recorded on the optical disk built in the drive 1. The reproduced data output from the drive 1 is supplied to the demodulator 2 and demodulated, and then supplied to the ECC circuit 3 for error detection and correction. The data subjected to this processing is supplied to the data separation circuit 21 of the multiplexed data separation device 5 via the ring buffer 4.
[0012]
The data separation circuit 21 is controlled by the control circuit 28 and separates the video data and the audio data from the data supplied from the ring buffer 4 and supplies them to the video code buffer 6 and the audio code buffer 8, respectively. In addition, SCR, DTSV, and DTSA are separated and supplied to STC register 26, DTSV register 22, and DTSA register 24, respectively, and stored therein.
[0013]
The STC register 26 stores the SCR, counts the clock output from the clock generation circuit 27 thereafter, and increments the stored value corresponding to the clock. The stored value of the STC register 26 is supplied to the comparators 23 and 25 as the internal time (STC).
[0014]
The DTSV register 22 holds the DTSV supplied first after the reproduction is started by the drive 1. As a result, the decoding start time for the first picture of the data stored in the video code buffer 6 is obtained.
[0015]
Similarly, the DTSA register 24 holds the DTSA supplied first after the reproduction is started. As a result, of the data stored in the audio code buffer 8, it has a decoding start time for the first decoding unit.
[0016]
The SCR corresponds to the time when data is supplied from the ring buffer 4 to the multiplexed data separator 5 and demultiplexing is started. That is, it corresponds to time t1 in the timing chart of FIG. The STC register 26 outputs the time data (current time) from this time t1 to one input of the comparators 23 and 25.
[0017]
The DTSV register 22 supplies the time DTSV at which the video decoder 7 starts decoding to the other input of the comparator 23. The comparator 23 outputs a video decode start signal to the video decoder 7 when the current time output from the STC register 26 coincides with the decode start time output from the DTSV register 22 (at time t2 in FIG. 7). When this video decode start signal is input, the video decoder 7 reads out one frame of video data written in the video code buffer 6 and starts decoding.
[0018]
In FIG. 7, a straight line A indicates a state of writing data to the video code buffer 6 (the inclination indicates a write transfer rate), and a broken line B indicates that the video decoder 7 is connected to the video code buffer 6. It shows the state of reading data. Therefore, data remains in the video code buffer 6 in the shaded range in the figure. The storage capacity of the video code buffer 6 is represented by the distance between the straight line A and the straight line C in the vertical direction.
[0019]
The video decoder 7 starts decoding when the video decode start signal is supplied, and generates a video vertical synchronization signal when the decoding is completed, that is, at the timing when the video decode delay (VIDEO_DECODE_DELAY) has elapsed after the start of decoding. Subsequently, a video signal is output. That is, the display is started after the video decoding delay time has elapsed after the start of decoding.
[0020]
Similarly, the comparator 25 outputs an audio decoding start signal when the current time output from the STC register 26 coincides with the decoding start time of the audio data output from the DTSA register 24. When this audio decoding start signal is input, the audio decoder 9 reads data from the audio code buffer 8 and starts decoding processing. As a result of the decoding process, the generated audio signal is output to a circuit (not shown).
[0021]
The above is the operation when the transfer rate is a fixed rate. FIG. 8 shows a timing chart when the variable rate is adopted. Before the time t3 and after the time t6, the high rate mode of 8 Mbps is set, and the low rate mode of 2 Mbps is set between the times t3 and t6. This transfer rate is specified on the encoder (not shown) side when encoding data.
[0022]
In FIG. 8, a broken line D indicates a state of writing data to the video code buffer 6, and a slope indicates a transfer rate. A broken line F indicates a state in which the video decoder 7 reads data from the video code buffer 6. Therefore, data remains in the video code buffer 6 in the shaded range in the figure. The storage capacity of the video code buffer 6 is represented by the distance between the straight line D and the straight line E in the vertical direction.
[0023]
Here, attention is focused on the picture W in the lower diagram of FIG. 8 (a diagram showing an enlarged view from time t3 to time t4). The time when the data of the picture W starts to be loaded into the video code buffer 6 is t4. That is, the SCR attached to the pack in which the head portion (G) of the data of the picture W is stored indicates t4. Further, the decoding start time of the picture W is t5, and the DTSV attached to the packet in which the head portion of the picture W is stored indicates t5.
[0024]
The input unit 29 is operated to instruct the control circuit 28 to start reproduction from the picture W. The control circuit 28 issues a command to the drive 1, accesses a predetermined position of the optical disk built in the drive 1, and reproduces recorded data. The reproduced data output from the drive 1 is supplied to the demodulator 2 and demodulated, and then supplied to the ECC circuit 3 for error detection and correction. The data subjected to this processing is supplied to the data separation circuit 21 of the multiplexed data separation device 5 via the ring buffer 4.
[0025]
MUX_RATE is arranged at the head of each pack, and the transfer rate of the corresponding pack can be known by referring to this data. For example, the data separation circuit 21 controls the data transfer rate based on this value. Further, control of variable rate data is described in, for example, GB 2 259 229 A (Date of publication 03.03.1993).
[0026]
The data separation circuit 21 is controlled by the control circuit 28 and separates the video data from the data supplied from the ring buffer 4 and supplies it to the video code buffer 6. Further, the SCR and DTSV are separated and supplied to the STC register 26 and the DTSV register 22 for storage. The explanation regarding the audio system is the same as that described above, and is omitted here.
[0027]
The STC register 26 stores the SCR, thereafter counts the clock output from the clock generation circuit 27, and increments the stored value corresponding to the clock. The stored value of the STC register 26 is supplied to the comparators 23 and 25 as the internal time (STC).
[0028]
The SCR corresponds to the time when the data of the picture W is supplied from the ring buffer 4 to the multiplexed data separator 5 and demultiplexing is started. That is, it corresponds to time t4 in the timing chart of FIG. The STC register 26 outputs the time data (current time) from the time t4 as STC to one input of the comparators 23 and 25.
[0029]
The DTSV register 22 supplies the time DTSV at which the video decoder 7 starts decoding the picture W to the other input of the comparator 23. The comparator 23 outputs a video decode start signal to the video decoder 7 when the current time output from the STC register 26 coincides with the decode start time output from the DTSV register 22 (at time t5 in FIG. 8). When this video decode start signal is input, the video decoder 7 reads out one frame of video data written in the video code buffer 6 and starts decoding.
[0030]
[Problems to be solved by the invention]
In the conventional apparatus of FIG. 5, as described above, the time from SCR (t4) to DTS (t5) is managed by counting a clock with a constant frequency, and data is written to the buffer during that time. . As a result, the transfer rate is fixed to the one specified on the encoder side, and even if the data supply rate to the multiplexed data separator 5 is slower than the fastest transfer rate and there is a margin, the startup delay can be shortened. There wasn't.
[0031]
The present invention has been made in view of such a situation, and improves the responsiveness of the system by shortening the startup delay.
[0032]
[Means for Solving the Problems]
  The multiplexed data demultiplexing apparatus according to claim 1, wherein the first encoded data and the first timing data indicating the decoding start time of the first encoded data are each time-division multiplexed to the input data. And a multiplexed data separation device that separates second encoded data different from the first encoded data and second timing data indicating a decoding start time of the second encoded data, from input data Separating means for separating the first encoded data, the first timing data, the second encoded data, and the second timing data, and the time indicated by the first timing data separated by the separating means And a comparing means for comparing the time indicated by the second timing data,The decoding start time of the first encoded data is prioritized over the decoding start time of the second encoded data,When the time indicated by the second timing data is temporally earlier than the time indicated by the first timing data, the separation unit supplies the second encoded data to the decoder.In the case where the decoding start time of the second encoded data has priority over the decoding start time of the first encoded data, the time indicated by the first timing data is the second timing data If the time is before the indicated time, the separating means does not supply the first encoded data to the decoderIt is characterized by that.
[0033]
  The first encoded data can be encoded video data, and the second encoded data can be encoded audio data..
[0034]
  The multiplexed data separation method according to claim 3, wherein the first encoded data and the first timing data indicating the decoding start time of the first encoded data are each time-division multiplexed to the input data. And a multiplexed data separation method for separating second encoded data different from the first encoded data and second timing data indicating a decoding start time of the second encoded data, from input data The first timing data, the first encoded data, the second encoded data, and the second timing data are separated, and the time indicated by the separated first timing data and the second timing data Compared with the time indicated byThe decoding start time of the first encoded data is prioritized over the decoding start time of the second encoded data,The second encoded data is supplied to the decoder during a period in which the time indicated by the second timing data is temporally before the time indicated by the first timing data.In the case where the decoding start time of the second encoded data has priority over the decoding start time of the first encoded data, the time indicated by the first timing data is the second timing data The first encoded data is not supplied to the decoder for a time period before the indicated time.It is characterized by that.
[0035]
  The first encoded data can be encoded video data, and the second encoded data can be encoded audio data..
[0036]
In the multiplexed data separating apparatus and method having the above-described configuration, the DTSV or DTSA and the SCR are compared by the comparator 23 or the comparator 25. Accordingly, data can be input at a higher transfer rate specified in the bit stream corresponding to the comparison result, and the responsiveness at the start of reproduction can be improved.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a configuration of an embodiment of a multiplexed data demultiplexing apparatus according to the present invention, and the same reference numerals are given to portions corresponding to those in FIG. In this embodiment, the multiplexed data separation device 5 includes a data separation circuit 21, a DTSV register 22, a DSTA register 24, comparators 23 and 25, an STC register 26, a clock generation circuit 27, an SCR register 31 and a switch circuit. 51, 52, 53, 54 are provided.
[0038]
The output of the DTSV register 22 is input to the comparator 23 and also to the input terminal a1 of the switch circuit 51. Similarly, the output of the DTSA register 24 is input to the comparator 25 and also input to the other input terminal a2 of the switch circuit 51. The output of the output terminal b of the switch circuit 51 is input to the STC register 26 and stored therein. The STC register 26 counts the 90 kHz frequency clock output from the clock generation circuit 27 and increments the stored value to generate an STC. The STC output from the STC register 26 is connected to the input terminal c2 of the switch circuit 52.
[0039]
The SCR separated by the data separation circuit 21 is supplied to the SCR register 31. The output of the SCR register 31 is connected to the other input terminal c1 of the switch circuit 52.
[0040]
The output terminal d of the switch circuit 52 is connected to the other input terminal of each of the comparator 23 and the comparator 25.
[0041]
The output of the comparator 23 is connected to the input terminal e of the switch circuit 53. Of the output terminals of the switch circuit 53, one f 1 is connected to the video decoder 7 and the other f 2 is connected to the control circuit 28.
[0042]
Similarly, the output of the comparator 25 is connected to the input terminal g of the switch circuit 54. Of the output terminals of the switch circuit 54, one h 1 is connected to the audio decoder 9 and the other h 2 is connected to the control circuit 28.
[0043]
The switch circuits 51, 52, 53, 54 are controlled by the control circuit 28.
[0044]
Next, the operation will be described. The input unit 29 is operated to instruct the control circuit 28 to start reproducing the optical disk. At this time, the control circuit 28 sets the multiplexed data separator 5 to the initial setting mode. That is, the contact of the switch circuit 52 is set to the c1 side so that the output of the SCR register 31 is supplied to the comparators 23 and 25. Further, the contact of the switch circuit 53 is set to the f2 side, and similarly, the contact of the switch circuit 54 is set to the h2 side so that the comparison result of the comparators 23 and 25 is supplied to the control circuit 28.
[0045]
The data separation circuit 21 is controlled by the control circuit 28 and separates the video data and the audio data from the data supplied from the ring buffer 4 and supplies them to the video code buffer 6 and the audio code buffer 8, respectively. Also, SCR, DTSV, and DTSA are separated, and supplied to SCR register 31, DTSV register 22, and DTSA register 24, respectively, and stored.
[0046]
The SCR register 31 stores and outputs the latest one of the supplied SCR data. The DTSV register 22 holds the DTSV supplied first after the reproduction is started. That is, the DTSV register 22 has a decoding start time for the first picture among the data stored in the video code buffer 6.
[0047]
Similarly, the DTSA register 24 holds the DTSA supplied first after the reproduction is started. In other words, the data stored in the audio code buffer 8 has a decoding start time for the first decoding unit.
[0048]
The switch circuit 52 has its contact closed on the c1 side by a command from the control circuit 28, and the outputs of the DTSV register 22 and the DTSA register 24 and the output of the SCR register 31 are input to the comparators 23 and 25, respectively. Has been.
[0049]
Here, with reference to FIG. 2 and FIG. 3, the reproduction start from the picture W and the data flow will be described. FIG. 3 shows the timing described in the conventional example for comparison.
[0050]
When the start of reproduction is instructed from the input unit 29, the control circuit 28 issues a reproduction instruction to the drive 1, so that data reproduced from the optical disk built in the drive 1 is supplied to the demodulator 2 and demodulated. The demodulated data is subjected to error detection and correction processing in the ECC circuit 3 and then supplied to the data separation circuit 21 via the ring buffer 4.
[0051]
Assume that the first data including the picture W is supplied from the ring buffer 4 to the data separation circuit 21 at time t7 in FIG. 2 (time t4 in FIG. 3). Video data starting from the picture W is supplied to the video code buffer 6, and audio data multiplexed at the same time is supplied to the audio code buffer 8.
[0052]
The DTSV indicating the decoding start time of the picture W is separated by the data separation circuit 21 and supplied to the DTSV register 22. The DTSV register 22 holds and outputs the DTSV of the picture W. Here, since the decoding start time of the picture W is t8 (time t5 in FIG. 3), this value is held in the DTSV register 22 and inputted to one input terminal of the comparator 23.
[0053]
Similarly, the DTSA register 24 holds and outputs the DTSA of the audio data supplied first.
[0054]
In this embodiment, it is assumed that DTSV is a value smaller than DTSA (decoding is started temporally before audio data).
[0055]
The SCR at the head of each pack is supplied to the SCR register 31. The SCR register 31 sequentially holds and outputs the newest one of the supplied SCRs. Since the time when the first pack of the picture W is supplied is t7 (t4 in FIG. 3), the SCR supplied to the SCR register 31 starts from t7 (t4 in FIG. 3).
[0056]
Immediately after the data starts to be supplied (J = t7 in FIG. 2),
(Output of SCR register 31) <(Output of DTSV register 22)
It is. The control circuit 28 monitors the output of the comparator 23, and supplies the data from the ring buffer 4 to the data separation circuit 21 at the maximum speed during the period when the output indicates that this inequality holds. That is, as apparent from the comparison between FIG. 2 and FIG. 3, the transfer rate of the data input to the data separation circuit 21 (input to the video code buffer 6) from time t7 or time t4 is as shown in FIG. Is faster than FIG.
[0057]
When time elapses (writing to the video code buffer 6 proceeds) and the time t8 (time t5 in FIG. 3) is reached, data necessary for decoding the picture W is written to the video code buffer 6 and then supplied. The SCR is larger than the DTSV of the picture W. At this time, the comparator 23 comparing the output of the DTSV register 22 with the output of the SCR register 31 notifies the control circuit 28 that the value of the SCR register 31 has become larger than the value of the DTSV register 22.
[0058]
Here, the control circuit 28 sets the multiplexed data separator 5 to the decode mode. At this time, the multiplexed data separator 5 temporarily stops the input of data from the ring buffer 4 and changes the internal state. That is, the contact of the switch circuit 51 is closed to the a1 side, and the output (t8) of the DTSV register 22 is input to the STC register 26 and held. Then, the contact of the switch circuit 52 is closed to the c2 side, and the output (t8) of the STC register 26 is supplied to the comparators 23 and 25.
[0059]
Further, the contact of the switch circuit 53 is closed to the f1 side, the contact of the switch circuit 54 is closed to the h1 side, and the outputs of the comparators 23 and 25 are input to the video decoder 7 and the audio decoder 9, respectively.
[0060]
After changing the internal state in this way, the multiplexed data separator 5 resumes data input. At the same time, the count (increment) from t8 of the STC register 26 is started. The comparator 23 compares the output DTSV of the DTSV register 22 (in this case, t8) with the count value STC of the STC register 26 (incrementing sequentially from t8), and STC is equal to or greater than DTSV. When this occurs, a video decode start signal is generated for the video decoder 7. Thereby, the video decoder 7 starts decoding the video data.
[0061]
Similarly, the comparator 25 compares the output of the DTSA register 24 with the output of the STC register 26, and outputs a decode start signal to the audio decoder 9 when the STC value is equal to or larger than the DTSA. appear. As a result, the audio decoder 9 starts decoding the audio data.
[0062]
In the above embodiment, the video decoding start time (DTSV) is earlier than the audio decoding start time (DTSA). However, even if the DTSA is earlier, the same operation is possible.
[0063]
In the above embodiment, DTSV and DTSA are used as the decoding start time, but PTS (Presentation Time Stamp) can also be used. This PTS is arranged in the packet header of some packets, and the value represents the time at which the part starting with the first access unit in the packet is to be displayed. In audio data, PTS and DTS have the same value, and in video data, PTS and DTS can be converted into each other by simple calculation.
[0064]
As described above, conventionally, the time from the SCR to the DTS is counted by counting clocks having a constant frequency, and data is written to the video code buffer 6 during that time. As a result, the data transfer rate is specified by the clock frequency and is slow.
[0065]
On the other hand, in this embodiment, when a DTS of a predetermined picture is input, the video code buffer 6 is written at the highest transfer rate, and the SCR of the read data is sequentially compared with the DTS, Based on the relationship between the two, since it is determined whether or not the amount of data necessary for decoding the picture has been written (determining whether or not the decoding start time has been reached), a quick response is possible.
[0066]
Further, when the video decode start time is prioritized over other decode start times (for example, audio decode start time), such as when it is necessary to synchronize the system with the video synchronization signal, there is the following method.
[0067]
FIG. 4 is a block diagram showing the configuration of another embodiment of the multiplexed data demultiplexer according to the present invention. The same reference numerals are given to the portions corresponding to those in FIG. In this embodiment, DTSV and DTSA separated by the data separation circuit 21 are input to the DTSV register 22 and DTSA register 24 and also to the control circuit 28, respectively. In addition, a video synchronization signal is input to the control circuit 28. Other configurations are the same as those in FIG.
[0068]
Next, the operation will be described. The input unit 29 is operated to instruct the control circuit 28 to start reproduction. The control circuit 28 sets the multiplexed data separator 5 to the initial setting mode.
[0069]
Here, with reference to FIG. 2, the reproduction start from the picture W and the data flow will be described.
[0070]
In FIG. 2, it is assumed that the first data including the picture W is supplied from the ring buffer 4 to the data separation circuit 21 at time t7. Video data starting from the picture W is supplied to the video code buffer 6. Since video data is given priority now, audio data is discarded at the beginning. That is, the data separation circuit 21 does not supply audio data to the audio code buffer 8.
[0071]
The DTSV indicating the decoding start time of the picture W is separated by the data separation circuit 21 and supplied to the DTSV register 22 and the control circuit 28. The DTSV register 22 holds and outputs the DTSV of the picture W. Here, since the decoding start time of the picture W is t8, this value is held in the DTSV register 22 and input to one input terminal of the comparator 23. The control circuit 28 holds this DTSV data (t8).
[0072]
Similarly, the DTSA is separated by the data separation circuit 21 and supplied to the DTSA register 24 and the control circuit 28. The control circuit 28 compares the input DTSA data with the DTSV data. If the DTSA data is smaller, the control circuit 28 controls the DTSA register 24 to discard the DTSA data (not to hold it in the DTSA register 24). Similarly, when the DTSA data is input before the DTSV data is input to the control circuit 28, the data is discarded. On the other hand, when the DTSA data is larger than the held DTSV data (after time), the DTSA register 24 is instructed to hold and output the DTSA. Furthermore, the data separation circuit 21 is instructed to supply the separated audio data to the audio code buffer 8.
[0073]
The SCR at the head of each pack is supplied to the SCR register 31. The SCR register 31 sequentially holds and outputs the newest one of the supplied SCRs. Since the time when the first pack of the picture W is supplied is t7, the SCR supplied to the SCR register 31 starts from t7.
[0074]
Immediately after the data starts to be supplied (J = t7 in FIG. 2),
(Output of SCR register 31) <(Output of DTSV register 22) (t8)
It is. While this inequality holds, the control circuit 28 supplies the data from the ring buffer 4 to the data separation circuit 21 at the maximum speed.
[0075]
When time elapses and time t8 is reached, the supplied SCR becomes larger than the DTSV of picture W. At this time, the comparator 23 comparing the output of the DTSV register 22 with the output of the SCR register 31 notifies the control circuit 28 that the value of the SCR register 31 has increased.
[0076]
Here, the control circuit 28 sets the multiplexed data separator 5 to the decode mode. As a result, the internal state is switched as in the case of FIG.
[0077]
The control circuit 28 performs the following operation in synchronization with the input video synchronization signal in order to synchronize the video decoder 7 with the video synchronization signal. That is, in synchronization with the video synchronization signal, the multiplexed data separator 5 restarts data input. At the same time, counting (increment) of the STC register 26 is started, and a video decoding start signal is issued to the video decoder 7 as described above.
[0078]
Further, the comparator 25 compares the output of the DTSA register 24 with the output of the STC register 26, and generates a decode start signal for the audio decoder 9 when the STC value is equal to or larger than the DTSA. .
[0079]
As described above, in this embodiment, the video decoder 7 is the main and the audio decoder 9 is the subordinate. However, any decoder can be operated in the same manner. Further, it is obvious that the same applies even if there are a plurality of types of subordinates, or a plurality of subordinates and subordinates.
[0080]
In the above two embodiments, the comparators 23 and 25 always perform the comparison operation. However, by comparing after the valid data is input to the corresponding DTSV register 22 and DTSA register 24, respectively, It is also possible to perform certain operations.
[0081]
【The invention's effect】
As described above, according to the multiplexed data demultiplexing apparatus and method of the present invention, the data indicating the decoding start timing and the data indicating the time are compared by the comparing means. Thus, data can be input at a higher transfer rate than specified in the bit stream, and the responsiveness at the start of reproduction can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of a multiplexed data demultiplexer according to the present invention.
FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1;
FIG. 3 is a conventional timing chart for comparison with FIG. 2;
FIG. 4 is a block diagram showing the configuration of another embodiment of the multiplexed data separator according to the present invention.
FIG. 5 is a block diagram showing a configuration of an example of a conventional multiplexed data separator.
6 is a diagram for explaining a multiplexed bit stream in the example of FIG. 5. FIG.
7 is a timing chart for explaining the operation of the example of FIG.
FIG. 8 is a timing chart for explaining the operation at the variable rate in the example of FIG. 5;
[Explanation of symbols]
1 drive, 2 demodulator, 3 ECC circuit, 4 ring buffer, 5 multiplexed data separator, 6 video code buffer, 7 video decoder, 8 audio code buffer, 9 audio decoder, 21 data separator, 22 DTSV register, 23 Comparator, 24 DTSA register, 25 Comparator, 26 STC register, 27 Clock generation circuit, 28 Control circuit, 31 SCR register, 51, 52, 53, 54 Switch circuit

Claims (4)

The first encoded data, the first timing data indicating the decoding start time of the first encoded data, and the first encoded data, which are each time-division multiplexed to the input data, are different from each other. In a multiplexed data separator for separating second encoded data and second timing data indicating a decoding start time of the second encoded data,
Separating means for separating the first encoded data, the first timing data, the second encoded data, and the second timing data from the input data;
Comparing means for comparing the time indicated by the first timing data and the time indicated by the second timing data separated by the separating means;
The decoding start time of the first encoded data is prioritized over the decoding start time of the second encoded data, and the time indicated by the second timing data is the first timing data. When the time is before the time indicated by the above, the separating means does not supply the second encoded data to the decoder ,
The decoding start time of the second encoded data is prioritized over the decoding start time of the first encoded data, and the time indicated by the first timing data is the second timing data. If the time is before the time indicated by, the demultiplexing means does not supply the first encoded data to the decoder . The multiplexed data separation apparatus according to claim 1, wherein the first encoded data is encoded video data, and the second encoded data is encoded audio data. The first encoded data, the first timing data indicating the decoding start time of the first encoded data, and the first encoded data, which are each time-division multiplexed to the input data, are different from each other. In a multiplexed data separation method for separating second encoded data and second timing data indicating a decoding start time of the second encoded data,
Separating the first timing data, the first encoded data, the second encoded data, and the second timing data from the input data;
Comparing the time indicated by the separated first timing data with the time indicated by the second timing data;
The decoding start time of the first encoded data is prioritized over the decoding start time of the second encoded data, and the time indicated by the second timing data is the first timing data. Without supplying the second encoded data to the decoder for a period that is earlier in time than the time indicated by
The decoding start time of the second encoded data is prioritized over the decoding start time of the first encoded data, and the time indicated by the first timing data is the second timing data. The multiplexed data separation method is characterized in that the first encoded data is not supplied to the decoder for a period of time before the time indicated by . The multiplexed data separation method according to claim 3 , wherein the first encoded data is encoded video data, and the second encoded data is encoded audio data.

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