JP2003324691A - Multiplex data separator and separating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten start-up delay. <P>SOLUTION: At time t<SB>7</SB>, DTSV indicating the decode starting time (t<SB>8</SB>) of a video decoder is inputted and video data is written in a video code buffer at a maximum transfer rate. During that interval, SCR indicating the current time is monitored and a decision is made whether the SCR is equal to the DTSV(t<SB>8</SB>) or not. When the SCR becomes equal to the DTSV(t<SB>8</SB>) (at the time t<SB>8</SB>), decoding of video data is started thus shortening start-up delay. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexed data demultiplexing apparatus and method, which is suitable for use in, for example, reproducing and demultiplexing video data and audio data recorded by time division multiplexing on an optical disc. The present invention relates to a multiplexed data demultiplexing apparatus and method.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of an example of a conventional multiplexed data demultiplexing device. The drive 1 reproduces the data recorded on the built-in optical disc.
Video data and audio data are time-division multiplexed and recorded on this optical disc. The reproduction data output from the drive 1 is supplied to the demodulation device 2 and demodulated. The ECC circuit 3 performs error detection and correction of the data output from the demodulation device 2, and supplies the data to the ring buffer 4.
The ring buffer 4 accumulates the supplied data in a predetermined amount and then outputs it to the multiplexed data demultiplexing device 5.

The multiplexed data demultiplexing device 5 demultiplexes the video data and the audio data from the data supplied from the ring buffer 4, and at the same time, the SCR (System Clock Reference) as timing data.
ce), for video (DTSV), and for audio (D
DSA (Decoding Time St) of TSA
It has a data separation circuit 21 that separates the data from the (amp).

The format of the data supplied to the multiplexed data demultiplexing device 5 is defined as shown in FIG. 6, for example. This format is MPEG (ISO1
1172) is defined as a multiplexed bit stream. As shown in the figure, the multiplexed bitstream is composed of one or more packs (PACK).
And each pack contains one or more packets (PACKE
T). A pack header (PACK HEADER) is arranged at the head of the pack, and a pack start code (PACK START CODE) indicating the start point of the pack, SCR and M are arranged in the pack header.
UX_RATE is located. The SCR represents the time when the last byte is input to the multiplexed data demultiplexing device 5 (time when demultiplexing starts). MUX_RATE indicates a transfer rate.

In the example of FIG. 6, a video packet (VIDEO PACKET) and an audio packet (AUDIO PACKET) are arranged next to the pack header. A packet header is placed at the beginning of these packets, and this packet header contains a video packet start code (VIDEO PACKET START) indicating the start point of a video or audio packet.
CODE) or audio packet start code (AUDIO PACKET START CODE)
And DTSV or DTSA indicating the start time of decoding video or audio data. Then, next to each packet header, video data or audio data is arranged. However, since the video data has a larger amount of data per unit time than the audio data, the DTSV is arranged once in a plurality of packs.

Timing data such as SCR and DTS (DTSV or DTSA) is represented by a count value of a clock having a frequency of 90 kHz and has a 33-bit significant figure.

The video data is stored in the video code buffer 6
(FIFO). The audio data is supplied to the audio code buffer 8 (FIFO). Further, the SCR is supplied to the STC register 26 and stored therein. Then, the STC register 26 counts the clock of the frequency of 90 kHz output from the clock generation circuit 27, increments the stored value, and generates STC (System Time Clock).

DTSV and DTSA are respectively DTSV
The data is supplied to and stored in the register 22 and the DTSA register 24. The data stored in the DTSV register 22 and the DTSA register 24 are supplied to the comparators 23 and 25, respectively, and compared with the STC output from the STC register 26. The control circuit 28 is composed of, for example, a CPU or the like, and controls the data separation circuit 21 based on a command input from the input unit 29 in response to a user operation.

The video data stored in the video code buffer 6 is read out and supplied to the video decoder 7. Then, the video signal decoded and generated by the video decoder 7 is output to a circuit (not shown). The video decoder 7 includes a comparator 2
The video decoding start signal output from the circuit 3 is supplied.

Similarly, the data output from the audio code buffer 8 is supplied to the audio decoder 9,
It is designed to be decoded. The output of the comparator 25 is supplied to the audio decoder 9 as an audio decoding start signal.

Next, the operation will be described with reference to the timing chart of FIG. The input unit 29 is operated to instruct the control circuit 28 to start reproduction. Control circuit 28
Issues a command to the drive 1 to reproduce the data recorded on the optical disc built in the drive 1. The reproduced data output from the drive 1 is supplied to the demodulation device 2, demodulated, and then supplied to the ECC circuit 3 to be subjected to error detection and correction processing. The data that has undergone this processing is
It is supplied to the data separation circuit 21 of the multiplexed data separation device 5 via the ring buffer 4.

The data separation circuit 21 is controlled by the control circuit 28 and separates video data and audio data from the data supplied from the ring buffer 4 and supplies them to the video code buffer 6 and the audio code buffer 8, respectively. Further, the SCR, DTSV and DTSA are separated and supplied to the STC register 26, the DTSV register 22 and the DTSA register 24, respectively, and stored therein.

The STC register 26 stores the SCR,
After that, the clock output from the clock generation circuit 27 is counted, and the stored value is incremented corresponding to the clock. The stored value of the STC register 26 is the internal time (S
It is supplied to the comparators 23 and 25 as TC).

The DTSV register 22 holds the DTSV first supplied after the reproduction is started by the drive 1. As a result, of the data stored in the video code buffer 6, it has the decoding start time for the first picture.

Similarly, the DTSA register 24 holds the DTSA supplied first after the reproduction is started. As a result, of the data stored in the audio code buffer 8, it has the decoding start time for the first decoding unit.

The SCR corresponds to the time when data is supplied from the ring buffer 4 to the multiplexed data demultiplexing device 5 and demultiplexing is started. That is, it corresponds to time t1 in the timing chart of FIG. STC
The register 26 outputs the time data (current time) from the time t1 to one input of the comparators 23 and 25.

The DTSV register 22 supplies the time DTSV at which the video decoder 7 starts decoding to the other input of the comparator 23. When the current time output by the STC register 26 matches the decoding start time output by the DTSV register 22 (at time t2 in FIG. 7), the comparator 23 outputs a video decoding start signal to the video decoder 7. When the video decoding start signal is input, the video decoder 7 reads the video data written in the video code buffer 6 for one frame and starts decoding.

In FIG. 7, the straight line A indicates the state of writing data to the video code buffer 6 (the slope thereof indicates the write transfer rate), and the broken line B indicates the video coded from the video code buffer 6. The state in which the decoder 7 reads data is shown. Therefore, data remains in the video code buffer 6 in the shaded area in the figure. The storage capacity of the video code buffer 6 is represented by the distance between the straight line A and the straight line C in the vertical direction.

The video decoder 7 starts decoding when the video decoding start signal is supplied, and at the time when the decoding is completed, that is, after the decoding is started, the video decoding delay (VIDEO_DECODE_DELA).
At the timing when the time of Y) has elapsed, a video vertical synchronizing signal is generated, and subsequently the video signal is output. That is, the display is started after the video decoding delay time has elapsed after the start of decoding.

Similarly, the comparator 25 outputs an audio decode start signal when the current time output by the STC register 26 matches the decode start time of the audio data output by the DTSA register 24.
When the audio decoding start signal is input, the audio decoder 9 reads out the data from the audio code buffer 8 and starts the decoding process.
Then, as a result of the decoding process, the generated audio signal is output to a circuit (not shown).

The above is the operation when the transfer rate is a fixed rate. FIG. 8 shows a timing chart when a variable rate is adopted. Before time t3 and t6
After that, the high-rate mode of 8 Mbps is set, and the time is t3.
From 2 to t6, the low rate mode of 2 Mbps is set. This transfer rate is specified at the encoder (not shown) side when data is encoded.

In FIG. 8, a polygonal line D shows the state of writing data to the video code buffer 6, and the slope shows the transfer rate. A polygonal line F shows a state in which the video decoder 7 reads data from the video code buffer 6. Therefore, data remains in the video code buffer 6 in the shaded area in the figure. The storage capacity of the video code buffer 6 is represented by the distance between the straight line D and the straight line E in the vertical direction.

Here, in the lower part of FIG. 8 (a diagram showing an enlarged view from time t3 to time t4), the picture W is focused. The time when the data of the picture W starts to be loaded in the video code buffer 6 is t4. That is, the SCR attached to the pack in which the head portion (G) of the data of the picture W is stored indicates t4. Further, the decoding start time of the picture W is t5, and the DTS attached to the packet in which the head of the picture W is stored.
V indicates t5.

The input unit 29 is operated to instruct the control circuit 28 to start reproduction from the picture W. Control circuit 2
Reference numeral 8 issues a command to the drive 1 to access a predetermined position of the optical disc built in the drive 1 to reproduce the recorded data. The reproduction data output from the drive 1 is supplied to the demodulation device 2 and demodulated, and then E
It is supplied to the CC circuit 3 and subjected to error detection and correction processing. The data subjected to this processing is passed through the ring buffer 4 and the data separation circuit 21 of the multiplexed data separation device 5.
Is supplied to.

MUX_RATE is arranged at the head of each pack, and the transfer rate of the corresponding pack can be known by referring to this data. For example, the data separation circuit 21 controls the data transfer rate based on this value. For controlling variable rate data, for example, GB 2 259 229 A (Date of
Publication 03.03.1993).

The data separation circuit 21 is controlled by the control circuit 28, separates video data from the data supplied from the ring buffer 4, and supplies it to the video code buffer 6. The SCR and DTSV are separated from each other and supplied to the STC register 26 and the DTSV register 22, respectively, and stored therein. Note that the description of the audio system is the same as the case described above, and therefore will be omitted here.

The STC register 26 stores the SCR, and thereafter counts the clock output from the clock generation circuit 27 and increments the stored value corresponding to the clock. The stored value of the STC register 26 is the internal time (S
It is supplied to the comparators 23 and 25 as TC).

The SCR corresponds to the time when the data of the picture W is supplied from the ring buffer 4 to the multiplexed data demultiplexing device 5 and the demultiplexing is started. That is,
It corresponds to time t4 in the timing chart of FIG. The STC register 26 uses the time data (current time) from the time t4 as the STC, and the comparators 23 and 25.
Will be output to one of the inputs.

The DTSV register 22 stores the time DTSV at which the video decoder 7 starts decoding the picture W.
It is supplied to the other input of the comparator 23. Comparator 23
Indicates that the current time output from the STC register 26 is DTS
When it coincides with the decoding start time output from the V register 22 (at time t5 in FIG. 8), the video decoding start signal is output to the video decoder 7. When the video decoding start signal is input, the video decoder 7 reads the video data written in the video code buffer 6 for one frame and starts decoding.

[0030]

In the conventional apparatus of FIG. 5, as described above, the SCR (t4) to DTS
The time until (t5) is counted and managed by counting clocks having a constant frequency, and data is written in the buffer during that time. As a result, the transfer rate is fixed to the one specified on the encoder side, and the start-up delay cannot be shortened even if the data supply rate to the multiplexed data demultiplexing device 5 is slower than the fastest transfer rate and there is a margin. There wasn't.

The present invention has been made in view of such a situation, and improves the response of the system by shortening the startup delay.

[0032]

According to a first aspect of the present invention, there is provided at least a first encoded data and a first encoded data indicating a decoding start time of the first encoded data.
In the multiplexed data demultiplexing method for demultiplexing the multiplexed data in which the second timing data indicating the reference time of the system clock is multiplexed, the first encoded data and the first encoded data And the second timing data are separated, the time indicated by the separated first timing data is compared with the time indicated by the second timing data, and the time indicated by the second timing data is When the time is before the time indicated by the timing data 1, the multiplexed data is read out from the buffer at the maximum transfer rate.

The coded data can be coded video data.

According to a third aspect of the multiplexed data separation method of the present invention, at least first encoded data, first timing data indicating a decoding start time of the first encoded data, and second encoded data. In a multiplexed data demultiplexing method for demultiplexing multiplexed data in which data and second timing data indicating a decoding start time of the second encoded data are demultiplexed, the first timing data from the multiplexed data, The first encoded data, the second encoded data, and the second timing data are separated, and the time indicated by the separated first timing data and the time indicated by the second timing data are compared. , The second encoded data is not supplied to the decoder during a period in which the time indicated by the second timing data is earlier than the time indicated by the first timing data.

The first coded data can be coded video data and the second coded data can be coded audio data.

In the multiplexed data demultiplexing apparatus and method having the above configuration, the DTSV or DTSA and the SCR are compared by the comparator 23 or the comparator 25. Therefore,
Data can be input at a higher transfer rate specified in the bit stream corresponding to the comparison result, and responsiveness at the start of reproduction can be improved.

[0037]

1 is a block diagram showing the configuration of an embodiment of a multiplexed data demultiplexing apparatus of the present invention, and FIG.
The same reference numerals are attached to the portions corresponding to the case. In this embodiment, the multiplexed data demultiplexing device 5
Data separation circuit 21, DTSV register 22, DS
In addition to the TA register 24, the comparators 23 and 25, the STC register 26, the clock generation circuit 27, the SCR register 31
And switch circuits 51, 52, 53, 54 are provided.

The output of the DTSV register 22 is the comparator 23.
To the input terminal a1 of the switch circuit 51
Has been entered in. Similarly, the output of the DTSA register 24 is input to the comparator 25 and the switch circuit 51
Is input to the other input terminal a2. The output from the output terminal b of the switch circuit 51 is input to and stored in the STC register 26. The STC register 26 outputs 90 kHz output from the clock generation circuit 27.
The clock of the frequency is counted and the stored value is incremented to generate the STC. The STC output from the STC register 26 is connected to the input terminal c2 of the switch circuit 52.

The SCR register 31 is supplied with the SCR separated by the data separation circuit 21. SCR
The output of the register 31 is connected to the other input terminal c1 of the switch circuit 52.

The output terminal d of the switch circuit 52 is connected to the other input terminals of the comparator 23 and the comparator 25, respectively.

The output of the comparator 23 is connected to the input terminal e of the switch circuit 53. One of the output terminals of the switch circuit 53, f1 is connected to the video decoder 7,
On the other hand, f2 is connected to the control circuit 28.

Similarly, the output of the comparator 25 is connected to the input terminal g of the switch circuit 54. Switch circuit 5
Of the four output terminals, one h1 is the audio decoder 9
, While h2 is connected to the control circuit 28.

The switch circuits 51, 52, 53, 54 are
It is controlled by the control circuit 28.

Next, the operation will be described. The input unit 29 is operated to instruct the control circuit 28 to start reproduction of the optical disc. At this time, the control circuit 28 sets the multiplexed data demultiplexing device 5 in the initial setting mode. That is, the contact of the switch circuit 52 is set to the c1 side so that the output of the SCR register 31 is supplied to the comparators 23 and 25. Further, the contact of the switch circuit 53 is set to the f2 side, and the contact of the switch circuit 54 is set to the h2 side in the same manner, so that
The comparison result of 5 is supplied to the control circuit 28.

The data separation circuit 21 is controlled by the control circuit 28 and separates the video data and the audio data from the data supplied from the ring buffer 4 and supplies them to the video code buffer 6 and the audio code buffer 8, respectively. Further, the SCR, DTSV and DTSA are separated from each other and supplied to the SCR register 31, the DTSV register 22 and the DTSA register 24, respectively, and stored therein.

The SCR register 31 receives the supplied SCR.
The latest data is stored and output. DTSV
The register 22 holds the DTSV supplied first after the reproduction is started. That is, the DTSV register 22
Of the data stored in the video code buffer 6 has a decoding start time for the first picture.

Similarly, the DTSA register 24 holds the first supplied DTSA after the reproduction is started. That is, of the data stored in the audio code buffer 8, it has a decoding start time for the first decoding unit.

The switch circuit 52 has its contact closed on the c1 side in response to a command from the control circuit 28, and the comparators 23 and 25 have DTSV registers 22 and DT, respectively.
The output of the SA register 24 and the output of the SCR register 31 are input.

Now, the reproduction start from the picture W and the data flow will be described with reference to FIGS. For comparison, FIG. 3 shows the timing described in the conventional example.

Since the control circuit 28 issues a reproduction command to the drive 1 when the start of reproduction is instructed from the input unit 29, the data reproduced from the optical disk built in the drive 1 is supplied to the demodulation device 2 and demodulated. To be done. The demodulated data is subjected to error detection and correction processing in the ECC circuit 3 and then supplied to the data separation circuit 21 via the ring buffer 4.

At time t7 in FIG. 2 (time t4 in FIG. 3), it is assumed that the ring buffer 4 supplies the first data including the picture W to the data separation circuit 21. Video data starting from picture W is video code buffer 6
Further, the audio data simultaneously multiplexed is supplied to the audio code buffer 8.

DT indicating the decoding start time of the picture W
The SV is separated by the data separation circuit 21, and the DTSV
It is supplied to the register 22. The DTSV register 22 is
The DTSV of the picture W is held and output. Here, the decoding start time of the picture W is t8 (time t in FIG. 3).
5), this value is held in the DTSV register 22 and input to one input terminal of the comparator 23.

Similarly, the DTSA register 24 holds and outputs the DTSA of the audio data initially supplied.

In this embodiment, it is assumed that DTSV is smaller than DTSA (the decoding of video data is started before the audio data in time).

The SCR at the head of each pack is supplied to the SCR register 31. The SCR register 31 sequentially holds and outputs the latest supplied SCR. The time when the first pack of the picture W is supplied is t
7 (t4 in FIG. 3), the SCR supplied to the SCR register 31 starts from t7 (t4 in FIG. 3).

Immediately after the data is supplied (J = t7 in FIG. 2), (output of SCR register 31) <(DTSV register 2)
2 output). The control circuit 28 monitors the output of the comparator 23,
The output causes the data from the ring buffer 4 to be supplied to the data separation circuit 21 at the maximum speed during the period when this inequality is shown to hold. That is, as is clear from comparison between FIG. 2 and FIG. 3, the transfer rate of data input to the data separation circuit 21 (input to the video code buffer 6) from time t7 or time t4 is as shown in FIG. Is Figure 3
It's getting faster.

Time has passed (writing to the video code buffer 6 progresses), and time t8 (time t8 in FIG. 3).
When 5) is reached, the data necessary for decoding the picture W is written in the video code buffer 6, so that the SCR supplied thereafter becomes larger than the DTSV of the picture W. At this time, the output of the DTSV register 22 and S
The comparator 23, which compares the output of the CR register 31,
It informs the control circuit 28 that the value of the SCR register 31 has become larger than the value of the DTSV register 22.

Here, the control circuit 28 sets the multiplexed data demultiplexing device 5 in the decode mode. At this time, the multiplexed data demultiplexing device 5 suspends the input of data from the ring buffer 4 and changes the internal state. That is,
The contact of the switch circuit 51 is closed to the a1 side, and the output (t8) of the DTSV register 22 is input to the STC register 26 and held. Then, the contact of the switch circuit 52 is closed to the c2 side, and the output (t8) of the STC register 26 is output to the comparator 2
3 and 25.

Further, the contact of the switch circuit 53 is closed to the f1 side, and the contact of the switch circuit 54 is closed to the h1 side.
The outputs of the comparators 23 and 25 are respectively supplied to the video decoder 7
To the audio decoder 9.

After changing the internal state in this way, the multiplexed data demultiplexing device 5 restarts data input. ST at the same time
Counting (increment) from t8 of the C register 26 is started. The comparator 23 uses the DTSV register 2
2 output DTSV (t8 in this case) and the count value STC of the STC register 26 (increment sequentially from t8)
And STC is equal to or larger than DTSV, a video decoding start signal is generated for the video decoder 7. As a result, the video decoder 7 starts decoding the video data.

Similarly, the comparator 25 compares the output of the DTSA register 24 and the output of the STC register 26, and ST
When the value of C becomes equal to or larger than DTSA, a decode start signal is generated for the audio decoder 9. As a result, the audio decoder 9 starts decoding the audio data.

In the above embodiment, the video decoding start time (DTSV) is earlier than the audio decoding start time (DTSA).
Even if is faster, the same operation is possible.

In the above embodiment, DTSV and DTSA are used as the decoding start time, but PTS (Presentation Time S) is used.
stamp) can also be used. This PTS is placed in the packet header of some packets, and its value represents the time when the portion beginning with the first access unit in the packet should be displayed. In audio data, PTS and DTS have the same value, and even in video data, PTS and DTS can be calculated by a simple calculation.
Mutual conversion is possible.

As described above, conventionally, the time from SCR to DTS is counted by counting clocks of a constant frequency, and during that time, data is written in the video code buffer 6. As a result, the data transfer rate is regulated by the clock frequency and becomes slow.

On the other hand, in the present embodiment, when the DTS of a predetermined picture is input, the data is written into the video code buffer 6 at the highest transfer rate, and the SCR of the read data is sequentially transferred to the DTS. By comparing and determining whether the amount of data necessary for decoding the picture has been written (determining whether the decoding start time has been reached) from the relationship between the two, a quick response is possible. become.

If the video decoding start time has priority over other decoding start times (for example, audio decoding start time), such as when the system needs to be synchronized with the video synchronization signal, the following method is used. is there.

FIG. 4 is a block diagram showing the configuration of another embodiment of the multiplexed data demultiplexing device of the present invention, in which parts corresponding to those in FIG. 1 are designated by the same reference numerals. In this embodiment, the DTSV and DTSA separated by the data separation circuit 21 are respectively the DTSV register 22.
Is input to the DTSA register 24 and also to the control circuit 28. Further, a video synchronizing signal is input to the control circuit 28. Other configurations are similar to those in FIG.

Next, the operation will be described. The input unit 29 is operated to instruct the control circuit 28 to start reproduction. The control circuit 28 sets the multiplexed data demultiplexing device 5 in the initial setting mode.

Now, with reference to FIG. 2, the reproduction start from the picture W and the data flow will be described.

In FIG. 2, it is assumed that the first data including the picture W is supplied from the ring buffer 4 to the data separation circuit 21 at time t7. Video data starting from the picture W is supplied to the video code buffer 6. Now, since the video data has priority, the audio data is discarded at the beginning. That is, the data separation circuit 21
Does not supply audio data to the audio code buffer 8.

DT indicating the decoding start time of the picture W
The SV is separated by the data separation circuit 21, and the DTSV
It is supplied to the register 22 and the control circuit 28. The DTSV register 22 holds the DTSV of the picture W and outputs it. Here, since the decoding start time of the picture W is t8, this value is held in the DTSV register 22,
It is input to one input terminal of the comparator 23. Control circuit 2
8 holds this DTSV data (t8).

Similarly, the DTSA is separated by the data separating circuit 21 and supplied to the DTSA register 24 and the control circuit 28. The control circuit 28 compares the input DTSA data with the DTSV data, and when the DTSA data is smaller, controls the DTSA register 24 and
The TSA data is discarded (not held in the DTSA register 24). Similarly, when DTSA data is input before the DTV data is input to the control circuit 28, the DTSA data is also discarded. On the other hand, when the DTSA data is larger than the held DTSV data (later in time), the DTSA register 24 is instructed to hold and output the DTSA. Further, the data separation circuit 21 is instructed to supply the separated audio data to the audio code buffer 8.

The SCR at the head of each pack is supplied to the SCR register 31. The SCR register 31 sequentially holds and outputs the latest supplied SCR. The time when the first pack of the picture W is supplied is t
7, the SCR supplied to the SCR register 31
Starts at t7.

Immediately after the data is supplied (J = t7 in FIG. 2), (output of SCR register 31) <(DTSV register 2)
2 output) (t8). The control circuit 28 allows the data from the ring buffer 4 to be supplied to the data separation circuit 21 at the maximum speed while the inequality is satisfied.

When the time elapses and the time t8 is reached, the supplied SCR becomes larger than the DTSV of the picture W. At this time, the output of the DTSV register 22 and the SCR
The comparator 23 comparing the output of the register 31
The control circuit 28 indicates that the value of the R register 31 has increased.
Let us know.

Here, the control circuit 28 sets the multiplexed data demultiplexing device 5 in the decode mode. This allows
Similar to the case in FIG. 1, the internal state is switched.

Further, the control circuit 28 includes the video decoder 7
The following operation is performed in synchronization with the input video synchronization signal in order to synchronize the video synchronization signal with the video synchronization signal. That is, the multiplexed data demultiplexing device 5 is made to restart data input in synchronization with the video synchronization signal. At the same time, the STC register 26 starts counting (incrementing), and the video decoding start signal is issued to the video decoder 7 as described above.

Further, the comparator 25 includes the DTSA register 2
4 and the output of the STC register 26 are compared, and the STC
When the value of is equal to or larger than that of DTSA, a decode start signal is generated for the audio decoder 9.

As described above, in this embodiment, the video decoder 7
, And the audio decoder 9 as a subordinate, but any decoder that is the main one can operate similarly. Also, there are multiple types of subordinates, or
It is self-evident that the same is true even if there are multiple masters and slaves.

In the above two embodiments, the comparator 2
Although 3 and 25 are always compared, the corresponding DTSV register 22 and DTSA register 24 are associated with each other.
It is also possible to perform a reliable operation by performing comparison after valid data is input to.

[0081]

As described above, according to the multiplexed data demultiplexing apparatus and method of the present invention, the data indicating the decoding start timing and the data indicating the time are compared by the comparing means. Data can be input at a transfer rate higher than that specified in the bit stream in accordance with the comparison result, and responsiveness at the start of reproduction can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a multiplexed data demultiplexing device of the present invention.

FIG. 2 is a timing chart explaining the operation of the embodiment of FIG.

FIG. 3 is a conventional timing chart for comparison with FIG.

FIG. 4 is a block diagram showing the configuration of another embodiment of the multiplexed data demultiplexing device of the present invention.

FIG. 5 is a block diagram showing a configuration of an example of a conventional multiplexed data demultiplexing device.

6 is a diagram illustrating a multiplexed bitstream of the example of FIG.

FIG. 7 is a timing chart explaining the operation of the example of FIG.

FIG. 8 is a timing chart for explaining the operation at the variable rate in the example of FIG.

[Explanation of symbols]

1 drive, 2 demodulator, 3 ECC circuit,
4 ring buffer, 5 multiplexed data demultiplexer, 6
Video code buffer, 7 Video decoder, 8
Audio code buffer, 9 audio decoder, 21 data separation circuit, 22 DTSV register, 23 comparator, 24 DTSA register, 2
5 comparator, 26 STC register, 27 clock generation circuit, 28 control circuit, 31 SCR register, 51, 52, 53, 54 switch circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 7/081 H04N 7/08 Z 7/24 F term (reference) 5C053 FA23 GA11 GB06 GB21 JA07 JA12 JA22 5C059 KK00 RC04 RC32 SS11 UA05 UA32 5C063 AB03 AB07 AC01 AC05 CA23 DA07 DA13 DB10 5D044 AB05 AB07 BC02 CC04 DE25 DE39 DE53 FG10 FG18 FG21 GK08 GK11 HH05 5K028 AA11 EE03 KK03 KK32

Claims (4)

[Claims] 1. At least first coded data, first timing data indicating a decoding start time of the first coded data, second coded data, and the second coded data.
In the multiplexed data demultiplexing device for demultiplexing the multiplexed data obtained by multiplexing the second timing data indicating the decoding start time of the encoded data, the first encoded data and the first encoded data from the multiplexed data. No. 1 timing data, the second coded data, and the second timing data are separated from each other, the time indicated by the first timing data separated by the separation unit, and the second Comparing means for comparing the time indicated by the timing data with time, the time indicated by the second timing data is earlier in time than the time indicated by the first timing data,
The multiplexed data demultiplexing device, wherein the demultiplexing means does not supply the second coded data to a decoder. 2. The multiplexed data according to claim 1, wherein the first coded data is coded video data, and the second coded data is coded audio data. Separation device. 3. At least first coded data, first timing data indicating a decoding start time of the first coded data, second coded data, and the second coded data.
A multiplexed data demultiplexing method for demultiplexing multiplexed data obtained by multiplexing the second timing data indicating the decoding start time of the encoded data of
The first encoded data, the second encoded data, and the second timing data are separated, and the time indicated by the separated first timing data and the second timing data are indicated. A period of time when the time indicated by the second timing data is earlier than the time indicated by the first timing data,
A method for separating multiplexed data, wherein the second encoded data is not supplied to a decoder. 4. The multiplexed data according to claim 3, wherein the first coded data is coded video data, and the second coded data is coded audio data. Separation method.