JP3772727B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
JP3772727B2
JP3772727B2 JP2001328573A JP2001328573A JP3772727B2 JP 3772727 B2 JP3772727 B2 JP 3772727B2 JP 2001328573 A JP2001328573 A JP 2001328573A JP 2001328573 A JP2001328573 A JP 2001328573A JP 3772727 B2 JP3772727 B2 JP 3772727B2
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Prior art keywords
resistor
region
well region
anode
negative voltage
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JP2003133919A (en
Inventor
伸一 手塚
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は、力率改善を必要とされる各種電源に用いられる電源制御用CMOS−ICなどの半導体集積回路装置に関する。
【0002】
【従来の技術】
冷蔵庫やエアコンなどに用いられる電源で、力率改善を必要とする各種電源においては、電源の起動時などに、電源に搭載される電源制御用ICに、−5Vを超す大きな負電圧の入力電圧が入力される場合がある。但し、定常動作時には、−1Vから0V程度の小さな負電圧が入力されている。
【0003】
図3は、従来の電源制御用バイポーラICの要部回路図である。電源の高電位側VCCに抵抗R4の一端が接続し、抵抗R4の他端を抵抗R5の一端に接続し、抵抗R5の他端を負電圧入力端子13に接続し、抵抗R4と抵抗R5の接続点のB点を制御回路12のpnpバイポーラトランジスタのベースに接続する。
通常、負電圧入力端子13に負電圧を入力しても、B点の電位が正電圧となるように抵抗R4、抵抗R5の抵抗値を決める。この抵抗R4、抵抗R5は拡散で形成される拡散抵抗(図4のp層のこと)である。
【0004】
しかし、前記のように、電源の起動時に大きな負電圧が負電圧入力端子13に印加されと、B点の電位も大きな負電圧となり、pnpトランジスタのグランドと接続しているコレクタから、ベースを通り、負電圧入力端子13へ向かって、抵抗R5を介して、電流が流れる。ただし、抵抗R5で電流が制限されることもあり、pnpトランジスタは破壊しない。破壊に至るには、拡散抵抗とnエピタキシャル層によるpn接合の逆耐圧を超えない限り発生しない。実際には、図4に示すpn接合(図4参照)の逆耐圧が−80V程度と高いために、破壊が生じない。
【0005】
しかし、この電源制御用バイポーラICでは、電流駆動素子であるバイポーラトランジスタを用いているために、低消費電力化や高速化は困難である。
今後、低消費電力化や、高速化を実現するために、電源制御用ICを構成する単位素子の微細化が必要となり、MOSFETで構成される電源制御用CMOS−IC(CMOSとは、MOSFETで構成される相補回路のこと)が標準となるものと考えられる。
【0006】
【発明が解決しようとする課題】
しかし、このMOSFETで構成される電源制御用CMOS−ICでは、大きな負電圧を入力した場合、入力部のpチャネルMOSFETのソースとゲート間に大きな負電圧が印加されて、pチャネルMOSFETのゲート絶縁膜が絶縁破壊を起こし、pチャネルMOSFETが破壊する。
【0007】
この発明の目的は、負電圧の入力を可能とする電源制御用CMOS−ICなどの半導体集積回路装置を提供することにある。
【0008】
【課題を解決するための手段】
前記の目的を達成するために、負電圧を入力信号として動作する半導体集積回路装置において、複数の抵抗の分圧によって、負電圧を正電圧に変換するレベルシフト回路と、該レベルシフト回路から出力される入力信号として動作するMOSFETで構成される制御回路とを具備する構成とする。
【0009】
また、前記レベルシフト回路が、電源の高電位側に一端が接続する第1抵抗と、該第1抵抗の他端と一端とが接続する第2抵抗と、該第2抵抗の他端と、アノードが接続する第1ダイオードと、該第1ダイオードのカソードが電源のグランド側と接続し、前記第2抵抗と前記ダイオードのアノードの接続点に、一端が接続する第3抵抗と、該第3抵抗の他端に接続する負電圧入力端子と、前記第1抵抗と前記第2抵抗の接続点にカソードが接続する第2ダイオードと、該第2ダイオードのアノードが電源のグランド側に接続し、前記第1抵抗と前記第2抵抗の接続点と接続する出力端子とを具備する構成とする。
【0010】
また、前記第1抵抗、第2抵抗および第3抵抗が、ポリシリコンで形成されるとよい。
また、負電圧を入力信号として動作する半導体集積回路装置において、第1導電型の半導体基板の表面層に選択的にCMOSで構成される制御回路を形成し、該半導体基板の表面層に前記制御回路と離して形成される第2導電型の第1ウェル領域および第2ウェル領域と、該第1ウェル領域に少なくとも1個形成される第1導電型の第3ウエル領域と、該第3ウエル領域の表面層に形成される第1ダイオードの第2導電型の第1カソード領域と第1導電型の第1アノード領域と、前記第2ウェル領域の表面層に少なくとも1個形成される第1導電型の第4ウェル領域と、該第4ウェル領域の表面層に第2ダイオードの第2導電型の第2カソード領域と第1導電型の第2アノード領域と、前記第1ウエル領域に形成される第2導電型の第1拡散領域と、前記第2ウェル領域の表面層に形成される第2導電型の第2拡散領域と、前記半導体基板上に絶縁膜を介して独立して形成される第1抵抗、第2抵抗、第3抵抗とを具備し、
電源の高電位側に一端が接続する第1抵抗と、該第1抵抗の他端と一端とが接続する第2抵抗と、該第2抵抗の他端と、第3抵抗の一端および第1アノード領域と接続し、該抵抗の他端と負電圧入力端子と接続し、第1カソード領域と電源のグランドと接続し、前記第2抵抗の一端と第2カソード領域と接続し、第2アノード領域と電源のグランドと接続し、前記第1カソード領域と前記第1拡散領域と接続し、前記第2カソード領域と第2拡散領域と接続し、前記第1抵抗と前記第2抵抗の接続点と、前記制御回路の入力点とを接続する構成とする。
【0011】
【発明の実施の形態】
図1は、この発明の半導体集積回路装置の要部回路構成図である。ここでは、レベルシフト回路1と制御回路2で構成される電源制御用CMOS−IC100を例として挙げた。この制御回路2は、MOSFETで構成される図示しないCMOS−IC回路が主要回路である。
【0012】
電源の高電位側VCCを抵抗R1の一端と接続し、抵抗R1の他端を抵抗R2の一端と接続し、抵抗R2の他端を抵抗R3の一端と、ツェナーダイオードZD1のアノードとに接続し、抵抗R3の他端を負電圧入力端子3に接続し、ツェナーダイオードZD1のカソードとツェナーダイオードZD2のアノードと接続し、ツェナーダイオードZD2のカソードと電源のグランドGNDを接続し、抵抗R1と抵抗R2の接続点をA点とし、このA点とツェナーダイオードZD3のカソードを接続し、ツェナーダイオードZD3のアノードと電源のグランドGNDを接続する。前記のA点が点線で示すレベルシフト回路1の出力点となり、この出力点と制御回路2の入力とを接続する。このレベルシフト回路1と制御回路2で電源制御用CMOS−IC100が構成される。
【0013】
電源の高電位側VCCから負電圧入力端子3まで、抵抗R1、抵抗R2、抵抗R3で構成し、A点の電圧を制御回路2に入力することで、正電圧へのレベルシフトとする。また抵抗R1、抵抗R2、抵抗R3については、負電圧が入力された場合、半導体基板からの電流を防止するため、拡散抵抗ではなく、ポリシリコン抵抗を用いる。また、ツェナーダイオードZD1、ツェナーダイオードZD2と抵抗R3の構成で、負電圧入力端子3に負電圧が入力された場合に、グランドGNDからの負電圧入力端子3方向に過電流が流れるのを防止する。尚、ツェナーダイオードの個数は、負電圧の大きさにより決め、負電圧が低い場合は1個でもよく、また、高い場合は2個以上とするとよい。
【0014】
また、ツェナーダイオードZD3は、より大きな負電圧が入力されて、A点の電位が負電圧となった場合、A点の電位を−0.6Vにクランプさせる役目を持つ。
さて、負電圧が入力された場合にA点の電圧が正電圧となる条件について説明する。
A点電圧=(VCC+Vin絶対値)×(R2+R3)/(R1+R2+R3)−Vin絶対値>0・・・・・・(1)
ここで、VCCは電源の高電位側VCCの電圧、R1、R2、R3は抵抗R1、抵抗R2、抵抗R3の抵抗値、Vin絶対値は負電圧入力端子3の入力電圧Vinの絶対値である。
A点電圧が正電圧になるように、R1、R2、R3を決める。一例をつぎに説明する。
VCC=5V、Vinを−1Vとした場合
(5+(−1の絶対値))×(R2+R3)/(R1+R2+R3)−(−1の絶対値)=6×(R2+R3)/(R1+R2+R3)−1>0
つまり、(R2+R3)/(R1+R2+R3)>1/6・・・・(2)
となる。この(2)式を満足するR1、R2、R3の値を決める。
【0015】
例えば、R1=15kΩ、R2=2KΩ、R3>1kΩとすると、A点の電圧を正電圧とすることができる。この他にR1、R2、R3には各種組み合わせがあることは勿論である。
図2は、この発明の第2実施例の半導体集積回路装置の要部断面図である。この要部断面図は、図1のレベルシフト回路部の断面図である。
【0016】
- 基板10の表面層に、第1nウェル領域11と第2nウェル領域12を形成し、第1nウェル領域11の表面層に2個の第1pウェル領域13と第2pウェル領域14を形成し、第1および第2pウェル領域13、14にツェナーダイオードZD1、ZD2のn+ カソード領域16、18とp+ アノード領域17、19を形成する。前記の第2nウェル領域12の表面層に第3pウェル領域15を形成し、第3pウェル領域15の表面層にツェナーダイオードZD3のn+ カソード領域20とp+ アノード領域21を形成する。
【0017】
また、第1、第2ウェル領域11、12の電位を固定するために、第1nウェル領域11と第2nウェル領域12の表面層に、第1pウェル領域、第2pウェル領域および第3pウェル領域と離して、n+ 領域22、23をそれぞれ形成する。
また、第1nウェル領域11を2個のnウェル領域に分割して、それぞれの1個のnウェル領域に、1個のツェナーダイオード(ZD1またはZD2)を形成してもよい。
【0018】
また、p- 基板10の表面に絶縁膜24を選択的に被覆し、その上に抵抗R1、抵抗R2、抵抗R3となるポリシリコン抵抗25を形成する。この絶縁膜24は選択酸化膜であってもよい。
電源の高電位側VCCと抵抗R1の一端と接続し、他端と抵抗R2の一端と接続し、抵抗R2の他端と抵抗R3の一端と接続し、他端と負電圧入力端子3と接続し、抵抗R3の一端とツェナーダイオードZ1のp+ アノード領域19と接続し、n+ カソード領域18とツェナーダイオードZD2のp+ アノード領域17と接続し、n+ カソード領域16とn+ 領域22と接続し、n+ 領域22とグランドGNDと接続し、ツェナーダイオードZD3のp+ アノード21とグランドと接続し、ツェナーダイオードZD3のn+ カソード20とn+ 領域23と抵抗R2の一端と接続する。この接続点がA点である。このp- 基板10には当然、制御回路2も形成されている。
【0019】
このように、同一の半導体基板(p- 基板10)に、制御回路2とレベルシフト回路1を集積することで、小型化と製造コストの低減を図ることができる。
勿論、p- 基板に上記と逆の導電型の領域を形成する場合もある。
【0020】
【発明の効果】
この発明によれば、負電圧入力信号を正電圧に変換するレベルシフト回路を備えたことにより、負電圧の入力信号が印加されても、集積下MOSFETのゲート絶縁膜は破壊されることはなくなるため、電源制御などの半導体集積回路にMOSFETを採用でき、低消費電力化、高速化を図ることができる。
【図面の簡単な説明】
【図1】この発明の第1実施例の半導体集積回路装置の要部回路構成図
【図2】この発明の第2実施例の半導体集積回路装置の要部断面図
【図3】従来の電源制御用バイポーラICの要部回路図
【図4】拡散抵抗の図
【符号の説明】
1 レベルシフト回路
2 制御回路
3 負電圧入力端子
10 p- 基板
11 第1nウェル領域
12 第2nウェル領域
13 第1pウェル領域
14 第2pウェル領域
15 第3pウェル領域
16、18、20 n+ カソード領域
17、19、21 p+ アノード領域
22、23 n+ 領域
24 絶縁膜
25 ポリシリコン抵抗
100 電源制御用IC
VCC 電源の高電位側/電源電圧
R1、R2、R3 抵抗/抵抗値
ZD1、ZD2、ZD3 ツェナーダイオード
Vin 負電圧入力端子/入力電圧
GND グランド
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device such as a power supply control CMOS-IC used for various power supplies requiring power factor improvement.
[0002]
[Prior art]
In various power supplies that require power factor improvement, such as refrigerators and air conditioners, a large negative input voltage exceeding -5V is applied to the power control IC mounted on the power supply when the power supply is started. May be entered. However, during steady operation, a small negative voltage of about -1V to 0V is input.
[0003]
FIG. 3 is a principal circuit diagram of a conventional power supply control bipolar IC. One end of the resistor R4 is connected to the high potential side VCC of the power supply, the other end of the resistor R4 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the negative voltage input terminal 13, and the resistors R4 and R5 The connection point B is connected to the base of the pnp bipolar transistor of the control circuit 12.
Normally, even if a negative voltage is input to the negative voltage input terminal 13, the resistance values of the resistors R4 and R5 are determined so that the potential at the point B becomes a positive voltage. The resistors R4 and R5 are diffusion resistors formed by diffusion (the p layer in FIG. 4).
[0004]
However, as described above, when a large negative voltage is applied to the negative voltage input terminal 13 at the time of starting the power source, the potential at the point B also becomes a large negative voltage and passes through the base from the collector connected to the ground of the pnp transistor. A current flows toward the negative voltage input terminal 13 through the resistor R5. However, the current may be limited by the resistor R5, and the pnp transistor is not destroyed. The breakdown does not occur unless the reverse resistance of the pn junction by the diffusion resistance and the n epitaxial layer is exceeded. Actually, since the reverse breakdown voltage of the pn junction (see FIG. 4) shown in FIG. 4 is as high as about −80 V, no breakdown occurs.
[0005]
However, since this bipolar IC for power control uses a bipolar transistor which is a current driving element, it is difficult to reduce power consumption and speed.
In the future, in order to realize low power consumption and high speed, it will be necessary to miniaturize the unit elements constituting the power control IC, and the power control CMOS-IC composed of MOSFETs (CMOS is a MOSFET) Complementary circuit configured) is considered to be the standard.
[0006]
[Problems to be solved by the invention]
However, in the power supply control CMOS-IC configured by this MOSFET, when a large negative voltage is input, a large negative voltage is applied between the source and gate of the p-channel MOSFET in the input section, and the gate insulation of the p-channel MOSFET. The film causes dielectric breakdown, and the p-channel MOSFET is destroyed.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device such as a power supply control CMOS-IC capable of inputting a negative voltage.
[0008]
[Means for Solving the Problems]
To achieve the above object, in a semiconductor integrated circuit device that operates using a negative voltage as an input signal, a level shift circuit that converts the negative voltage to a positive voltage by dividing a plurality of resistors, and an output from the level shift circuit And a control circuit composed of a MOSFET that operates as an input signal.
[0009]
The level shift circuit includes: a first resistor having one end connected to the high potential side of the power supply; a second resistor connected to the other end of the first resistor; and the other end of the second resistor; A first diode connected to the anode; a cathode of the first diode connected to a ground side of a power supply; a third resistor connected at one end to a connection point between the second resistor and the anode of the diode; A negative voltage input terminal connected to the other end of the resistor, a second diode having a cathode connected to a connection point of the first resistor and the second resistor, and an anode of the second diode connected to the ground side of the power source, An output terminal connected to a connection point of the first resistor and the second resistor is provided.
[0010]
The first resistor, the second resistor, and the third resistor may be formed of polysilicon.
In a semiconductor integrated circuit device that operates using a negative voltage as an input signal, a control circuit composed of CMOS is selectively formed on the surface layer of the first conductivity type semiconductor substrate, and the control is formed on the surface layer of the semiconductor substrate. Second conductivity type first well region and second well region formed apart from the circuit, at least one first conductivity type third well region formed in the first well region, and the third well At least one first-conductivity-type first cathode region and first-conductivity-type first anode region of the first diode formed on the surface layer of the region, and at least one formed on the surface layer of the second well region. A conductive type fourth well region; a second conductive type second cathode region of a second diode; a first conductive type second anode region; and a first conductive type second anode region formed on a surface layer of the fourth well region. First conductivity type second diffusion A second diffusion region of a second conductivity type formed in the surface layer of the second well region, and a first resistor, a second resistor formed independently on the semiconductor substrate via an insulating film, A third resistor,
A first resistor having one end connected to the high potential side of the power supply, a second resistor connecting the other end and one end of the first resistor, the other end of the second resistor, one end of the third resistor, and the first Connected to the anode region, connected to the other end of the resistor and the negative voltage input terminal, connected to the first cathode region and the ground of the power source, connected to one end of the second resistor and the second cathode region, and second anode A connection point between the first resistor and the second resistor, a first cathode region and the first diffusion region, a second cathode region and a second diffusion region, and a connection point between the first resistor and the second resistor; And an input point of the control circuit.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a principal circuit configuration diagram of a semiconductor integrated circuit device according to the present invention. Here, the power supply control CMOS-IC 100 including the level shift circuit 1 and the control circuit 2 is taken as an example. The control circuit 2 is mainly composed of a CMOS-IC circuit (not shown) composed of a MOSFET.
[0012]
The high potential side VCC of the power supply is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to one end of the resistor R3 and the anode of the Zener diode ZD1. The other end of the resistor R3 is connected to the negative voltage input terminal 3, the cathode of the Zener diode ZD1 is connected to the anode of the Zener diode ZD2, the cathode of the Zener diode ZD2 is connected to the ground GND of the power source, and the resistor R1 and the resistor R2 Is connected to the cathode of the Zener diode ZD3, and the anode of the Zener diode ZD3 is connected to the ground GND of the power source. The point A becomes an output point of the level shift circuit 1 indicated by a dotted line, and this output point and the input of the control circuit 2 are connected. The level shift circuit 1 and the control circuit 2 constitute a power supply control CMOS-IC 100.
[0013]
From the high potential side VCC of the power source to the negative voltage input terminal 3, it is constituted by a resistor R1, a resistor R2, and a resistor R3. By inputting the voltage at point A to the control circuit 2, a level shift to a positive voltage is made. For the resistors R1, R2, and R3, when a negative voltage is input, a polysilicon resistor is used instead of a diffused resistor in order to prevent a current from the semiconductor substrate. Further, the configuration of the Zener diode ZD1, the Zener diode ZD2, and the resistor R3 prevents overcurrent from flowing from the ground GND toward the negative voltage input terminal 3 when a negative voltage is input to the negative voltage input terminal 3. . Note that the number of Zener diodes is determined by the magnitude of the negative voltage, and may be one when the negative voltage is low, or two or more when the negative voltage is high.
[0014]
Further, the Zener diode ZD3 has a function of clamping the potential at the point A to −0.6 V when a larger negative voltage is input and the potential at the point A becomes a negative voltage.
Now, the conditions under which the voltage at point A becomes a positive voltage when a negative voltage is input will be described.
A point voltage = (VCC + Vin absolute value) × (R2 + R3) / (R1 + R2 + R3) −Vin absolute value> 0 (1)
Here, VCC is the voltage of the high potential side VCC of the power supply, R1, R2, and R3 are the resistance values of the resistors R1, R2, and R3, and the Vin absolute value is the absolute value of the input voltage Vin of the negative voltage input terminal 3. .
R1, R2, and R3 are determined so that the point A voltage becomes a positive voltage. An example is described next.
When Vcc = 5 V and Vin is −1 V (5+ (absolute value of −1)) × (R2 + R3) / (R1 + R2 + R3) − (absolute value of −1) = 6 × (R2 + R3) / (R1 + R2 + R3) −1> 0
That is, (R2 + R3) / (R1 + R2 + R3)> 1/6 (2)
It becomes. The values of R1, R2, and R3 that satisfy this equation (2) are determined.
[0015]
For example, if R1 = 15 kΩ, R2 = 2 KΩ, and R3> 1 kΩ, the voltage at point A can be a positive voltage. Of course, there are various combinations of R1, R2, and R3.
FIG. 2 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to the second embodiment of the present invention. This principal part sectional drawing is a sectional view of the level shift circuit part of FIG.
[0016]
A first n well region 11 and a second n well region 12 are formed on the surface layer of the p substrate 10, and two first p well regions 13 and a second p well region 14 are formed on the surface layer of the first n well region 11. The n + cathode regions 16 and 18 and the p + anode regions 17 and 19 of the Zener diodes ZD1 and ZD2 are formed in the first and second p well regions 13 and 14, respectively. A third p well region 15 is formed in the surface layer of the second n well region 12, and an n + cathode region 20 and a p + anode region 21 of the Zener diode ZD3 are formed in the surface layer of the third p well region 15.
[0017]
Further, in order to fix the potentials of the first and second well regions 11 and 12, the first p well region, the second p well region, and the third p well region are formed on the surface layers of the first n well region 11 and the second n well region 12, respectively. And n + regions 22 and 23 are formed.
Alternatively, the first n-well region 11 may be divided into two n-well regions, and one zener diode (ZD1 or ZD2) may be formed in each n-well region.
[0018]
Further, an insulating film 24 is selectively covered on the surface of the p substrate 10, and a polysilicon resistor 25 serving as a resistor R 1, a resistor R 2, and a resistor R 3 is formed thereon. This insulating film 24 may be a selective oxide film.
The high potential side VCC of the power supply is connected to one end of the resistor R1, the other end is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R3, and the other end is connected to the negative voltage input terminal 3. Then, one end of the resistor R3 is connected to the p + anode region 19 of the Zener diode Z1, connected to the n + cathode region 18 and the p + anode region 17 of the Zener diode ZD2, and the n + cathode region 16 and the n + region 22 The n + region 22 and the ground GND are connected, the p + anode 21 of the Zener diode ZD3 and the ground are connected, and the n + cathode 20 and the n + region 23 of the Zener diode ZD3 and one end of the resistor R2 are connected. This connection point is point A. Of course, the control circuit 2 is also formed on the p substrate 10.
[0019]
Thus, the same semiconductor substrate - the (p substrate 10), the control circuit by integrating 2 and level shift circuit 1, it is possible to reduce the size and manufacturing cost.
Of course, a region of the opposite conductivity type may be formed on the p substrate.
[0020]
【The invention's effect】
According to the present invention, since the level shift circuit for converting a negative voltage input signal into a positive voltage is provided, even when a negative voltage input signal is applied, the gate insulating film of the integrated MOSFET is not destroyed. Therefore, a MOSFET can be employed in a semiconductor integrated circuit such as power supply control, and low power consumption and high speed can be achieved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of the main part of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the main part of a semiconductor integrated circuit device according to a second embodiment of the present invention. Main circuit diagram of bipolar IC for control [Figure 4] Diagram of diffused resistor [Explanation of symbols]
1 level shift circuit 2 control circuit 3 the negative voltage input terminal 10 p - substrate 11 first 1n-well region 12 a 2n-well region 13 a 1p-well region 14 a 2p-well region 15 a 3p-well region 16, 18, 20 n + cathode region 17, 19, 21 p + anode region 22, 23 n + region 24 insulating film 25 polysilicon resistor 100 power supply control IC
High potential side of VCC power supply / power supply voltages R1, R2, R3 Resistance / resistance values ZD1, ZD2, ZD3 Zener diode Vin Negative voltage input terminal / input voltage GND Ground

Claims (3)

負電圧を入力信号として動作する半導体集積回路装置において、複数の抵抗の分圧によって、負電圧を正電圧に変換するレベルシフト回路と、該レベルシフト回路の出力を入力信号として動作するMOSFETで構成された制御回路とを具備し、前記レベルシフト回路が、電源の高電位側に一端が接続する第1抵抗と、該第1抵抗の他端と一端とが接続する第2抵抗と、該第2抵抗の他端と、アノードが接続する第1ダイオードと、該第1ダイオードのカソードが電源のグランド側と接続し、前記第2抵抗と前記ダイオードのアノードの接続点に、一端が接続する第3抵抗と、該第3抵抗の他端に接続する負電圧入力端子と、前記第1抵抗と前記第2抵抗の接続点にカソードが接続する第2ダイオードと、該第2ダイオードのアノードが電源のグランド側に接続し、前記第1抵抗と前記第2抵抗の接続点と接続する出力端子とを具備することを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device that operates using a negative voltage as an input signal, it is composed of a level shift circuit that converts the negative voltage to a positive voltage by dividing a plurality of resistors, and a MOSFET that operates using the output of the level shift circuit as an input signal. The level shift circuit includes a first resistor having one end connected to the high potential side of the power supply, a second resistor connected to the other end and one end of the first resistor, and the second resistor The other end of the two resistors, the first diode to which the anode is connected, the cathode of the first diode is connected to the ground side of the power source, and one end is connected to the connection point of the second resistor and the anode of the diode. Three resistors, a negative voltage input terminal connected to the other end of the third resistor, a second diode having a cathode connected to a connection point of the first resistor and the second resistor, and an anode of the second diode being a power source Connected to the ground side, the semiconductor integrated circuit device characterized by comprising an output terminal connected to the connection point of the first resistor and the second resistor. 前記第1抵抗、第2抵抗および第3抵抗が、ポリシリコンで形成されることを特徴とする請求項に記載の半導体集積装置。2. The semiconductor integrated device according to claim 1 , wherein the first resistor, the second resistor, and the third resistor are formed of polysilicon. 負電圧を入力信号として動作する半導体集積回路装置において、第1導電型の半導体基板の表面層に選択的にCMOSで構成される制御回路を形成し、該半導体基板の表面層に前記制御回路と離して形成される第2導電型の第1ウェル領域および第2ウェル領域と、該第1ウェル領域に少なくとも1個形成される第1導電型の第3ウエル領域と、該第3ウエル領域の表面層に形成される第1ダイオードの第2導電型の第1カソード領域と第1導電型の第1アノード領域と、前記第2ウェル領域の表面層に少なくとも1個形成される第1導電型の第4ウェル領域と、該第4ウェル領域の表面層に第2ダイオードの第2導電型の第2カソード領域と第1導電型の第2アノード領域と、前記第1ウエル領域に形成される第2導電型の第1拡散領域と、前記第2ウェル領域の表面層に形成される第2導電型の第2拡散領域と、前記半導体基板上に絶縁膜を介して独立して形成される第1抵抗、第2抵抗、第3抵抗とを具備し、
電源の高電位側に一端が接続する第1抵抗と、該第1抵抗の他端と一端とが接続する第2抵抗と、該第2抵抗の他端と、第3抵抗の一端および第1アノード領域と接続し、該抵抗の他端と負電圧入力端子と接続し、第1カソード領域と電源のグランドと接続し、前記第2抵抗の一端と第2カソード領域と接続し、第2アノード領域と電源のグランドと接続し、前記第1カソード領域と前記第1拡散領域と接続し、前記第2カソード領域と第2拡散領域と接続し、前記第1抵抗と前記第2抵抗の接続点と、前記制御回路の入力点とが接続することを特徴とする半導体集積回路装置。
In a semiconductor integrated circuit device that operates using a negative voltage as an input signal, a control circuit composed of CMOS is selectively formed on a surface layer of a first conductivity type semiconductor substrate, and the control circuit and the control circuit are formed on the surface layer of the semiconductor substrate. A second well-type first well region and a second well region formed separately, at least one first-conductivity-type third well region formed in the first well region, and the third well region A first conductivity type formed on the surface layer of the second well region and a first conductivity type first cathode region, a first conductivity type first anode region of the first diode formed on the surface layer, and the second well region. A fourth well region, a second conductivity type second cathode region and a first conductivity type second anode region of a second diode formed on a surface layer of the fourth well region, and the first well region. A first diffusion region of a second conductivity type; A second diffusion region of the second conductivity type formed in the surface layer of the second well region, and a first resistor, a second resistor, and a third resistor formed independently on the semiconductor substrate via an insulating film And
A first resistor having one end connected to the high potential side of the power supply, a second resistor connecting the other end and one end of the first resistor, the other end of the second resistor, one end of the third resistor, and the first Connected to the anode region, connected to the other end of the resistor and the negative voltage input terminal, connected to the first cathode region and the ground of the power source, connected to one end of the second resistor and the second cathode region, and second anode A connection point between the first resistor and the second resistor, a first cathode region and the first diffusion region, a second cathode region and a second diffusion region, and a connection point between the first resistor and the second resistor; And an input point of the control circuit are connected to each other.
JP2001328573A 2001-10-26 2001-10-26 Semiconductor integrated circuit device Expired - Lifetime JP3772727B2 (en)

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