JP3764964B2 - Expansion board controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an expansion board control apparatus that connects a plurality of expansion boards, or connects a single expansion board when a plurality of expansion boards can be connected, and exchanges data with the expansion board.
[0002]
[Prior art]
Expansion of RAM in personal computers and expansion of LAN boards and centro boards in printing apparatuses are widely performed today. Use of such an expansion board is used for expansion of a memory or expansion of a printing function, and usually one or two expansion boards are used.
[0003]
The board controller controls data input / output with the expansion board. The board control device performs input / output control of data with the expansion board, and at that time, requests the CPU (MPU) to permit direct memory access (DMA) for data transfer. Data exchange between the expansion board and the board control device is performed via a buffer.
[0004]
In such an expansion board control device, (a) the buffer uses a dedicated buffer for each expansion board to be connected, and when one expansion board is connected, a dedicated buffer corresponding to the expansion board is used. When two expansion boards are connected, their dedicated buffers are used to control data input / output.
[0005]
Also, (b) conventionally, when the expansion board control device performs direct memory access (DMA) processing for data transfer, the CPU (MPU) has forcibly provided an interval for a predetermined time to accept a request.
[0006]
[Problems to be solved by the invention]
However, the conventional apparatus has the following problems.
First, in the case of (b) above, since a dedicated buffer is used for each expansion board, it takes time to exchange data. For example, when only one board is connected even though it has two buffers, only one dedicated buffer can be used, and it takes time to exchange data. Also, even when two boards are connected, the use of the buffer is dedicated, so even though there is no data transfer to one board, an empty buffer cannot be used, It took time to give and receive.
[0007]
Furthermore, processing priorities are set in advance for a plurality of (for example, two) expansion boards, and it has not been possible to perform a reception process of data that is flexibly selected and input from the expansion boards.
[0008]
Therefore, in the conventional expansion board control device, the data transfer to the expansion board is extremely inefficient.
In the case of (b), when a direct memory access (DMA) request is made from the expansion board controller, an interval is forcibly provided for a predetermined time. Therefore, the data processing time is totally delayed and the data cannot be exchanged efficiently.
[0009]
The object of the present invention can be achieved by providing an expansion board control device that can efficiently use a plurality of buffers and perform data transfer processing at high speed.
[0018]
[Means for Solving the Problems]
  Claim1In order to solve the above-described problems, the described invention includes a first expansion board and a second expansion board.Selectively as neededIn the connectable expansion board controller, the first buffer, the second buffer, and either the first expansion board or the second expansion boardIf installed, it was installedAlternating output control means for alternately outputting data output from the expansion board to the first buffer and the second buffer;By the alternate output control meansAlternate transmission output means for alternately transmitting and outputting data stored in the first buffer and the second buffer;When both the first expansion board and the second expansion board are mounted, individual output control means for controlling output of data output from both expansion boards to the corresponding first buffer and second buffer, respectively. And individual transmission output means for individually transmitting and outputting the data stored in the first buffer and the second buffer by the individual output control means,This can be achieved by providing an expansion board control device characterized by comprising:
[0019]
  In the invention of this example, the first expansion board and the second expansion board areSelectively as neededIn a connectable expansion board controller, even when a board is connected to only one expansion board, the first and second buffers are used alternately, and data transfer processing is efficiently performed by so-called double buffer processing. It is.
[0020]
In other words, since the conventional buffer is dedicated for each expansion board, data transfer processing is performed using only the buffer corresponding to the connected expansion board. By alternately using these, data can be written and read at the same time to efficiently perform data transfer processing.
[0021]
  Claim2Description of the claim1The data output by the transmission output means is supplied to, for example, a memory. This exampleInData stored in the expansion board is Centro data or LAN data. These data are alternately stored in the first and second buffers, and then supplied to a memory such as a RAM or an EEPROM by the transmission output means.
[0022]
  Claim3Is described in the above claim.1The data output from the transmission output unit to the memory is configured to be output by, for example, a direct memory access process.
[0023]
  That is, the data of the first expansion board or the second expansion board stored in the buffer is stored in the direct memory access process (DMA).InTherefore, it is written in the memory.
[0024]
Here, although not described in the above claims, when performing direct memory access (DMA), the expansion board control device of this example makes an access request to the MPU, for example, but at this time, a certain time interval is necessary. Met. For this reason, the data transfer rate to be transferred to the memory is increased, and a long time is required for the data transfer.
[0025]
Therefore, the following invention may be added. That is,
Request output means for requesting DMA transfer, counting means for detecting an inactive state of the MPU and counting a certain time after detecting the state, and after the DMA transfer request is output from the request output means, the counting means Provides an expansion board control device having a HOLD signal output means for outputting a HOLD signal upon completion of counting for a predetermined time, and a means for outputting a DMA transfer permission signal after the HOLD signal output means outputs the HOLD signal. To do.
[0026]
By using the expansion board controller configured as described above, data stored in the buffer can be transferred to a memory or the like in a shorter time, and data transfer using direct memory access (DMA) can be performed at higher speed.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings.
<< First Embodiment >>
FIG. 2 is a diagram for explaining the expansion board control device of the present invention, and is a system configuration diagram showing an example in which the expansion board control device of the present invention is applied to a printer device.
[0028]
In FIG. 1, a printer apparatus 1 includes an interface controller (hereinafter referred to as an I / F controller) 2 and a printing apparatus (engine) 3 connected to the I / F controller 2. The I / F controller 2 includes a personal computer. 4 is connected.
[0029]
The I / F controller 2 has a function of creating one-to-one bitmap data corresponding to recording paper in accordance with print information output from the personal computer 4, and includes an MPU 5, ROM 6, RAM 7, an operation panel control unit 8, an image The control unit 9, engine control unit 10, memory control unit 11, DMA control unit 12, expansion board control unit 13, and interface unit 14 are configured. Each part in the I / F controller 2 is connected by a bus line.
[0030]
Here, the above-described expansion board control unit 13 corresponds to the expansion board control apparatus of the present invention, and one of the expansion boards 15 and 16 or the expansion boards 15 and 16 is connected to the expansion board control unit 13. Parallel centro data or LAN data is input from the expansion board 15 and stored in the RAM 7 described above. Note that the centro data or LAN data stored in the RAM 7 is converted into, for example, bitmap data by the I / F controller 2 in the same manner as the data input from the personal computer 4.
[0031]
The MPU 5 is a microprocessor unit that performs print control of the printer apparatus 1 of this example, and performs print control according to a program stored in the ROM 6. The RAM 7 has a work area when the MPU 5 performs print processing, and also has a storage area for storing data input via the personal computer 4 and the expansion board control unit 13 described above.
[0032]
The operation panel control unit 8 outputs a key operation signal supplied from an operation panel (not shown) to the MPU 5 to execute processing instructed by the operator. The engine control unit 10 outputs a control signal to each unit in the printing apparatus (engine) 3, such as a transfer unit, a printing unit, a developing unit, and the like, and performs drive control of each unit.
[0033]
Although not shown, the printing apparatus 3 includes a paper transport mechanism, an image forming unit, a fixing unit, and the like. The paper transport mechanism sends the paper transported from the paper feed cassette to the standby roll via the paper transport path, For example, the paper is supplied onto the conveyance belt at the same timing as the toner image formed on the photosensitive drum. Further, while the sheet moves on the conveyance belt, a toner image is transferred from the image forming unit to the sheet on the conveyance belt, and a transfer process to the sheet is performed. Thereafter, a heat fixing process is performed by the fixing unit, and the sheet is discharged out of the apparatus by a sheet discharge roll.
[0034]
On the other hand, the memory control unit 11 and the DMA control unit 12 together with the above-described expansion board control unit 13 constitute an expansion board control device. The memory control unit 11 and the DMA control unit 12 perform memory control and data transfer control of the printer 1, and also perform data input / output control between the expansion boards 15 and 16 and the I / F controller 2.
[0035]
FIG. 1 is a diagram for explaining the configuration of the expansion board control device of this example. A memory control unit 11 and a DMA control unit 12 arranged on the main board A side (in FIG. A connection configuration of the expansion board control unit 13 and the two expansion boards 15 and 16 provided on the expansion board B side is shown.
[0036]
In the same figure, the expansion boards 15 and 16 are boards for inputting Centro data and LAN data as described above. For example, the expansion boards 15 and 16 are inserted into the expansion slots provided in the main board A so that the expansion boards 15 and 16 are expanded. It can be connected to the control unit 13. With this connection, the signal line and the data line between the expansion board control unit 13 and the expansion boards 15 and 16 are connected.
[0037]
For example, a data transmission request signal (Dreq1) is output from the expansion board 15 to the expansion board control unit 13 via this signal line, and a data transmission permission signal (Dack1) is output from the expansion board control unit 13 to the expansion board 15. . Similarly, the data transmission request signal (Dreq2) is output from the expansion board 16 to the expansion board control unit 13 via the signal line, and the data transmission permission signal (Dack2) is output from the expansion board control unit 13 to the expansion board 16. . Further, the 8-bit data D1 is output from the expansion board 15 to the expansion board control unit 13 via the data line, and the 8-bit data D1 'is output from the expansion board control unit 13 to the expansion board 15. Similarly, 8-bit data D2 is output from the expansion board 16 to the expansion board controller 13 via the data line, and 8-bit data D2 'is output from the expansion board controller 13 to the expansion board 16. The reason why the 8-bit data is output from the expansion board control unit 13 to the expansion boards 15 and 16 is that the data is output from the printer device 1 via the Centronics interface.
[0038]
On the other hand, the expansion board control unit 13 is connected to the memory control unit 11, the DMA control unit 12, and the memory (RAM) 7 via a bus line. In FIG. 1, as described above, the memory control unit 11 and the DMA control unit 12 are shown as one block by the memory / DMA control unit 18. Here, between the expansion board control unit 13 and the memory / DMA control unit 18, DMA (direct memory access) processing request signals (DMAreq 1) and (DMAreq 2) are sent from the expansion board control unit 13 to the memory / DMA control unit 18. And the DMA processing permission signals (DMAack1) and (DMAack2) are output from the memory / DMA control unit 18 to the expansion board control unit 13. Here, the above-mentioned request signal (DMAreq1) is a signal output when 64 bits of data supplied from the expansion board 15 are stored in a buffer, which will be described later, and the permission signal (DMAack1) is used when the above-mentioned request is permitted. This is an output signal. Similarly, the request signal (DMAreq2) is output when 64 bits of data supplied from the expansion board 16 are stored in a buffer described later, and the permission signal (DMAack2) is output when the above request is permitted. Signal.
[0039]
Data D output from the expansion board control unit 13 to the memory (RAM) 7 is data supplied from the expansion board 15 or 16 to the expansion board control unit 13, and 64-bit data is stored in the memory (RAM). ) Is output to 7. Conversely, the data D may be output from the memory (RAM) 7 to the expansion board control unit 13.
[0040]
The data a supplied from the memory / DMA control unit 18 to the memory (RAM) 7 is address data. When data is input from the expansion board control unit 13 or when data is output from the memory (RAM) 7. , Data specifying a write or read address in the memory (RAM) 7.
[0041]
Further, the HOLD signal output from the memory / DMA control unit 18 is a request signal for performing a DMA transfer process on the MPU 5, and the HOLDA signal is transmitted from the MPU 5 to the memory / DMA control unit 18. This signal is output when it is permitted to perform The data b supplied from the MPU 5 to the memory / DMA control unit 18 is address data, and the data d is actual data (data stored in the memory (RAM) 7 or data output from the memory (RAM) 7). ).
[0042]
FIG. 3 is a specific circuit diagram of the expansion board controller 13 described above. The expansion board control unit 13 includes a bus arbiter 20, board control units 21 and 22, buffers 23 and 24, an AND circuit 25, and a selector 26. As can be seen from the figure, the data transmission request signal (Dreq1) output from the expansion board control unit 13 is specifically output from the board control unit 21, and the data transmission permission signal (Dack1) is output from the board control unit. 21. Similarly, the data transmission request signal (Dreq2) output from the above-described expansion board control unit 13 is output from the board control unit 22, and the data transmission permission signal (Dack2) is input to the board control unit 22.
[0043]
The DMA processing request signal (DMAreq1) output from the expansion board control unit 13 to the memory / DMA control unit 18 is also output to the bus arbiter 20, and the permission signal (DMAack1) is also input to the bus arbiter 20. Similarly, a DMA processing request signal (DMAreq 2) output from the expansion board control unit 13 to the memory / DMA control unit 18 is also output to the bus arbiter 20, and a permission signal (DMAack 2) is also input to the bus arbiter 20.
[0044]
The buffers 23 and 24 are buffers corresponding to the expansion boards 15 and 16, respectively. The buffer 23 corresponds to the expansion board 15 and the buffer 24 corresponds to the expansion board 16. However, the buffers 23 and 24 only correspond to the expansion boards 15 and 16, respectively, and the corresponding expansion boards are not dedicated. Therefore, it is a structure which can be used freely depending on the case. For this reason, the write signal w1 is supplied from the board control unit 21 to the buffers 23 and 24 via the AND circuit 25, and the write signal w2 is supplied from the expansion board control unit 22 to the buffers 23 and 24 via the AND circuit 25. .
[0045]
The selector 26 is configured to select data output from the buffers 23 and 24 and output the data to the memory (RAM) 7 described above. From the selection signal S1 output from the board controller 21 or the board controller 22 Data selection processing is performed by the output selection signal S2. For example, when the selection signal S 1 is selected, the selector 26 outputs the data output from the buffer 23 to the memory (RAM) 7. Further, when the selection signal S2 is selected, the selector 26 is configured to output data output from the buffer 24 to the memory (RAM) 7.
[0046]
The processing operation of the expansion board control apparatus having the above configuration will be described below. The expansion board control device of this example has two expansion slots, and an expansion board can be attached to only one or both of them. Therefore, in the following description, a case where one expansion board is used and a case where two expansion boards are used will be described separately.
<< In the case of one expansion board >>
First, a case where one expansion board is used will be described. In this example, it is assumed that only the expansion board 15 is used.
[0047]
4 to 6 are diagrams for explaining this process. FIG. 4 is a process for storing the data D1 transmitted from the expansion board 15 in the buffers 23 and 24. FIG. 5 is a process for the bus arbiter 20 at that time. FIG. 6 is a flowchart showing the operation, in which data D1 stored in the two buffers 23 and 24 is DMA-transferred to the memory (RAM) 7.
[0048]
The data transmission request signal “Dreq1” (or “Dreq2”) is active when “0”, and inactive when “1”. The data transmission permission signal “Dack1” (or “Dack2”) is also active when “0”, and inactive when “1”.
[0049]
First, in the flowchart of FIG. 4, an initial setting process is performed (step (hereinafter referred to as S) 1). This initial setting processing is processing such as clearing data remaining in the buffers 23 and 24, setting the selector 26 to an initial position on the buffer 23 side, and clearing data remaining in the memory (RAM) 7, for example. In addition, flags “H” and “F” (not shown) are initialized to “0”, and the counter is initialized to “0”.
[0050]
After performing such processing, judgment (S2) is executed. This determination (S2) is a process for determining whether or not “H = 1”. This “H” is, for example, a flag in the board control unit 21, and when 64-bit data is stored in the buffer 23, The flag “H” becomes “1”. Specifically, the data D1 (8-bit data) is input from the expansion board 15 by the write signal W1 output from the board control unit 21, and the write signal W1 is output eight times to output 64-bit data to the buffer 23. Data is stored and flag “H” is set to “1”.
[0051]
However, the initial flag “H” is “0” (S2 is NO), and it is determined whether the data transmission request signal (Dreq1) is output from the expansion board 15 (S3). This data transmission request signal (Dreq1) is a signal that is output when the expansion board 15 desires to output data to the buffer 23. If there is no request, the data transmission request signal (Dreq1) waits for the input of the data transmission request signal (Dreq1) (S3 NO).
[0052]
On the other hand, when the data transmission request signal (Dreq1) is present (S3 is YES), the board control unit 21 outputs a data transmission permission signal (Dack1) to the expansion board 21 via the bus arbiter 20, and buffers the write signal W1. 23 (S4). By this process, 8-bit data is written in the buffer 23, and it is determined that the data transmission request signal (Dreq1) from the expansion board 15 has become “1” (S5 is YES), and further a data transmission permission signal (Dack1). ) Is set to “1” (S6).
[0053]
With the above process, the process of writing the 8-bit data to the buffer 23 is completed. For example, it is determined whether the counter provided in the board control unit 21 has counted up to “7”. In the first process, the counter value is “0”. Therefore, the counter value is incremented by 1 (S7 is NO, S8). By this processing, the count value of the counter becomes “1”, and the process returns to the above-described determination (S3) to determine the input of the data transmission request signal (Dreq1) (S3).
[0054]
Thereafter, the above processing is repeated (S3 to S8), data is written to the buffer 23 every 8 bits, and the counter value is added as “1” → “2” → “3”,. When “7” is set, the determination (S7) is YES, and the aforementioned flag “H” is set to “1” (S8 ′). That is, it is assumed that 64-bit data is stored in the buffer 23 by the above-described eight times of data supply, and the flag “H” is set in the board controller 21 (the flag “H” is “1”).
[0055]
Next, it is determined whether or not one expansion board is installed (S9). In the description of this example, since only the expansion board 15 is connected as described above, the determination (S9) is YES.
[0056]
Therefore, it is next determined whether or not the flag “F” is “1” (S10). This “F” is a flag that is set to “1” when 64-bit data is stored in the buffer 24. Since this flag is initially set as described above at the initial stage, the determination (S10) is NO, and it is then determined again whether there is a data transmission request signal (Dreq1) (S11). If there is no such request, it waits for the input of a data transmission request signal (Dreq1) (NO in S11).
[0057]
On the other hand, when the data transmission request signal (Dreq1) is present (S11 is YES), the board control unit 21 outputs the data transmission permission signal (Dack1) to the expansion board 21 via the bus arbiter 20 in the same manner as described above. The signal W1 is output to the buffer 24 (S12), and 8-bit data is written to the buffer 24. Then, it is determined that the data transmission request signal (Dreq1) from the expansion board 15 is “1” (S13 is YES), and the data transmission permission signal (Dack1) is set to “1” (S14). Thereafter, as described above, it is determined whether the counter has counted up to “15”. In the first process, the counter value is “7” described above, and the counter value is incremented by 1 (S15 is NO, S16). These processes are repeated (S11 to S16). Therefore, while the above processing is repeated, the counter value is added as “8” → “9” → “10”,..., And when the count value becomes “15”, the determination (S15) becomes YES, and The flag “F” is set to “1” (S17). That is, 64-bit data is stored in the buffer 24 by supplying data eight times, and the above-described flag “F” is set in the board control unit 21 (the flag “F” is set to “1”).
[0058]
By controlling as described above, the data output from the expansion board 15 is first stored in the buffer 23 with 64-bit data, and then in the buffer 24 with 64-bit data. Thereafter, by performing the same control, the processing of the flowchart shown in FIG. 4 is repeated again, and the data output from the expansion board 21 is alternately stored in the buffer 23 and the buffer 24.
[0059]
Therefore, by repeating the above processing, the data is alternately supplied to the buffer 23 and the buffer 24, and the data is output from the non-supply side buffer 24 or the buffer 23 as described later, thereby efficiently transferring the data. Can do. The data transfer processing from the buffers 23 and 24 will be described later with reference to the flowchart of FIG.
[0060]
On the other hand, FIG. 5 shows the data storage processing in the buffers 23 and 24 as seen from the bus arbiter 20, and first, initial setting processing (step (hereinafter referred to as ST) 1) is performed. This process is the same as the above-described initial setting process (S1), and the data in the bus arbiter 20 is cleared.
[0061]
Next, the input of the data transmission request signal (Dreq1) is determined (ST2). If the data transmission request signal (Dreq1) is supplied from the expansion board 15 or 16 to the board control unit 21 or 22, it is determined whether only one expansion board is mounted (ST3). Here, in the description of this example, since the board is connected only to the expansion board 15 (ST3 is YES), it is assumed that the data transmission request signal (Dreq1) is output from the board control unit 21 (ST4). Then, the output of the data transmission permission signal (Dack1) to the expansion board 15 is confirmed (ST5), the transmission signal and the permission signal are set to 1, and the process is terminated (ST6, ST7).
[0062]
Next, it is determined whether or not the data transmission request signal (Dreq2) is output from the expansion board 16 (ST8). In the description of this example, since the expansion board is not connected to the expansion board 16, the determination (ST8) NO, returning to the above process, the same process is repeated (ST2 to ST8). That is, the bus arbiter 20 stores data alternately in the buffers 23 and 24 by the above-described processing.
Next, a data transfer processing operation for outputting the data D1 stored in the two buffers 23 and 24 to the memory (RAM) 7 will be described. The 64-bit data stored in the buffers 23 and 24 is transferred to the memory (RAM) 7 according to the processing shown in FIG.
[0063]
First, as in the above example, initial setting processing is performed (step (hereinafter referred to as STP) 1). Next, the board control unit 21 determines whether the flag “H” is “1” (STP2). Here, when the flag “H” is “1”, it indicates that the 64-bit data has already been stored in the buffer 23 as described above, and the board controller 21 sends the data to the memory / DMA controller 18. On the other hand, a request signal (DMAreq1) is output (STP3).
[0064]
In response to the input of this request signal (DMAreq1), the memory / DMA control unit 18 outputs a HOLD signal to the MPU 5 and waits for the MPU 5 to output a HOLDA signal. When this signal is supplied from the MPU 5, the MPU 5 determines that the bus has been released for DMA processing, and the memory / DMA control unit 18 returns a permission signal (DMAack1) to the board control unit 21 (STP4). .
[0065]
When this data transmission permission signal (DMAack1) is input, the board controller 21 DMA-transfers the 64-bit data stored in the buffer 23 to the memory (RAM) 7. Thereafter, the output of the data transmission request signal (DMAreq1) is stopped (STP5), it is determined that the output of the data transmission permission signal (Dack1) is stopped (STP6 is YES), and the flag “H” is set to “0”. (STP7).
[0066]
Next, the board control unit 21 determines whether the flag “F” is “1” (STP8). At this time, since the 64-bit data is stored in the buffer 24 as described above, the flag “F” is “1” (YES in STP8), and the board control unit 21 sends the data to the memory / DMA control unit 18. On the other hand, a request signal (DMAreq1) is output (STP9).
[0067]
In response to the output of this request signal (DMAreq1), the memory / DMA control unit 18 outputs a HOLD signal to the MPU 5, as described above. When the HOLDA signal is output from the MPU 5, the MPU 5 uses the bus for DMA processing. The memory / DMA control unit 18 determines that it has been released, and returns a permission signal (DMAack1) to the board control unit 21 (YES in STP10).
[0068]
When this data transmission permission signal (DMAack1) is input, the board controller 21 DMA-transfers the 64-bit data stored in the buffer 24 to the memory (RAM) 7 as described above, and stops outputting the request signal (DMAreq1). (STP11) Further, it is determined that the output of the permission signal (DMAack1) is stopped (STP12 is YES), and the flag “F” is set to “0” (STP13).
[0069]
As described above, when only one expansion board is used, the buffers 23 and 24 are alternately used, and the data supplied from the expansion board 15 is alternately stored in the buffers 23 and 24. By efficiently outputting the data stored in 24 to the memory (RAM) 7, efficient data transfer can be performed.
<< When there are two expansion boards >>
Next, a case where two expansion boards are used will be described. Also in this case, the flowcharts of FIGS. 4 and 5 are used. However, the flowchart of FIG. 6 is not used. Hereinafter, a specific processing operation will be described.
[0070]
First, in the flowchart of FIG. 4, the same initial setting process as described above is performed (S1). Next, it is determined whether or not “H = 1” (S2). As described above, the initial flag “H” is “0” (S2 is NO), and the data transmission request signal (S2 is NO). It is determined whether or not (Dreq1) is output (S3). This data transmission request signal (Dreq1) is a signal output when the expansion board 15 desires to output data to the buffer 23, and stores 64-bit data in the buffer 23 while counting up the counter as described above. (S2-S8). In this way, 64-bit data is stored in the buffer 23, and the flag “H” is set to “1” (S8 ′).
[0071]
Next, it is determined whether or not one expansion board is installed (S9). In the description of this example, since there are two sheets, the determination (S9) is NO, and the determination of the flag “H” = “1” is performed again. Thereafter, every time a data transmission request signal (Dreq1) is output from the expansion board 15, 64-bit data is stored in the buffer 23.
[0072]
Further, the above-described processing is an explanation for the data output from the expansion board 15. When the data transmission request signal (Dreq2) is input from the expansion board 16 in the same manner, the buffer 24 is processed by the same processing as described above. 64-bit data is written.
[0073]
In the flowchart shown in FIG. 5, the writing process to the above-described buffers 23 and 24 will be described. After the initial setting process (ST1), the input of the data transmission request signal (Dreq1) is determined (ST2) and connected. It is determined whether there is only one expansion board (ST3). Here, since the two expansion boards 15 and 16 are connected in the description of this example (ST3 is NO), the determination (ST4 ') is executed. This determination is to determine whether a request signal (DMAreq1) or a permission signal (DMAack1) is output to the memory / DMA control unit 18 described above. If the data is exchanged between the two, the data stored in the buffer 23 is being DMA-transferred, so the data storage processing in the new buffer 23 is not performed (NO in ST4 ′).
[0074]
On the other hand, if the data stored in the buffer 23 is not being DMA-transferred (ST4 'is Y), 64-bit data is stored from the expansion board 15 to the buffer 23 as described above (ST2 to ST8).
[0075]
Next, it is determined whether a data transmission request signal (Dreq2) is output from the expansion board 16 (ST8). In this example, since two expansion boards are connected, a data transmission request signal (Dreq2) may be input. Therefore, when there is a data transmission request signal (Dreq2) from the expansion board 16 (YES in ST8), it is determined whether there is one expansion board (ST9), and in this example, two expansion boards are connected. Therefore, as described above, the board control unit 22 outputs a request signal (DMAreq2) and a permission signal (DMAack2) to the memory / DMA control unit 18, and determines whether or not DMA transfer processing is in progress (ST10). If the DMA transfer is in progress, the new data is not stored in the buffer 24 (NO in ST10).
[0076]
On the other hand, if the data stored in the buffer 24 is not undergoing DMA transfer, 64-bit data is stored in the buffer 24 from the expansion board 16 as described above (ST11 to ST14).
[0077]
As described above, when a plurality of expansion boards 15 and 16 are connected, data from the expansion board having a data transmission request signal (Dreq) is preferentially stored in the corresponding buffer 23 or 24, and the buffer 23 , 24 are used efficiently.
[0078]
Finally, data transfer processing for outputting the data D1 and D2 stored in the two buffers 23 and 24 to the memory (RAM) 7 is performed. Although this process is not particularly shown in the flowchart, it is driven when 64-bit data is stored in the buffer 23 or 24 and the flag “H” or “F” is set to “1”. For example, when 64-bit data is stored in the buffer 23, a flag “H” is set in the board control unit 21, and data is transferred from the buffer 23 to the memory (RAM) 7 based on the setting of the flag. On the other hand, when 64-bit data is stored in the buffer 24, the flag “F” is set in the expansion board control unit 22, and the data is DMA-transferred from the buffer 24 to the memory (RAM) 7 based on the setting of this flag. .
[0079]
From the above control, in this example, 64-bit data is stored in the buffer 23 or 24, and a request signal (DMAreq1) is output from the expansion board controller 21 or 22 corresponding to the buffer in which the 64-bit data is stored. In other words, data is transmitted from the buffer 23 or 24 to the memory (RAM) 7.
[0080]
With this configuration, it is possible to efficiently use the buffers 23 and 24 and perform data transfer processing.
<Second Embodiment>
Next, a second embodiment will be described.
[0081]
FIG. 7 is a diagram for explaining the second embodiment. The basic configuration of this example is the same as that of FIG. 2 used in the description of the first embodiment. Therefore, the expansion board control device of the present invention is applied to the printer device 1, and the printer device 1 is composed of an I / F controller 2 and a printing device (engine) 3 connected to the I / F controller 2. Is connected to a personal computer 4. Further, the I / F controller 2 has a function of creating bitmap data corresponding to the recording paper on a one-to-one basis in accordance with the print information output from the personal computer 4. The MPU 5, ROM 6, RAM 7, and operation panel controller 8 , An image control unit 9, an engine control unit 10, a memory control unit 11, a DMA control unit 12, an expansion board control unit 13, and an interface unit 14.
[0082]
Here, the above-described expansion board control unit 13 corresponds to the expansion board control device of the present invention, and expansion boards 15 and 16 are connected to the expansion board control unit 13. The MPU 5 is a microprocessor unit that performs print control of the printer apparatus 1 of the present example, as in the above-described embodiment, and performs print control according to a program stored in the ROM 6.
[0083]
Here, a specific configuration of the expansion board control device used in this example will be described with reference to FIG. The expansion board 15 (or 16) is connected to the main board A, and the expansion board control unit 13 has the same configuration as described above. A request signal (REQ) is output from the expansion board 15 (or 16), and an acknowledge signal (ACK) and address data are output from the expansion board control unit 13 to the expansion board 15 (or 16). Data D is exchanged between the expansion board 15 (or 16) and the expansion board control unit 13.
[0084]
Here, the request signal (REQ) corresponds to the data transmission request signal (Dreq1 (or Dreq2)), and the acknowledge signal (ACK) corresponds to the data transmission permission signal (Dack1 (Dack2)). .
[0085]
On the other hand, the expansion board control unit 13 outputs a HOLD signal to the MPU 5, and the MPU 5 outputs a HOLDA signal to the expansion board control unit 13. The HOLD signal described above is a signal for requesting permission of direct memory access (DMA) transfer to the MPU 5, and the HOLDA signal is a response signal.
[0086]
FIG. 8 shows a circuit configuration in the expansion board controller 13 which is a feature of this example. However, the expansion board control unit 13 is not, of course, constituted only by the circuit shown in FIG. In the figure, an interval setting circuit 32 including a NAND gate 30 and a timer 31 is provided. The interval setting circuit 32 counts the time from when the HOLDA signal output from the MPU 5 becomes inactive, counts a certain interval time, and then outputs the HOLD signal to the MPU 5 on condition that the request signal (REQ) is output. The circuit that outputs to Specifically, the timer 31 is driven from the time when the HOLDA signal output from the MPU 5 becomes inactive, the interval time set in the timer 31 is counted and output to the NAND gate 30. When the time-up signal is input from the timer 31 and the request signal (REQ) is also input to the NAND gate 30, the NAND gate 30 outputs a HOLD signal to the MPU 5. The HOLD signal is a DMA transfer request to the MPU 5. When the HOLD signal is input, the MPU 5 then outputs the HOLDA signal to the expansion board control unit 13. This HOLDA signal functions as an acknowledge signal (ACK) to the expansion board control unit 13.
[0087]
Further, the expansion board control unit 13 is also provided with a buffer 33 to temporarily hold the address data output from the MPU 5. In addition, the counter 34 provided in the expansion board control unit 13 is a counter for counting data every 8 bits at the time of data transmission / reception and outputting the data as, for example, 64-bit data.
[0088]
The processing operation of the second embodiment having the above configuration will be described below.
FIG. 9A is a time chart for explaining the processing operation of this example. First, when a request signal (REQ) is output from the expansion board 15 (or 16), the expansion board control unit 13 outputs a HOLD signal to the MPU 5. Thereafter, when the HOLDA signal output from the MPU 5 becomes inactive, the timer 31 detects this and counts for a certain interval time (t). Therefore, the HOLDA signal becomes active in a short time thereafter, and the output timing of the acknowledge signal (ACK) can be advanced.
[0089]
That is, FIG. 9B shows a time chart of the processing operation in the conventional case, and since the fixed time (t) is counted after the output stop of the request signal (REQ), the end time of the output of the HOLD signal is counted. Therefore, the supply timing of the HOLDA signal output from the MPU 5 is also delayed.
[0090]
As described above, in the conventional example, the output of the HOLDA signal output from the MPU 5 is delayed, and the delay leads to a delay in data processing in total. However, according to the present example, after the HOLDA signal becomes inactive, a predetermined interval time (t) is counted in advance by the timer 31. Therefore, after the HOLD signal is output, the HOLDA signal (acknowledge signal ( ACK)) can be output to the expansion board controller 13, and data transfer can be performed at high speed.
[0091]
【The invention's effect】
As described above, according to the present invention, the following effects occur.
According to one aspect of the invention, even when a plurality of expansion boards are connected, it is possible to efficiently use the buffer and perform efficient data transmission / reception processing.
[0092]
According to one invention, when a plurality of expansion boards can be connected, when only one expansion board is connected, buffers can be used alternately to perform efficient data transmission / reception processing. .
[0093]
  In addition, DMABy counting the interval time in advance, the output timing of the transfer permission signal is advanced, and the total DMATransfer processing can be performed at high speed.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a board control apparatus according to an embodiment.
FIG. 2 is a system configuration diagram of the printer apparatus showing an example in which the expansion board control apparatus according to the embodiment is applied to the printer apparatus.
FIG. 3 is a specific circuit diagram of an expansion board control unit.
FIG. 4 is a flowchart illustrating a writing process of an expansion board control unit.
FIG. 5 is a flowchart showing the processing operation of the bus arbiter.
FIG. 6 is a flowchart illustrating DMA processing of an expansion board control unit.
FIG. 7 is a diagram for explaining a second embodiment.
FIG. 8 is a time chart of a delay circuit showing a circuit configuration in the extension board control unit;
9A is a time chart for explaining the processing operation of this example, and FIG. 9B is a time chart for the processing operation in the conventional case.
[Explanation of symbols]
1 Printer device
2 I / F controller
3 Printing device (engine)
4 Personal computer
5 MPU
6 ROM
7 RAM
8 Operation panel controller
9 Image controller
10 Engine control unit
11 Memory controller
12 DMA controller
13 Expansion board controller
14 Interface controller
15, 16 Expansion board
18 Memory / DMA controller
30 Nand Gate
31 timer
32 Interval setting circuit
33 buffers
34 counters

Claims (3)

In the expansion board control device in which the first expansion board and the second expansion board can be selectively connected as necessary ,
A first buffer;
A second buffer;
When either the first expansion board or the second expansion board is mounted, the data output from the mounted expansion board is alternately output to the first buffer and the second buffer. Alternating output control means;
Alternate transmission output means for alternately transmitting and outputting data stored in the first buffer and the second buffer by the alternate output control means ;
When both the first expansion board and the second expansion board are mounted, individual output control means for controlling output of data output from both expansion boards to the corresponding first buffer and second buffer, respectively. When,
Individual transmission output means for individually transmitting and outputting the data stored in the first buffer and the second buffer by the individual output control means;
An expansion board control device comprising: Data to which the alternating transmission output means and the individual transmission output means outputs the expansion board control apparatus according to claim 1, characterized in that it is supplied to the memory. Data to which the alternating transmission output means and the individual transmission output means outputs to said memory expansion board control device according to claim 1, wherein the output in accordance with a direct memory access process.

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