JP3762831B2 - Information recording / reproducing circuit and information recording / reproducing apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information recording / reproducing method, an information recording / reproducing circuit, and an information recording / reproducing apparatus using the same for realizing high-density and high-reliability digital information recording / reproducing.
[0002]
[Prior art]
In a high-density information recording / reproducing system / apparatus, in order to improve the reliability of data reproduction from a low-quality recording / reproducing signal obtained from a recording medium, a maximum likelihood sequence estimation method or maximum likelihood sequence detection (MLSD: Maximum- Data decoding technology using Likelihood Sequence Detection) is widely used, which is a technology that has been widely used as an effective means of error correction decoding methods such as convolutional codes in the communication field.
[0003]
This maximum likelihood sequence detection is a technique for minimizing the probability of error occurrence in a decoded code sequence by estimating the decoded code sequence in time series using the memory or correlation of the decoded data. When the sequence {Y (n)} (n is an integer indicating the discrete signal generation order and time) is given to the decoding input, the signal from all possible recorded information (code) sequences {X (n)} A sequence (maximum likelihood sequence) having the greatest likelihood (likelihood) that the sequence {Y (n)} is reproduced is selected and output as a decoded information (code) sequence {Z (n)}. That is, the maximum likelihood sequence decoder receives the entire sequence of a certain reproduced signal sequence {Y (n)}, under the condition that a certain recorded information (code) sequence {X (n)} is assumed. The recorded information (code) sequence {X (n) is maximized so that the posterior prior probability P [{Y (n)} / {X (n)}] that the reproduced signal sequence {Y (n)} is received and reproduced is maximized. )} Is selected, and maximum likelihood sequence estimation of the decoded information (code) sequence {Z (n)} is performed. At this time, the recorded information (code) sequence {X (n)} is not estimated independently of each other but estimated in the context thereof. Such maximum likelihood sequence detection is performed under the condition that all possible recorded information (code) sequences {X (n)} are recorded with equal probability, in other words, each recorded information (code) sequence {X (n) } Under the condition that no information on the probability of occurrence of \ is given at the time of decoding, the correct decoding probability P [{X (n)} & {Z (n)}] (recorded information (code) sequence {X (n)} And the decoding information (code) sequence {probability of matching {Z (n)}) are maximized to provide decoding with the best decoding error probability.
[0004]
This maximum likelihood sequence detection is efficiently realized by using a Viterbi algorithm in a dynamic programming format. As a paper on maximum likelihood sequence detection and Viterbi algorithm, Day. Forney, “The Viterbi Algorithm,” GDForney, “The Viterbi Algorithm”, Proceedings of the IEEE, vol.61, No.3, March 1973, pp.268-278 And G. Ungerbock, “Adaptive Maximum-Likelihood Receiver for Carrer-Modulated Data Transmission Systems”, G.E. IEEE Transactions on Communications), vol.COM-22, No.5, May 1974, pp.624-638. These papers are based on the reception / playback apparatus using maximum likelihood sequence detection or a part of it. Indicates the format. The practical means of implementing the Viterbi algorithm is Feeling Row, “Implementing the Vitrbi Algoithm”, “Implementing the Vitrbi Algoithm”, Hui-Ling Lou, “Implementing the Vitrbi Algoithm”, IEEE Signal Processing Magazine), Sept. 1995, pp. 42-52, and G. Fetway's End H. Meir, “High-Speed Parallel Viterbi Decoding: Algorithm and VIE Architecture”, G. Fettweis and H. Meyr, “High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture ", IEEE Communications Magazine), May 1991, pp.46-55.
[0005]
Such maximum likelihood sequence estimation methods and maximum likelihood sequence detection technologies are rapidly spreading and developing through application to information communication systems and transmission systems, in order to ensure the reliability of information transmission and maintain communication quality. Plays a big role. Further, as disclosed in US Pat. No. 203413 and the like, it has been widely applied to high-density information reproducing systems, and PRML (combination of partial response transmission waveform equalization technology and maximum likelihood sequence detection technology). The Partial-Response Maximum-Likelihood) method is remarkably put to practical use as a typical known technique.
[0006]
In order to further improve the noise resistance performance and the decoding reliability in the data decoding technology using the maximum likelihood sequence detection technology, the trellis coding / modulation technology and the expanded partial response transmission have been conventionally used. Attempts have been made to positively apply technology. As described above, in the maximum likelihood sequence detection, a sequence (maximum likelihood sequence) having the highest likelihood (likelihood) to be received and reproduced is selected from the context of the reproduced signal sequence, and this is most likely decoded information (code). Output as a sequence and use as decoding result. For this reason, in the known technology as described above, various constraint conditions and storage elements are added to the information transmission path of the recording code sequence and the recording / reproducing system by the encoding / modulation technology and the extended partial response, and the correlation of the decoded data is increased. By increasing the Euclidean signal distance (likelihood difference) between reproduced signal sequences for all recorded code sequences, the discriminating margin for noise of the likelihood difference is intended to be expanded.
[0007]
In addition, in order to ensure the desired decoding reliability in the information recording / reproducing apparatus and information transmission apparatus, error correction coding technology has been actively introduced, including Reed-Solomon code, extremely high error correction capability, In addition, a highly practical encoding / decoding method has been developed, and this has been introduced into high-density information recording / reproducing systems and high-speed information transmission systems. Reliability has improved dramatically.
[0008]
[Problems to be solved by the invention]
Under an information recording / reproducing system whose recording density is increasing, the quality of the reproduced signal is increasingly deteriorated and the reliability of data demodulation is lowered. Therefore, it is required to further improve the noise resistance performance in the data reproducing means using the conventional maximum likelihood sequence detection. The application of the trellis coding / modulation technique and the extended partial response transmission equalization technique as described above produces gains due to the Euclidean signal distance expansion of the received signal sequence, while various constraints on the transmission code sequence and transmission signal sequence. The addition of conditions causes an increase in redundancy in the recorded information (code) sequence. For this reason, in application to high-speed and high-density information recording / reproducing systems such as magnetic disk devices, the loss of recorded information due to the increased redundancy of the recorded information series, and the narrow band recording / reproducing system signal transmission path The reproduction signal is deteriorated due to a large signal band loss, which is not always an effective method. Furthermore, such a technique often requires an excessively complicated recording code processing circuit or an additional circuit, and a decoder based on maximum likelihood sequence detection is exponential in order to take into account the increased correlation of decoded data. A large circuit scale requirement cannot be avoided, and a great amount of hardware resources are required. In addition, the maximum likelihood sequence detection technique can provide high reliability by detecting from the context of the reproduced signal sequence, but when a detection error occurs, this causes decoding error propagation due to the sequence error. Often, it produces a burst of continuous code error propagation. This causes a significant loss in the correction capability of the error correction code used together, and lowers the data demodulation reliability in the entire recording / reproducing system / recording / reproducing apparatus. Also, due to this, in order to improve the reliability of data decoding by maximum likelihood sequence detection using an error correction code, an extremely strong error correction capability is required. This promotes the complexity of the error correction code and the increase in redundancy, and also hinders the realization of an effective and economical highly reliable data decoding means.
[0009]
An object of the present invention is to efficiently improve the maximum likelihood decoding error rate (decoding reliability) in data decoding of an information recording / reproducing signal by such maximum likelihood sequence detection technology, and to provide simple and simple means and hardware. It is to provide means for realizing this by using resources and circuits. In the present invention, by combining the maximum likelihood sequence decoding method and the error correction coding technology positively and effectively, higher data decoding can be achieved while keeping coding redundancy low and maintaining a simple implementation configuration. An information recording / reproducing method, an information recording / reproducing circuit, and an information recording / reproducing apparatus using the same are provided.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention positively utilizes the characteristics of the decoding sequence error in the maximum likelihood sequence decoding method, unlike the prior art. In general, error correction coding can improve the correction capability or simplify the correction process by knowing information related to the target code error event in advance and then decoding and coding. . In the present invention, the error correction encoding / decoding means is connected to the maximum likelihood sequence decoding method, thereby utilizing the characteristics of the decoding error event in the maximum likelihood sequence decoding method, and using the error correction encoding with low redundancy. Provide a means to realize highly efficient error correction and high reliability improvement.
[0011]
Since the decoding error event in the maximum likelihood sequence decoding is determined depending on the likelihood difference between the transmission (recording) code sequences corresponding to the Euclidean signal distance between the reception (reproduction) signal sequences, the sequence decoding error is determined. In the decoding code error pattern, a large deviation occurs in the occurrence probability frequency. In the present invention, attention is paid to this, and further, since an error event due to such a high-frequency specific decoding code error pattern (code error syndrome) dominates the maximum likelihood decoding error probability, And a means for combining an error correction coding method for performing a limited error correction process for a sequence error having a decoding code error pattern (code error syndrome) having a high probability of occurrence with this maximum likelihood sequence decoding. . By limiting the decoding code error pattern (code error syndrome) to be corrected in this way, the error correction coding method can be configured with a very simple and low redundancy. In addition, the error probability in the maximum likelihood decoding can be improved efficiently by preferentially performing the correction process from the frequently occurring decoding error event.
[0012]
Furthermore, on the decoded code sequence from the maximum likelihood sequence decoding, a sequence decoding error event (burst-type code error event) having a decoding code error pattern (code error syndrome) as described above is randomly generated under random noise conditions. Note the distribution. In other words, it takes advantage of the fact that it is extremely rare for sequence-like random error events that dominate the decoding error probability to concentrate at short intervals. Therefore, a predetermined number of decoding code sequence sections (decoded code sequence blocks) that are significant in improving the maximum likelihood decoding error probability compared to the average occurrence interval of each sequence decoding error event. An error correction coding method is provided so that the above error correction processing is performed only up to error events. That is, the error correction encoding method can be configured for the purpose of detecting and correcting only an average random error event according to a specific decoding code error pattern (code error syndrome), which is lower than that of the known technique. It can be realized with redundancy and a simple configuration. In the present invention, an error code by error correction coding configured as described above is inserted and added into a data code to be recorded and reproduced, and decoding code error correction processing using this is effectively performed with maximum likelihood decoding error characteristics. By implementing an error correction decoder directly connected to the decoding output of the maximum likelihood sequence decoder so that it can be utilized, the most effective maximum likelihood decoding error probability can be obtained with efficient error correction coding redundancy. There are means to improve.
[0013]
As described above, in the present invention, by utilizing the characteristics of the decoding sequence error in the maximum likelihood sequence decoding method, by means of an active combination in which the error correction encoding / decoding method and the maximum likelihood sequence decoding are efficiently connected, Provided are an information recording / reproducing method and an information recording / reproducing circuit / information recording / reproducing apparatus realizing method for effectively improving the decoding reliability. Further, in the present invention, attention is paid to the fact that a decoding sequence error in the maximum likelihood sequence decoding method as described above occurs depending on a specific recording code sequence / decoded code sequence pattern, or The error correction encoding / decoding method is further improved by actively using a modulation modulation process to limit the occurrence points of the high-frequency decoded code error pattern (code error syndrome) error event on the decoded code sequence. Provide a means to realize simply and with high reliability. In addition, by using a complementary combination of the second error correction coding method for the purpose of correcting burst errors due to random noise and the error correction coding method, error detection by the error correction coding / decoding method can be utilized. By implementing the second error correction encoding / decoding method in which the locations of error code positions are limited, data demodulation reliability of the information recording / reproducing method, information recording / reproducing circuit / information recording / reproducing apparatus provided by the present invention is provided. A means for improving the efficiency more efficiently and effectively is disclosed.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention are deeply related to the maximum likelihood sequence decoding / detection method (maximum likelihood sequence estimation method) in the reproduction of digital data and the use of the decoder / decoding device using the method, and this maximum likelihood sequence decoding and The principle is generally widely implemented using a Viterbi algorithm or the like. In order to show an embodiment of the present invention, first, an outline of a maximum likelihood sequence decoder based on the Viterbi algorithm will be described with reference to FIGS. In general, the information processing flow in the information recording / reproducing system is similar to that in the information transmission system, and can be described using common processing components and flow.
[0015]
FIG. 10A shows an outline of a general flow of an information sequence in the information transmission system and the recording / reproducing system. In a transmission or recording process, a transmission code sequence {X (k)} 100 (k is a natural number indicating time on the sequence) that is transmission or recording information is added with a predetermined constraint condition by the encoder 102. The signal is converted into a signal information sequence in an analog or digital format that can be transmitted through the channel 104 by the modulator 103 and output to the channel 104. The channel 104 is an information transmission medium including a transmission or recording medium, a transducer sensor, and the like. In particular, in the information storage / reproduction apparatus, the modulator 103 transmits a transmission code sequence {X (k)} 100 that is recording information. The channel 104 corresponds to a recording / reproducing system including a recording head, an information storage medium, and a reproducing head. In addition, an additional noise 105 is added to the signal in the transmission process, which makes the decoding from the received (decoded input) signal sequence {Y (k)} 107 to the original information uncertain in the reception or reproduction process. To do. In the reception or reproduction process, the signal output from the channel 104 is subjected to predetermined processing such as signal amplification, filtering, and waveform equalization by the reception signal processing circuit 106, and then received (decoded input). Decoding from the signal sequence {Y (k)} 107 to the decoded code sequence {Z (k)} 109 is performed via the maximum likelihood sequence decoder 108. The maximum likelihood sequence decoder 108 corresponds to the transmission code sequence {X (k)} 100 which is the original transmission or recording information, and estimates the most likely decoded code sequence {Z (k)} 109 for this. I do.
[0016]
For the maximum likelihood sequence decoder 108, various storage elements may exist in the information transmission system 101, which is a pre-processing process from the encoder 102 to the reception signal processing circuit 106. For example, in the encoder 102, in order to perform decoding error detection / correction using a convolutional code, a trellis code, or the like, or to give the transmission code some constraint necessary in the transmission process such as run length limitation, In some cases, redundancy is intentionally added to the transmission code sequence {X (k)} 100 by convolution processing or mapping processing of input / output codes of the encoder 102 sequentially stored in a finite number of storage elements. In the transmission process from the modulator 103 to the received signal processing circuit 106, there may be a storage element on the channel due to addition of natural or intentional intersymbol interference. When such a storage element exists in each process of the information transmission system 101, each value of the received signal sequence {Y (k)} 107 is each value of the corresponding transmission code sequence {X (k)} 100. Is determined in correspondence with the state in the storage element depending on the history of the transmission code sequence {X (k)} 100 at each time. The maximum likelihood sequence decoder 108 estimates the transition of the internal state held by the storage element on the information transmission system 101 and utilizes the storage performance (redundancy) of the transmission system, so that the reliability of the decoding process for noise can be improved. Thus, the reception / reproduction side can provide a more accurate decoded code sequence {Z (k)} 109 with respect to the transmission code sequence {X (k)} 100.
[0017]
FIG. 10C shows the received signal sequence {Y (k)} 107 and the transmission code sequence {X (k)} 100 and the storage on the information transmission system 101 in the transmission channel model shown in FIG. It is an example of the Markov state transition diagram model which showed the correspondence with the state in an element. In this state transition diagram example, the information transmission system 101 can be equivalently represented by a model with three 1-bit delay storage elements 110a to 110c (D1, D2, D3) as shown in FIG. Assume a case. Then, the value at each time k of the received signal sequence {Y (k)} 107 is the code bit at three times immediately before the transmission code sequence {X (k)} held in these 1-bit delay storage elements 110a to 110c. And the addition / subtraction calculation elements 111a to 111c are determined by the following linear convolution calculation relationship.
[0018]
Y (k) = X (k) + X (k-1)-X (k-2)-X (k-3)
A transmission code sequence {X (k)} 100 is assumed to be a binary code (X (k) = + 1 or −1), and an information transmission system is obtained by combining each content of the 3-bit delay storage element. 101 can take a total of eight states. The information transmission system 101 modeled in this manner is called a class 4 extended partial response class (EPR4) channel, and is often used in an information transmission (recording / reproducing system) channel of a magnetic recording / reproducing system. . This is disclosed in detail in US Pat. No. 203413. In addition, the partial response characteristic polynomial G (D) = 1 + D-D2-D3 = (1-D) (1) is often used for the above expression of the convolution operation channel characteristic of the class 4 extended partial response channel. + D)² (Dk represents a k-bit delay operator) is used. In magnetic recording / reproducing systems that realize high-density recording, the characteristic polynomial G (D) = (1-D) (1 + D)ⁿA partial response channel characterized by (n is an appropriate natural number) is actively applied. Since such a partial response channel allows a null frequency characteristic in a DC frequency component and a required transmission band (1/2 of the maximum transmission / recording frequency), a high-density magnetic recording having a low-frequency cutoff characteristic and a narrow-band frequency characteristic. It is suitable for application to a reproduction system.
[0019]
In the maximum likelihood sequence decoder 108, in order to perform maximum likelihood sequence estimation using the storage property (redundancy) of the information transmission system 101, the transition of the holding state inside the storage element on the information transmission system 101 Must be specified and described. The state transition diagram of FIG. 10C shows each storage element of the class 4 extended partial response channel information transmission system 101 shown in FIG. 10B every time one bit of the transmission code sequence {X (k)} is transmitted. Transition state in all cases, and how the received signal sequence {Y (k)} 107 is received as the expected signal value {E (k)} It expresses. The eight states Sj (j = 0, 1, 2,..., 7) in this figure and the 1-bit delay storage elements D1, D2, and D3 (FIG. 10 (b) 110a-c) on the information transmission system 101 The correspondence relationship with the contents of the binary transmission code {X (k)} (X (k) = + 1 or −1) held is as shown in the correspondence table in FIG. When an arbitrary transmission code sequence {X (k)} 100 is given, the transmission code sequence and the received signal expected value sequence are indicated by a unique transition path sequence on this state transition diagram (added to the transition branch arrow sequence). E) {X (k)} and {E (k)}. FIG. 10D is a representation of a trellis (lattice) diagram in which the state transition diagram of FIG. 10C is expanded in the horizontal and time axis directions in order to express the temporal transition of this state transition path sequence. . The transition state corresponding to each time k is expressed as Sj (k) (that is, S0 (k), S1 (k), S2 (k),..., S7 (k)), which is transmitted at time k. The state of the code holding in the storage elements D1, D2, and D3 determined by the input of the code X (k) is shown. Further, at each time k, each branch arrow indicating a transition from the state Si (k-1) to the state Sj (k) has a transmission code for the state transition from the state Si to the state Sj. X (i, j) (in other words, the decoding code when this transition is confirmed) and the expected received signal E (i, j) output from the transmission channel when this transition occurs are X (i, j) j) / E (i, j). (In the time-invariant information transmission system 101, the state transition structure is constant in time and does not change with time k. Therefore, X (i, j) and E (i, j) also change with time k. It is a constant value that depends on only the state Si and the state Sj, and the following discussion can be easily generalized even in a time-varying case.) According to this figure, the transmission code {X (k )} And the corresponding state transition path and received signal expected value {E (k)} can be clearly expressed. For example, as shown in the example of FIG. 10 (f), the path sequence 112 represented by the five state transition paths (branches) 112a connected at time k to (k + 4) is a 5-bit transmission code sequence { + 1, + 1, -1, + 1, -1} and information transmission system 101 channel state transition S0 (k-1) → S1 (k) → S3 (k + 1) → S6 (k + 2) → S5 (k + 3) → S2 (k + 4) transition process, and the expected value of the received signal sequence output on the channel at this time is {+ 2, + 4,0, -2 , 0}.
[0020]
In consideration of the state transition of the information transmission system 101, the maximum likelihood sequence estimation in the maximum likelihood sequence decoder 108 is based on the received signal sequence {Y (n)} on which the actually observed noise is superimposed and the state transition diagram. Evaluate the amount of error from the received signal expectation value {E (n)} in each path of, and uniquely determine the transition of the state transition path that minimizes the total error in the entire received signal sequence {Y (n)}. Thus, the transmission code sequence {X (n)} for this definite path is output as a decoded sequence {Z (n)}. This is nothing but estimation of a signal (code) sequence using a pattern matching technique based on the principle of the so-called least square method. The Viterbi algorithm sequentially rejects candidate decoding code sequences that are not suitable for the received signal sequence, and performs a pattern matching process for this continuous time series signal in a finite manner by using a method that only survives the decoded code sequence that best matches the received signal sequence. Provided is a means for efficiently realizing in real time within a finite processing delay time and a hardware resource (storage element for storing time-series signal information).
Next, means for specifically realizing the maximum likelihood sequence decoding (maximum likelihood decoding or Viterbi decoding) by the Viterbi algorithm will be described. Here, as an example of the target information transmission system 101, the EPR4 channel shown in FIG. 10B is assumed, and the state transition diagram and diagram of the EPR4 transmission path channel based on the binary transmission code sequence in FIG. The outline and basic configuration of the Viterbi decoding process will be described with reference to the trellis diagram of 10 (d). In the following description, the embodiment will be described based on the above-described example of the EPR4 transmission channel by the binary transmission code string. The Viterbi algorithm is described by a state transition model as shown in FIG. It can be applied to any problem that estimates the maximum likelihood event transition that is probabilistically high for any event, that is, results in maximum likelihood transition sequence estimation. In addition, the following description of the embodiment does not depend on the specific characteristics or limitations of the EPR4 transmission channel, but is described in various state transition diagrams having storage elements in various forms as described above. The present invention discloses a general embodiment that can be easily applied to a transmission channel or model without any restrictions and extended to a target channel or model in the same manner.
[0021]
First, attention is focused on FIG. 10 (d) that defines the state transition process at one time k on the trellis diagram for the EPR4 channel. Viterbi decoding corresponds to this and each state transition path branch (arrow) every time a reception (decoding input) signal value Y (k) at time k is input, in accordance with the state transition regulation according to this specific trellis diagram. By evaluating the error with the received signal expected value {E (i, j)}, the path branches that transition to each of the states S0 (k) to S7 (k) at each time are narrowed down to one by one, Repeat the process to select. For this reason, the history of the connected path branch sequence transitioned to each state S0 (k-1) to S7 (k-1), selected by repeating the same process until the previous time (k-1), is stored in each state. On the other hand, it is stored as one surviving path sequence P0 (k-1) to P7 (k-1). In addition, for each of the surviving path sequences P0 (k-1) to P7 (k-1) reaching the respective states S0 (k-1) to S7 (k-1), the reception indicated on each path sequence Cumulative errors (path metrics) M0 (k-1) to M7 (k-1) between the expected signal sequence {E (k)} and the actual received signal sequence {Y (k)} are evaluated. Are stored simultaneously as a metric (likelihood) indicating the likelihood of each of the surviving path sequences. Surviving path sequences P0 (k-1) to P7 (k-1) and path metrics M0 (k-1) for the states S0 (k-1) to S7 (k-1) up to this time (k-1) The contents of ~ M7 (k-1) are changed to the new survivor path sequences P0 (k) ~ P7 (k) and path metrics M0 (k) ~ M7 (k) by the process described below at the next time k. ), And this is repeated as a recursive process every hour. As shown in FIG. 10E, when attention is paid to each state on the trellis diagram, the state Si as a transition process to the state Sn (k) (n = 0, 1,..., 7) at the time k. If there is a possibility of transition from either (k-1) or state Sj (k-1) (i, j = 0,1, ..., 7), the specific processing procedure is as follows: Are summarized in
[0022]
(1) With respect to the received signal value Y (k) input at time k, the received signal expected value E (i corresponding to each transition path from the state Si (k-1) and the state Sj (k-1) , n) and E (j, n), the square error values (branch metrics) BM (i, n) (k) and BM (j, n) (k) corresponding to each transition path branch are Calculate as follows.
[0023]
Transition branch metric from state Si (k-1) to Sn (k):
BM (i, n) (k) = [Y (k) -E (i, n)] ^²
Transition branch metric from state Sj (k-1) to Sn (k):
BM (j, n) (k) = [Y (k) -E (j, n)] ^²
It is known that the metric based on the square error gives an optimal likelihood metric for maximum likelihood sequence estimation when the noise sequence superimposed on the received signal sequence {Y (k)} is independent white Gaussian noise. Other error evaluation values such as absolute value errors can be used depending on the decoding implementation conditions.
[0024]
(2) Cumulative error (path metric) PM (i) for likelihood comparison with respect to a path sequence transitioning from each of states Si (k-1) and Sj (k-1) to state Sn (k) , n) (k) and PM (j, n) (k). Therefore, the survival paths Pi (k-1) and Pj (k-1) to the states Si (k-1) and Sj (k-1) evaluated by the processing up to the previous time (k-1) State transition branch metric BM (i, n) (k) calculated in (1) for each corresponding path sequence cumulative error (path metric) Mi (k-1) and Mj (k-1) And BM (j, n) (k) are newly accumulated as follows.
[0025]
Path metric from state Si (k-1) to Sn (k):
 PM (i, n) (k) = Mi (k-1) + BM (i, n) (k)
Path metric from state Sj (k-1) to Sn (k):
     PM (j, n) (k) = Mj (k-1) + BM (j, n) (k)
Further, the values of path metrics PM (i, n) (k) and PM (j, n) (k) for the two-path transition are compared in magnitude, and likelihood comparison is performed. A transition path having a smaller path metric, which is an accumulated error of each path series, is selected as a more reliable and highly likely path series that reaches the state Sn (k) at time k, and the other is rejected. Further, the path metric value on the selected path side of the compared path metrics PM (i, n) (k) and PM (j, n) (k) is used to transit to the state Sn (k). The contents of Mn (k) are updated as a new path metric value of the surviving path sequence.
[0026]
Survival path metric leading to state Sn (k):
Mn (k) = Min [PM (i, n) (k), PM (j, n) (k)]
Min [•] is an operation for selecting the minimum value. (3) The surviving path sequence history Pn (k) for the state Sn (k) at time k is updated. In Pn (k), connection information of (D + 1) transition states on the surviving path that goes back from the current time k to the finite time D is stored in time order. For example, refer to the stored contents of Pn (k) = {Sn (k), Si (k-1), Sj (k-2), ~, Sl (k-D + 1), Sm (kD)} The state transition on the surviving path sequence to the state Sn (k) selected by the processing up to time k is Sm (kD) → Sl (k-D + 1) → Sj (k-2) → Si It is shown that they are connected in the order of (k-1) → Sn (k) and change. Whether the surviving transition path to state Sn (k) at time k is a transition path from Si (k-1) or a transition path from Sj (k-1) by (2) Is selected and confirmed, the new survivor path sequence history Pn (k) to the state Sn (k) determined by the selection process is the state Si (k-1) up to the previous time (k-1). Survival path sequence history for Sj (k-1) Pi (k-1) and Pj (k-1) are updated as follows using the surviving path sequence history of the selected path side state. .
[0027]
Survival path history to state Sn (k):
Pn (k) = {Sn (k), Pi (k-1)} (when selecting a transition path from Si (k-1))
         = {Sn (k), Pj (k-1)} (when selecting a transition path from Sj (k-1))
In the above update process, Pi (k-1) or Pj (k-1) is selected according to the selected state transition path, and this temporal storage position is moved to the past one hour at a time. After the past stored contents ((D + 2) -th element) are extracted as the result of Viterbi decoding, the new stored state Sn (k) is added to the storage position of the latest time and the stored contents of Pn (k) Means an operation to be transcribed. In the prior art, this is generally constituted by a storage circuit such as a shift register that sequentially shifts the stored contents at each time (shift register replacement method), and a configuration method using various storage circuits is disclosed. Has been. Further, in many cases, the stored content in the path sequence history Pk (n) is not the information of the selected transition state (state number) itself, but the transmission code for the path branch to the selected transition state. Remember. For example, when the transition path from the state Si (k−1) is selected as the surviving path for the state Sn (k) at the time k, the recorded content in the surviving path history is the state Si (k The value of the transmission code X (i, n) corresponding to the path branch from -1) to Sn (k) can be used. Thus, when the stored path history information is referred to, the transmission code sequence {X (n)} indicated by the surviving path can be immediately obtained as a decoded code result. Further, in the description of the update processing of surviving path sequence history information in (3) above, the storage information (path history information for the latest time) for time k in the surviving path sequence history Pn (k) reaching state Sn (k) is The state Sn (k) is constant irrespective of the path selection state from time k-1. Therefore, actually, this path information itself does not need to be physically stored, and only the surviving path sequence history information before time k-1 connected to this state Sn (k) is physically stored in the storage circuit. It only has to be recorded. The path history storage information Sn (k) for time k can be represented by the fact (storage position information) that this path history information is stored as a surviving path sequence history Pn (k) that reaches the state Sn (k). In the processing at the next time k + 1, when referring to the stored contents of the surviving path sequence history Pn (k), the path history storage information Sn (k) for this time k may be referred to. As described above, this also applies to the case where the value of the transmission code X (i, n) corresponding to the selected path branch is stored as the recorded content in the surviving path history. In sequence history Pn (k), history information from time k fixed before being a path transition to state Sn (k) until a predetermined time (in the case of EPR4 channel, from time k to time k-2) The 3-bit transmission code history) is omitted by indicating the storage location information itself stored as the surviving path sequence history Pn (k), and the amount of hardware of the storage device is reduced by supplementing this information at the time of reference. Can be saved.
[0028]
The series of Viterbi decoding processes (1), (2), and (3) above are repeated each time the received signal value Y (k) at each time is input. Specific components for implementing this are shown in FIG. 11 (a). The calculation of the branch metrics BM (i, n) (k) and BM (j, n) (k) in (1) is performed by the square error calculation circuit 201. The path metrics Mi (k-1) and Mj (k-1) of the surviving paths for the states Si (k-1) and Sj (k-1) are held in the metric storage circuits 202a and 202b, and the metric cumulative addition The circuit 203 calculates the path metrics PM (i, n) (k) and PM (j, n) (k) in (2), and the comparator 204 compares these path metric values. The comparison result is output to the selection signal 205, and the metric selection circuit 206 selects either the path metric PM (i, n) (k) or PM (j, n) (k) according to the selection signal 205, Using this, the contents of the metric storage circuit 202c holding the surviving path metric Mn (k) to the state Sn (k) are updated and stored. On the other hand, surviving path histories Pi (k-1) and Pj (k-1) that reach states Si (k-1) and Sj (k-1) are stored in path history storage circuits 207a and 207b. In the process of updating the contents of the surviving path history Pn (k) to the state Sn (k) in 3), the path history selecting circuit 208 selects either the contents of the path history storage circuit 207a or 207b instructed by the selection signal 205. Then, the storage position of this content is shifted by one time, and is newly updated and stored as the content of the path history storage circuit 207c holding Pn (k). At this time, the surviving path history information selected from the last storage position of the path history storage circuit 207a or 207b is output as a decoding result (decoded code sequence Z (k) 109).
[0029]
In actual Viterbi decoding, the above processes (1) to (3) for the received signal Y (k) at each time are independently performed for all states of the trellis diagram to be subjected to maximum likelihood sequence estimation. Need to be done. Therefore, in an actual Viterbi decoder implementation configuration, the implementation components for the state Sn (k) shown in FIG. 11A are provided in parallel for the number of states in the same configuration. For example, for the trellis diagram of FIG. 10 (d), as shown in the configuration of the maximum likelihood decoder based on the Viterbi algorithm of FIG. 11 (b), eight states S0 (k) to S7 (k) The implementation components of FIG. 11A assigned to each are provided in parallel in a total of 8 series. At this time, the metric storage circuits 202a to 202h for storing the surviving path metrics M0 (k) to M7 (k) and the path history storing circuits 207a to 207h for storing the surviving path sequence histories P0 (k) to P7 (k). Is assigned to each of the states S0 (k) to S7 (k), and these reference destinations are connected to a plurality of locations according to the next stage connection state on the trellis diagram of each state. . For example, if there is a trellis diagram path connection relationship between the state Si (k) and the state Sj (k + 1) (i, j = 0,1, -7), the state Si (k) One of the reference destinations of the assigned metric storage circuit 202 is the other of the metric cumulative adders 203 assigned to the state Sj (k) that performs addition with the branch metric BM (i, j) (k). One of the reference destinations of the path history storage circuit 207 assigned to the state Si (k) is an input to the path history selection circuit 208 assigned to the state Sj (k). Also, since the value of the received signal expectation value E (i, j) on the actual trellis diagram is often common to several path branches, a square error calculation circuit that performs calculations on this branch metric In many cases, the configuration 201 is also commonly used, and a configuration that is input to the corresponding plurality of metric cumulative adders 203 is actually used. As described above, as shown in FIG. 11B, the Viterbi decoder configuration uses the branch metric calculation unit (BMU) 200a that receives the received signal Y (k) and performs (1) processing, and uses this branch metric output. (2) A path metric comparison / selection unit (ACS calculation unit) 200b that executes processing and selects a surviving path to each state, and receives this selection output, and (3) stores and updates the surviving path history by processing And is roughly divided into a path memory unit (PMU) 200c that narrows down and determines the decoding result. The above is the implementation method and configuration method of the maximum likelihood sequence decoding process by the Viterbi algorithm.
[0030]
Next, in order to clarify the principle of implementation of the present invention, FIG. 12 shows an example of state transition on the trellis diagram on the EPR4 channel of FIG. 10 (d). A process from selection of a surviving path in decoding processing to determination of a decoding result will be described. By using the above-described conventional Viterbi decoding implementation method and configuration method, using the received (decoded input) signal sequence {Y (k)} 107 at each time, a state transition path to each time and each state on the trellis diagram ( Path branches) 112a are always selected one by one. In this way, the selection of the surviving path sequence 113 is repeatedly performed, so that the surviving path series at each time is further narrowed down. For example, as shown in the history of the surviving path sequence 113 in FIG. 12, eight surviving path sequences to each state selected at each time at time k are gradually rejected by the subsequent path selection, and finally At the end of the selection process at time (k + 10), the concatenated survivor path sequence (thick arrow sequence) converges to one, at this time, convergence from time (k-1) to (k + 8) Thus, the surviving path sequence is determined as the deterministic maximum likelihood path sequence 114, so that the decoded code Z (k) at time k becomes the only state transition path (path branch) 112 b that survives on the deterministic maximum likelihood path sequence 114. It is determined by referring to the assigned transmission code X (i, j). The operation of narrowing down the surviving path sequence (path rejection) moves the contents of the selected path history Pj (k-1) or Pj (k-1) to the past in the past in the decoding process (3) described above. However, the stored content of the new Pk (n) is nothing but an operation to transfer. In FIG. 11B, if the path history storage circuits 207a to 207h for storing the surviving path sequence histories P0 (k) to P7 (k) have a sufficient storage length, the selection of this path history storage circuit is performed. By repeating the reference and transcription, the contents of the storage positions at the end of each of the storage circuits 207a to 207h (the path branch selection history at the past time) all converge to the same stored contents, and either of these contents is The result of decoding can be referred to. As described above, the maximum likelihood path determination operation in the maximum likelihood sequence decoding is performed by repeatedly rejecting / selecting surviving path candidates that reach each state on the determined maximum likelihood path sequence 114 at each time. The finalized maximum likelihood path sequence 114 finally converged and obtained as a decoding result has a higher likelihood in the state transition path selection at all times on this path sequence, and remains only without being rejected. Survival path series.
[0031]
The present invention is effective in improving the error detection and correction coding technique in order to efficiently improve the decoding error event in the conventional maximum likelihood sequence decoding processing shown so far, to make it simple and to provide higher reliability. It is an object of the present invention to provide a means for realizing an information recording / reproducing method and an information recording / reproducing apparatus using a decoding processing method that has been utilized in a practical manner. The second trellis transition diagram example of FIG. 13 (a) shows an example of the surviving path sequence 113 in the binary code transmission sequence EPR4 transmission channel channel as in FIG. This is for explaining the relationship between the decoding error path sequence and the normal path sequence caused by the uncertainties. In this figure, the state transition sequence S6 (k-1) → S5 (k) → S3 (k + 1) → S6 (k + 2) → S4 (k + 3) → S0 (k + 4) → S0 (k +5) → S1 (k + 6) → S3 (k + 7) A regular maximum path sequence 114 including a decoding error event (decoding error sequence) with respect to a normal path sequence 115 represented by a path transition of: State transition sequence S6 (k-1) → S5 (k) → S3 (k + 1) → S6 (k + 2) → S5 (k + 3) → S2 (k + 4) → S4 (k + 5) → When it is determined by the path transition of S1 (k + 6) → S3 (k + 7), this decoding error event (decoding error sequence) is the state S1 at time (k + 6) on the determined maximum likelihood path sequence 114. This occurs because the error path selection 117 occurs for the two surviving path branch candidates flowing into (k + 6). That is, two surviving path branches that branch from state S6 (k + 2) at time (k + 2) on regular path sequence 117 and flow into state S1 (k + 6) at time (k + 6) By making a comparison and selection error between candidates, a partial path sequence S6 (k + 2) → S4 (k + 3) → S0 (k + 4) → S0 (k + 4) on the normal path sequence 115 which is one of the surviving path branch candidates → S0 (k + 5) → S1 (k + 6) (thick dotted arrow path sequence) is the other path sequence S6 (k + 2) → S5 (k + 3) → S2 (k + 4) → S4 (k + 5) → S1 (k + 6) is replaced, and a decoding error occurs as a code sequence error. As processing in the decoding circuit, surviving path metrics PM (0,1) (k + 6) and PM (4) in the above-described decoding processing (2) for the state S1 (k + 6) at time (k + 6). , 1) Magnitude judgment of (k + 6):
M1 (k) = Min [PM (0,1) (k + 6), PM (4,1) (k + 6)]
In this case, PM (4,1) (k + 6) is selected instead of PM (0,1) (k + 6). This selects the surviving path sequence on the state transition S4 (k + 5) → S1 (k + 6) side instead of the surviving path sequence on the state transition S0 (k + 5) → S1 (k + 6) side. In the decoding process (3) for determining and updating the survival path sequence history,
P1 (k + 6) = {S1 (k + 6), P4 (k + 5)}
When the path history replacement process is executed, a sequence error occurs. As a result, the content of the surviving path sequence history P0 (k + 5) having the normal path sequence 115 up to the time (k + 5) state S0 (k + 5) is rejected, and the surviving path sequence history having the error path sequence 116 The content of P4 (k + 5) is selected as a surviving path sequence and remains in the updated path history storage circuit. Under noisy conditions, this selection error of surviving path branch candidates does not occur with a uniform probability frequency in each state on the deterministic maximum likelihood path sequence 114, but the two surviving path sequences flowing into each state. The smaller the accumulated sum (difference between signal sequences or path metric difference) of expected received signal differences of candidates, the greater the possibility and frequency of errors in the comparison operation in the maximum likelihood decoding process (2). That is, in the comparison / selection of the path metric likelihood between two surviving path sequences, the expected value of the identification difference (likelihood difference) between the path metrics is smaller, and the above-described random determination as the comparison margin for noise becomes narrower. Decoding error events due to noise are more likely to occur. The expected values of the received signal sequences of the normal path sequence 115 and the error path sequence 116 of FIG. 13A are {−4, −, respectively, at the 4-bit time from time (k + 3) to time (k * 6). 2,0, + 2} and {−2,0, −2,0} are discriminated, and the cumulative sum of square errors (distance between signal sequences) is 16. The accumulated sum 16 of square errors is equal to the minimum square error accumulation amount (the least square Euclidean distance and the minimum free distance) guaranteed between all the received signal sequences on the binary code transmission sequence EPR4 transmission channel. Further, the determination of the decoding reliability (decoding error rate) of the transmission channel under noise is mainly due to an error event between transmission code sequences having such a least square Euclidean distance. This is a well-known fact in communication theory. In the example of FIG. 13A, due to the comparison / selection error of the path metric likelihood in the state S1 (k + 6), from the time (k + 3) in the surviving path history P1 (k + 6) to (k + The 4-bit content up to 6) is replaced with the content of the error path sequence 116, and an error sequence event occurs.
[0032]
From the error event generation process described above, the nature of the decoding error event in the maximum likelihood sequence decoding is summarized as follows.
[0033]
(A) Since a decoding error event in maximum likelihood sequence decoding is caused by replacement of an error path sequence, a sequence-like error event that can simultaneously include a plurality of bits of code errors occurs. As a result, in a single decoding error event, a bursty code error (local error spillover) in which a plurality of code errors are partially localized / concentrated on the decoded code sequence frequently occurs. For this reason, the error code in a random decoding error under noise conditions is not a random distribution of single code errors in the decoded code sequence, but a burst error event in which a plurality of error codes are localized (ie, a partial code sequence state). Error events) are randomly distributed.
[0034]
(B) A sequence of code error patterns generated in bursts, that is, an error code pattern sequence (code error syndrome) is a distance (Euclidean distance) between received signal sequences of the corresponding error path sequence and normal path sequence. Depending on, the probability of occurrence is different. Accordingly, error events in maximum likelihood sequence decoding are biased in frequency to a specific error code pattern sequence (code error syndrome), and error events occur frequently between code sequences having a least square Euclidean distance between received signal sequences. Occurs.
[0035]
In the present invention, there is provided a method for efficiently improving a code error caused by using two basic properties of a decoding error event in the maximum likelihood sequence decoding and using an error code detection and correction technique. Conventionally, in error code detection and correction technology for maximum likelihood sequence decoding, the occurrence of burst error events (error spread) due to (a) causes a decrease in error code detection and correction capability, and these are completely detected with a predetermined probability. In order to correct, a complicated error code detection and correction encoding method having a relatively high correction capability was used. Also, burst-like long continuous error events are divided into random single error events on multiple code sequences by randomization techniques such as code sequence interleaving (interleaving), and each of them is performed by independent error code detection and correction coding. By performing detection and correction, practical error detection and correction has been realized by using a relatively simple error code detection and correction encoding method in parallel. In the present invention, the nature of the burst-like decoding error event occurrence as in (a) is not canceled as in the prior art, but is regarded as extremely high correlation information regarding the error code occurrence position and actively utilized. Thus, more efficient decoding error detection and correction can be realized. In general, error correction coding improves the correction capability, reduces redundancy, or simplifies the correction process by knowing information about the target code error event in advance and then decoding and coding. It becomes possible to do. In the present invention, by connecting the error correction encoding / decoding means to the maximum likelihood decoding method, the characteristics of the decoding error event in the maximum likelihood decoding method are actively used for error correction encoding / decoding, and low redundancy is achieved. Thus, the decoding reliability is efficiently improved by using the error correction coding.
[0036]
Therefore, attention is paid to each error code pattern sequence (code error syndrome) from among burst-like, sequence-like decoding error events, and further, between the received signal sequences from this error code pattern sequence (code error syndrome). The error code pattern sequence (code error syndrome) should be ordered according to the frequency of occurrence determined depending on the distance, starting from the highest occurrence frequency and subjected to detection and correction processing from the higher one (code error syndrome). To decide. In this way, focusing on error events of high-frequency error code pattern sequences (code error syndrome), this is detected preferentially from high-frequency error code pattern sequence (code error syndrome) events. By performing error code detection / correction coding to correct, simple and low redundancy error code detection / correction coding can be used to efficiently improve desired decoding reliability or higher decoding than before A reliable error code detection and correction coding technique can be realized. Thereby, a high-density and highly reliable information recording / reproducing method and information recording / reproducing apparatus can be realized.
[0037]
As described above, in carrying out the present invention, an error code pattern sequence (code error syndrome) of a specific error event having a high occurrence frequency in maximum likelihood sequence decoding is set in advance, and this error code pattern sequence is set. Encoding and decoding of error code detection and correction codes that can detect and correct up to a predetermined number of (code error syndrome) error events are performed on the transmission code sequence and the decoded code sequence. This high-frequency error code pattern sequence (code error syndrome) is derived from the process of replacement of the contents of the normal path sequence and error path sequence due to the path selection error in the surviving path history. Can be easily estimated by using the fact that a path sequence selection error occurs in the occurrence probability depending on the signal sequence distance (Euclidean distance) between the received signal sequences of the normal path sequence and the error path sequence. That is, if the distance structure between the received signal sequences is defined in advance by the constraint condition added to the transmission code sequence and the target trellis transition diagram of the maximum likelihood sequence decoding process by modulation processing or intentional code processing, In many cases, focusing on a pair of limited signal sequences having a large square Euclidean distance sequentially from the least square Euclidean distance, or a limited signal sequence having a small square Euclidean distance equivalent to this from the least square Euclidean distance. By paying attention to the pair, it is possible to preliminarily limit and predict error code pattern sequences (code error syndromes) that occur frequently due to selection errors between sequences. Then, from the events of this frequently occurring error code pattern sequence (code error syndrome), the error event is improved by the error detection / correction coding technique in order, thereby improving the next best decoding error rate (reliability). Can get well. As shown in the example of FIG. 10 (c), under the fact that maximum likelihood sequence decoding is applied and designed, the target information transmission / recording / reproduction channel always has a specific Markov state transition. It is uniquely defined by the figure and modeled. Therefore, as described above, focusing on the Euclidean distance structure between received signal sequences, it is possible to limit and predict a high-frequency error code pattern sequence (code error syndrome) by an exploratory / analytical method. . Also, the estimation of this error code pattern sequence (code error syndrome) by the square Euclidean distance between the received signal sequences is most effective when the noise factor on the received signal sequence is considered as additive white Gaussian noise, In the case of noise factors that follow other characteristics, such as colored noise, this kind of estimation method can be expanded by evaluating the stochastic variation of the distance structure between signal sequences on the specified Markov state transition diagram. It is possible to limit and predict error code pattern sequences (code error syndromes) that occur at a high frequency. This is a technique described in the known transmission / communication theory, which is beyond the scope of the present invention, and is not described here. Further, in actual maximum likelihood sequence decoding, a bias in error event occurrence frequency with respect to a specific error code pattern sequence (code error syndrome) is often very significant. Therefore, the maximum likelihood sequence decoding process is performed before the implementation of the present invention. The actual code or the simulated method is used on a trial basis, and the decoded code sequence is compared with the normal transmission code sequence, so that a high-frequency error code pattern sequence (code error syndrome) is obtained from the actual statistical frequency. It is also effective to decide. At this time, separation / discrimination of individual code error events on the decoded code sequence is such that the number of normal codes between adjacent error codes is equal to or greater than the channel memory length integer n of the target channel (n = 3 in the case of EPR4 channel), That is, the determination is made based on whether or not the number of bits defines the state of the Markov state transition diagram of the target channel. If there are more than one channel code length normal code between the two error codes, the two error codes are due to different path error events, otherwise the same sequence error (path error event). ). By using the actual statistical information of the error code pattern sequence (code error syndrome) obtained in this way, an optimum error code detection and correction means is designed in advance, dynamically and variablely. The decoding reliability can be optimally improved and maintained by changing the structure or selecting an optimum one from a plurality of error code detection / correction means.
[0038]
An example of a high-frequency error code pattern sequence (code error syndrome) determined for the error code detection / correction means by the above method is shown below. In the surviving path sequence 113 of FIG. 13 (a), the normal path sequence 115 and the error path sequence 116 are time (k + 3) to time (k + 6) on the path sequence and on the received (decoded input) signal sequence 107. Different sequences are taken between 4 bit times. As mentioned earlier, the two sequence pairs are signal sequence pairs having a least square Euclidean distance on the trellis transition diagram, and the error event between the sequences is the most frequent decoding error event, most often This is one of the decoded error code pattern sequences (code error syndrome). That is, on the transmission code sequence or the decoded code sequence 109, the normal path sequence 115 and the error path sequence 116 have code sequences that are different from each other only by 1 bit at time (k + 3). When a difference sequence between code sequences is defined as a decoding error pattern sequence 119 and an error event, that is, an error code pattern sequence (error syndrome) is described, it can be expressed as a 1-bit decoding error pattern 121a. Here, in the decoding error pattern series 119, 0 indicates no code error, +1 indicates a bit position where the code “1” is erroneously set to “0”, and −1 indicates a bit position where the code “0” is erroneously changed to “1”. . That is, on the binary code sequence, a non-zero position on the decoded error pattern sequence has a meaning of an error occurrence location, and serves as a pointer indicating a code position of an inverted bit error. In addition, it is shown that code errors in the same direction occur at code positions where the non-zero polarity has the same sign, and code errors in the opposite direction occur at code positions where the non-zero polarity is different. In such a representation of the decoded error pattern sequence 119, the difference between the normal code or the error code with respect to the error code can be distinguished from each other at the indicated error code position. On the surviving path sequence 113, after branching to two paths indicating different transmission (decoding) codes at the same time, the same state is obtained via three-bit length different path sequences indicating the same transmission (decoding) code sequence. Join S1 (k + 6). This is obvious from the definition of the trellis diagram in which the channel state is determined by the past 3-bit code history, and this is one form of a path sequence pair having the least square Euclidean distance. As described above, in an EPR4 transmission channel using a binary transmission code, replacement of an error path sequence having a length of 4 bits occurs frequently from any trellis diagram state, and the bit time of occurrence of a path selection error event ( In the example of the error path sequence in FIG. 13A, the decoding position relatively 3 bits before (the error path sequence example in FIG. 13A) with reference to the error path selection detection position 122 at time (k + 6). In this case, an error syndrome error event in which the normal code at the time (k + 3)) causes a 1-bit inversion error, that is, an error event having the 1-bit decoding error pattern 121a is an error pattern sequence having a high occurrence frequency. One can be predicted in advance. In general, in the decoding error pattern, each code at an error bit position can take both plus and minus codes while maintaining the same sign order between the codes. Therefore, as an error pattern sequence (code error syndrome), each code Two sets in which the signs are reversed are conceivable. In the present specification, one description is used to represent both.
[0039]
FIG. 13B shows another specific example of the relationship between the normal path sequence 115 and the error path sequence 116 in the maximum likelihood sequence detection on the EPR4 transmission channel by the binary transmission code similar to FIG. It is shown. The generation of the error path sequence 116 in this specific example is due to the occurrence of the error path selection 117 in the surviving path selection process for the state S3 (k + 5) at time (k + 5) on the deterministic maximum likelihood path sequence 114. This occurs as a 6-bit sequence error from time k to time (k + 5). The normal path sequence 115 and the error path sequence 116 on the received (decoded input) signal sequence 107 have a least square Euclidean distance 16 and, like the error event in FIG. Can be regarded as one. When the relationship between the normal path sequence 115 and the error path sequence 116 is compared on the decoded code sequence 109, the decoded error pattern sequence 119 has an error path selection detection position at time (k + 5) that is a bit time of occurrence of an error event. With reference to 122, the normal code of the continuous 3-bit code position (time k to (k + 2)) up to the decoding position of time (k + 2), which is relatively 3 bits earlier, is inverted as in FIG. It can be regarded as a decoding error event of an error syndrome causing an error, and such a 3-bit decoding error pattern 121b can be predicted in advance as a frequent decoding error event of the channel.
[0040]
The decoding error event of the 1-bit decoding error pattern 121a shown in FIG. 13A occurs from any state on the target trellis transition diagram, does not depend on the transmission code sequence, and has only the structure of the trellis transition diagram. This is one of decoding error pattern sequences (code error syndromes) determined with a high probability of occurrence. On the other hand, in an EPR4 transmission channel using a binary transmission code, there exists a signal sequence pair having a least square Euclidean distance depending on a specific transmission code sequence. FIG. 13B shows a 3-bit decoding error pattern 121b as this example. In such a code error pattern, a transmission code sequence of “... 01010...” Or “... 10101...” In which code bits on the transmission code sequence are alternately inverted by 3 bits or more is transmitted through the transmission channel. This is the case. When either one of these two transmission (reception) code sequences is transmitted, in the code string portion where alternating inversion of transmission code bits is repeated, n bits before the last bit position (n is an integer of 2 or more) A decoding error pattern in which all consecutive code bits are inverted can occur at a high frequency. For example, the transmission code sequence “... 0010000 ... "is transmitted, the 3-bit code string portion of" 010 "matches the above code pattern, and each bit of this code string is inverted" ... 0101“000...” Is a signal sequence pair having the minimum Euclidean distance. That is, the decoding error pattern sequence 119 is “... 0.-1 +1 -1 0 0 0... ”And an error pattern sequence of a code error syndrome (3-bit decoding error pattern 121 b) that causes a 3-bit continuous inversion error.01010000 ... "is transmitted, the 5-bit code string portion of" 01010 "matches the above code pattern, and the last 3 bits (when n = 2), 4 bits (n = 3) ) Inverted each bit of 5 bits (when n = 4) "... 001101000 ... "," ... 000101000 ... "," ... 010101000 ... "is a pair of signal sequences having the minimum Euclidean distance, and all are decoded error code sequences having the highest occurrence probability. That is, the decoded error pattern sequence (code error syndrome) is" ... 000.-1 +1 -1 000 ... "," ... 00+1 -1 +1 -1 000 ... "," ... 0-1 +1 -1 +1 -1 000... ”And becomes a code error pattern (3 to 5 bit code error pattern sequence) of a code error syndrome causing a continuous alternating inversion error of 3 to 5 bits. Thus, a transmission code string to be transmitted is a continuous code. An error pattern event in which a partial sequence becomes a continuous inversion bit error when it has an inversion pattern is also a decoding code error pattern sequence having a high probability of occurrence equivalent to the 1-bit decoding error pattern 121a from the relationship of the minimum Euclidean distance ( On the contrary, if a decoded code error pattern sequence (code error syndrome) consisting of a plurality of bit error code positions is assumed, an error having this decoded code error pattern sequence (code error syndrome) is assumed. Refer to the transmitted code sequence or the decoded decoded code sequence for the location where the event occurred. In other words, in the decoded code error pattern sequence (code error syndrome), the polarity code of the non-zero position indicating the code error position is the direction of the code error in the error event at each code position (code “ Since the relative relationship between the two directions, “1” is mistaken to “0” or the code “0” is wrong to “1”), the decoding error pattern sequence (code error syndrome) is determined. Is determined by referring to the transmitted code sequence or the decoded decoded code sequence. For example, the above-mentioned code error syndrome causing the 3-bit continuous alternating inversion error " … 0-1 +1 -1 The error event “0...” Indicates that a consecutive 3-bit code error always indicates a code error in a different direction at adjacent bit positions.010… ”Or“…101It is obvious that this only occurs in the partial code sequence of “...”. On the other hand, on the decoded code sequence, the code error syndrome ”... 0-1 +1 -1 An error event of “0…” is “…010… ”Or“…101It can also be determined by referring only to the decoded code sequence that it cannot occur at the location of the 3-bit partial code sequence other than "...". Using this fact, a specific decoded code error pattern sequence (code error syndrome) can be determined. ), When the transmission code sequence is subjected to encoding for error code detection / correction, or when the error code detection / correction processing by this error code detection / correction code is applied to the decoded code sequence, By referring to the code sequence pattern of the transmission code sequence or the decoded code sequence, the range of the transmission / decoding code sequence to be encoded or corrected can be limited. This can be used to simplify correction processing and improve correction efficiency and performance, and as described above, the code error syndrome is n bits of non-zero. Since the code error direction at each code position is defined and the code locations on the transmission code sequence where the error event can occur are limited, the occurrence probability on the random code sequence is About 1/2 for 1-bit code error^(n-1)Will be reduced. Further, when the transmission code sequence has a predetermined constraint condition by the modulation process, a more accurate occurrence probability is predicted by taking this into consideration. Considering the appearance frequency probability of such a specific transmission code sequence pattern, the error event occurrence probability of each decoded code error pattern sequence (code error syndrome) is predicted more accurately, and the most frequent decoding code error A pattern sequence (code error syndrome) can be set.
[0041]
As described above, the setting of a high-frequency decoding error pattern sequence (code error syndrome) differs depending on the target transmission channel characteristics and the constraint conditions added to the transmission code sequence by encoding / modulation processing or the like. In general, the partial response characteristic polynomial G (D) = (1-D) (1 + D) F (D) (F (D ) Is an arbitrary characteristic polynomial), which is often in the form of a transmission channel in many practical applications. The transmission channel of this form includes a DC component (sequential sequence of the same code) and a highest recording frequency, that is, a frequency component that is 1/2 of the code transmission frequency component (continuous inversion) among the frequency components of the binary transmission code sequence to be transmitted. As shown by the example of the EPR4 transmission channel described above, from the structure of the common channel state transition, the received signal sequence is The most frequent decoding error pattern sequence that defines the least square Euclidean distance is a continuous inversion code error sequence of 1 bit or more, and the portion of the continuous inversion code sequence on the transmission code sequence transmitted through the channel. A common feature is that this continuous inversion code error occurs with the most frequent probability. Therefore, the present invention provides the transmission code sequence with error code detection / correction coding means capable of correcting a continuous inversion code error sequence (adjacent error codes are different from each other) up to a predetermined length. Effectively implemented for channels. On the other hand, by limiting the maximum code length of the continuous inversion code sequence on the transmission code sequence to a certain code length or less by adding a constraint condition such as run length restriction by the encoding modulation process, the maximum code length exceeding this code length is obtained. Can be prevented from occurring. Therefore, an upper limit of the generated code length of the continuous inversion code error sequence is defined by preliminarily performing a coding modulation process for limiting the maximum length of the continuous inversion code sequence for the transmission code sequence, and By applying error code detection / correction coding that detects and corrects error events of continuous inverted code error sequences that are less than or equal to the maximum length of this limited continuous inverted code sequence, more frequent error events It is possible to detect and correct completely and effectively, and to simplify the configuration of the error code detection and correction code. As described above, the occurrence of a part of the decoding error pattern sequence (code error syndrome) events out of the error events of the plurality of high-frequency decoding error pattern sequences (code error syndrome) that are predicted and limited is encoded modulation. By using processing, it is avoided by excluding / prohibiting the appearance of a specific transmission code sequence pattern in which this decoding error pattern sequence (code error syndrome) can occur with respect to the transmission code sequence, and other decoding error patterns Generation of a sequence (code error syndrome) event can be avoided by performing error code detection / correction coding on the specific decoding error pattern sequence (code error syndrome) for the transmission code sequence, and detecting and correcting this. In addition, the present invention is more effectively implemented by using the encoding modulation process and the error code detection / correction process in a complementary manner. In this case, as described above, the error event of the decoding error pattern sequence (code error syndrome) having a relatively long code length is avoided by the encoding modulation process, and the error of the relatively short decoding error pattern sequence (code error syndrome) is avoided. It is appropriate that the event is corrected by error detection and correction coding, and for the coding and modulation process, limiting the appearance of a relatively long specific transmission code sequence pattern relaxes the restrictions and constraints on the code. This is desirable. In addition, for error detection and correction coding, it is desirable to configure so as to detect and correct a relatively short specific decoding error pattern sequence (code error syndrome), and such an embodiment provides coding modulation and error detection and correction coding. This is suitable for simplifying the mutual configuration and suppressing an increase in code redundancy for the transmission code sequence by both.
[0042]
Further, as a similar method, the generation of a specific transmission code sequence pattern that may cause the most frequent decoding error pattern sequence (code error syndrome) by coding modulation processing is time-varying or changed on the actual transmission code sequence. It is also possible to add constraints to allow or exclude periodically. In this case, error code detection / correction coding for detecting and correcting the decoding error pattern sequence (code error syndrome) is performed only on a time-phase code on a transmission code sequence in which a specific transmission code sequence pattern is allowed. Even in the correction process, the error code detection and correction process can be performed only on a decoded code of a specific time phase synchronized with the decoded code sequence. For example, when the detection and correction of the decoding error pattern sequence (code error syndrome) of the 3-bit decoding error pattern 121b shown in FIG. Pattern events can occur ...010… ”Or“…101... ”(Pattern of pattern pattern start bit) is allowed only in an n-bit period (n is a natural number). This allows the error correction position to be detected and corrected so that only the 3-bit continuous code error starting from the bit position of the n-bit period similar to the above is detected and corrected on the transmission code sequence. An error code detection / correction code can be configured by narrowing down, and the correction processing target can also be limited to a periodic code position synchronized with the n-bit period on the decoded code sequence. By allowing the appearance of specific code patterns that are prone to errors on a periodic basis, the restrictions on coding modulation processing are relaxed and changed compared to the case where the appearance of this code pattern is completely restricted and prohibited. In addition, since the error detection and correction process may be performed periodically on the code sequence, the error detection and correction code is simplified, and the redundancy for the transmission code sequence is reduced. It leads to keeping it relatively low.
[0043]
In the description so far, the transmission code sequence 100 is channel-transmitted as it is, and the decoded code sequence output from the maximum likelihood sequence decoder is also described as being decoded and output to a code sequence equal to the transmission code sequence. However, in the transmission channels of the various embodiments, various processes including pre-code processing or post-code processing are performed on the decoded sequence before input of the transmission channel or within the maximum likelihood sequence decoder or immediately after output. Code conversion processing and signal processing operations are often performed. In this case, the error code position of the code error pattern sequence (error syndrome) is obtained by mapping the processing code position to the error sequence on the decoded sequence by the code conversion processing / signal processing operation similar to the information code. Can be obtained. For example, when a transmission code sequence on a channel is subjected to postcode processing (1 + D * D) (+ is an addition modulo 2 to a binary code) as a decoded code sequence The code error pattern sequence (symbol error syndrome) “... 0 + 1-1 + 1-1 + 100. -1 + 1..., And error correction coding may be performed using this as a decoded code error pattern sequence (code error syndrome). Since the code conversion process in the information transmission system guarantees code reproducibility, a code error pattern sequence (code error syndrome) and a code sequence position can be one-to-one correspondence before and after conversion. Therefore, it is possible to execute processing equivalent to the above-described embodiment processing on the transmission code sequence on the decoded code sequence subjected to various code processing.
[0044]
In the present invention, in order to easily and more efficiently perform error code detection and correction processing for maximum likelihood sequence decoding as in the above embodiment, the decoded code sequence is a unit of a decoded code sequence block having a predetermined code length. Dividing and executing processing for error code detection and correction within each decoded code sequence block. This is based on the nature of random decoding error events under the noise conditions described in (a) above. When each code error event is regarded as a sequence (burst) error event, each error event is This is because it is considered to be randomly distributed on the decoded code sequence. In this way, the present invention achieves a practical decoding error probability by paying attention to the fact that the probability of random decoding error events caused by noise elements occurring at a certain code location is extremely rare. A decoding code sequence block having a predetermined code length is set so that the above is sufficient, and the number of decoding error events that can be detected and corrected in this decoding code sequence block is limited. As a result, the configuration of the error detection / correction code added on the transmission code sequence is relatively simple, the code length (redundancy) of the error detection / correction code string is kept low, and the decoding error rate is practically improved. Can fulfill. In the present invention, error detection correction coding is performed in advance so that a series of decoded code sequences continuously output from maximum likelihood sequence decoding can be subjected to error detection correction processing in units of decoded code sequence blocks. That is, a transmission code sequence before recording / transmission or a transmission (recording) code sequence supplied to a channel is divided into transmission or transmission (recording) code sequence block units corresponding to the decoded code sequence block, The error correction coding is applied to the transmission or transmission (recording) code sequence block so that a limited number of specific code error syndrome error events as described in the above embodiments can be corrected. Thus, a redundancy check code sequence for correction processing is generated. Then, it is transmitted / recorded by inserting / adding it to the transmission code sequence in correspondence with the transmission or transmission (recording) code sequence block. For example, if the error probability at the output of maximum likelihood sequence decoding is 1.0E-3, the decoding code sequence block length is set to about 1000 bits in the reciprocal order, thereby averaging the number of decoding error events occurring therein. It can be about 1 piece. Therefore, the transmission (recording) code sequence block length is set so that the corresponding decoded code sequence block is 1000 bits or less, and an error detection that can detect a specific error event in each transmission (recording) code sequence block By performing correction coding and adding a redundant check code sequence (error correction code sequence) for error detection and correction, error event relief and decoding error rate can be implemented. Further, when correcting an error event of a specific code error syndrome spanning a plurality of decoded code sequence blocks, a high frequency specified as a predetermined code error pattern sequence (code error syndrome) set in error correction coding A partial sequence of the code error pattern sequence (code error syndrome) is included and set.
[0045]
In general, in a decoding system having a certain decoding error rate, a redundancy check code sequence (error correction code sequence) is set to increase the detection and correction capability of an error correction code to be added as the transmission (recording) code sequence block length is set larger. The code length of the transmission (recording) code sequence and the configuration and length of the redundancy check code sequence (error correction code sequence) are each selected according to the embodiment. . In the present invention, error detection / correction coding and correction processing configured for a transmission (recording) code sequence block includes a known error detection code / error correction code such as a cyclic redundancy check (CRC). It can be easily configured by technology. Therefore, providing an effective error detection and correction code construction method having a low redundancy for a specific code error pattern and correction number capability is beyond the scope of the present invention and will not be described here. Further, as described above, performing error correction in units of transmission (recording) code sequence blocks divided into a predetermined code length is further advantageous when this error correction processing is performed by soft decision processing. A method of increasing the gain of correction coding by correcting the error event of the specific code error syndrome of the present invention by soft decision processing using analog code information can be given from a known technique. The realization scale of the error correction processing circuit generally increases in proportion to the power of the code length of the correction processing. As the number of error correction processing circuits (error correction decoders) increases, the error correction is performed by limiting the code length of each error detection and correction process to the transmission (recording) code sequence block unit as described above. It is possible to reduce the required circuit scale of the processing circuit (error correction decoder) and provide a real scale implementation. As described above, in the present invention, the decoding error characteristic information of the maximum likelihood sequence decoding is effectively used, and efficient decoding reliability is improved by simple error correction means with low redundancy. For this reason, an error correction means is connected to the maximum likelihood sequence decoder and a processing configuration in which both are positively combined is adopted. In the present invention, based on the nature of the maximum likelihood sequence decoding error of (a) and (b), a high-frequency code error event having a specific code error syndrome is limited within a code sequence of a predetermined length. By constructing a low-redundancy error correction code that corrects up to the number of occurrences, the reliability of transmission / recording / reproduction information can be improved by using an error correction detection code with a simple configuration according to existing technology. It will be an advantage. The above is the implementation principle of the present invention.
[0046]
FIG. 1 is a first basic embodiment showing a flow of processing of an information code sequence in an information recording / reproducing method and recording / reproducing apparatus according to the present invention. In this embodiment, the information code sequence 300 to be recorded / reproduced is subjected to a code conversion process to which a predetermined constraint condition such as a run length restriction is added via an encoding / modulation circuit 301 (recording code modulation process). Is done. A first error correction encoding circuit (first error correction encoder circuit) 304 performs a first error correction encoding process on the pre-recorded recording code sequence 302 converted and output by this processing. . In the present embodiment, the first error correction encoding circuit 304 generates an error check redundant code sequence (first error correction code sequence) for error detection and correction for the input recording code sequence 302. An error correction code string generation circuit 304 a and an error correction code string insertion circuit 304 b that inserts / adds the generated check redundant code string (first error correction code string) at a predetermined code position on the recording code sequence 302. Is done. As described in the above-mentioned principle of implementation of the present invention, a specific high-frequency code error pattern on a decoded code sequence limited by the configuration of the recording / reproducing system channel and the maximum likelihood sequence decoding method (decoder) An event is set in advance as a predetermined code error pattern (code error syndrome), and the error correction code string generation circuit 304a converts an input recording code string 302 into recording code string blocks 302a, 302b, and 302c each having a predetermined code length. .., And the decoding error event of the set high-frequency code error pattern (code error syndrome) is recorded for each recording code sequence block. Each recording code sequence block 302a, 302b, 302c. In order to detect and correct up to a predetermined number within the code sequence unit (first code error detection and correction process), Against recording code sequence block, performs error correction coding. When the error correction encoding to be realized is based on systematic encoding that is often used for this type of error correction encoding, such as cyclic redundancy encoding, each recording code sequence block 302a, 302b is generally used. , 302c... Corresponding to error check redundant code strings (first error correction code strings) 303a, 303b, 303c. The error correction code string insertion circuit 304b divides the input recording code sequence 302 into recording code sequence blocks 302a, 302b, 302c... And in many cases, immediately after each recording code sequence block 302a, 302b, 302c. Are sequentially inserted into error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c,... Corresponding to the recording code sequence block generated and output from the error correction code sequence generation circuit 304a. This is output as a channel recording code sequence 305. The error correction code string insertion circuit 304b can be easily configured by a delay memory circuit that delays the input recording code series 302 in units of recording code series blocks 302a, 302b, 302c. Further, when the error correction coding to be realized is systematic coding such as convolutional coding, redundancy for error checking is added to each recording code sequence block 302a, 302b, 302c. In this state, it is output from the error correction code string generation circuit 304a and sequentially output as a channel recording code sequence 305. In this way, the channel recording code sequence 305 to which the recording code sequence 302 is subjected to error correction coding or to which an error check redundant code sequence (first error correction code sequence) is added is recorded in the recording / reproducing system. Supplied to channel 306. The configuration of the recording / reproducing system channel 306 specifically differs depending on the information recording / reproducing system to which the present invention is to be implemented, but generally, the recording signal processing system 306a, recording head 306b, recording medium 306c, reproducing head 306d The reproduction signal processing system 306e is used. As an example, the recording signal processing system 306 a includes a code processing circuit 307 a that performs predetermined code processing such as precoding on the channel recording code sequence 305, and a code signal conversion circuit that converts the channel recording code sequence 305 into a recording signal sequence 308. 307b, a recording signal processing circuit 307c for performing predetermined signal processing such as recording signal correction processing on the recording signal series 308, a recording signal amplifier 307d, and the like. The recording signal sequence 306f output through the recording signal processing system 306a is supplied to the recording head 306b, whereby the channel recording code sequence 305 is recorded on the recording medium 306c.
[0047]
Information of the channel recording code sequence 305 recorded in the recording process as described above is extracted as a reproduction signal sequence 306g from this output using the reproduction head 306d in the reproduction process, and is supplied to the reproduction signal processing system 306e. Predetermined processing. As an example, the reproduction signal processing system 306e includes a reproduction signal amplifier 308a that amplifies an input reproduction signal sequence 306g, a variable gain amplification circuit 308b that compensates for signal amplitude variation of the reproduction signal sequence 306g, and a reproduction signal sequence 306g. Filter circuit 308c for removing unnecessary (high frequency) noise (high frequency cutoff), sampling circuit (analog / digital converter) 308d for discretizing and quantizing the analog reproduction signal series 306g into digital signal values, reproduction It comprises an equalization processing circuit 308e for performing signal waveform equalization processing on the signal series 306g, and reproduces a gain control signal 308g for the variable gain amplification circuit 308b, a sample timing control signal 308h for the sampling circuit 308d, etc. Tie for reproducing and extracting from information of signal series 306g Such ring play-gain control circuit 308f is also often included. The reproduction signal sequence 306e subjected to the above processing by the reproduction signal processing system 306e is output as a decoded signal sequence 309 and supplied as an input of the maximum likelihood sequence decoding circuit 310. The maximum likelihood sequence decoding circuit 310 performs decoding processing by the maximum likelihood sequence estimation method as described above, and outputs a decoded code sequence 311 as a decoding result. At this time, the decoding code sequence 311 may be subjected to predetermined code processing such as post-code processing as necessary. The output of the maximum likelihood sequence decoding circuit 310 includes a first error detection and correction processing circuit (first error correction circuit) corresponding to the first error correction coding circuit (first error correction encoder circuit) 304 in the recording process. Correction decoder circuit) 313 is provided. In the first error detection / correction processing circuit (first error correction decoder circuit) 313, a decoded code sequence 311 corresponding to the recording code sequence blocks 302a, 302b, 302c,. The first code error detection / correction process is performed on each of the decoded code sequence blocks 311a, 311b, 311c. That is, the first error detection / correction processing circuit (first error correction decoder circuit) 313 synchronously supports error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c,. Decoding error check redundant code sequences (first error correction code sequences) 312a, 312b, 312c,... On the decoded code sequence 311 to be used, A predetermined first code error detection and correction process is performed. In the configuration example of the present embodiment, the first error detection / correction processing circuit (first error correction decoder circuit) 313 includes a code error check correction circuit 313a and an error check redundant code sequence removal circuit 313b. The code error check and correction circuit 313a converts the input decoded code sequence 311 into recording code sequence blocks 302a, 302b, 302c... (Decoded code sequence blocks 311a, 311b, 311c...) And error check redundant code sequences 303a, 303b, 303c. (Decoding error check redundant code sequences 312a, 312b, 312c,...), And the decoded code sequence blocks 311a, 311b, 311c,. The error code inspection based on the first code error detection and correction process is performed. The error check redundant code sequence removal circuit 313b converts the input decoded code sequence 311 into recording code sequence blocks 302a, 302b, 302c (decoded code sequence blocks 311a, 311b, 311c...) And error check redundant code sequences 303a, 303b, 303c... (Decoding error check redundant code string 312a, 312b, 312c...), And the decoded error check redundant code string 312a, 312b, 312c. Then, only the decoded code sequence blocks 311a, 311b, 311c... After being subjected to the error check correction by the code error check correction circuit 313a are used as the corrected decoded code sequence 314 of the continuous code time series at a predetermined code reproduction speed. Output. The error check redundant code sequence removal circuit 313b can be easily configured by a delay storage circuit that delays an input code sequence in units of decoded code sequence blocks 311a, 311b, 311c. Further, when the error correction coding scheme to be realized is based on non-systematic coding, the redundancy for error checking is in a form inherent in each decoded code sequence block 311a, 311b, 311c. One error detection / correction processing circuit (first error correction decoder circuit) 313 separates an input decoded code sequence 311 into decoded code sequence blocks 311a, 311b, 311c,. Are subjected to a predetermined error correction process, and the decoded code sequence block after the error correction process is output as a corrected code sequence 314 of a continuous code time series at a predetermined code reproduction speed. (The error check redundant code sequence removal circuit 313b is in the form inherent in the code error check correction circuit 313a.) Also, as in a known example described later, decoded code sequence blocks 311a, 311b, 311c,. Even when the code strings 312a, 312b, 312c,... Are separated and recorded / reproduced, the first error detection / correction processing circuit (first error correction decoder circuit) 313 is .., The decoded code sequence 311 is separated into decoded code sequence blocks 311a, 311b, 311c..., And a decoding error check redundant code sequence (first error correction code) corresponding to each decoded code sequence block input simultaneously. Sequence) 312a, 312b, 312c... Are used for the decoded code sequence block to perform error correction processing, and the decoded code sequence block after error correction processing is performed. The click, as correction decoding code sequence 314 consecutive code time series, and outputs a predetermined symbol recovery speed. (The function of the error check redundant code sequence removal circuit 313b is not required.) Finally, the corrected decoded code sequence output via the first error detection / correction processing circuit (first error correction decoder circuit) 313. 314 is input to the demodulation processing circuit 315 (recording code demodulation processing), and through this, the code conversion processing corresponding to the code conversion processing in the encoding / modulation processing circuit 301 (recording code modulation processing) in the recording process is performed. The decoded code sequence 316 corresponding to the original information code sequence 300 is reproduced. The above is the outline of the first basic embodiment of the present invention in FIG. In the implementation of the present invention, since the first code error check and correction process is premised on the use of the decoding error characteristic of the maximum likelihood sequence decoder 310, generally, as shown in FIG. The decoded code sequence 311 decoded and output from the likelihood sequence decoder 310 is input to the first error correction encoding circuit (first error correction encoder circuit) 304 without logically changing the code order. Or entered directly. The processing such as the above-described postcode only performs constant processing sequentially on each code without logically replacing or replacing the code order of the decoded code sequence 311. Therefore, before and after the processing, the decoding error syndrome can correspond one-to-one, is not spread on the code sequence, and does not perform an operation of changing the logical order. In accordance with the principle of the invention, a first error correction coding circuit (first error correction encoder circuit) 304 as a first code error check and correction means is connected to a maximum likelihood sequence decoder 310 as a decoding means. The point which takes this structure is the structural feature of the present invention. This often results in embodiments in which the invention is implemented with integrated circuits, where both are mounted on a single integrated circuit.
[0048]
FIG. 2 is a diagram for explaining the flow of the code sequence in the first basic embodiment of FIG. The information code sequence 300 recorded and reproduced in the present invention is converted into the recording code sequence 302 by the recording code modulation processing in the encoding / modulation processing circuit 301, and then the first error correction coding circuit (first (Error correction encoder circuit) 304 is divided into recording code sequence blocks 302a, 302b, 302c,... Of a predetermined code length, and error check redundant code sequences (first codes) are recorded for the respective recording code sequence blocks 302a, 302b, 302c,. (One error correction code sequence) 303a, 303b, 303c... The generated error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c... Is placed at a predetermined recording position corresponding to the recording code sequence block, and the recording code sequence blocks 302a, 302b. , 302c... If the error check redundant code string (first error correction code sequence) 303a, 303b, 303c,... Can be reproduced together while corresponding to the recording code sequence block, they are recorded in a separated form. Although reproduction processing may be performed, in many cases, recording / reproduction processing is performed as a batch code sequence. In this case as well, error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c... Are recorded on and reproduced from the recording code sequence 302 in correspondence with the recording code sequence block. In many cases, it is inserted / added immediately before / after the recording code sequence block or at a predetermined code position inside. Most generally, each error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c,... Is generated and processed with reference to the recording code sequence block. In addition, each is inserted and added to the code position immediately after the recording code sequence. This is a processing delay even when performing error correction processing on the decoded code sequence block using each error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c. The correction processing efficiency is the best by shortening the time. Each of the error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c,... Is configured as a check redundant code sequence with an extremely low redundancy and a very short code length according to the principle of the present invention. Therefore, even if the encoding / modulation processing circuit 301 adds a predetermined constraint condition such as a run length limit to the recording code sequence 302 after being added in a distributed manner, this constraint condition is greatly hindered. It will not be. Further, since the configuration of the error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c,... Is relatively simple and has a short code length, for example, a simple guard code is used when configuring this. It is also possible to generate error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c,... When the generated error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c,... Is relatively long, and it becomes a problem to destroy the above code constraint condition by inserting and adding it. Can be avoided by dividing each error check redundant code string (first error correction code sequence) into a plurality of parts and inserting / adding them at predetermined recording positions and code positions. . A recording code sequence 302 into which error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c,... Are inserted is supplied as a channel recording code sequence 305 to a recording / reproducing system channel 306 and recorded. It is processed. Each recording code sequence block 302a, 302b, 302c,... Is a series of code sequence blocks that are successively decoded by a single maximum likelihood sequence decoder 310 in the reproduction process, as will be described later. Therefore, in the normal recording / reproducing mode, the channel recording code sequence 305 is recorded / reproduced in this code order, and is recorded on the recording medium 306c at physically continuous recording positions in this code order and code form. Will be. Such recorded code forms on the medium illustrate the practice of the present invention. The decoded code sequence 311 output from the maximum likelihood sequence decoder 310 also has a code form similar to that of the channel recording code sequence 305, and the decoded code sequence blocks 311a, 311b, corresponding to the recording code sequence blocks 302a, 302b, 302c,. 311c, and immediately after the decoded code sequence block, the decoded error check redundant code sequence (first error correction code sequence) corresponding to the error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c. (Sequence) 312a, 312b, 312c... The first error detection / correction processing circuit (first error correction decoder circuit) 313 uses the decoded error check redundant code sequence (first error correction code sequence) 312a, 312b, 312c. After the first error code detection and correction process is performed on the sequence block, only the decoded code sequence blocks 311a, 311b, 311c,... Are output as the corrected decoded code sequence 314. In the demodulating circuit 315 (recording code demodulating process), a code conversion process corresponding to the recording code modulation process is performed on this, and the decoded code sequence 316 corresponding to the original information code sequence 300 is reproduced.
[0049]
The implementation of the present invention described above can take various forms depending on the target information recording / reproducing method, information recording / reproducing apparatus, and recording / reproducing system channel. Further, as described above, the details of the configuration of the invention in FIG. 1 are also changed by means of error code detection / correction coding and correction processing used in the first error detection / correction processing. The basic feature is that a first error correction encoding circuit (first error correction encoder circuit) 304 is a recording code sequence block 302a, 302b, 302c in which a recording code sequence 302 is a code sequence unit of a predetermined code length. Are logically separated into each of the recording code sequence blocks, and the first error correction encoding process is performed on each recording code sequence block, which is then output, and the first error correction processing circuit ( The first error correction decoder circuit) 313 logically separates the decoded code sequence 311 into decoded code sequence blocks 311a, 311b, 311c,. system The block, after straining facilities the first error detection and correction processing is that for output. Check redundancy for error detection and correction generated in the first error correction coding circuit (first error correction encoder circuit) 304, that is, error check redundant code string (first error correction code sequence) 303a. , 303b, 303c,... Are added to the recording code sequence 302 (information code sequence) as shown in FIG. 1 in many embodiments, but this includes means for managing only the correspondence between each other. They may be handled separately from each other and recorded and reproduced by different recording media 306 c and different recording / reproducing channels 306. According to the principle of implementation of the present invention, check redundancy for error detection and correction generated in the first error correction coding circuit (first error correction encoder circuit) 304, that is, an error check redundant code string (first error correction code string) The size of one error correction code sequence (303a, 303b, 303c,...) Can be made extremely small relative to the size of the information code to be recorded / reproduced. It is reasonable to separate the code strings (first error correction code sequences) 303a, 303b, 303c... And record / reproduce them in consideration of processing efficiency, hardware costs, or recording / reproduction costs. There are many cases. Recording code sequence blocks 302a, 302b, 302c... And error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c... Are recorded on different recording positions on the same recording medium 306c and on the same recording / reproducing apparatus. A plurality of recording / reproducing devices of the same type and a plurality of recording / reproducing means of the same type (for example, a plurality of magnetic disk devices) or different types of recording / reproducing devices and recording / reproducing means (for example, the magnetic recording device) Various forms such as recording the device and the latter in the semiconductor memory means / device) can be implemented. In addition, it is possible to realize a form in which the two pieces of information recorded separately are simultaneously reproduced by a plurality of transducers (reproducing heads 306d), or are reproduced by being temporally separated by the same transducer (reproducing head 306d). . The most rational and economical embodiment is realized by combining the information recording / reproducing method and the information recording / reproducing apparatus or the combination of different information recording / reproducing methods and information recording / reproducing apparatuses. . Further, the second basic feature of the above-described embodiment configuration is that each sequence of the decoded code sequence blocks 311a, 311b, 311c,... Is always physically continuous from the specific maximum likelihood sequence decoder 310. A method of separating the recording code sequence blocks 302a, 302b, 302c,... From the recording code sequence 302 corresponding to the units of the decoded code sequence blocks 311a, 311b, 311c,. Is the point to be determined.
[0050]
FIG. 3 shows a second basic embodiment for clarifying the second feature, and the present invention in the case where a single recording code sequence 302 is recorded / reproduced by a plurality of recording / reproduction system channels 306. An example is shown. Here, a plurality of recording / reproducing system channels as shown in FIG. 3, including an information recording / reproducing method and an embodiment of the information recording / reproducing apparatus, in which a plurality of the above-described target information can be separated and recorded and processed at the same time. An embodiment is shown in which 306 is provided and these units operate simultaneously for one recording / playback processing unit. In this way, a single information code sequence 300 is separated and recorded / reproduced by a plurality of recording / reproducing system channels 306 by a multiplexer circuit (code sequence selection circuit) 348a and a demultiplexer circuit (code sequence selection circuit) 348b. In the case of an information recording / reproducing method or information recording / reproducing apparatus in which each channel output is decoded in parallel or separated by a plurality of maximum likelihood sequence decoders 310, each maximum likelihood sequence decoding is performed. The first error detection and correction processing by the first error correction encoding circuit (first error correction encoder circuit) 304 is logically performed on the decoded code sequence 311 output from the generator 310. The code sequence 311 is applied independently while maintaining the physical code output order. This is because the principle of the present invention uses the nature of the decoding sequence error of the maximum likelihood sequence decoder 310 as described above.
[0051]
Therefore, in many embodiments in such a case, the first error detection is independently performed for each output of the maximum likelihood sequence decoder 310 connected to each recording / reproducing system channel 306 as shown in FIG. A correction processing circuit (first error correction decoder circuit) 313 is provided. (Each sequence may be provided independently from the encoding / modulation processing circuit 301.) Then, the decoding code sequence 311 serially output from each maximum likelihood sequence decoder 310 is maintained in a predetermined code order. The first error detection and correction process is performed. At this time, the decoding code sequence 311 from the maximum likelihood sequence decoder 310 connected to each recording / reproducing system channel 306 is independently set to a decoding code sequence block 311a, 311b, 311c,. Then, a predetermined first error detection and correction process is performed on each decoded code sequence block. In the recording process, the information code sequence 300 is separated into a plurality of sequences for supply to a plurality of recording / reproducing channels 306, and then a first error correction coding circuit (first .., 304 is used to separate each sequence into recording code sequence blocks 302a, 302b, 302c... Corresponding to the decoded code sequence blocks 311a, 311b, 311c. Is supplied to each recording / reproducing system channel 306 to perform recording processing. In this embodiment, a first error correction coding circuit (first error correction encoder circuit) 304 and a first error detection correction processing circuit (first error correction decoder circuit) 313 are connected to a recording / playback channel. Although a plurality of independent units are provided for each 306, it is possible to realize an equivalent processing method and configuration by a single circuit and means. As described above, in the present invention, in order to effectively use the decoding error characteristic of the maximum likelihood sequence decoder 310, the decoded code sequence 311 from the maximum likelihood sequence decoder 310 is not changed in code order. The embodiment supplied to the error correction encoding circuit (first error correction encoder circuit) 304 is effective. Therefore, in many embodiments, as in the example of FIG. 1 or FIG. 3, the output of the decoded code sequence 311 from the maximum likelihood sequence decoder 310 is a first error correction coding circuit (first error correction coding circuit). The encoder circuit) 304 is directly connected to or close to the input. Since there is a code conversion process between the two, in many cases, the code error pattern (code error syndrome) to be set increases in the first error correction encoding process and the first error detection correction process. , Processing becomes impossible, or error encoding / correction processing, first error correction encoding circuit (first error correction encoder circuit) 304 and first error detection correction processing circuit (first error correction) This is because the decoder circuit 313 becomes extremely complicated. Therefore, as seen in the above first and second embodiments, predetermined code constraint conditions such as run-length restriction on the channel recording code sequence 395 in information recording / reproduction to which the present invention is applied. When a recording code modulation process and a recording code demodulation process for adding a constraint condition are required, the recording code modulation process for the information code sequence 300 is performed before the first error correction encoding process is performed. The recording code demodulating process for the code sequence 311 is effectively performed after the first error code detection / correction process. Therefore, in the implementation of the present invention, the first code error check and correction process is based on the assumption that the decoding error characteristic of the maximum likelihood sequence decoder 310 is used. Therefore, as shown in FIG. The decoded code sequence 311 decoded and output from the maximum likelihood sequence decoder 310 logically changes the code order with respect to the first error correction encoding circuit (first error correction encoder circuit) 304. It is input without it, or it is input directly. In accordance with the principle of the invention, a first error correction coding circuit (first error correction encoder circuit) 304 as a first code error check and correction means is connected to a maximum likelihood sequence decoder 310 as a decoding means. This configuration is a structural feature of the present invention. As described above, when the present invention is implemented by an integrated circuit, it often results in an embodiment in which both are mounted on a single integrated circuit.
[0052]
FIG. 4 shows a third basic embodiment of the present invention. In this embodiment, in the recording process, the second error correction encoding circuit (second error correction encoder circuit) 317 for the information code sequence 300 is replaced with the first error correction encoding circuit (first error correction code). Device circuit) 304 before the second error correction coding process. In the reproduction process, a second error detection correction processing circuit (in order to perform the second error code detection correction processing corresponding to the second error correction encoding processing on the reproduction code sequence 316 before output) (Second error correction decoder circuit) 318 is placed after the first error correction encoding circuit (first error correction encoder circuit) 313. The second error correction coding process and the second error code detection / correction process are the same as the first error code detection / correction process (the specific error code event of the set predetermined code error syndrome in the above embodiments). In addition to decoding error events that cannot be detected and corrected in a process that detects and corrects up to a predetermined number of occurrences), or other than random noise factors that can occur in the actual recording / reproduction process It is provided for the purpose of obtaining a desired recording / reproducing reliability by relieving a decoding error event which cannot be predicted.
[0053]
According to the implementation principle of the present invention, the probability of occurrence of error code events of code error syndromes not subject to correction in the first error code detection and correction process, and a predetermined number (error detection and correction capability in a single decoded code sequence block) The occurrence probability of error code events exceeding ()) is relatively low, so in the present invention, decoding error events that cannot be corrected by the first error code detection / correction processing or error correction processing are performed. It is noted that the probability that a decoding error event occurs continuously or frequently in a plurality of decoded code sequence blocks is extremely small. Therefore, in the present embodiment, in the recording process, for example, on the information code sequence 300 that is continuously recorded and reproduced in one operation unit of recording and reproduction processing such as a sector unit in the disk device and a block unit in the tape device. Code sequence unit (recording frame) or a code sequence unit on the information code sequence 300 corresponding to a plurality of batch recording code sequence blocks 302a, 302b, 302c. A processing unit (information code frames 319a, 319b, 319c,...) In correction coding and second error code detection and correction processing. In the recording process, the second error correction encoding circuit (second error correction encoder circuit) 317 performs the second error correction on the information code sequence 300 on each of the information code frames 319a, 319b, 319c,. Error correction coding processing is performed, or error check redundant code strings (second error correction code sequences) 320a, 320b, 320c,. In the reproduction process, the second error detection / correction processing circuit (second error correction decoder circuit) 318 reproduces reproduction code frames 325a, 325b corresponding to the information code frames 319a, 319b, 319c,. 325c... As a processing unit, decoded error check redundant code sequence (second error correction code sequence) decoded corresponding to error check redundant code sequence (second error correction code sequence) 320a, 320b, 320c. 326 a, 326 b, 326 c... Are used for the reproduction code frame 325, the second error code detection and correction process is performed, and this is output as a final reproduction code sequence (1) 316 a.
[0054]
As described above, the second error correction encoding process and the second error code detection correction process are intended to correct a non-correctable or uncorrectable code event in the first error code detection correction process, Such code error events include many burst-like code error events due to a decoding error propagation phenomenon in the maximum likelihood sequence decoder 310. In addition, the occurrence of error code events exceeding the predetermined number (correction capability of the first error code detection / correction process) is treated as a set of multiple error events, and is erroneously corrected by the first error code detection / correction process. The resulting error event is also a relatively long code error event. In addition, decoding error events due to factors other than the random noise factors that occur in practice in recording and playback devices (defects on recording media and partial defects in the playback signal sequence) are also relatively low in probability, but are predicted during high-density recording. It is necessary to assume a difficult burst code error event having a very long code length. In view of the above, the second error correction coding process and the second error code detection correction process have various code errors compared to the first error correction coding process and the first error code detection correction process. It is necessary to apply a relatively strong error correction coding correction method such as a Reed-Solomon code for a long code error event taking a syndrome as a target of correction processing. In the known technique, such a powerful error correction coding correction method generally requires a code structure having a complicated and high check redundancy, and an error check configured and added to the information code sequence 300 by coding. Redundancy required for redundant code strings (second error correction code sequences) 320a, 320b, 320c,... In the present invention, the second error correction encoding process and the second error code detection correction process are performed from the nature of the occurrence probability of the code error event to be corrected in the second error correction encoding process as described above. Compared with the first error correction coding process and the first error code detection and correction process, a relatively long code string unit on the information code sequence 300 (information code frames 319a, 319b, 319c... And reproduction code frame 325a, 325b, 325c, etc. Thereby, it is possible to avoid a decrease in recording / reproduction efficiency and a complicated error correction coding and correction process due to an increase in the check code redundancy. Random short code errors that occur frequently are the first errors of relatively low redundancy that are distributedly encoded on the recording code sequence 302 in units of recording code sequence blocks. A long code error that occurs in a relatively low frequency continuous burst is a second error correction code that uses a long information code frame 319 as a unit of correction processing. In this way, correction processing is performed using a strong (high redundancy) error correction code, and the first error correction encoding and the first error code detection correction processing, By using the error correction coding and the second error code detection / correction processing in a complementary manner, in the second error code detection / correction processing, the burden on the correction processing and the correction capability for a wide range of random decoding errors are corrected. Loss can be avoided, and the optimal configuration of error correction coding / correction processing with an emphasis on the correction target for long burst decoding error events can be facilitated. Therefore, it is possible to effectively and efficiently improve the error correction efficiency and decoding reliability in the entire recording / reproducing process, and without using the first error code detection / correction process as in the past, the second error In contrast to the case where the same decoding reliability is to be ensured only by the code detection and correction process, the required error check redundancy can be kept low, and an efficient error detection and correction means in information recording and reproduction can be realized. The configuration method of the error correction code and the second error code detection / correction process in the second error correction encoding process are not described in detail here because they can be realized by a known technique. The processing capability required for the processing and the second error code detection / correction processing, the configuration of the error correction code, the code length of the information code frames 319a, 319b, 319c,... Appropriate settings can be made according to the live channel and device and the desired information recording / reproduction reliability. As seen in the present embodiment, in information recording / reproduction to which the present invention is applied, a recording code modulation process and a recording code for adding a predetermined code constraint condition such as run length restriction or a constraint condition on the channel recording code sequence 305 When demodulation processing is required, since the error check redundant code string in the second error correction coding is relatively long, the second code for the information code sequence 300 is used to hold the code constraint condition and the constraint condition. An embodiment in which the recording code modulation process is performed after the error correction coding process is performed and the recording code demodulation process is performed on the decoded code sequence 311 and then the second error code detection and correction process is performed. A second error correction encoding circuit (second error correction encoder circuit) 317 is placed in front of the encoding / modulation processing circuit 301, and a second error code detection correction processing circuit ( Form second error correction decoder circuit) 318 is arranged downstream with respect to the demodulation processing circuit 315 is often taken in the form of a simple practical implementation.
[0055]
FIG. 5 is a diagram for explaining the flow of the code sequence in the third basic embodiment of FIG. The information code sequence 300 recorded and reproduced in the present invention is first input to a second error correction encoding circuit (second error correction encoder circuit) 317 provided in advance, and a predetermined information code frame 319 is processed. As a unit, the second error correction encoding process as described above is performed. When the second error correction coding is systematic error correction coding such as Reed-Solomon coding, the information code frames 319a, 319b, 319c,... Have error check redundancy. Error check redundant code sequences (second error correction code sequences) 320a, 320b, 320c,... Are generated and placed at predetermined recording positions corresponding to the information code frame 319 on the information code sequence (1) 300a. Both are recorded and played back. As in the case of the error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c... In the first error correction encoding, the error check redundant code sequence (second error correction code sequence). 320a, 320b, 320c... May be recorded / reproduced in the form of being separated as long as they can be recorded / reproduced together with the corresponding information code frame 319. Even if both are recorded and reproduced at different recording positions, recording media, recording devices and recording means, or are recorded and reproduced by different recording / reproducing channels, the present invention is implemented. Although possible, in many cases, both are recorded and reproduced as a batch of code sequences as shown in FIG. Also in this case, the error check redundant code sequence (second error correction code sequence) 320a, 320b, 320c... Is added to a predetermined code position if it can be recorded / reproduced in correspondence with the information code frame 319 on the information code sequence. However, in many cases, it is inserted / added immediately before / after the information code frame 319 or inside a predetermined code position. Most generally, each error check redundant code sequence (second error correction code sequence) 320a, 320b, 320c... Is generated and processed with reference to the information code frame 319. 1) Insertion is added to the code position immediately after the information code frame 319 on 300a. In the reproduction process, a second error code detection / correction process is performed on the information code frame 319 using each error check redundant code string (second error correction code sequence) 320a, 320b, 320c. Even in this case, the processing delay is shortened, and the correction processing efficiency is the highest. However, some code constraint condition has already been added to the information code sequence 300 input to the second error correction encoding circuit (second error correction encoder circuit) 317, and the error check redundant code sequence (Second error correction code sequence) 320a, 320b, 320c,..., And when it becomes a problem that this is destroyed, each error check redundant code sequence (second error correction code sequence) This can be avoided by dividing 320a, 320b, 320c,... Into a plurality of pieces and distributing and inserting them at predetermined recording positions and code positions in the information code frame 319. In many cases, the information code on the information code sequence (1) 300a output from the second error correction encoding circuit (second error correction encoder circuit) 317 as in the embodiment of FIG. After inserting / adding error check redundant code strings (second error correction code sequences) 320a, 320b, 320c,... At predetermined code positions corresponding to the frames 319a, 319b, 319c,. The recording code modulation process is performed.
As shown in FIG. 5, when the encoding / modulation processing circuit 301 is provided and the code conversion process is performed, each information code frame 319a, 319b, 319c,... Is added by adding a predetermined code constraint condition or code redundancy. On the recording code sequence 302, code conversion is performed corresponding to the recording code frames 321a, 321b, 321c. Further, error check redundant code sequences (second error correction code sequences) 320a, 320b, 320c,... Correspond to error check redundant code conversion sequences (second error correction code sequences) 322a, 322b, 322c,. Code conversion. (If the encoding / modulation processing circuit 301 is not provided, the information code frames 319a, 319b, 319c... And the recording code frames 321a, 321b, 321c. The conversion strings 322a, 322b, 322c,... Coincide with each other.) The first error correction encoding circuit (first error correction encoder circuit) 304 is similar to the embodiment of FIGS. The recording code frames 321a, 321b, 321c,... Are separated into recording code sequence blocks, and a first error correction encoding process is performed on each of the recording code sequence blocks. In the present embodiment, the first error correction encoding process is not performed on the error check redundant code conversion sequence (second error correction code sequence) 322a, 322b, 322c,... The error check redundant code conversion sequence (second error correction code sequence) 322a, 322b, 322c,... Is subjected to a first error correction encoding process and a subsequent first error code detection / correction process. There may be. In this case, each recording code frame (information sequence part) 300a, 300b, 300c... And the error check redundant code conversion sequence (second error correction code sequence) 320a, 320b, 320c. Assuming that recording code sequence blocks 302a, 302b, 302c,... Of a predetermined length are set, a first error correction encoding process and a first error code detection correction process for each separated recording code sequence block In addition, as shown in FIG. 5, only the recording code frames (information sequence sections) 300a, 300b, 300c,... Are separated into recording code sequence blocks 302a, 302b, 302c,. The first error correction encoding process and the first error code detection correction process for each are performed, and the error check redundant code conversion sequence (first Error correction code sequences) 320a, 320b, 320c,..., Independently, depending on the case, may be separated into blocks of a predetermined code length, and the same first error correction coding process and first error may be performed. A code detection correction process may be performed.
[0056]
As described above, error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c... And error check redundant code conversion sequences (second error correction code sequences) 322a, 322b, 322c. The added channel recording code sequence 305 is supplied to the recording / reproducing system channel 306 and subjected to recording processing. In the normal recording / reproducing mode, the channel recording code sequence 305 is recorded / reproduced in this code order, and is also recorded on the recording medium 306c at physically continuous recording positions in this code order and code form. It will be. Such recorded code forms on the medium illustrate the practice of the present invention. The decoded code sequence 311 output from the maximum likelihood sequence decoder 310 also takes the same code form as the channel recording code sequence 305, and in addition to the code form of the decoded code sequence 311 in the embodiment of FIG. , 321b, 321c,..., 321a, 323b, 323c,... Immediately after the decoded code frame 323, an error check redundant code conversion sequence (second error correction code sequence) 322a, .., 322b, 322c,..., A code sequence form to which decoding error check redundant code conversion sequences (second error correction code sequences) 324a, 324b, 324c,. In the first error detection / correction processing circuit (first error correction decoder circuit) 313, in each decoded code frame 323a, 323b, 323c,..., Decoding error check redundant code string (first error correction code sequence) 314a. 314b, 314c, etc., the first error code detection / correction process is performed on the decoded code sequence block. Thereafter, the decoded error check redundant code sequence (first error correction code sequence) 312a, 312b, 312c... Is excluded, and the corrected decoded code sequence 314 is output. On the other hand, the demodulation processing circuit 315 (recording code demodulation processing) performs code conversion processing corresponding to the recording code modulation processing. The decoded code frames 323a, 323b, 323c,... On the corrected decoded code sequence 314 are code-converted into reproduction code frames 325a, 325b, 325c,. 324a, 324b, 324c,... Are code-converted into decoded error check redundant code sequences (second error correction code sequences) 326a, 326b, 326c,... To obtain a reproduction code sequence (1) 316a. In the second error detection / correction processing circuit (second error correction decoder circuit) 318, on the reproduction code sequence (1) 316a, each reproduction code frame 325a, 325b, 325c,. Using the redundant code string (second error correction code sequence) 326a, 326b, 326c,..., After performing the first error code detection correction process, obtain the normal reproduction code frames 325a, 325b, 325c,. Reproduced and output as a reproduced code sequence 316. In the above description of the embodiment, when the second error correction coding means is unorganized error correction coding such as convolutional coding, an error check redundancy code string (second The error correction code series (320a, 320b, 320c,...) Are inserted and added in each information code frame 319a, 319b, 319c,. Therefore, the error check redundant code conversion sequence (second error correction code sequence) 322a, 322b, 322c..., The decoding error check redundant code conversion sequence (second error correction code sequence) 324a, 324b, 324c. The check redundant code strings (second error correction code sequences) 326a, 326b, 326c,... Are not distinguished from each other and are not subjected to recording / reproduction processing, but a second error detection / correction processing circuit (second error correction decoder circuit). In 318, the error detection redundancy inherent in each reproduction code frame 325a, 325b, 325c,... Is used to perform a second error code detection / correction process on each reproduction code frame, and this is performed as a reproduction code sequence 316. Output as.
[0057]
In general, in many information recording / reproducing methods and recording / reproducing apparatuses, the unit of the second error correction encoding process and the second error code detection / correction process is, for example, a disk device for convenience in controlling the recording / reproducing process. Code sequence units (record frames) on the information code sequence 300 that are continuously recorded / reproduced in one operation unit of recording / reproduction processing, such as a sector unit in a tape unit or a block unit in a tape device, The frame 319 is reasonable.
[0058]
FIG. 6A shows the recording code form of the recording frame, that is, the code form of the information code series 300 in this embodiment and the channel recording code series 305 continuously recorded on the recording medium 306c. On the information code sequence 300, the recording frame (information encoding unit) 326 is configured by adding a preamble 326a and a postamble 326b as necessary. In particular, the preamble 326a includes the recording frame (information encoding unit) 349. Information indicating a recording position, information for performing signal gain control / signal timing detection, learning information for adjusting the recording signal processing system 306a / reproduction signal processing system 306e, and a recording frame (information encoding unit) 349 The synchronization information indicating the start is included. In this embodiment, the recording frame (information code portion) 326 corresponds to each of the information code frames 319a, 319b, 319c,... In the embodiment of FIG. 5, but in other embodiments, the preamble 326a and the postamble 326b. In some cases, all or part of the information code frame 319 may be processed. In this embodiment, on the channel recording code sequence 305, the recording code frame 321 which is the information after the recording code modulation processing of the recording frame (information code unit) 326 is recorded code sequence blocks 302a, 302b having a predetermined code length, Divided into 302c... As shown in the embodiment of FIGS. 2 and 5, error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c,... It is divided or inserted / added into a predetermined code position corresponding to the sequence block and recorded on the recording medium 306c. In this embodiment, each error check redundant code sequence (first error correction code sequence) is collectively inserted and added at the code position immediately after the recording code sequence block, and is recorded on the recording medium 306c. To be recorded.
[0059]
Further, as shown in the embodiment of FIG. 5, the error check redundant code conversion sequence (second error correction) is applied to the recording frame (information encoding unit) 326 by the second error correction encoding process and the recording code modulation process. When the (code sequence) 322 is configured, the information is divided or inserted and added to a predetermined code position corresponding to the recording code frame 321 as the information, and is recorded on the recording medium 306c. In this embodiment, each error check redundant code conversion sequence (second error correction code sequence) 322 is collectively inserted / added to the code position immediately after the recording code frame 321 to record the recording medium 306c. Recorded above. As described in the embodiment of FIG. 5, in the other embodiments, the first error correction coding is applied to the error check redundant code conversion sequence (second error correction code sequence) 322 as well. In some cases, an error check redundant code sequence (first error correction code sequence) 303 is added, and this error check redundant code conversion sequence (second error correction code sequence) 322 is included in the recording code frame 321. In some cases, the first error correction coding target. Further, as described above, when using the non-systematic error coding method, error check redundant code sequences (first error correction code sequences) 303a, 303b, 303c,... Are recorded in the corresponding record code sequence blocks 302a, 302b. , 302c... Or the error check redundant code conversion sequence (second error correction code sequence) 322 is included in the recording code frame 321. In the present embodiment, the recording frame 349 is continuously recorded on the recording medium 306c by the recording code form of the channel recording code sequence 305 as described above.
[0060]
As shown in the embodiments of FIGS. 4 and 5, in the present invention, the second error correction coding process and the second error code detection and correction process have a relatively long code error event. Therefore, error correction coding using a continuous code sequence (information symbol) having a predetermined code length, such as Reed-Solomon error correction coding, as a unit of correction processing is used. Therefore, the information code frame 319 to be processed in the second error correction encoding process is often regarded as such a sequence of information symbols 327 (for example, in units of bytes) and handled. Further, in the second error correction encoding process and the second error code detection correction process, in order to easily detect and correct a code error event having a longer code length, the second error correction encoding process The information code frame 319 to be processed is divided into n independent information symbol sequences (n is a natural number) by interleave processing in units of information symbols, and a second error correction is performed for each information symbol sequence. It is practical to perform the encoding process. FIG. 6B shows a recording code form of the information code frame 319 subjected to such interleaving processing (n = 4). In the second error correction coding process, in the information code frame 319 regarded as a sequence of information symbols 327, every (n−1) information symbols 327 are regarded as a series of sequences, and for each sequence, An error check redundant code string (second error correction code sequence) 320 is configured. As a result, while applying error correction coding with the same correction capability as the second error correction coding process, this is performed independently and in parallel on the n information symbols 327, so that the second error code detection and correction process is performed. The maximum information symbol length of burst code error correction processing in this case can be made n times. In the present embodiment, each information symbol 327 in the information code frame 319 is regarded as one continuous series by every third information symbol 327 indicated by the same diagonal line by four series of interleaving processes. In the second error correction coding process, error check redundant code strings A, B, C, and D (second error correction are performed for each of four sequences A, B, C, and D of information symbols 327. Code sequence) 328a, 328b, 328c, and 328d are configured and added to the information code frame 319 on the information code sequence (1) 300a in units of information symbols 327 in the same interleave format. In FIG. 6B, information code frames 319 are included in the information symbols 327 constituting the error check redundant code sequences A, B, C, and D (second error correction code sequences) 328a, 328b, 328c, and 328d, respectively. The same hatching as that of the information symbol 327 of the series is attached. By such an interleaving process, a code error event that continuously occurs in four information symbols 327 on the information code sequence (1) 300a is logically divided into four single information symbols 327 and corrected. Even if the second error correction encoding process having the same correction capability is used, it is possible to correct a burst code error event having a four times information symbol length by correcting the four sequences independently and in parallel. .
[0061]
FIG. 6C shows a recording code form of the information code frame 319 subjected to such interleaving processing (n = 4), that is, a code form in the channel recording code sequence 305. A channel recording code sequence 305 is obtained by performing a predetermined recording code modulation process on the information code sequence (1) 300 having the code form of FIG. 6B and then performing a first error correction encoding process. Is obtained. In this embodiment, the code length of the recording code sequence blocks 302a, 302b,... Corresponds to the code string unit of the continuous natural number of information symbols 327 constituting the information code frame 319 before the recording code modulation process. It is desirable to do. Thus, the code unit (recording code sequence block 302) of the encoding / correction processing in the first error correction encoding process and the first error code detection / correction process is recorded on the information code sequence 300 on the recording code sequence 302. And a configuration corresponding to a code sequence unit composed of natural number of code units (information symbols 327) of encoding / correction processing in the second error correction encoding processing and second error code detection / correction processing. Is preferable in linking both together for error correction coding. For example, when the error can be detected in the recording code sequence blocks 302a, 302b, 302c,... By the first error code detection and correction process but cannot be corrected, the recording code sequence blocks 302a, 302b, 302c,. In the second error code detection / correction process, the information symbol 327 or code on the information code sequence 300 and the information code sequence (1) 300a corresponding to... Thus, erasure code error correction for these information symbols 327 and the corresponding codes can be realized. This efficiently improves the error correction capability in the second error code detection and correction process. At this time, the fact that the code lengths of the recording code sequence blocks 302a, 302b, 302c,... Correspond to the continuous natural number of code units of the information symbols 327 on the information code sequence 300 is information that may contain errors. It is more preferable to indicate the symbol 327.
[0062]
Also, on the recording code sequence 302, the code unit (recording code sequence block 302) of the encoding / correction processing in the first error correction encoding processing and the first error code detection / correction processing is recorded in the recording code modulation processing or recording code. The code unit corresponding to a natural number multiple of the code processing unit of the code conversion process in the demodulating process can be configured to expand the spreading of the code error by the recording code demodulating process to the adjacent recording code sequence block 302. This is a more preferable configuration of the present invention.
[0063]
FIG. 7 shows an embodiment in which erasure error correction is performed in the second error code detection and correction process. In the first error detection / correction processing circuit (first error correction decoder circuit) 313, an error block flag 328 is set for the decoded code sequence blocks 311a, 311b, 311c,. publish. The error pointer generation circuit 329 receives this error block flag 328 and takes into account the code processing unit of the recording code demodulation processing in the demodulation processing circuit 315, and the decoded code sequence blocks 311a and 311b of the error indicated by the error block flag 328. 311c, the information symbol 327 or the code may include an error event in synchronization with the code or the information symbol 327 output from the demodulation processing circuit 315. An error symbol / error code erasure pointer 330 is issued to indicate that there is an error. The second error detection / correction processing circuit (second error correction decoder circuit) 318 performs erasure error correction on the information symbol 327 or code indicated by the error symbol / error code erasure pointer 330. This efficiently improves the error correction capability in the second error code detection and correction process.
[0064]
As described in the embodiments so far, in the information recording / reproducing method and recording / reproducing apparatus using the error correction coding provided by the present invention, the characteristic of the decoding error by the maximum likelihood sequence decoder 310 is used to specify a specific An error correction coding and error code detection / correction process specialized for a decoding error pattern sequence (code error syndrome) of a high frequency error event is provided to improve decoding reliability. This decoding error pattern sequence (code error syndrome) takes different forms depending on the transfer characteristics of the target recording / reproducing system channel 306 and the constraint condition added to the channel recording code sequence 305 by encoding / modulation processing or the like. It will be. As described in the principle of implementation of the present invention, many high-density magnetic recording / reproducing channels include the class 4 extended partial response (EPR4) channel of the binary transmission code sequence shown in FIG. Partial response characteristic polynomial Binary expressed by G (D) = (1-D) (1 + D) F (D) (D is a 1-bit delay operator, F (D) is an arbitrary characteristic polynomial) A code record partial response channel is often applied. When a binary information code is assigned to a binary signal level on a recording signal sequence and recording / reproduction is performed, such a partial response channel generally has a transmission frequency characteristic as shown in FIG. , To allow the null frequency characteristics in the DC frequency component and the maximum recording frequency (recording / reproducing code transmission required band, transmission Nyquist frequency, half of recording / reproducing code transmission frequency 1 / T) with respect to the recording signal frequency, For application to a high-density magnetic recording / reproducing system channel that requires band cut-off characteristics and narrow band transmission frequency characteristics, it has suitable transmission characteristics. In this type of partial response channel, the characteristic polynomial G (D) = (1-D) (1 + D)ⁿ The class 4 type channel form represented by (natural number n) is actively applied to a magnetic disk device or the like. When n = 1, PR4 channel, when n = 2, extended PR4 (EPR4) channel, In the case of n = 3, it is called an extended EPR4 channel, which is very well matched with a narrow-band limited high-density magnetic recording / reproducing system channel. In a recording / reproducing channel in which information is recorded at a high frequency or a high recording density, a class 4 type partial response channel channel characteristic in which the high frequency deterioration of the signal transmission frequency characteristic becomes extremely large is applied, and FIG. As shown in (2), by appropriately selecting the order n with respect to the operating conditions of the recording / reproducing system, it is possible to realize a recording / reproducing system channel with little influence of high frequency deterioration.
[0065]
Such a partial response channel adjusts the (high-frequency cutoff) filter circuit 308a and equalization processing circuit 308e of the reproduction signal processing system 306e on the recording / reproduction system channel 305 in the embodiment of FIG. Realized. In the recording / reproducing system channel 306 that realizes this kind of partial response channel characteristics, a recording signal sequence A331a (same level) having only a DC frequency component is derived from the null frequency characteristics on the transmission frequency characteristics shown in FIG. Recording corresponding to a non-inverted continuous code sequence of code values) and maximum recording frequency (transmission Nyquist frequency, 1/2 of recording / reproducing code transmission frequency 1 / T), that is, continuous signal level inversion at the recording / reproducing operating frequency of the channel When a signal sequence B331b (corresponding to a continuous inverted code sequence of binary level code values) is applied as a recording signal sequence 306f and recorded and reproduced, a reproduced signal sequence (decoded signal) at the output of the recording / reproducing system channel 306 corresponding thereto The sequence 311) has a feature that a zero value continuous signal sequence appears in any case.
[0066]
When the decoded signal sequence 311 output from such a recording / reproducing system channel 306 is decoded using the maximum likelihood sequence decoder 310, it is representatively shown as an example of the class 4 extended partial response (EPR4) channel described above. As described above, due to the common channel state transition structure, a high-frequency decoded error pattern sequence (square Euclidean distance) between reproduced signal sequences (decoded signal sequence 311) becomes small (square Euclidean distance). Code error syndrome) is concentrated on a sequence of continuously inverted code errors of a binary level code value having a code length of 1 bit or more. That is, according to the above-described notation of the decoding error pattern sequence (code error syndrome), an n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 having an n-bit (n is a natural number) continuous error code. Is “… 0 0+1 -1 +1 ... 0 0... ”(The underlined portion indicates the n-bit continuous inversion code position of +1 −1 +1...). FIG. 8B shows an n-bit continuous inversion code error pattern sequence (n-bit continuous Inverted code error syndrome) 332 shows an example of a code error event (when n = 4), which includes two channel recording code sequence A 332a and channel recording code sequence B 332b (a recording signal sequence when this is recorded). A code error event occurs between two channel recording signal patterns A333a and B333b applied as 306f (on the decoded code sequence 311 the channel recording signal pattern A333a is a channel recording signal pattern sequence). B332b or channel recording code sequence A332a is erroneously decoded as channel recording code sequence B332b.) The recording / reproducing system In the channel 306, the frequency of occurrence of each code error event with respect to the code length n of the continuous error varies depending on the influence of correlation characteristics and statistical properties such as noise that cause decoding errors, but a relatively short code length. Code error event of n n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332, for example, “... 0 up to about 3 bits in code length+1 0… ”,“… 0+1 -10… ”,“… 0+1 -1 +1The code error event corresponding to “0 ...” becomes dominant in the occurrence probability.
[0067]
Therefore, for the recording / reproducing system channel 306, an error event (n-bit continuous inversion code error pattern) of a continuous inversion code sequence having such a predetermined code length of n bits (n = 1, 2, 3 bits in the above example). The first error correction coding process / error code detection / correction process is performed in such a manner that the first error correction coding circuit (first error correction encoder) ) 304 and the first error code detection / correction processing circuit (first error correction decoder) 313, correction is performed from a decoding error event having a high probability of occurrence, and effective decoding reliability can be improved.
[0068]
As described above, in this embodiment, in the first error correction coding circuit (first error correction encoder) 304, an error check redundant code string (first error correction code) configured for the recording code sequence 302 is obtained. The code sequence 303 follows a decoding error event (n-bit continuous inversion code error pattern sequence 332) of a binary level code value continuous inversion code sequence having a predetermined code length of n bits (n = 1, 2, 3 bits in the above example). Binary code decoding error events) are set to a predetermined number i (i is a natural number, in many cases, a plurality of code lengths n) in each recording code sequence block 302a, 302b, 302c. 1) It is configured to correct up to the following. The first error code detection / correction processing circuit (first error correction decoder) 313 uses the error check redundant code sequence (first error correction code sequence) 303 for the decoded code sequence 311. , A decoding error event of a binary level code value continuous inversion code sequence having a predetermined code length of n bits (n = 1, 2, 3 bits in the above example) or less (binary in accordance with an n-bit continuous inversion code error pattern sequence 332) (Code decoding error event) is equal to or less than the predetermined number i in the respective recording code sequence blocks 302a, 302b, 302c... Processing to detect and correct up to. Further, the code length of each recording code sequence block 302a, 302b, 302c... Is set to a code length that can improve the desired decoding reliability from the decoding reliability of the actual maximum likelihood sequence decoder 310. For example, from the decoding error probability of the maximum likelihood sequence decoder 310, the average number of occurrences of the decoding error event is determined by the respective recording code sequence blocks 302a, 302b, 302c... (Decoded code sequence blocks 311a, 311b, 311c. ), The code lengths of the recording code sequence blocks 302a, 302b, 302c... (Decoded code sequence blocks 311a, 311b, 311c. Thus, the decoding reliability can be improved. Further, when correcting the decoding error event of the binary level code value continuous inversion code sequence over a plurality of recording code sequence blocks 302a, 302b, 302c (decoded code sequence blocks 311a, 311b, 311c,...), It is necessary to set a predetermined code error pattern sequence (code error syndrome) set in one error correction coding including a partial sequence of the code error pattern sequence (code error syndrome). In the present embodiment, a partial sequence of a continuously inverted code error pattern sequence (continuous code error syndrome) having a predetermined code length n = 1, 2, and 3 bits set in advance is also included in this.
[0069]
In this embodiment, the decoded code sequence 311 output from the maximum likelihood sequence decoder 310, such as the channel recording code sequence A332a and the channel recording code sequence B332b shown in FIG. Is represented by a code form (binary level code or NRZ record code representation) in which a binary code is assigned to each of the two recording signal levels of the signal, and based on this code form, n bits as a high-frequency code error pattern A continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 is defined. In this n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332, when the code representation form of the decoded code sequence 311 is different (for example, whether or not level inversion on the recording signal sequence 306f is a binary code) If the decoded code sequence 311 is subjected to some precoder processing as described above, it may be expressed as a different code pattern on the decoded code sequence 311. The code error pattern sequence (code error syndrome) expression in the case of (2) is also converted to 2 on the recording signal sequence 306f as shown in FIG. By converting the value level code value into a sequence error event representation, the n-bit continuous inversion code error pattern sequence (n It is possible to check that Tsu preparative continuous inversion code error syndromes) 332 and those equivalent. In the first error correction coding process and the first error code detection / correction process described in the present invention, the set code error pattern sequence (code error syndrome) is a code representation for such a decoded code sequence 311. This includes all cases of equivalent conversion through code processing, and the first error correction coding processing and the first error code detection / correction processing are expressed by a binary level code value sequence on the recording signal sequence 306f. This includes all error correction coding and detection correction processing for an error event equivalent to the above-described code error.
[0070]
Next, an embodiment using recording code modulation processing and recording code demodulation processing will be described. As is apparent from FIG. 8B, the code error event of the n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 is a continuous signal of the recording / reproducing code period T on the recording signal sequence 306f. It can occur only in the sequence portion where level inversion occurs more than (n-1) times. For example, if the continuous signal level inversion of the recording signal series 306f is limited to a maximum of 2 times, an n-bit continuous inversion code with a code length n of n = 4 bits or longer as shown in FIG. 8B. An error event of the error pattern series 332 cannot occur. From this, recording code modulation processing in the encoding / modulation processing circuit 301 performs recording so that the maximum number of continuous signal level inversions is limited to a predetermined number k (k is a natural number) on the recording signal sequence 306f. By adding a code constraint condition to the signal sequence 302, the maximum code sequence length n of the code error event of the frequently occurring n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 is expressed as (k + 1) Can be limited to: In this case, in the first error correction encoding circuit (first error correction encoder) 304, an error check redundant code sequence (first error correction code sequence) 303 configured for the recording code sequence 302 is: From the limited code length of (k + 1) bits or less, all or a part thereof is selected as a predetermined code length n bits depending on the occurrence frequency, and a binary level code of this predetermined code length n bits is selected. Decoding error events of the value continuous inversion code sequence (binary code decoding error events in accordance with the n-bit continuous inversion code error pattern sequence 332) are stored in each recording code sequence block 302a, 302b, 302c. Is a natural number, often configured to correct one of each error event to 1) or less. The first error code detection / correction processing circuit (first error correction decoder) 313 uses the error check redundant code sequence (first error correction code sequence) 303 for the decoded code sequence 311. , Decoding error event of binary level code value continuous inversion code sequence having a predetermined code length of n bits (3 bit code length in the above example) or less (binary code decoding error event according to n bit continuous inversion code error pattern sequence 332) ) Is detected and corrected up to the predetermined number i (one of each error event as described above) or less in each recording code sequence block 302a, 302b, 302c. When the maximum number k of continuous signal level inversions of the recording signal sequence 306f is limited to 2, the high-frequency n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 is at most 3 bits long. Since it is limited to the following, the first error correction coding / error detection / correction for all or part of this may be performed. Such an embodiment is effective in simplifying encoding and correction processing.
[0071]
As is clear from FIG. 8B, decoding from the channel recording code sequence A332a to the channel recording code sequence B332b under the code constraint condition in which the maximum number k of continuous recording signal level inversions is limited to 3. If an error occurs, the recording signal pattern B333b is clearly contrary to this, so that this decoding error can be avoided. If this code constraint condition is taken into consideration for the decoded code sequence 311, the maximum code sequence length n of the generated continuously inverted code error pattern sequence can be limited to k = 3 or less. In the maximum likelihood sequence estimation process in the maximum likelihood sequence decoder 310, a code constraint on the maximum number k of continuous recording signal level inversions added by the recording code modulation is taken into consideration, and a decoding code sequence 311 that is inappropriate for this is determined as the maximum likelihood. It can be easily excluded from the candidates for sequence estimation and output. At this time, the maximum code sequence length n of the frequently occurring n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 can be limited to k or less. Error events that can be subject to error detection and correction can be further limited.
[0072]
As another embodiment using the recording code modulation processing / recording code demodulation processing, there is a method in which the code constraint condition for the recording code sequence 302 is given time-variably or periodically. This is a method of providing a constraint condition only for a pattern of the recording code sequence 302 starting from a specific code time on the recording code sequence 302 or loosening the constraint condition. For example, a 4-bit continuous inversion code error When the pattern sequence is to be excluded by the recording code modulation process and the first error detection / correction process, only the maximum number k of continuous recording signal level inversions starting from a code time having a specific period on the recording code series 302 is set to 4. The maximum number k of continuous recording signal level reversals starting from other code times is limited to 3. As described above, when the decoding code sequence that does not satisfy the constraint condition is excluded from the candidates by the maximum likelihood sequence decoder 310, the above-described periodic recording code modulation processing also increases the decoding code sequence 311. The code error generation of the 4-bit length continuous inversion code error pattern sequence is allowed only at the limited four consecutive code points corresponding to the corresponding code time of the period of the above, and at the four consecutive code points corresponding to other code times, Its occurrence is limited. Therefore, the first error correction for correcting the error of the 4-bit length continuous inversion code error pattern sequence only for the periodically limited code portion where the 4-bit length continuous inversion code error pattern sequence can occur. Encoding / error code correction processing is performed. In this way, it is possible to ease the burden of adding code redundancy in the recording code modulation process by loosening the constraint conditions in a time-varying and periodic manner, and this can be compensated by the first error correction coding / error code correction process. Thus, the overall decoding reliability of the recording / reproducing system is increased.
[0073]
Further, as apparent from FIG. 8B, the decoding error event of the binary level code value continuous inversion code sequence as described above (the binary code decoding error event according to the n-bit continuous inversion code error pattern sequence 332) is Since it is apparent that the recording code sequence 302 and the decoded code sequence 311 occur only at the code portion where the continuous recording signal level inversion occurs, the recording code sequence 302 and the decoded code sequence 311 are referred to and the code sequence concerned The code location corresponding to the pattern can be limited as a position where a decoding error event of the continuous inversion code sequence can occur. FIG. 9A shows a configuration for implementing this, and in the recording process, referring to the recording code sequence 302, the location of a specific code sequence pattern in which a predetermined code error syndrome can occur is shown. A code sequence pattern matching circuit 334 for collation, a code sequence pattern pointer 335 indicating the code position of the collated code sequence pattern, and information on the code sequence pattern pointer 335 are received, and a first error for the code error syndrome is received. An encoding pointer 337 that indicates a target code position of correction encoding and an encoding pointer generation circuit 336 that generates the encoding pointer 337 are provided. In the first error correction encoding circuit (first error correction encoder circuit) 304, the first error corresponding to the code error syndrome is targeted for the code position indicated by the encoding pointer 337 on the recording code sequence 302. Apply correction coding. Similarly, in the reproduction process, with reference to the decoded code sequence 311, a code sequence pattern verification circuit 334 for verifying a specific code sequence pattern where a predetermined code error syndrome can occur, the verified code sequence The code sequence pattern pointer 335 that indicates the code position of the pattern, the information of the code sequence pattern pointer 335, and the correction pointer 339 that indicates the target code position of the first error code detection and correction process for the code error syndrome. A correction pointer generation circuit 338 is provided. In the first error code detection / correction circuit (first error correction decoder circuit) 313, the first error code corresponding to the code error syndrome is targeted for the code position indicated by the correction pointer 339 on the decoded code sequence 311. Perform detection and correction processing. The above embodiment of the present invention may implement only the recording process means for the first error correction coding, or only the reproducing process means for the first error code detection and correction process. These provide simplification of the configuration or improvement of error correction accuracy in the first error correction coding or the first error code detection and correction process.
[0074]
Further, in the recording / reproducing system channel 306 having the signal transfer characteristic characteristic having the characteristics described in FIG. 8A, that is, the recording / reproducing system channel generally represented by the above-described transfer polynomial G (D). As shown in FIG. 8C, the response signal waveform at the output of the reproduction signal processing system 306e for the single isolated signal level inversion 340 of the recording signal series 306f is intentionally given phase distortion before and after the time. It is more preferable to incline so that the asymmetric shape response signal 341 is obtained. Usually used characteristic polynomial G (D) = (1-D) (1 + D)ⁿ All of the class 4 type partial response channels represented by (natural number n) take a symmetric response signal shape. By making this an asymmetric response signal shape, the above-described high occurrence frequency of n-bit continuous The code length of the inverted code error pattern sequence (n-bit continuous inverted code error syndrome) 332 can be made probabilistic and relatively short. This is because the combination of code sequences in which the Euclidean distance between the reproduced signal sequences becomes small is stochastically reduced due to asymmetry, and this fact is an error of the first error correction coding in the implementation of the present invention. It is more preferable for improving the correction effect and simplifying the implementation. Further, such an asymmetric response signal waveform is realized on the recording / reproducing system channel 305 by adjusting mainly the (high-frequency cutoff) filter circuit 308a and the equalization processing circuit 308e of the reproducing signal processing system 306e. 8A, the response signal waveform at the output of the reproduction signal processing system 306e with respect to the inversion of the isolated recording signal level is brought close to the minimum phase transition waveform characteristic of the response signal waveform in the reproduction signal series 306g. As shown by the shape response signal channel characteristics 342, this is achieved while achieving better matching with the transmission frequency characteristics of the target recording / reproducing system channel 306 as compared to the class 4 type partial response channel described above. Is possible. In a high-density magnetic recording / reproducing apparatus, G (D) = (1-D) (1 + D) (5 + 4D + 2) is the fourth-order transfer polynomial of the partial response channel suitable for realizing this. Yes, this has the same number of channel memories as the extended EPR4 channel and is decoded by the maximum likelihood sequence decoder 310 of the same scale.
[0075]
Further, in the recording / reproducing apparatus and the recording / reproducing system, the decoding error characteristic in the maximum likelihood sequence decoder 310 is different for each recording / reproducing system or apparatus due to a difference in the recording / reproducing apparatus / conditions and use environment conditions and various disturbance factors. It often changes over time. In an actual recording / reproducing apparatus or system, a unique decoding error event that is difficult to expect can often occur due to a nonlinear physical phenomenon. In such a recording / reproducing apparatus or recording / reproducing system in which the decoding error characteristic may vary, a predetermined decoding code error pattern (code error syndrome) set in the first error correction coding / error code detection / correction processing is previously stored. It is not preferable to use a fixed one. A plurality of predetermined decoding code error patterns (code error syndromes) to be set are facilitated, statistical information of decoding error characteristics in an actual recording / reproducing apparatus or recording / reproducing system is collected, and this is appropriately selected. It is desirable to use it.
[0076]
FIG. 9B shows an embodiment in this case, a fifth basic embodiment of the present invention. In the present embodiment, a code error syndrome detection circuit 343 for detecting a code error and a decoded code error pattern (code error syndrome) on the decoded code sequence 311 output from the actual maximum likelihood sequence decoder 310 is provided. The decoded code error syndrome detection circuit 343 collates a known channel recording code sequence 305 with a decoded code sequence 311 output by recording / reproducing the recording code sequence 30 by the target recording / reproducing system channel 306, A decoding error is detected, and a decoding code error pattern (code error syndrome) is determined. The method of distinguishing the event of each decoded code error pattern (code error syndrome) is as described above, and the determined code error syndrome pattern is instructed to be output by the syndrome output signal 344. The code error syndrome totaling circuit 345 counts the frequency of occurrence of the code error syndrome instructed by the syndrome output signal 344, and the first error code corresponding to the code error syndrome having the high occurrence frequency is selected via the selection signal 346 and the selection circuit 347. An error correction coding circuit (first error correction encoder circuit) 304 and a first error detection / correction processing circuit (first error correction decoder circuit) 313 are selected from a plurality, and this is used as actual information. Used in recording / playback processing. The change of the code error syndrome in such encoding / correction processing is to select a circuit means corresponding to the code error syndrome processing candidates set in advance as shown in FIG. 9B. The first error correction encoding circuit (first error correction encoder circuit) 304 and the first error corresponding to the code error syndrome processing selected by the code error syndrome totaling circuit 345 may be used. The encoding / correction processing configuration in the detection / correction processing circuit (first error correction decoder circuit) 313 may be changed logically or programmable. By providing the means as described above, the known channel recording code sequence 302 is used as a test code sequence at the time of production of the recording / reproducing apparatus or recording / reproducing system, or before the start of the information recording / reproducing operation or during an idle period. If the optimization operation as described above is performed, the first error correction coding / error code detection / correction processing can be more effectively performed in the actual recording / reproducing apparatus.
[0077]
As described above, any of the embodiments of the present invention can be easily configured using the existing digital circuit technology, and is mounted on a single integrated circuit or divided into a plurality of integrated circuit groups. In addition, a high-speed, small, and low-power information recording / reproducing circuit can be provided. An information recording / reproducing circuit realized in such a form mounted on an integrated circuit can be easily mounted on a small portable recording / reproducing apparatus that requires higher density recording, and can improve reliability of data demodulation. Can provide. In the embodiments of the present invention, the information recording / reproducing method and the recording / reproducing circuit / device are all integrated with a recording process (recording circuit, recording device), a reproducing process (reproducing circuit, reproducing device), and a recording medium. This is not a configuration requirement for implementing the present invention. Each of them may be configured independently, and it is only necessary that the functions can be integrated as described in this embodiment. Each configuration of a recording process (recording circuit, recording device), a reproducing process (reproducing circuit, a reproducing device) and a recording medium in which the present invention is implemented includes a first error correction encoding process (encoding circuit, code) 1), first error code detection / correction processing (correction circuit, correction means), first error correction code sequence, and the like are separately included. The implementation of the invention is clear, and the functions of the present invention realized when the respective configurations are integrated are also clear. In particular, when the present invention is mounted on a semiconductor integrated circuit, there are various modes of implementation in which the configuration requirements of the present invention are separately mounted in a plurality of integrated circuit groups for convenience of integration with other realization functions. Can be taken. The scope of the present invention includes the described features of the present invention, and includes a separately configured recording process (recording circuit, recording device), reproducing process (reproducing circuit, reproducing device), recording medium, or other All forms of separation configuration are included.
[0078]
【The invention's effect】
The decoding reliability of the decoding process by maximum likelihood sequence detection can be improved by using simple circuit resources and error correction codes with low redundancy.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first basic embodiment of the present invention.
FIG. 2 is a diagram for explaining the flow of a code sequence in the first basic embodiment.
FIG. 3 is a diagram showing a second basic embodiment of the present invention.
FIG. 4 is a diagram showing a third basic embodiment of the present invention.
FIG. 5 is a diagram for explaining the flow of a code sequence in the third basic embodiment.
FIG. 6A is a diagram for explaining a recording code form of a recording frame in the present invention.
FIG. 6B is a diagram showing an example for explaining a recording code form of an information code frame in the present invention by n interleaving processing;
FIG. 6c is a diagram showing another example for explaining a recording code form of an information code frame in the present invention by n interleaving processing.
FIG. 7 is a diagram showing a basic embodiment of the present invention using erasure error correction processing.
FIG. 8a is a diagram showing channel response frequency characteristics of a partial response recording / reproducing system.
FIG. 8b is a diagram showing an n-bit consecutive inversion code error event in a binary partial response recording / reproducing channel.
FIG. 8c is a diagram showing a waveform shape of a reproduction response signal with respect to inversion of an isolated recording signal level.
FIG. 9a shows a fourth basic embodiment of the invention.
FIG. 9b shows a fifth basic embodiment of the present invention.
FIG. 10a is a diagram showing a flow of an information sequence in an information transmission system or a recording / reproduction system.
FIG. 10b shows an EPR4 partial response runway channel model.
FIG. 10c is a state transition diagram (binary code transmission sequence EPR4 transmission channel).
FIG. 10d is a diagram showing a trellis transition at time k (binary code transmission sequence EPR4 transmission channel).
FIG. 10e is a diagram (binary code transmission sequence EPR4 transmission path channel) showing path transition to each state at time k.
FIG. 10f is a diagram showing a state transition path example at time k to k + 4 (binary code transmission sequence EPR4 transmission path channel);
FIG. 11a is a diagram for explaining specific components for performing a Viterbi decoding process;
FIG. 11B is a diagram showing a configuration of a maximum likelihood decoder (maximum likelihood sequence decoder, Viterbi decoder) based on the Viterbi algorithm.
FIG. 12 is a trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the maximum likelihood decoding process by surviving path sequence selection.
FIG. 13a is a first trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining a relationship between a normal path sequence and an error path sequence in a maximum likelihood decoding process;
FIG. 13b is a second trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the relationship between the normal path sequence and the error path sequence in the maximum likelihood decoding process;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Transmission code sequence, 101 ... Information transmission system, 102 ... Encoder, 103 ... Modulator, 104 ... Channel, 105 ... Additional noise, 106 ... Reception signal processing circuit, 107 ... Reception (decoding input) signal sequence, 108 ... Maximum likelihood sequence decoder, 109 ... decoding code sequence, 110a, 110b, 110c ... 1-bit delay storage element, 111a, 111b, 111c ... addition / subtraction operation element, 112 ... path sequence, 112a, 112b ... state transition path (path branch) 113 ... Surviving path sequence, 114 ... Deterministic maximum likelihood sequence, 115 ... Regular path sequence, 116 ... Error path sequence, 117 ... Error path selection, 119 ... Decoding error pattern sequence, 121a ... 1-bit decoding error pattern, 121b ... 3-bit code error pattern, 122... Error path selection detection position, 200a. , 200b... ACS calculation unit, 200c... Path memory unit, 201... Square error calculation circuit, 202a to 202h .. metric storage circuit, 203 .. metric accumulating addition circuit, 204 ... comparator, 205 ... selection signal, 206 ... metric selection Circuit, 207a to 207h ... Path history storage circuit, 208, 208a to 208h ... Path history selection circuit, 300 ... Information code sequence, 300a ... Information code sequence (1), 301 ... Encoding / modulation processing circuit, 302 Recording code sequence 302a, 302b, 302c ... recording code sequence block, 303 ... error check redundant code sequence (first error correction code sequence), 303a, 303b, 303c ... error check redundant code sequence (first error correction code sequence), 304: first error correction encoding circuit (first error correction encoder circuit), 304a: error correction code Generation circuit 304b Error correction code string insertion circuit 305 Channel recording code sequence 306 Recording / reproduction system channel 306a Recording signal processing system 306b Recording head 306c Recording medium 306d Reproduction head 306e Reproduction signal Processing system, 306f ... recording signal sequence, 306g ... reproduction signal sequence, 307a ... code processing circuit, 307b ... code signal conversion circuit, 307c ... recording signal processing circuit, 307d ... recording signal amplifier, 308a reproduction signal amplifier, 308b ... variable gain Amplifying circuit, 308c (high frequency cutoff) filter circuit,
308d: sampling circuit (analog / digital converter), 308e: equalization processing circuit,
308f: Timing reproduction / gain control circuit, 308g: Gain control signal, 308h ... Sample timing control signal, 309 ... Decoded signal sequence, 310 ... Maximum likelihood sequence decoder, 311 ... Decoded code sequence, 311a, 311b, 311c ... Decoded code Sequence block, 312, 312 a, 312 b, 312 c... Decoding error check redundant code sequence (first error correction code sequence),
313: First error detection / correction processing circuit (first error correction decoder circuit), 313a: Code error check correction circuit, 313b: Error check redundant code sequence removal circuit, 314: Correction decoding code sequence, 315: Demodulation processing Circuit, 316, reproduction code sequence, 316a, reproduction code sequence (1),
317 ... second error correction coding circuit (second error correction encoder circuit), 318 ... second error detection and correction processing circuit (second error correction decoder circuit), 319, 319a, 319b, 319c ... Information code frame, 320, 320a, 320b, 320c ... Error check redundant code sequence (second error correction code sequence), 328a ... Error check redundant code sequence A (second error correction code sequence), 328b ... Error check redundancy Code sequence B (second error correction code sequence), 328c... Error check redundant code sequence C (second error correction code sequence), 328d ... Error check redundant code sequence D (second error correction code sequence), 321 , 321a, 321b, 321c ... recording code frames 322, 322a, 322b, 322c ... error check redundant code conversion sequence (second error correction code sequence), 328a ... error check redundant code Conversion sequence A (second error correction code sequence), 328b... Error check redundant code conversion sequence B (second error correction code sequence), 328c... Error check redundant code conversion sequence C (second error correction code sequence) 328d: Error check redundant code conversion sequence D (second error correction code sequence), 323, 323a, 323b, 323c ... decoded code frame, 324, 324a, 324b, 324c ... decoded error check redundant code conversion sequence (second Error correction code sequence), 325, 325a, 325b, 325c ... reproduced code frame, 326, 326a, 326b, 326c ... decoded error check redundant code sequence (second error correction code sequence), 327 ... information symbol, 328 ... Error block flag, 329, error pointer generation circuit, 330, error symbol / error code erasure pointer, 331a, recording signal sequence A, 3 1b: Recording signal sequence B, 332: n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome), 332a: Channel recording code sequence A, 332b: Channel recording code sequence B, 333a: Recording signal pattern A, 333b: Recording signal pattern B, 334: Code sequence pattern matching circuit, 335: Code sequence pattern pointer, 336 ... Encoding pointer generation circuit, 337 ... Encoding pointer, 338 ... Correction pointer generation circuit, 339 ... Correction pointer, 340 ... Isolated signal level inversion, 341 ... asymmetric shape response signal, 342 ... asymmetric shape response signal channel characteristics, 343 ... code error syndrome detection circuit, 344 ... syndrome output signal, 345 ... code error syndrome aggregation circuit, 346 ... selection signal, 347 ... Select circuit, 348a ... multi Lexus circuit (code sequence selection circuits), 348b ... demultiplexer circuit (code sequence selection circuit), 349 ... recording frame (information code unit), 349a ... preamble, 349b ... postamble.

Claims (19)

A circuit means (recording processing circuit) for converting and outputting an input information code sequence to a recording signal sequence or a control signal sequence for generating the recording signal sequence, and an input reproduction signal sequence to a maximum likelihood sequence estimation circuit ( An information recording / reproducing circuit having circuit means (reproduction processing circuit) for decoding and reproducing the information code sequence using a maximum likelihood sequence detecting circuit, a maximum likelihood decoding circuit, and a Viterbi decoding circuit,
(1) The information code sequence before being converted and output from the recording processing circuit includes the information code sequence (recording code sequence block) having a predetermined code length that is continuously decoded by the maximum likelihood sequence estimation circuit. as a unit, have the first error correction coding is facilities said first error correction encoder circuit for composing the first error correcting code sequence corresponding to the recording code sequence block of each is provided In addition, the first error correction coding by the first error correction encoder circuit and the configuration of the first error correction code sequence are such that the Euclidean distance on the state transition diagram in the maximum likelihood sequence estimation circuit is below a certain value. after having preset code error pattern based on the reference, the outermost likelihood sequence estimation circuit the relevant decoded by the recording code sequence blocks and the error correction codes in sequence, a predetermined bit error the preset Specific code error events with a turn (code error syndromes), which is performed to enable detection and correction to a predetermined number (first code error detection and correction process),
(2) a first error correction code sequence, the recording signal based sequence or includes a circuit means for converting the output to the control signal sequence for generating the recording signal sequence, or the first error correcting code sequence , A first code to be divided or collectively inserted / added to a predetermined code position immediately before / after the recording code sequence block on the information code sequence before being converted and output from the recording processing circuit The code sequence output from the code sequence processing circuit is supplied to the recording processing circuit and converted into a recording signal sequence or a control signal sequence for generating the recording signal sequence. ,
(3) In the information code sequence decoded and output from the maximum likelihood sequence estimation circuit, the first error correction coding, or the first error correction coding decoded together with the recording code sequence block as a processing unit. A first error correction decoder circuit for performing a first code error detection and correction process using an error correction code sequence is provided, and the first error correction decoder circuit is provided immediately after the maximum likelihood sequence estimation circuit. And the information code sequence decoded and output from the maximum likelihood sequence estimation circuit is supplied to the first error correction decoder circuit without logically changing the code order on the information code sequence, Alternatively, the information code sequence to be decoded output from the outermost likelihood sequence estimation circuit is directly the information recording and reproducing circuit according to claim Rukoto is inputted to the first error correction decoder circuit.   The information code sequence before being converted and output from the recording processing circuit is subjected to a predetermined recording code modulation process before the construction of the first error correction coding sequence and the first error correction code sequence in (1) above. A code modulation processing circuit for performing a first code sequence conversion process is provided in front of the first error correction encoder circuit, and the information code sequence decoded and output from the maximum likelihood sequence estimation circuit Code demodulation for performing a second code sequence conversion process by a predetermined recording code demodulation process corresponding to the recording code modulation process after the first error code detection correction process in (3) is performed. 2. The information recording / reproducing circuit according to claim 1, wherein the processing circuit is provided after the first error correction decoder circuit. The information recording / reproducing circuit according to claim 1 or 2 ,
(4) The information code sequence before being converted and output from the recording processing circuit includes the information recording / reproduction before the construction of the first error correction coding and the first error correction code sequence in (1) above. In the recording / reproduction processing operation of the apparatus, a continuous processing unit (recording frame) of the information code sequence, or a code sequence unit corresponding to a plurality of recording code sequence blocks is used as a second code error detection / correction processing unit The second error correction encoder circuit that performs the second error correction coding as a frame) or constitutes the second error correction code sequence corresponding to each information code frame is used as the first error correction. Provided in front of the encoder circuit,
(5) comprising a circuit means for converting and outputting the second error correction code sequence to a recording signal sequence or a control signal sequence for generating the recording signal sequence; Before the configuration of the first error correction coding and the first error correction code sequence in (1) above, the information code sequence before being converted and output from the recording processing circuit is immediately before the information code frame. A second code sequence processing circuit that is inserted immediately after or at a predetermined code position or inserted / added at once is provided. The code sequence output from the code sequence processing circuit is the first code sequence processing circuit. Is supplied to the recording processing circuit, converted into a recording signal sequence or a control signal sequence for generating the recording signal sequence,
(6) The information code sequence decoded and output from the maximum likelihood sequence estimation circuit is subjected to the first code error detection and correction process in (3) above, and then the information code frame as a processing unit. A second error correction decoder circuit for performing a second code error detection and correction process using the second error correction code sequence to be decoded together or the second error correction code sequence to be decoded together. An information recording / reproducing circuit, which is provided after the device circuit. The information code sequence before being converted and output from the recording processing circuit includes the second error correction coding and the second error correction code sequence in (4) above, or the information code sequence in (5) above. After the insertion / addition of the second error correction code sequence, a code modulation processing circuit for performing the first code sequence conversion processing is provided after the second error correction encoder circuit or the second code sequence processing circuit. The information code sequence decoded and output from the maximum likelihood sequence estimation circuit is subjected to the second code sequence before the second error code detection and correction process in (6) is performed. 4. The information recording / reproducing circuit according to claim 3 , wherein a code demodulation processing circuit for performing conversion processing is provided in front of the second error correction decoder circuit.   The recording code sequence block is obtained by dividing the recording frame, and the first error correction code sequence is converted into the information code sequence before being converted and output from the recording processing circuit. A first code sequence processing circuit that divides or collectively inserts / adds to a predetermined code position corresponding to a recording code sequence block, or a corresponding code position immediately before, immediately after, or inside the recording code sequence block. The information recording / reproducing circuit according to claim 1, further comprising: The recording code sequence block is obtained by dividing the recording frame, and the first error correction code sequence is converted into the information code sequence before being converted and output from the recording processing circuit. A first code sequence processing circuit that divides or collectively inserts / adds to a predetermined code position corresponding to a recording code sequence block, or a corresponding code position immediately before, immediately after, or inside the recording code sequence block. And the second error correction code sequence on the information code sequence before being converted and output from the recording processing circuit, a predetermined code position corresponding to the recording frame, or immediately before the recording frame. - immediately after or inside the corresponding code position, split or collectively second code sequence processing information recording reproducing times according to claim 3, characterized in that it comprises a circuit for insertion, addition . The information code frame is regarded as an information symbol sequence having a continuous code sequence (information symbol) of a predetermined code length as a unit, and the configuration of the second error correction coding and the second error correction code sequence in (4) above Before and before the second code error detection and correction process in (6) above, the information code frame is divided into n independent information symbol sequences (n is a natural number) using the information symbol as a division processing unit. An interleave processing circuit is provided in front of the second error correction encoder circuit and the second error correction decoder circuit, and in the above (4), the n independent information symbol sequences On the other hand, a second error correction encoder circuit that performs the second error correction encoding or constitutes the second error correction code sequence is provided independently, and in the above (6), n The book To stand information symbol sequence, independently, claim 3, wherein the second error correction decoder circuit for performing a second code error detection and correction processing of the information symbols and the error detection and correction processing unit is provided The information recording / reproducing circuit described in 1. 8. The information recording / reproducing circuit according to claim 7 , wherein the recording code sequence block is composed of a natural number of the information symbols continuously converted and output from the recording processing circuit. The said recording code sequence block is comprised from the natural number of the code sequence used as the minimum process unit in a 1st code sequence conversion process or a 1st code sequence conversion process, The Claim 2 or 3 characterized by the above-mentioned. Information recording / reproducing circuit. In the first code error detection and correction process of (3) above, error correction flag information is sent to a code or information symbol belonging to a recording code sequence block in which a code error is detected and it is determined that the code error correction is impossible In the second code error detection and correction process of (6) above, the flag generation circuit performs a erasure code error correction process on the code or information symbol indicated by the error correction flag output from the flag generation circuit. The information recording / reproducing circuit according to claim 3 , further comprising a second error correction decoding circuit. The code modulation processing circuit performs a first code sequence conversion process by a predetermined recording code modulation process on the information code sequence before being converted and output from the recording processing circuit. Only in the information code position, a code constraint condition is added by allowing the appearance of a predetermined information code sequence pattern corresponding to the predetermined code error pattern (code error syndrome) that has been set, and (1) The first error correction encoder circuit in FIG. 5 is configured to perform predetermined processing on an information code at a predetermined information code position in the recording code sequence block on the information code sequence before being converted and output from the recording processing circuit. The first error correction coding is performed so that a specific code error event having the code error pattern (code error syndrome) can be detected and corrected, or the first error correction code sequence is configured. And the first error correction decoder circuit in (3) uses the first error correction coding or the first error correction code sequence to The predetermined code error pattern (code error syndrome) is applied only to the decoded code corresponding to the predetermined information code position in the recording code sequence block on the information code sequence decoded and output from the likelihood sequence estimation circuit. information recording and reproducing circuit according to claim 2 or 3, characterized in that the straining facilities the first code error detection and correction processing for detecting and correcting a specific code error event with. A recording processing circuit for converting and outputting a recording signal sequence having a binary signal level or a control signal for generating the recording signal sequence, and recording a binary information code sequence through the recording processing circuit and the reproduction processing circuit; A circuit to reproduce,
(7) When recording / reproducing a binary information code sequence (non-inverted continuous code sequence of the same level code value) with the recording signal sequence having only a DC frequency component, and continuous signal level inversion at the recording / reproducing operating frequency When a binary information code sequence (continuous inversion code sequence of binary level code values) is recorded and reproduced by the recorded signal sequence, the reproduced signal sequence input to the maximum likelihood sequence estimation circuit in each case is zero. Comprising the recording processing circuit and the reproduction processing circuit having a signal transfer characteristic to be a continuous signal sequence,
(8) With respect to the binary information code sequence before being converted and output from the recording processing circuit, the first error correction encoder circuit in (1) is decoded and output from the maximum likelihood sequence estimation circuit. Up to a predetermined number of code error events corresponding to consecutive code errors of a binary level code value continuously inverted code sequence having a predetermined continuous code length in the recording code sequence block on the binary information code sequence. The first error correction coding is performed so that the first code error detection and correction process can be performed, or the first error correction code sequence is configured, or decoded from the maximum likelihood sequence estimation circuit For the output binary information code sequence, the first error correction decoder circuit in (3) described above corresponds to a code corresponding to a continuous code error of a binary level code value continuous inverted code sequence having a predetermined continuous code length. Error events Information recording and reproducing circuit according to claim 1, characterized in that performing a first code error detection and correction processing for detecting and correcting until the number of the constant. A recording processing circuit for converting and outputting a recording signal sequence having a binary signal level or a control signal for generating the recording signal sequence, and recording a binary information code sequence through the recording processing circuit and the reproduction processing circuit; A circuit to reproduce,
(9) When recording / reproducing a binary information code sequence (non-inverted continuous code sequence of the same level code value) with the recording signal sequence having only a DC frequency component, and continuous signal level inversion at the recording / reproducing operating frequency When a binary information code sequence (binary level code value continuous inversion code sequence) is recorded and reproduced by the recorded signal sequence, the reproduced signal sequence input to the maximum likelihood sequence estimation circuit in each case is zero. Comprising the recording processing circuit and the reproduction processing circuit having a signal transfer characteristic to be a continuous signal sequence,
(10) The code modulation processing circuit performs a first code sequence conversion process by a predetermined recording code modulation process on the binary information code sequence before being converted and output from the recording processing circuit, and A code constraint condition is added so as to limit the maximum number of continuous signal level inversions on a recording signal sequence to a predetermined number k (k is a natural number),
(11) The first error correction encoder circuit in the above (1) for the binary information code sequence before being converted and output from the recording processing circuit is decoded and output from the maximum likelihood sequence estimation circuit. A code error event corresponding to a continuous code error of a binary level code value continuous inversion code sequence having a predetermined continuous code length of (k + 1) or less in the recording code sequence block in the base information code sequence is determined in advance. The first error correction coding is performed so that the first code error detection and correction processing for detecting and correcting the number of the first error correction is possible, or the first error correction code sequence is configured, or the For the binary information code sequence decoded and output from the likelihood sequence estimation circuit, the first error correction decoder circuit in (3) described above is a binary level code having a predetermined continuous code length of (k + 1) or less. Consecutive code error of value continuous inversion code sequence Information recording and reproducing circuit according to claim 2 or 3 the corresponding code error events, and characterized in that applying a first code error detection and correction processing for detecting and correcting up to a predetermined number of the. The configurations of the first error correction coding and the first error correction code sequence in the above (7) to (9) include the binary information code sequence before being converted and output from the recording processing circuit. A circuit that references an information code in a recording code sequence block, and information in the recording code sequence block that matches the binary level code value continuous inversion code sequence having a predetermined continuous code length using the referenced information code A code verification circuit for checking the code position of the code, and the first error correction encoder circuit is instructed by the code position information from the code verification circuit in the recording code sequence block The first error correction coding is performed only on the information code, or the first error correction code sequence is formed, or the first code error detection in the above (7) to (9) For the correction process, On the binary information code sequence decoded and output from the maximum likelihood sequence estimation circuit, a circuit for referring to the decoded code in the recording code sequence block and a predetermined continuous code length using the referenced decoded code A code verification circuit that checks the code position of the decoded code in the recording code sequence block that matches the binary level code value continuous inversion code sequence, and the first error correction decoder circuit includes: the recording code sequence block, the decoded code only indicated by the information of said code positions from said code collation circuit, according to claim 12 or, characterized in that performing a first code error detection and correction process 14. An information recording / reproducing circuit according to item 13 . The code modulation processing circuit performs a first code sequence conversion process by a predetermined recording code modulation process on the binary information code sequence before being converted and output from the recording processing circuit, and the binary information code sequence In addition, a code constraint condition that allows the appearance of a binary level code value continuously inverted code sequence having a predetermined continuous code length only at a predetermined information code position is added, and the first in (9) above The error correction encoder circuit has a predetermined continuous code length for an information code at a predetermined information code position in the recording code sequence block on the binary information code sequence before being converted and output from the recording processing circuit. The first error correction coding is performed so that the code error event corresponding to the continuous code error of the binary level code value continuous inversion code sequence having can be detected or corrected, or the first error correction code sequence is configured Also And the first error correction decoder circuit in (9) uses the first error correction encoding or the first error correction code sequence to estimate the maximum likelihood sequence. Binary level code value continuous having a predetermined continuous code length only for a decoded code corresponding to a predetermined information code position in the recording code sequence block on the binary information code sequence decoded and output from the circuit 14. The information recording / reproducing circuit according to claim 13 , wherein a first code error detection and correction process for detecting and correcting a code error event corresponding to a continuous code error of an inverted code sequence is performed. A response signal waveform on a reproduced signal sequence input from the recording / reproducing system to the maximum likelihood sequence estimating circuit when the binary information code sequence is recorded / reproduced by the recorded signal sequence having only a single isolated signal level inversion 13. The information recording / reproducing circuit according to claim 12 , further comprising the recording processing circuit and the reproducing processing circuit having a signal transmission characteristic having asymmetric shape. Information recording and reproducing apparatus for mounting the information recording and reproducing circuit according to any one of claims 1 to 16. An integrated circuit on which the information recording / reproducing circuit according to any one of claims 1 to 16 is mounted. An information recording / reproducing apparatus equipped with the integrated circuit according to claim 18 .

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