KR101361238B1  Error Correcting Methods and Circuit over Interference Channel Environment, Flash Memory Device Using the Circuits and Methods  Google Patents
Error Correcting Methods and Circuit over Interference Channel Environment, Flash Memory Device Using the Circuits and Methods Download PDFInfo
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 KR101361238B1 KR101361238B1 KR1020120060606A KR20120060606A KR101361238B1 KR 101361238 B1 KR101361238 B1 KR 101361238B1 KR 1020120060606 A KR1020120060606 A KR 1020120060606A KR 20120060606 A KR20120060606 A KR 20120060606A KR 101361238 B1 KR101361238 B1 KR 101361238B1
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 G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
 G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
 G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
 G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
 G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature

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 G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
 G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
Description
The present invention relates to an error correction method and a circuit, and a flash memory device using the same. In particular, an error that can improve an error correction capability by performing error correction reflecting the influence of interference between data in an interference channel environment such as a flash memory is disclosed. A correction method and circuit, and a flash memory device using the same.
In recent years, various electronic devices have been significantly bottlenecked in the operation speed because the speed of the auxiliary memory device is considerably slower than the speed of the main memory device such as a processor and a RAM. Conventional auxiliary storage devices such as a hard disk drive (HDD) may not only cause a bottleneck but also easily damage the data due to a shock. Solid state drives (SSDs) composed of semiconductor devices using MOSFET structures have emerged as the next generation auxiliary memory devices.
The SSD has the advantage that it can perform data input / output at high speed without delay due to the search time because it is possible to perform random access to the device in which the data is stored and the processing speed is faster than the conventional auxiliary memory devices. In addition, the mechanical delay and the failure rate are remarkably low, and the data is not easily damaged even in the external impact. In addition, the SSD has low power consumption, low power consumption, low noise and low power consumption because it does not need any mechanical device.
The SSD includes a NOR flash memory configured by a NOR method and a NAND flash memory configured by a NAND method. Among them, flash memory is generally used in most large capacity SSDs because NAND flash is easy to make large capacity and has high read / write speed. NAND flash memory devices tend to be miniaturized and multivalued due to the use of microprocesses and increasing the number of bits stored per cell in order to increase memory storage density, Is increasing.
1 is a diagram showing a distribution of threshold voltages according to the number of bits stored per cell in a flash memory.
Referring to FIG. 1, a singlelevel cell (SLC) flash memory (a) is a NAND device for storing 1bit information per cell, and a multilevel cell (MLC) flash memory (b) , A TriLevel Cell (TLC) flash memory (c) is a 3bit information, and a QLC (QuadLevel Cell) flash memory (d) is a NAND device that stores 4 bits of information. In each of FIGS. 1 (a), (b), (c), and (d), E indicates a state in which data of each cell of the flash memory is erased.
As shown in FIG. 1, as the number of bits to be stored per one cell increases, the noise margin decreases. As a result, the probability of occurrence of an error due to interlevel interference during a read operation increases, As the operation is repeated, the probability of occurrence of errors is greatly increased and the reliability of the product is lowered. Therefore, low power and high throughput error correction circuits are essential to design reliable NAND flash memory at a reasonable price.
An error correction circuit generally uses an error correction code, which requires extra bits containing information for error detection and error correction. Thus, extra cells are required to store the extra bits. However, in order to maximize the storage capacity of the storage medium, the area of the cell required to store the extra bits must be minimized, so that there is a need to minimize the extra bits.
In addition, due to the increase of stored data error, the complexity that exponentially increases according to the number of errors and the new error that replaces the existing BCH (BoseChaudhuriHocquenghem) code or RS (ReedSolomon) A correction code is required.
LowDensity ParityCheck (LDPC) codes are error correction codes that approach the Shannon's channel capacity limits using a message passing algorithm such as the BP (Belief Propagation) algorithm. It can show error correction performance. Due to this high performance error correction capability, it has been in the spotlight as the next generation error correction code in many fields that require error correction including communication. However, in order to derive the decoding performance of the lowdensity parity check code, soft decision information is essential to the decoding part. However, in the case of flash memory, only the hard decision information is transmitted to the decoding part, so the lowdensity parity check code is transmitted. The situation is not fully utilized.
An object of the present invention is to provide an error correction method of improving error correction performance by utilizing information on interference in an interference channel environment for error correction.
Another object of the present invention is to provide an error correction circuit with improved error correction capability.
It is still another object of the present invention to provide a flash memory device including an error correction circuit.
An error correction method according to an embodiment of the present invention for achieving the above object is an error correction method for a signal transmitted through a channel in which statistical analysis is performed on a channel, comprising: receiving a plurality of signals; Calculating a magnitude of an average interference and a random noise included in the first signal according to the statistical analysis by at least one second signal successively received after the first signal among the plurality of signals; Determining the value of the first signal by applying the predetermined maximum likelihood sequential search algorithm (MLSD) in consideration of the magnitude of the average interference calculated from the first signal and the magnitude of the random noise; And accumulating the first signals whose values are determined, and correcting values of the plurality of accumulated first signals using an error correction code. .
The maximum likelihood sequential search algorithm is characterized by the use of a branch metric considering the magnitude of the average interference and the magnitude of the random noise.
The step of calculating according to the statistical analysis is defined such that the average interference and the random noise included in the first signal are affected only by one second signal which is continuously received after the first signal; And calculating the magnitude of the average interference and the magnitude of the random noise included in the first signal by the second signal according to the statistical analysis. And a control unit.
The branch metric is
Where r _{k} is a first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is equal to the second signal. Is the magnitude of the interference of the first signal, and σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ).
The determining and applying to the maximum likelihood sequential search algorithm (MLSD) comprises: quantizing the first signal; And determining the value of the first signal by substituting the quantized first metric, the average interference, and the random noise by applying the branch metric to a preset quantization branch metric.
The quantization branch metric is
Where d _{k} is a quantized first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is the second signal. Is the magnitude of the interference of the first signal by the signal, σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ), and D is a quantization function. It is characterized in that the calculation.
According to another exemplary embodiment of the present invention, an error correction circuit includes a magnitude and an arbitrary amount of average interference included in the first signal by at least one second signal continuously received after a first signal among a plurality of received signals. The first signal is calculated using a maximum likelihood sequential search algorithm (MLSD) calculated according to the statistical analysis, and considering the magnitude of the average interference calculated from the first signal and the magnitude of the random noise. A data judging unit for determining a value of; And an error correction unit for receiving a plurality of first signals whose values are determined from the data determination unit, and correcting the received plurality of first signals using an error correction code. .
The maximum likelihood sequential search algorithm is characterized by determining the value of the first signal using a branch metric considering the magnitude of the average interference and the magnitude of the random noise.
The data determining unit defines that the average interference and the random noise included in the first signal are affected only by one second signal that is continuously received after the first signal, and wherein the one signal is determined according to the statistical analysis. The magnitude of the average interference and the random noise included in the first signal by the two signals are calculated.
The data determining unit quantizes the first signal, and determines the value of the first signal by substituting the quantized first signal to a preset quantization branch metric by applying the branch metric.
According to another aspect of the present invention, there is provided a receiving apparatus including: a receiving unit receiving a modulated signal that is modulated and transmitted; A demodulator for receiving and demodulating a modulated signal from the data receiver, generating a plurality of signals, and determining and correcting the values of the plurality of signals including an error correction circuit; Wherein the error correction circuit is configured to statistically analyze the magnitude of the average interference and the magnitude of the random noise included in the first signal by at least one second signal continuously received after a first signal of the plurality of signals. And a data plate for determining the value of the first signal using a predetermined maximum likelihood sequential search algorithm (MLSD) in consideration of the magnitude of the average interference and the magnitude of the random noise calculated from the first signal. government; And an error correction unit for receiving a plurality of first signals whose values are determined from the data determination unit, and correcting the received plurality of first signals using an error correction code. .
In accordance with still another aspect of the present invention, a flash memory device includes a memory cell array configured to store a plurality of memories; A page buffer for latching data written to and read from the memory cell array; An error correction circuit for generating an error correction code for correcting and detecting an error from the data at the time of recording and correcting and detecting an error of the data from the data and the error correction code at the time of the reading; An address decoding and control circuit for outputting a control signal for writing and reading the data to the memory cell, decoding an address, and controlling input / output of data from the page buffer; And a Ygating circuit operable in response to address information provided from the address decoding and control circuit, wherein the error correction circuit is adapted to at least one second signal continuously received after a first signal of the plurality of signals. Calculates the magnitude of the average interference and the random noise included in the first signal according to the statistical analysis, and considers the magnitude of the average interference calculated from the first signal and the magnitude of the random noise, A data determination unit for determining a value of the first signal using a likelihood sequential search algorithm (MLSD); And an error correction unit for receiving a plurality of first signals whose values are determined from the data determination unit, and correcting the received plurality of first signals using an error correction code. .
Therefore, the error correction method and circuit and the flash memory device using the same correct the error including the influence of the interference on the data through the preliminary work before the error correction circuit in the situation where the statistical analysis of the interference channel is performed. It can be improved. Therefore, by reducing the number of times of rereading a decoded page from the flash memory, the error correction performance can be improved and the throughput and processing delay time can be drastically reduced.
1 is a diagram showing a distribution of a threshold voltage according to the number of bits stored in each cell in a flash memory.
2 is a diagram showing the structure of a general flash memory.
3 is a diagram showing a quantization method in a flash memory.
4 is a block diagram illustrating an error correction circuit according to an exemplary embodiment of the present invention.
FIG. 5 is a block diagram illustrating a flash memory device including the error correction circuit of FIG. 4.
6 is a block diagram illustrating an SSD including the flash memory device of FIG. 5.
7 illustrates a communication system according to another embodiment of the present invention.
In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.
Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.
Throughout the specification, when an element is referred to as " including " an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.
In the present invention, a channel means all paths through which data and signals can be transmitted, and can include both a wired and a wireless path.
Although the present invention has been described based on data, which is a digital value stored in a memory cell, the present invention can be applied to various fields such as a communication system, and thus, the signals and symbols may be used as the same meaning in the present invention.
2 is a diagram showing the structure of a general flash memory.
Hereinafter, the structure of the NAND flash memory, the unit of decoding / decoding of the error correction code, and the interference channel environment will be described with reference to FIG.
Referring to FIG. 2, the error correction code of the NAND flash memory is read and written in units of one page. One block is composed of a plurality of word lines, and separately there are bit lines. One word line can be divided into odd / even bit lines and subdivided into page units according to the number of bits constituting each cell. For example, in the case of the MLC scheme in which two bits are stored in one cell, one word line is divided into a most significant bit (MSB) / least significant bit (LSB) unit of a cell belonging to each bit line, It consists of four pages. As described above, the error correction code of the NAND flash memory corrects an error occurring in a cell in units of one page. Here, the interference channel environment means a channel environment in which interference occurs between information input to a channel and damage to original information occurs. In the state of FIG. 2, the information input to a specific cell may be damaged due to an interference phenomenon occurring when information is newly input to cells existing at adjacent positions.
Although the present invention can be widely used in various interference channel environments, for convenience of description, it is assumed that a channel is assumed in an MLC flash memory environment. In the MLC flash memory environment, the channel environment can be defined as Equation (1).
In Equation (1), x represents data input to the memory. That is, input data that is damaged by interference, and data that generates an interference effect. In a typical channel, it can be viewed as the entire data of the channel input.
r _{jk} (x) denotes a signal that is a result of a change in data input by interference, that is, a corrupted data value, and a subscript denotes a symbol position. In this case, for example, the data of a cell located in the jth bit line, the kth word line, is a signal value modified by interference or the like. Since the changed signal is input from the error correction circuit, r _{jk} (x) is an input signal of the error correction circuit. The meaning is similar in common channels.
x _{jk} stands for the actual input symbol, that is, the original data. The meanings of subscripts are as described above. Since it is assumed that MLC is assumed, referring to FIG. 1, the value that x _{jk} can actually have is one of {E, PV 1, PV 2, PV 3}. In a general channel, it means an original symbol (signal) input to the channel.
f _{jk} (x) means the magnitude of the average interference applied to the position implied by the subscript. That is, when the data of the pattern x is inputted, it is the average interference or error magnitude applied to the data at the specific position. The magnitude of this average interference in memory or in a typical environment can be obtained through repeated experiments and statistical analysis.
n _{jk} (x) means any noise applied to the position indicated by the subscript. That is, it means the noise remaining after removing the influence of the average interference x _{jk} + f _{jk} (x) and the original symbol input from the corrupted data r _{jk} (x) for the given data pattern x. These noise terms can be modeled as averaging zero and following the Gaussian distribution with the variance, using the mean variance obtained from the statistical analysis. In other words, past obtained through statistical analysis, such as f _{jk} (x), according to the not fixed unlike the distribution f _{jk} (x) may have any value.
Referring to Equation (1), it can be said that the damage to the original data is determined by the pattern of the original data and the surrounding data. Equation (1) can be applied to all possible data patterns. Although the present invention also suggests a method that can be applied to all data patterns, it is assumed here that the damage to the original data is affected only by neighboring data, for convenience of explanation. This follows the results of a study on existing flash memory where the data that dominate the damage to the original data is single data of the neighboring word line adjacent to the original data. In this case, Equation (1) can be simplified as Equation (2).
According to Equation (2), the damaged kth data can be determined by the k + 1th data neighboring the original data input to the channel. Also, since the MLC flash memory is assumed for convenience of explanation, x _{k} and x _{k + 1} can express a range of values as follows.
In Equation (3), the erase (E) state in FIG. 1 is expressed by PV _{0} for convenience of explanation.
In this assumption, f (x _{k} , x _{k + 1} ) is obtained by statistical analysis of the pattern with a deterministic value for the 16 possible patterns. n (x _{k} , x _{k + 1} ) is determined according to each distribution for 16 possible patterns. n (x _{k,} x _{k + 1)} can follow an arbitrary distribution. However, here, with zero mean and variance σ ^{2} (x _{k,} x _{k} of the statistical analysis n (x _{k,} x _{k + 1)} obtained from the _{+1} ) to the Gaussian distribution with variance.
The following Llevel quantization scheme is assumed to reflect characteristics of the flash memory in which only hard decision information can be acquired.
3 is a diagram showing a quantization method in a flash memory.
Where d _{k} is the quantized value of r _{k} . D is a quantization function, V is a set of quantization values, and v, which can be included in a set of quantization values (V), is a quantization value element.
(V _{0} , v _{1} , ..., v _{L1} ) that can be included in the set of quantization values (V) are {PV _{0} , PV _{1} , PV _{2} , PV _{3} }to be.
In other words, the actual value r _{k} stored in the memory is inaccessible and only the quantized d _{k} of r _{k} is accessible. Here, D denotes a quantization function, and R _{i} and R _{i + 1} denote a lower limit and an upper limit of an actual value range, respectively, which will have an ith quantization level value. In the case of MLC flash memory, each cell has 2bit information, so the quantization level is L = 4.
Under these assumptions, the maximum likelihood sequence detection (MLSD) algorithm, which is known for interference cancellation, can be modified to fit the channel to improve the input of the error correction code decoder. If the input of the decoder has a lower bit error rate (BER) by considering the influence of interference, error correction performance can be improved in the conventional scheme. First, the MLSD algorithm considering interference can be considered by modifying the branch metric (BM) of the Viterbi algorithm.
Where BM represents the branch metric and σ (x _{k} , x _{k + 1} ) represents the standard deviation of n (x _{k} , x _{k + 1} ).
However, in the situation where only hard decision information such as flash memory is valid, the branch metric of Equation 6 may be modified as in Equation 7.
Where BM represents the branch metric and σ (x _{k} , x _{k + 1} ) represents the standard deviation of n (x _{k} , x _{k + 1} ).
Using the branch metric of Equation 7, the influence of interference by adjacent data may be included to obtain a value of the quantized original data. Then, as in the general error correction circuit, if the error is corrected using an error correction code, very accurate data can be obtained. In addition, since the error is corrected by using an error correction code in a state where the error due to interference is primarily reduced, the error is corrected in a state where the number of errors is small, thereby minimizing the number of extra bits required for error correction. .
As described above, the improved error correction performance may be disadvantageous in that the data (or symbol) value of the adjacent cell is known in addition to the cell to be corrected, but the adjacent cells are likely to be sequentially decoded. As a cost for improving the performance, it can be seen as cheap.
The error correction method in the interference channel proposed by the present invention can be applied to any situation having a similar channel as well as a flash memory device. As described above, the present invention can be basically applied to a NAND flash memory device, but it can also be applied to other types of memory devices such as a NOR flash memory.
4 is a block diagram illustrating an error correction circuit according to an exemplary embodiment of the present invention.
Referring to FIG. 4, the error correction circuit 100 according to the present invention includes a data determination unit 110 and an error correction unit 120.
The data determination unit 110 receives the data changed by the interference, and determines the data value of the received data in consideration of the influence of the interference between the data. The data determination unit 110 receives not only the current data r _{k} but also a predetermined number of adjacent data r _{k + 1} ,... Which are subsequently applied in order to consider the influence of the interference between the data. And adjacent to the data value of the current data (r _{k)} data (r _{k + 1,} ...) determined data on the maximum likelihood sequential search algorithm to apply the current data (r _{k)} in consideration of the influence of the interference by the (x Calculate and print _{k} ). In this case, since the maximum likelihood sequential search algorithm only the hard decision information is valid when the data has a quantized value, the maximum likelihood sequential search algorithm calculates the decision data x _{k} using the changed branch metric.
The error correction circuit 120 has a plurality of detection data (x _{k,} x _{k + 1,} ...) for receiving and determining the received plurality of data (x _{k,} x _{k + 1,} ...), the error correction Error correction is performed using a sign to output the errorcorrected output data (c _{k} , c _{k + 1} , ...).
FIG. 5 is a block diagram illustrating a flash memory device including the error correction circuit of FIG. 4.
The flash memory device includes a memory cell array 200 in which a plurality of electrically rewritable memory cells are arranged in a matrix form, a write circuit for writing write data to be written to the memory cell array 300 and a page buffer An error correction circuit 100 for correcting and detecting an error in read data from read data and an error correction code when outputting read data in addition to generating an error correction code for correcting and detecting an error from the record data, An address decoding and control circuit 300 for outputting a control signal for writing and reading data in the memory cell, decoding the address and controlling input / output of data from the page buffer 400, And a Ygating circuit (not shown) operating in response to the address information provided by the control circuit 300 It consists of 500. The memory cell array 200 is configured in such a manner that memory blocks including a series of memory cells are arranged in series. The memory cells existing in the memory block are connected to the page buffer 400 through a series of bit lines.
In FIG. 5, the error correction circuit 100 is an error correction circuit illustrated in FIG. 4, and includes a data determination unit 110 and an error correction unit 120, and the data determination unit 110 primarily inputs data. Since the error correction unit 120 corrects the data by using the error correction code after determining, the error correction rate is high and the number of spare memory cells for storing the error correction code can be greatly reduced. That is, the storage capacity of the flash memory device having the same number of memory cells can be made larger than that of the conventional flash memory device.
6 is a block diagram illustrating an SSD including the flash memory device of FIG. 5.
As shown in FIG. 6, the SSD typically includes at least one flash memory device 11 to 1n according to a storage capacity. And at least one buffer 21 to 2n provided corresponding to each of the at least one flash memory device 11 to 1n for buffering data input to and output from the corresponding flash memory device 11 to 1n, And an input / output control unit (3) for converting the data into an interface with an external device to be connected, and at least one buffer (21 to 2n) and at least one flash memory device (11 to 1n).
As shown in FIG. 5, each of the at least one flash memory device 11 to 1n includes an error correction circuit 100 that corrects an error in consideration of the influence of interference by adjacent data.
6 illustrates that at least one buffer 21 to 2n is provided corresponding to each of the at least one flash memory device 11 to 1n. However, in some cases, the plurality of flash memory devices 11 to 1n may be provided. One buffer may be provided. Also, the error correction circuit 100 may be provided with a single error correction circuit 100 in the plurality of flash memory devices 11 to 1n.
In a memory device in which a plurality of flash memory devices 11 to 1n may be provided, such as an SSD, the number of extra bits may be reduced in each of the flash memory devices 11 to 1n, thereby greatly increasing the overall data storage capacity. .
7 illustrates a communication system according to another embodiment of the present invention.
5 and 6 illustrate that an error correction circuit according to an embodiment of the present invention is applied to a flash memory device, the error correction circuit of the present invention may be applied to a general communication system 500. The communication system 500 includes a transmitting apparatus 510 and a receiving apparatus 520. The transmitting apparatus 510 includes a data modulating unit 511 for receiving and modulating the data x to be transmitted and a data transmitting unit 512 for transmitting the modulated data according to a predetermined communication method.
The receiving device 520 receives and demodulates the data received from the data receiving unit 521 and the data receiving unit 521 for receiving the signal transmitted from the transmitting device 510, corrects an error, and transmits the data transmitted from the transmitting device. And a data demodulation unit 522 for restoring the data. The data demodulator 522 may include an error correction circuit 100 according to the present invention to reduce communication errors.
Although FIG. 7 illustrates a wireless communication system, the present invention is not limited thereto and may be applied to a wired communication system. In the above description, the expression "data" is used in the assumption of digital data communication, but the present invention is also applicable to analog communication.
The method according to the present invention can be implemented as a computerreadable code on a computerreadable recording medium. A computerreadable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the recording medium include a ROM, a RAM, a CDROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and a carrier wave (for example, transmission via the Internet). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.
Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.
Claims (18)
 A method for error correction of a signal transmitted over a channel on which statistical analysis is performed on the channel,
Receiving a plurality of signals;
Calculating an average interference magnitude and an arbitrary noise magnitude included in the first signal by at least one second signal continuously received after a first one of the plurality of signals according to the statistical analysis;
Determining the value of the first signal by quantizing the first signal and substituting the quantized first signal and the average interference magnitude and the random noise magnitude into a preset maximum likelihood sequential search algorithm (MLSD); And
Accumulating the first signals having values determined, and correcting values of the plurality of accumulated first signals by using an error correction code; Including;
The maximum likelihood sequential search algorithm
And modifying a branch metric of a Viterbi algorithm to be proportional to the square of the average interference magnitude and inversely proportional to the random noise magnitude.  delete
 The method of claim 1, wherein the step of calculating according to the statistical analysis is
The average interference and the random noise included in the first signal are defined to be affected only by the one second signal received consecutively after the first signal; And
Calculating the magnitude of the average interference and the magnitude of the random noise included in the first signal by the second signal according to the statistical analysis; Error correction method comprising a.  4. The branch metric of claim 3 wherein the branch metric is
Equation
Where r _{k} is a first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is equal to the second signal. Is the magnitude of the interference of the first signal, and σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ).)
Error correction method characterized in that the calculated.  4. The method of claim 3, wherein the determining is applied to the maximum likelihood sequential search algorithm (MLSD).
Quantizing the first signal; And
And the value of the first signal is determined by substituting the quantized branch metric by applying the branch metric to the quantized first signal, the average interference, and the random noise. .  6. The method of claim 5, wherein the quantization branch metric is
Equation
Where d _{k} is a quantized first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is the second signal. Is the magnitude of the interference of the first signal by the signal, σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ), and D is a quantization function.)
Error correction method characterized in that the calculated.  The magnitude of the average interference and the amount of random noise included in the first signal by at least one second signal continuously received after the first signal among the plurality of signals transmitted through the channel for which statistical analysis on the channel is performed Calculated according to the above statistical analysis,
After quantizing the first signal, data for determining the value of the first signal by substituting the quantized first signal, the average interference magnitude, and the random noise magnitude into a preset maximum likelihood sequential search algorithm (MLSD) Determination unit; And
An error correction unit for receiving a plurality of first signals whose values are determined from the data determination unit, and correcting the received plurality of first signals using an error correction code; Including;
The maximum likelihood sequential search algorithm
And modifying a branch metric of a Viterbi algorithm to be proportional to the square of the mean interference magnitude and inversely proportional to the random noise magnitude.  delete
 The method of claim 7, wherein the data determination unit
The average interference and the random noise included in the first signal are defined to be affected only by one second signal that is continuously received after the first signal, and is determined by the one second signal according to the statistical analysis. And calculating a magnitude of an average interference and a magnitude of random noise included in the first signal.  10. The method of claim 9, wherein the branch metric is
Equation
Where r _{k} is a first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is equal to the second signal. Is the magnitude of the interference of the first signal, and σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ).)
Error correction circuit, characterized in that the calculation.  The method of claim 9, wherein the data determination unit
And quantizing the first signal and substituting the quantized first signal into a predetermined quantization branch metric by applying the branch metric to determine a value of the first signal.  12. The method of claim 11 wherein the quantization branch metric is
Equation
Where d _{k} is a quantized first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is the second signal. Is the magnitude of the interference of the first signal by the signal, σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ), and D is a quantization function.)
Error correction circuit, characterized in that the calculation.  A receiver for receiving a modulated signal transmitted through the channel on which a statistical analysis of the channel is performed; And
A demodulator for receiving and demodulating a modulated signal from the receiver to generate a plurality of signals and determining and correcting the values of the plurality of signals including an error correction circuit; Lt; / RTI >
The error correction circuit
The magnitude of the average interference and the amount of random noise included in the first signal are calculated according to the statistical analysis by the at least one second signal continuously received after the first signal of the plurality of signals, and the first signal A quantization unit, and a data determination unit determining the value of the first signal by substituting the quantized first signal, the average interference magnitude, and the random noise magnitude into a preset maximum likelihood sequential search algorithm (MLSD); And
An error correction unit for receiving a plurality of first signals whose values are determined from the data determination unit, and correcting the received plurality of first signals using an error correction code; Including;
The maximum likelihood sequential search algorithm
And a branch metric of a Viterbi algorithm is modified to be proportional to the square of the mean interference magnitude and inversely proportional to the random noise magnitude.  The method of claim 13, wherein the data determination unit
Determining a value of the first signal using a branch metric considering the magnitude of the average interference and the magnitude of the random noise;
The branch metric is
Equation
Where r _{k} is a first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is equal to the second signal. Is the magnitude of the interference of the first signal, and σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ).)
Receiving device, characterized in that calculated.  The method of claim 13, wherein the data determination unit
Quantize the first signal and substitute the quantized first signal into a predetermined quantization branch metric to determine a value of the first signal,
The quantization branch metric is
Equation
Where d _{k} is a quantized first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is the second signal. Is the magnitude of the interference of the first signal by the signal, σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ), and D is a quantization function.)
Receiving device, characterized in that calculated.  A memory cell array for storing a plurality of memories;
A page buffer for latching data written to and read from the memory cell array;
An error correction circuit for generating an error correction code for correcting and detecting an error from the data at the time of recording and correcting and detecting an error of the data from the data and the error correction code at the time of the reading;
An address decoding and control circuit for outputting a control signal for writing and reading the data to the memory cell, decoding an address, and controlling input / output of data from the page buffer; And
And a Ygating circuit operating in response to address information provided by the address decoding and control circuit,
The error correction circuit
The magnitude of the average interference and the amount of random noise included in the first signal by at least one second signal continuously received after a first signal of the plurality of signals transmitted through the channel on which a statistical analysis of the channel has been performed Is calculated according to the statistical analysis, the first signal is quantized, and the quantized first signal and the average interference magnitude and the random noise magnitude are substituted into a predetermined maximum likelihood sequential search algorithm (MLSD). A data determination unit that determines a value of the first signal; And
An error correction unit for receiving a plurality of first signals whose values are determined from the data determination unit, and correcting the received plurality of first signals using an error correction code; Including;
The maximum likelihood sequential search algorithm
And a branch metric of a Viterbi algorithm is generated by modifying the branch metric proportional to the square of the average interference magnitude and inversely proportional to the random noise magnitude.  The method of claim 16, wherein the data determination unit
Quantize the first signal and substitute the quantized first signal into a predetermined quantization branch metric to determine a value of the first signal,
The quantization branch metric is
Equation
Where d _{k} is a quantized first signal, x _{k} and x _{k + 1} are original signals of each of the first and second signals, and f (x _{k} , x _{k + 1} ) is the second signal. Is the magnitude of the interference of the first signal by the signal, σ (x _{k} , x _{k + 1} ) is the standard deviation of the random noise n (x _{k} , x _{k + 1} ), and D is a quantization function.)
Flash memory device, characterized in that calculated as.  At least one flash memory device according to claim 17;
At least one buffer corresponding to each of the at least one memory device and buffering data input to and output from the flash memory device; And
And an input / output controller for converting input / output data to / from the at least one buffer in accordance with a predetermined interface.
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JPH11317030A (en) *  19980508  19991116  Hitachi Ltd  Information recording and reproducing method, information recording and reproducing circuit and information recording and reproducing device using the circuit 
KR20020007414A (en) *  19990518  20020126  토토라노 제이. 빈센트  Error correction circuit and method for a memory device 
JP2005136517A (en) *  20031028  20050526  Japan Science & Technology Agency  Noisy environment adaptive digital receiver 
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JP2011142429A (en) *  20100106  20110721  Renesas Electronics Corp  Error correction control circuit, communication device, and error correction control method 

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JPH11317030A (en) *  19980508  19991116  Hitachi Ltd  Information recording and reproducing method, information recording and reproducing circuit and information recording and reproducing device using the circuit 
KR20020007414A (en) *  19990518  20020126  토토라노 제이. 빈센트  Error correction circuit and method for a memory device 
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