JPH10214461A - Digital magnetic recording/reproducing circuit and device using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the error correction capability of a viterbi detector by adding a function detecting a disappearance error bit judged that the probability that a decoding error occurs in the viterbi detector is high, detecting the decoding error estimated with a maximum likelihood series and correcting the error. SOLUTION: The veterbi detector 24 outputs a veterbi decoded result and a disappearance error detection flag to a recording decoder 25, and the recording decoder 25 performs record decoding processing to process in byte here. When the disappearance error bit detection flag is 1, the matter that an error exists in the decoded byte is found, and the recording decoder 25 outputs a disappearance error byte detection flag as flg-ebyte=1 to an error correction decoder 26 together with a record decoding result. When the detection flag is 0, the matter that no error exists in the decoded byte is judged, and the decoder 25 outputs the detection flag as flg-ebyte=0 to the error correction decoder 26. The error correction decoder 26 inputs the detection flag to perform error correction. Thus, when a disappearance error is detected precisely, double correction power of random error correction is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital magnetic recording / reproducing circuit and apparatus for recording and reproducing digital information on a recording medium such as a magnetic disk, and more particularly to a signal processing circuit capable of high-density recording and using the same. Related to the device.

[0002]

2. Description of the Related Art There is an increasing demand for high-density recording and high-speed recording in a magnetic disk drive, and signal processing technology of a recording / reproducing system which supports this has been adapted to high-density and high-speed recording. For the recording code, the encoding rate R
And R = 8/9 is often used at present.
More recently, various higher-rate 16/17 codes have been proposed and are becoming the mainstream of recording codes. Also, in order to cope with a decrease in the signal-to-noise ratio due to intersymbol interference due to high-density recording, a partial response (partial response) that detects a signal sequence closest to the reproduced signal using known interference configured on the reproduced channel is used. Partial Response,
The PR) equalization method has come into practical use. In particular, PR4ML (Partial Response C)
less 4 with Maximum Likelih
The OOD method is already mounted on a magnetic disk product as an LSI. In PR4ML, it can be described by a dicode channel represented by 1-D as is well known. Here, D represents a delay operator and is a channel memory. The channel state is the value of the magnetic information one time before stored in the channel memory D, and is either 0 or 1. Since the magnetic information is recorded in the direction of magnetization, it is represented by +1, -1 bipolar.
These pieces of magnetic information can also be represented in a binary format of 1,0. The channel output is determined as 1-D from the current magnetic information value and the value stored in the channel state, and the new magnetic information is stored as the next channel state.

In PR4ML, the minimum between signal sequences
Squared distance (MSED:MinimumSqualified
EuclideanDinstance) is 2 (equalization)
Output value is converted in binary format, and the same applies to the following)
It has been known. For this reason, PR4ML performs maximum likelihood estimation processing.
Detection that determines magnetic information only by 0 and 1 without performing
Compared with the system (MSED = 1), the margin for noise is
3 dB improvement.

[0004] As described above, the MSED of PR4ML is 2
However, in order to realize higher-density recording, a signal processing technique for further increasing the MSED is necessary to compensate for a decrease in the signal-to-noise ratio (S / N) accompanying an increase in the amount of interference. Becomes As a method to realize this, EPR4M
L (Extended PR4ML), EEPR4ML
(Extended EPR4ML), trellis codes, and the like are being studied. The former two are extensions of the PR4ML concept, and MSEDs are 4, 6 respectively.
Is known to be. The number of states increased with the expansion of MSED, 8 in EPR4ML and 1 in EEPR4ML.
It becomes 6. These are effective in a region where the linear recording density is high (in other words, the same decoding error rate can be obtained with a lower signal-to-noise ratio than in the case of PR4ML). Recently PR4
The transition from ML to the EPR4ML system capable of higher recording density is in progress, and trial production and commercialization using LSIs are progressing rapidly. Thus, at present, the digital magnetic recording / reproducing system based on EPR4ML is becoming mainstream.

FIG. 2 shows the configuration of a conventional digital magnetic recording / reproducing apparatus. E as a PR equalization circuit
Description will be made on the assumption that the PR4 channel is used. In the figure, on the recording side, digital information A is transmitted to an error correction encoder 10.
Thus, error correction coding is performed using Reed, Solomon codes and the like. Since Reed and Solomon codes can correct byte errors, they are often used in magnetic recording and reproducing devices that require high reliability. The error-correction-encoded sequence is recorded and encoded by the recording encoder 11 and converted into a format suitable for magnetic reproduction characteristics by giving a run length restriction or the like. The 8/9 code and more recently the 16/17 code are most often used. The recorded and encoded sequence is further processed by the precoder 12 in the form of NRZI (Non Return).
After being converted into a “to Zero Inverted” format, it is magnetically recorded on a recording medium 15 such as a magnetic disk through an amplifier 13 and a recording head 14.

On the other hand, on the reproducing side, the magnetic recording medium 1
5 is reproduced as an electric analog signal by the reproducing head 16 and the amplifier 17 and is controlled by the variable gain amplifier 18 to have a constant amplitude, and the A / D (An)
The overflow of the input amplitude to the alog to digital converter 19 is prevented. The A / D converter 19 converts the analog signal into a digital signal, and all the subsequent reproduction processing is digitally processed. The digitized signal is sampled at appropriate timing for each bit interval and input to the PR equalization circuit 20. In PR equalization (here, EPR4 equalization), the input sample sequence is used to perform EPR4 equalization to a channel having a transfer characteristic of 1 + DD {2-D} 3. Here, D is a channel memory, and ＾ is a power operation. The EPR4 channel is shown in FIG.
4 (details will be described in the embodiment). Here, S0, S1,..., S7
Are the channel states 000,001,..., 1
It is 11. Equalized signals corresponding to the upper and lower branches (paths) are output according to the value of the input signal to a certain state (0, 1, indicated by − and + in the figure), and the next channel state Transitions to. In the EPR4 channel, the equalized output has five values (2, 1, 0, -1, -2).

[0007] The EPR4 equalized sequence is subjected to maximum likelihood decoding by a Viterbi detector 21. This is a process of estimating the history of paths that have transitioned with the most probable probability (maximum likelihood sequence estimation) using the state transition diagram shown in the figure. The decoding result (0, 1) obtained by the maximum likelihood sequence estimation is recorded / decoded by the recording / decoding unit 22, and is inversely transformed into an input sequence to the reproduction side recording encoder. The sequence that has been recorded and decoded is subjected to byte error correction by Reed-Solomon decoding or the like by the error correction decoder 23, and then the restoration information A 'is reproduced.

FIG. 4 shows the configuration of the Viterbi detector 21. Here, a thick signal line and a thin signal line mean a multi-bit bus and a 1-bit bus, respectively (hereinafter, referred to as buses)
The same notation is used in other drawings). In the figure, a sequence yk that has been EPR4 equalized at time k is subjected to an EPR4 equalization output candidate (2, 1,
0, -1, -2) is calculated as a branch metric. The branch metric is calculated as the square distance between yk and the EPR4 equalization output candidate.
Here, the branch metrics for 2, 1, 0, -1, and -2 are BM (2), BM (1), and BM, respectively.
(0), BM (-1), and BM (-2).

After the branch metric is calculated, the ACS (Add, ComPare, Select) circuit 42 performs addition, comparison, and selection processing. FIG. 10 shows the detailed circuit configuration. As shown in the figure, in the ACS circuit, the adder 100 adds the branch metric and the state likelihood (cumulative value of the branch metric) for each state by an adder 100 according to an EPR4 state transition diagram (see FIG. 24). At 101, the smaller likelihood and the corresponding path are output as new state likelihoods S0,..., S7 and surviving path information SP0,. Here, the surviving path information SP0,..., SP7 is a value represented by 1 bit (0, 1) that identifies the upper path and the lower path in the state transition diagram 24. The state likelihoods S0,..., S7 are stored in the delay element 102, respectively, and are prepared for the next ACS calculation processing. In the figure, to avoid complexity, signal lines indicated by thick arrows are S0,.
S7 (from the output of the delay element 102 to the adder 10
0 input).

On the other hand, surviving paths SP0,.
7 are input to the data selection circuit 103, and the corresponding binary data d0,..., D7 are output from the surviving path information to the path memory circuit 43. In the path memory circuit 43, the binary data d0,..., D7 are stored for a sufficiently long period (path memory length), and the path memory length is determined by a traceback process (usually a well-known register exchange process). Then, the data that has been traced back is output as the Viterbi decoding result.

The above is the configuration of the magnetic recording / reproducing apparatus according to the prior art.

However, the density of magnetic recording has become steep at an annual rate of about 1.6 times.
(Magneto Resistive) head and GMR (Gigant MR) head have been further researched and developed, and this tendency has been further accelerated. At present, it has been demonstrated that the areal recording density of 5 Gb / in2 is technically feasible, and it is expected that the area will shift to 10 Gb / in2 in the year 2000. Therefore, it is difficult for the conventional magnetic recording / reproducing apparatus of FIG. 2 to withstand the demand for ultra-high density. Therefore, as a signal processing technology, EP
It is essential to realize a method capable of higher density recording than R4ML.

In recent years, trellis codes have been noticed and studied for the above technical problems. The trellis code is a type of recording code, and is a method in which information after error correction encoding is encoded according to a certain rule, and this is fused with a PR channel to expand MSED between signals. It can be considered that the recording encoder 11 and the recording decoder 22 in FIG. 2 are replaced with a trellis encoder and a trellis decoder, respectively (the conventional recording code does not have the ability to expand MSED). PR4
Trellis codes based on channels (hereinafter, PR4 trellis codes) have been most studied.

As a PR4 trellis code applied to magnetic recording, MSN (Matched Spectral N) is used.
(ull) sign. This matches the frequency characteristics of the code with those of the magnetic channel, resulting in a larger MSED.
Is what you get. The principle is documented: Matched
Spectral-Null Codes for Pa
rial-Response Channels, I
EEE Transactions on Inform
ation Theory, Vol. 37, No3, p
p. 818-855, May 1991. In this method, MSED = 4 is realized by performing coding based on the PR4 channel, and an S / N gain of 3 dB is obtained with respect to uncoded PR4ML.

The above MSN code can be applied to the EPR4 channel. In fact, it is described in the above document that MSED = 12 can be realized. However, only a coding rate as low as 1/2 has been found.

At present, an LSI using an MSN code having a coding rate of 8/10, 6 states as a PR4 trellis is being trial-produced, and its characteristics are described in Designa.
ndPerformance of a VLSI 120
Mb / s Trellis-Coded Partia
l Response Channels, IEEE,
Proceedings of 1994 The Mag
netic Recording Conference
It is described in.

More recently, permutation has been proposed as a technique for improving MSN codes and achieving higher rates.
A trellis coding scheme using n (permutation) has been proposed. This is to replace and connect the channel state corresponding to the last bit of the code word and the state corresponding to the first bit of the next code word while retaining only the channel bits,
Literature: Improved Trellis-Codin
g for Partial-Response Cha
nnels, IEEE, Proceedingsof 1
994 The Magnetic Recording
Conference, Literature: Finite Run
Cation Depth Trellis Codes
for the Diode Channel, IEEE
E, Transactions on Magnetic
s, Vol. 31, No. 6, pp. 3027-302
9, November 1995, and US Pat.
97384: Permuted Trellis Co
des for InputRestricted Pa
The details are described in the rial Response Channels. By the trellis coding method based on permutation, the degree of freedom of code assignment is increased, and a high-rate recording code equivalent to 8/9 can be relatively easily realized.

As described above, a trellis code based on a PR4 channel has been actively studied. The PR4 trellis is effective for increasing the density of the recording medium in the track direction and relieving a decrease in the signal-to-noise ratio due to inter-track interference and the like. However, since it is based on the PR4 channel, the linear recording density is effective only in a low region. In order to realize higher density recording, a signal processing method based on the EPR4 channel, which is advantageous in high linear recording density, is desirable. A study has been started to dramatically expand the MSED by applying the trellis code to the EPR4 channel, but generally the number of channel states becomes very large (about 16 or more), and the circuit configuration to be implemented becomes complicated.

[0019]

As described above, with the rapid progress toward high-density recording accompanying the demand for large-capacity storage, EPR4ML alone can no longer respond to the demand for ultra-high density. Further, the PR4 trellis cannot be applied to a high linear recording density area, and the MSED has a limit (about 4 or less). On the other hand, when the trellis code is applied to the EPR4 channel, the expansion of MSED can be expected, but it is difficult to increase the coding rate, the number of channel states is large, and the scale of the realized circuit becomes enormous.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a digital magnetic recording / reproducing circuit by signal processing capable of performing higher density recording with a simple configuration and a digital magnetic recording / reproducing apparatus using the same. It is in.

[0021]

According to the present invention, as a first method, a Viterbi detector detects a lost bit error of decoding, a recording decoder detects a lost byte error,
And means for correcting the lost byte error by the error correction decoder.

As a second method, instead of the recording encoder and the recording decoder used in the conventional invention, a second method is used.
Providing error correction encoding means and error correction decoding means,
The first method is applied.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment according to a first method of the present invention. In the figure, an error correction encoder 10, a recording encoder 11, a precoder 12, an amplifier 13, a recording head 14, a magnetic recording medium 15, a reproducing head 16, an amplifier 17, a variable gain amplifier 18, an A / D converter 19, and a PR The configuration and function of the equalization circuit 20 are the same as those of the conventional invention (see FIG. 2), and the conventional system can be used. The present invention improves the performance by providing means for increasing the decoding capability of the Viterbi detector 21. Therefore, the description of the configuration that can be diverted is omitted, and the configuration after the Viterbi detector will be described.

The Viterbi detector 24 and the recording / decoding device 2 of the present invention
5, and the error correction decoder 26 include means for detecting a lost bit error, means for detecting a lost byte error,
And means for correcting the lost byte error. Here, in the present invention, a bit or a byte determined to have a high possibility of occurrence of a decoding error is referred to as an erasure error bit or an erasure error byte. FIG. 5 shows the configuration of the Viterbi detector 24. Here, a thick signal line and a thin signal line mean a multi-bit bus and a 1-bit bus, respectively (hereinafter, the same notation is used in other drawings). In the figure, a sequence y EPR4 equalized at time k
For k, the branch metric calculation circuit 41 calculates the probability that the EPR4 equalization output candidate (2, 1, 0, -1, -2) is output as a branch metric. The branch metric is calculated as the square distance between yk and the EPR4 equalization output candidate. Here, 2,1,0, -1, -2
BM (2) and B
M (1), BM (0), BM (-1), and BM (-2). Up to this point, the configuration is the same as that of the conventional invention.

After the branch metric is calculated, the ACS circuit 1 (52) performs addition, comparison, and selection processing. FIG. 11 shows the circuit configuration. As shown in FIG.
In the CS circuit 1 (52), the branch metric and the state likelihood (cumulative value of the branch metric) are provided for each state.
Are added by the adder 100 according to the EPR4 state transition diagram (see FIG. 24), and are added to the comparison circuit 111.
In the present invention, the difference value DM0,.
, DM7 are output, and the sign bit is used as surviving path information SP0,..., SP7. Here, the difference value is a difference between two input signals in the comparison circuit 111. For example, in the case of the state S0, DM0 = (BM (0)
+ S0)-(BM (-1) + S4). DM
The same applies to 1,..., DM7. All digital processing uses 2's complement
t), the code bits survive the path information S
.., SP7. The state likelihoods S0,..., S7 correspond to the corresponding delay elements 11 respectively.
2 to be ready for the next ACS operation process. In the figure, signal lines indicated by thick arrows are S
.., S7 (from the output of the delay element 112 to the input of the adder 100) are respectively feedback-connected.

On the other hand, surviving path information SP0,.
SP7 is the output a0 of the threshold value determination circuit 112,.
., A7, and the corresponding data d0 ′,...,.
d7 'is output to the path memory circuit 53 together with the surviving path information SP0,..., SP7. Here, data d0 ',..., D7' are 1, 0, and disappearance X (= 0.
5). X represents an erasure bit and takes an intermediate value between 1 and 0, that is, 0.5. ai (i = 0, ...
., 7) indicates that the output di 'of the data selection circuit is 1, 0, X
Is a control signal that determines one of the following. When ai = 1, S
When di ′ = X and ai = 0 regardless of Pi, the data selection circuit 113 outputs binary data corresponding to SPi. The threshold value determination circuit 112 compares the absolute value of DMi with a threshold value R, and when | DMi |> R, ai = 0,
Otherwise, ai = 1 is output. That is, in the present embodiment, when the absolute value of the likelihood difference to be compared in the ACS is smaller than a certain threshold value, there is a high possibility that a decoding error due to S / N reduction occurs, and Is determined to be low in reliability, and X is output as an erasure error. If the absolute value is larger than the threshold value, a normal maximum likelihood decoding process is performed.

FIG. 20 is a conceptual diagram of the configuration of the path memory circuit 53. In the path memory circuit 53, the surviving path information S
By P0,..., SP7, selectors 0,.
.., the path memory register 200 ((reg0.1, reg0.reg.
2),..., (Reg7.1, reg7.2)), and reg0,.
Output to The selector i (i = 0,..., 7) (20
1) The path memory register 200 in the state Si
(Regi.1, regi.2) is a circuit for selecting an output. 1, regi. 2 stores the data history of the path leading to the state Si. Its depth is equal to the path memory length. In order to avoid complexity, it is assumed that the register outputs R0,..., R7 are connected in a feedback manner to the signal lines indicated at the corresponding positions. Its configuration is the same as the conventional invention.

On the other hand, the regi (202) also operates as a shift register, and its depth is determined by the path memory length (EP).
(In the case of R4ML, usually about 20 bits). The binary data di 'is serially input to the regi (202), and outputs data shifted out from the opposite side as a Viterbi decoding result. Here, the decryption result is 1,
It is either 0 or X. Register output R0, ...,
R7 is connected back to the signal line indicated at the corresponding position, and the path memory register 200 (reg.
regi. The content of 2) is updated. If the path memory length is made sufficiently long, the serial outputs of the regi (202) are all the same (the paths after traceback are merged). Therefore, here, reg0 in state S0
Decoded data is obtained using (202).

Although the path memory register 200 is shown in FIG. 1 to facilitate understanding of the operation concept, in the actual circuit configuration, the path memory register 2 is used.
The above operation can be realized by directly connecting to the selector i (201) using only the regi (202) without using 00.

Since the data sequence obtained as a result of the Viterbi decoding obtained by the above processing is based on maximum likelihood decoding, this is output to the erasure error detection circuit 1 (54) as the best sequence in FIG. FIG. 8 shows the configuration of the erasure error detection circuit 1 (54). The best series is 1,
Either 0 or X = 0.5, and these are identified by the threshold value judgment circuit 81. That is, when the input data d is 0.25 <d <= 0.75, it is determined that the erasure X has arrived, and the erasure error bit detection flag flg-
ebit is set to 1. Otherwise, the input data is determined to be 1 or 0, and the erasure error detection flag flg-ebit
Is set to 0.

By the above processing, the Viterbi detector 24 in FIG. 1 outputs the Viterbi decoding result and the erasure error bit detection flag to the recording decoder 25. In the record decoder 25,
The Viterbi decoding result and the erasure error bit detection flag are input, and recording and decoding processing is performed. Here, processing is performed in byte units. Therefore, the erasure error bit detection flag is 1
In the case of, it is known that there is an error in the byte after decoding, and the erasure error byte detection flag flg-
ebyte = 1, and outputs the result to the error correction decoder 26. When the erasure error bit detection flag is 0, it is determined that there is no erasure error in the byte after recording and decoding, and the erasure error byte detection flag flg-ebyte = 0 together with the decoding result.
Is output to the error correction decoder 26.

The error correction decoder 26 inputs the recording / decoding result and the erasure error byte detection flag, and performs erasure error correction. Assuming that the minimum Hamming distance of the code is d (bytes), random error correction can correct errors up to r = t (bytes). Here, it is assumed that t satisfies the relationship d = 2t + 1. On the other hand, if erasure error correction is applied to a code having the above Hamming distance, erasure errors up to e = d-1 = 2t (bytes) can be restored. This means that if the erasure error can be detected accurately, it has a correction capability about twice that of the random error correction.

Thus, according to the present embodiment, it is possible to improve the decoding error characteristic as the reproduction process by detecting the decoding error at the time of the maximum likelihood sequence estimation and correcting the erasure error byte derived therefrom.

FIG. 6 shows the configuration of a Viterbi detector showing a second embodiment according to the first method of the present invention. Except for the Viterbi detector, the system configuration (FIG. 1) is the same as that of the first embodiment.
Therefore, here, the configuration of the Viterbi detector will be described.

In the figure, the configuration of the branch metric calculation circuit 41 is the same as that of the first embodiment, and the obtained branch metrics BM (2), BM (1), BM
(0), BM (-1), BM (-2) are input to the ACS circuit 2 or 3 (62). ACS circuits 2 and 3
Is characterized by outputting the best sequence obtained by the maximum likelihood sequence estimation and the second optimal second sequence after the best sequence in the likelihood at the same time. In this embodiment, the configuration of the ACS circuit 2 shown in FIG. 12 is used. Before describing this, the principle of the 2nd sequence output method in this embodiment will be described with reference to FIGS. 23 and 24. In this embodiment, the systematic search method (FIG. 23A)
And apply this. Threshold judgment method (Fig. 2
3 (b)) will be described in the next embodiment. In the systematic search method, in the ACS operation, a state likelihood storage register and a path memory for 2nd sequence search are provided for each state,
The sorting process selects and stores the minimum value, the second smallest likelihood, and the corresponding path. b
When the path memories for the est sequence and the 2nd sequence completely match, the path memory corresponding to the third smallest likelihood is stored as a 2nd sequence in order to avoid a perfect match between the best sequence and the 2nd sequence. As shown in FIG. 23 (a), the basic operation of the sorting process is, for example, as an ACS operation process in state S0, {S0 + BM
(0), S0 '+ BM (0), S4 + BM (-1),
S4 '+ BM (-1)} is rearranged in ascending order,
Among them, the surviving path corresponding to the minimum value and the next smallest value are selected. Here, Si, Si ′ (i
= 0,..., 7) are the best sequence, 2nd
This is the state likelihood obtained corresponding to the sequence. By this processing, in addition to the best sequence in the ACS calculation, the second sequence estimated to have the next highest probability can be simultaneously obtained. Similar processing is performed for the other states S1,..., S7.

FIG. 24 shows an example of estimation of the best sequence and the second sequence. For simplicity, it is assumed that all 0 data sequences have been transmitted as the best sequence, and the path memory length is 10 bits. At this time, 000000000 and 001 are stored in the path memories for the best sequence and the second sequence, respectively.
1,000,000 is stored. From time (n-7) to (n-4), if a decoding error occurs due to noise or the like, the relationship between the best sequence and the 2nd sequence is reversed. In the conventional configuration, since only the best sequence is the maximum likelihood decoded output, a decoding error occurs at this point. On the other hand, the present invention has a 2nd sequence in which a correct decoding result is stored, and if either the best sequence or the 2nd sequence is output, a correct decoding result can be obtained. As described above, by performing decoding using the 2nd sequence together, it is possible to eliminate an error event of MSED = 4 in EPR4ML, and it is possible to equivalently expand MSED to 6. This means that the S / N gain of EPR4ML is improved by 1.8 dB.

The above is the bes by the systematic search method of the present invention.
This is a basic concept of an ACS operation using t and 2nd sequences. FIG. 12 shows an ACS circuit 2 (62) for realizing the above processing.
It is a structure of. The figure applies an organized search method. That is, in each state, the branch metric BM
(2), BM (1), BM (0), BM (-1), BM
(−2) and the state likelihood S0,.
State likelihood S0 ',... For S7 and 2nd sequence
S7 'is added to the adder 1 based on the state transition diagram (FIG. 24).
00, the sorting circuit 120 adds the minimum likelihood (best), the second (2nd), and the third (3r
d) has a small likelihood and the corresponding survivor path information (C
0-1, C0-2, C0-3),..., (C7-1,
C7-2, C7-3) are output. Here, the third one is also output, as described above, in order to avoid a perfect match between the best sequence and the second sequence. That is, bes in the path memory circuit 63
If the comparison results of the path memories corresponding to the t sequence and the 2nd sequence are the same, 1 is output to the control signals p0,..., p7, and the likelihood for the 3rd sequence is selected by the selector. '(I = 0,..., 7). The state likelihood Si ′ of the best and the 2nd sequence obtained in this way is the corresponding delay element 102
And ready for the next ACS. In the figure, to avoid complexity, signal lines indicated by thick arrows are S0,.
It is assumed that S7 and S0 ',..., S7' are respectively connected in a feedback manner (from the output of the delay element 102 to the input of the adder 100). On the other hand, the best, 2n
Surviving path information Ci-1, C for d, 3rd sequence
i−2 and Ci−3 (i = 0,..., 7) are input to the path memory circuit 63. Here, the surviving path information Ci-1, Ci-2, Ci-3 is represented by 2 bits.

FIG. 21 shows a conceptual diagram of the configuration of the path memory circuit 63. In the figure, selectors 0,..., Selector 7 (210) respectively store path memory registers 200 ((reg0.1, reg0.1) in states S0,.
g0.2, reg0.3, reg0.4), ...,
(Reg 7.1, reg 7.2, reg 7.3, reg
This is a circuit for selecting one for best, 2nd, and 3rd from 7.4)). Here, the path memory register 200 (regi.1, regi.2, regi.3,
regi. 4) (i = 0,..., 7) is a path memory length of a path data history (for example, R0, R0 ', R4, R4' in state S0) leading to each state Si and Si '. Minutes are memorized. The path memory registers corresponding to the best, 2nd, and 3rd series are selected by the selector circuit 210 based on the surviving path information Ci-1, Ci-2, and Ci-3.
i-1, ri-2, ri-3 (202).
The register 202 is also a shift register, and the best, 2nd, 3r
Data Di-1, Di-2, Di-3 for the d series are serially input. In the state S0, of the data D0-1 ', D0-2', and D0-3 'shifted out, D0-1' is the result of decoding the best sequence. D0-2 'and D0-3' are 2nd and 3 respectively.
The signal is input to the selector 213 as an rd decoded output. If the path memory length is made sufficiently long, the serial output is the same in any state (the paths after traceback are merged). Therefore, here, the decoding result of the best, 2nd, and 3rd series is obtained using the serial output in the state S0.

The registers ri-1 and ri-2 (20
In 2), the comparison circuit 211 checks whether the contents match, and if they match, sends the control signal pi = 1, otherwise, sets pi = 0 to the selector 121 in the ACS circuit 2 (62). I do. When pi = 1, the ri-2 output input to the selector 213 and D0-2 ′, r
Of the i-3 output and D0-3 ', the ri-3 output and D
0-3 'is selected, and when pi = 0, the ri-2 output and D0-2' are selected. D0-2 ′ or D0-
The selection result of 3 ′ is the final decoding result for the 2nd sequence.

In this way, the best sequence and the 2nd
The path memory register for the series is selected, and the registers ri-best and ri-
2nd (212). These are connected back to the corresponding signal lines, respectively, and are stored in the corresponding path memory registers 200 as updated path memories.

Although the path memory register 200 is shown in FIG. 1 to facilitate understanding of the operation concept, the path memory register 2 is used in an actual circuit configuration.
Without using 00, the registers ri-best and ri-2
nd (212) using only the selector i (210)
The above operation can be realized by connecting to.

With the above processing, the Viterbi detector in FIG.
The data for the sequence is decoded, and the result is output to the erasure error detection circuit 2 (64). FIG. 9 shows erasure error detection circuit 2
The structure of (64) is shown. The best and 2nd series are S /
P (Serial to Parallel) converter 91
Is converted into 1-byte parallel data, and then input to the exclusive OR circuit 92. Here, an exclusive OR is calculated for each bit in the parallel data. The processing result is compared with all zero byte data by the comparing circuit 93. If the byte data is different, it is determined that an erasure error has occurred, and the erasure error bit detection flag flg-ebi is determined.
Output to the recording and decoding decoder 25 (FIG. 1) as t = 1, otherwise, as flg-ebit = 0.

The recording / decoding unit 25 receives the Viterbi decoding result and the erasure error bit detection flag, and performs a recording / decoding process. Here, processing is performed in byte units. Therefore, when the erasure error bit detection flag is 1, it is known that there is an error in the byte after decoding, and the erasure error byte detection flag flg-ebyte = 1 is set together with the decoding result.
Output to the error correction decoder. When the erasure error bit detection flag is 0, it is determined that there is no erasure error in the byte after decoding, and the erasure error byte detection flag fl is added together with the decoding result.
The data is output to the error correction decoder 26 as g-ebyte = 0.

The error correction decoder 26 inputs the recording / decoding result and the erasure error byte detection flag, and performs erasure error correction. As described in the first embodiment, if the erasure error can be accurately detected, the correction ability is improved to about twice that of the random error correction.

Thus, according to the present embodiment, it is possible to improve decoding error characteristics as a reproduction process by detecting a decoding error at the time of maximum likelihood sequence estimation and correcting a lost error byte derived therefrom.

Next, a third embodiment according to the first method of the present invention will be described with reference to FIG. The basic concept of this embodiment is the same as that of the second embodiment.
This is a method that uses d series together. However, since the method of obtaining the second sequence is different from that of the second embodiment (threshold value determination method, FIG. 23B), the configurations of the ACS circuit 62 and the path memory circuit 63 are also different. The other configuration is the same as that of the second embodiment. Therefore, here, the 2nd sequence estimation method by the threshold value judgment method in the Viterbi detector will be described.

In this embodiment, as a method of obtaining the second sequence, a threshold value judging method is employed.
The principle and configuration will be described with reference to FIG. In FIG. 23 (b),
The principle of the 2nd sequence estimation method by the threshold value judgment method will be described. In this scheme, in ACS calculation, if the likelihood to be compared is smaller than a certain threshold, the best sequence is
The path memory selected by S and the 2nd sequence are output as the path memory not selected by ACS, and if the likelihood to be compared is not smaller than a certain threshold, both the best and 2nd sequences are ACS. And outputs the path memory selected by. That is, when the likelihood difference in the ACS is small, it is determined that the probability of occurrence of a decoding error is high, and the selected path is the best sequence as the first candidate, and the non-selected path is 2n as the second candidate.
It is determined to be d series. If the likelihood difference is sufficiently large, be
Without discriminating between the st and 2nd sequences, the sequences for which the maximum likelihood estimation is performed are both stored. For example, in the ACS in the state S0,
The likelihood to be compared is ｛α = S0 + BM (0), β = S4 +
BM (-1)}. If one of α and β is correct, the absolute value of the likelihood difference dM = α−β is theoretically 4 when there is no noise. However, in practice, d
M varies due to noise, and it becomes impossible to clearly distinguish α and β. Therefore, it is determined whether or not the reliability of the selection result by the ACS is high based on the magnitude of the likelihood difference dM, and the 2nd sequence is determined based on this. Assuming that the threshold value is DM, as shown in FIG. 213 (b), the likelihood difference d
The best and 2nd sequences are determined by the areas where the magnitude relationship between M and the threshold value DM is A, B, C, and D. Other states S
, S7.

FIG. 13 shows an ACS circuit 3 for realizing the above processing.
This is the configuration of (62). In the figure, the best, 2nd sequence is obtained by applying the threshold value judgment method. In the figure, processing up to addition and comparison is the same as in the conventional invention and the first embodiment. That is, the branch metric and the state likelihood for each state are added by the adder 100 according to the EPR4 state transition diagram (see FIG. 24), and the comparison circuit 1
At 11, the smaller likelihood is output and stored in the corresponding delay element 102. In the figure, signal lines indicated by thick arrows are S0,.
(From the output of the delay element 102 to the input of the adder 100). In the present embodiment, likelihood differences DM0,..., DM7 are output as outputs of the comparator 111 instead of surviving paths. The likelihood difference DMi (i = 0,..., 7) is calculated by a path determination circuit 7
Is input to Here, based on the principle described above, DM
Surviving path information (C0-1, C0-2) indicating the best sequence and the second sequence according to the value of i, (C7
-1, C7-2) to the path memory circuit. Here, the (Ci-1, Ci-2) (i = 0,...,
7) is represented by one bit of 0 or 1. FIG. 7 shows the configuration of the path determination circuit 7. In the figure, the likelihood difference DM
When i is input, the absolute value conversion circuit 71 takes its absolute value. At the same time, the DMi code bit is input to the path selection circuit 73. On the other hand, the absolute value is compared by a comparison circuit 72 with a threshold value DM in magnitude relation. The actual processing is to subtract the threshold value DM from the absolute value,
The sign bit is output to the path selection circuit 73. The path selection circuit 73 includes a sign bit of the DMi and a comparison circuit 7.
2, surviving path information Ci-1 and Ci-2 (i =
0,..., 7) to the path memory circuit 63. By the processing of the configuration shown in FIG. 7, the determination areas A, B, C, and D (see FIG. 23B) to which the likelihood difference DMi belongs are specified,
Surviving path information Ci-1 and Ci-2 for this can be determined.

On the other hand, in the path memory circuit 63, the best, 2
A Viterbi decoding result for the nd sequence is output. FIG. 22 is a conceptual diagram of the configuration of the path memory circuit 63. In the figure,
Selector (0.1, 0.2),... Selector (7.
1, 7.2) and (221) are states S0,.
.., The path memory register 200 ((reg0.1.1, re
g0.1.2), ..., (reg7.1.1, reg
7.1.2) and (reg 0.2.1, reg 0.2.
2),..., (Reg7.2.1, reg7.2.
2)), surviving path information (Ci-1, Ci-2)
This is a circuit for selecting a register corresponding to (i = 0,..., 7). Each of the path memory registers 200 has
Best data history R0,.
R7 and 2nd data histories R0 ',..., R7' are stored for the path memory length. Each of these is connected back to the indicated signal line. When the surviving path information (Ci-1, Ci-2) is input, the selector 221 selects the corresponding path memory register 200 by these, and registers (ri.1, ri.2) (2
02). On the other hand, the data selection circuit 2
22, the surviving path information (Ci-1, Ci-
According to 2), corresponding data is output. The registers (ri.1, ri.2) (202) are also shift registers, and serially input data (output of the data selection circuit 222) for the selected best path and second path. The shifted out data is the decoded output. If the path memory length is made sufficiently long, the serial output is the same in any state (the path after traceback is merged). Therefore, here, using the serial output in the state S0,
A Viterbi decoding result for the sequence and the second sequence is obtained.

Although the path memory register 200 is shown in the figure for easy understanding of the operation concept, in the actual circuit configuration, the path memory register 2 is used.
00 without using the register ri. 1 and ri. 2 (20
The above operation can be realized by directly connecting to the selector 221 using only 2).

With the above processing, the Viterbi detector in FIG.
Loss error detection circuit 2 (64)
Output to Subsequent processing is the same as in the second embodiment (FIG. 9). That is, the erasure error detection circuit 2 detects the erasure error bit by taking an exclusive OR of each bit of the best-converted best and 2nd sequence data, and detects the erasure error bit detection flag flg-ebit.
Is output to the recording / decoding device 25.

The recording / decoding unit 25 receives the Viterbi decoding result and the erasure error bit detection flag, and performs a recording / decoding process. Here, processing is performed in byte units. Therefore, when the erasure error bit detection flag is 1, it is known that there is an error in the byte after decoding, and the erasure error byte detection flag flg-ebyte = 1 is set together with the decoding result.
Output to the error correction decoder. When the erasure error bit detection flag is 0, it is determined that there is no erasure error in the byte after decoding, and the erasure error byte detection flag fl is added together with the decoding result.
The data is output to the error correction decoder 26 as g-ebyte = 0.

The error correction decoder 26 inputs the recording / decoding result and the erasure error byte detection flag, and performs erasure error correction. As described in the first and second embodiments, if the erasure error can be accurately detected, the correction capability is improved to about twice that of the random error correction.

Thus, according to the present embodiment, it is possible to improve the decoding error characteristic as the reproduction process by detecting the decoding error at the time of the maximum likelihood sequence estimation and correcting the erasure error byte derived therefrom.

Next, an embodiment according to the second method of the present invention will be described with reference to FIG. In the figure, (a) is an overall configuration diagram of the device, and (b) is a data configuration. FIG.
As shown in (a), in the second method, instead of the recording encoder 11 and the recording decoder 22 in the conventional invention (FIG. 2), an error correction encoder 1 (11) and an error correction decoder 1 ( 28) is provided. That is, the purpose of the second method of the present invention is to improve the decoding capability of the Viterbi detector by adding the error correction capability to the recording code.

In the drawing, on the recording side, the digital information A is subjected to error correction encoding by the error correction encoder 10 using Reed, Solomon code or the like as in the prior art. The error-encoded sequence is subjected to a second encoding in the error-correction encoder 1 (11). Here, a Hamming code, a parity check code, or the like can be applied to the second error correction code. The error correction encoder 1 forms an error correction code block 1 for each recording block in the data block shown in FIG. In the figure, a data block includes a synchronization signal, a recording block, and an error correction code block. The synchronization signal is an overhead for detecting the head of the data block. Since the overhead section is removed at the time of input to the device, the synchronization signal is not recorded as magnetic information. The recording block is where the information A is divided into a plurality of small blocks and stored, and is recorded as magnetic information together with the error correction block. An error correction code block is formed by the error correction encoder 10 for the information A. In the present invention, the second error correction coding is performed on the information A and the error correction code block for each recording block. Here, the error correction code block length in FIG. 3B is configured to be equal to a multiple of the recording block length.
Then, the error correction code block is also divided into recording block units, and the second error correction coding is performed. For this reason, the data block has a configuration in which the error correction code block 1 is inserted for each recording block, unlike the conventional case. The sequence encoded as described above is magnetically recorded on a recording medium 15 such as a magnetic disk through a precoder 12, an amplifier 13, and a recording head 14, as in the conventional invention.

On the reproducing side, the information recorded on the magnetic recording medium 15 is reproduced as an electric analog signal by the reproducing head 16 and the amplifier 17, and the variable gain amplifier 1
8. A digital signal sampled at an appropriate timing through an A / D converter 19 is input to a PR equalizer (here, EPR4 equalizer) 20. The EPR4 equalized sequence is subjected to maximum likelihood decoding by a Viterbi detector 27. The Viterbi detector 27 outputs the decoding result obtained by the maximum likelihood sequence estimation (in some cases, it is output together with the 2nd sequence) to the error correction decoder 1 (28). The error correction decoder 1 (28) performs second error correction decoding for each recording block using the Viterbi decoding result and the erasure error bit detection flag. Thereby, an error that cannot be corrected by Viterbi decoding is repaired. The restored sequence is further subjected to random byte error correction by Reed-Solomon decoding or the like by the error correction decoder 26, and then the restored information A 'is reproduced.

FIG. 14 shows a Viterbi detector 27 and an error correction decoder 1 (2) showing a first embodiment according to the second method of the present invention.
8). In the figure, the Viterbi detector 27 includes a branch metric calculation circuit 41 and an ACS circuit 1 (5
2) is composed of a path memory circuit 53,
Since the configuration is exactly the same as that described in the first embodiment (see FIGS. 5, 11, and 20) in the first method of the present invention, description thereof will be omitted. The Viterbi decoding result (1, 1,
0, X) is input to the error correction decoder 1 (28).
Here, the error correction decoder 1 (28) uses the erasure error correction circuit having the configuration shown in FIG. In this embodiment,
Viterbi decoding outputs are 1, 0 and 3 of erasure X (= 0.5)
The erasure error correction circuit in FIG. 17 performs erasure error correction processing using these values. That is, the Viterbi decoding result is converted from serial data into parallel data (the data length is equal to the sum of the recording block and the error correction code block 1 (FIG. 3B)) by the S / P converter 170, The erasure error is corrected by the correction decoding unit 171. The corrected result is a decoded output. On the other hand, when the erasure error correction decoding unit 171 cannot correct the error, the erasure error byte detection flag flg-ebyte = 1 is output to the error correction decoder 26 together with the decoding result. The error correction decoder 26 receives the decoding result and the erasure error byte detection flag and performs erasure error correction. As described in the embodiment according to the first method, if the erasure error can be accurately detected, the correction capability is improved to about twice that of the random error correction.

Therefore, according to the present embodiment, it is possible to improve the decoding error characteristic as the reproduction process by detecting the decoding error at the time of the maximum likelihood sequence estimation and correcting the erasure error byte derived therefrom.

FIG. 15 shows a second embodiment of the Viterbi detector 27 and the error correction decoder 1 (2) according to the second method of the present invention.
8). In the figure, a Viterbi detector 27 includes a branch metric calculation circuit 41, an ACS circuit 2 or 3
(62) and a path memory circuit (63), which are the structures described in the second and third embodiments in the first method of the present invention (see FIGS. 6, 12, 21, 13, and 22). )
Since it is exactly the same as above, its explanation is omitted. In this embodiment, the best sequence and the 2nd sequence are error-corrected by the Viterbi detector by the method (organized search method or threshold value determination method) described in the second and third embodiments of the first method. 1 (28). Here, the error correction decoder 1 (28) uses a decoding error detection circuit having the configuration shown in FIG. In the figure, the best and 2nd sequences are each converted into parallel data (the data length is equal to the sum of the recording block and the error correction code block 1 (FIG. 3B)) by the S / P converter 170, and error detection is performed. Circuit 180
In, processing is performed in block units. In the error detection circuit 180, error detection such as parity check is performed simultaneously and independently for each of the best and 2nd sequences. The error detection circuit 180 calculates best and 2
The syndromes S1 and S2 for each of the nd sequences are calculated, and output to the selector 181 together with the best and 2nd sequences. The selector 181 is connected to the S
The sequence in which 1 and S2 are 0 is determined as a correct decoding result, and this is selectively output. At the same time, the erasure error byte detection flag flg-ebyte is output as 0. S1, S2
If both are 0, either best or 2nd may be output. At this time, the erasure error byte detection flag flg-e
Byte is 0. If both S1 and S2 are 1, it means that an error has occurred in both streams,
The erasure error byte detection flag flg-ebyte becomes 1. The sequence selected by the selector 181 is sent to the error correction decoder 26 together with flg-ebyte as a decoding result. The error correction decoder 26 receives the decoding result and the erasure error byte detection flag and performs erasure error correction. As described in the above embodiment, if the erasure error can be accurately detected, the correction ability is improved to about twice that of the random error correction.

Therefore, according to the present embodiment, it is possible to improve the decoding error characteristic as the reproduction process by detecting the decoding error at the time of the maximum likelihood sequence estimation and correcting the erasure error byte derived therefrom.

FIG. 16 shows a Viterbi detector 27 and an error correction decoder 1 (2) showing a third embodiment according to the second method of the present invention.
8). In the figure, a Viterbi detector 27 includes a branch metric calculation circuit 41, an ACS circuit 2 or 3
(62) It is composed of a path memory circuit 63. These are the same as those described in the second and third embodiments in the first method of the present invention (see FIGS. 6, 12, 21, 13, and 22). Since they are exactly the same, their explanation is omitted. In the present embodiment, the second and third Viterbi detectors 27 in the first method are used.
The best sequence and the 2nd sequence are output to the error correction decoder 1 (28) by the method (systematic search method or threshold value determination method) described in the embodiment. Here, the error correction decoder 1
In (28), the erasure error correction circuit having the configuration shown in FIG. 19 is used. In the figure, the best and 2nd sequences are each converted into parallel data (data length is the sum of the recording block and the error correction code block 1 (FIG. 3) by the S / P converter 170.
(Equivalent to (b))), and processing is performed in block units. Bes converted to the parallel data
The exclusive OR circuit 190 takes an exclusive OR for each bit of the t, 2nd series. The result is output to erasure error correction decoding circuit 191 as an erasure error detection signal. If all bits of the erasure error detection signal are 0, it can be determined that no erasure error has occurred. If any bit of the erasure error detection signal is 1, it is considered that an erasure error has occurred at that bit position. The erasure error correction decoding circuit 191 receives the best sequence converted into the parallel data and the erasure error detection signal, and performs an erasure error correction decoding process. As a result, when the error is corrected, the erasure error byte detection flag flg-ebyte =
0, and if uncorrectable, outputs flg-ebyte = 1. The sequence subjected to the erasure error correction decoding by the above processing is sent to the error correction decoder 26 together with flg-ebyte as a decoding result. The error correction decoder 26 receives the decoding result and the erasure error byte detection flag and performs erasure error correction. As described in the above embodiment, if the erasure error can be accurately detected, the correction capability is about 2 times that of the random error correction.
Up to double.

Thus, according to the present embodiment, it is possible to improve decoding error characteristics as reproduction processing by detecting a decoding error at the time of maximum likelihood sequence estimation and correcting the erasure error byte derived therefrom.

As described above, according to the present invention, by providing a means for detecting a decoding error in Viterbi detection and correcting an erasure error byte derived therefrom, the decoding error characteristic of the reproduction processing can be improved with a simple configuration. And EPR
Characteristics exceeding 4 ML can be realized. Since no trellis code is used, EP without increasing the number of states
R4ML characteristics can be improved. Therefore, it is possible to provide a digital magnetic recording / reproducing apparatus which can perform high-density recording with a simple configuration as compared with the related art.

The present invention can be applied to any PR channel (PR4, EEPR4, etc.) other than the EPR4 channel. Also, generally, a signal processing method to which a maximum likelihood detection function based on a concept such as Viterbi decoding is applied, for example, DFE-F
DTS (DecisionFeedback Equa)
riser with Finite Delay Tre
e Search) method and the like.

[0066]

According to the present invention, a Viterbi detector is provided with a function of detecting an erasure error bit determined to have a high possibility of occurrence of a decoding error, thereby detecting a decoding error of maximum likelihood sequence estimation. By correcting the erasure error, the error correction capability of the Viterbi detector can be improved without increasing the number of channel states. Therefore, it is possible to improve the decoding error characteristic of the entire reproduction process, and to provide a digital magnetic recording / reproducing apparatus capable of performing higher-density recording than a conventional device with a simple configuration. The present invention is also applicable to any PR channel other than the EPR4 channel and DFE.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital magnetic recording / reproducing apparatus showing a first method of the present invention.

FIG. 2 is a configuration diagram of a digital magnetic recording / reproducing apparatus according to a conventional invention.

FIG. 3 is a configuration diagram of a digital magnetic recording / reproducing apparatus showing a second method of the present invention.

FIG. 4 is a configuration diagram of a Viterbi detector according to the related art.

FIG. 5 is a configuration diagram of a Viterbi detector in the first embodiment according to the first method of the present invention.

FIG. 6 is a configuration diagram of a Viterbi detector in the second and third embodiments according to the first method of the present invention.

FIG. 7 is a configuration diagram of a path determination circuit used in a Viterbi detector in a third embodiment according to the first method of the present invention.

FIG. 8 is a configuration diagram of an erasure error detection circuit in the first embodiment according to the first method of the present invention.

FIG. 9 is a configuration diagram of an erasure error detection circuit in the second and third embodiments according to the first method of the present invention.

FIG. 10 is a configuration diagram of an ACS circuit according to a conventional invention.

FIG. 11 is a configuration diagram of an ACS circuit in the first embodiment according to the first and second methods of the present invention.

FIG. 12 is a configuration diagram of an ACS circuit in a second embodiment according to the first and second methods of the present invention.

FIG. 13 is a configuration diagram of an ACS circuit in a third embodiment according to the first and second methods of the present invention.

FIG. 14 is a configuration diagram of a Viterbi detector in a first embodiment according to the second method of the present invention.

FIG. 15 is a configuration diagram of a Viterbi detector in a second embodiment according to the second method of the present invention.

FIG. 16 is a configuration diagram of a Viterbi detector in a third embodiment according to the second method of the present invention.

FIG. 17 is a configuration diagram of an error correction decoder in the first embodiment according to the second method of the present invention.

FIG. 18 is a configuration diagram of an error correction decoder in a second embodiment according to the second method of the present invention.

FIG. 19 is a configuration diagram of an error correction decoder in a third embodiment according to the second method of the present invention.

FIG. 20 is a configuration diagram of a path memory circuit in the first embodiment according to the first and second methods of the present invention.

FIG. 21 is a configuration diagram of a path memory circuit in a second embodiment according to the first and second methods of the present invention.

FIG. 22 is a configuration diagram of a path memory circuit in a third embodiment according to the first and second methods of the present invention.

FIG. 23 is a principle diagram showing a search method for a best sequence and a 2nd sequence by the Viterbi detector of the present invention.

FIG. 24 shows an EPR according to the 2nd sequence search method of the present invention.
FIG. 10 is a diagram for describing a decoding error rescue effect in 4ML.

[Explanation of symbols]

10: error correction encoder, 11: recording encoder, 1
2 ... Precoder, 13, 17 ... Amplifier, 14.
..Recording head, 15 ... magnetic recording medium, 16 ...
Reproduction head, 18: variable gain amplifier, 19: A
/ D converter, 20... PR equalization circuit, 21, 24, 2
7: Viterbi detector, 22, 25: recording / decoding device,
23, 26, 28 ... error correction decoder, 41 ... branch metric calculation circuit, 42, 52, 62 ... A
CS circuit, 43, 53, 63 ... path memory circuit, 5
4, 64: Erasure error detection circuit, 7: Path determination circuit, 71: Absolute value conversion circuit, 72, 93, 10
1, 111, 211 ... comparison circuit, 73 ... path selection circuit, 81, 112 ... threshold value judgment circuit, 91,
170: S / P conversion circuit, 92, 190: exclusive OR circuit, 100: adder, 102: delay element, 103, 113, 214, 222: data selection circuit 120: sorting circuit, 121, 18
1,191,201,210,213,221 ... selector circuit, 171,191 ... erasure error correction circuit,
180... Decoding error detection circuit, 200, 202, 21
2. Register circuit.

Claims (16)

[Claims] 1. Digital information is encoded by an error correction encoding means,
Means for recording on a recording medium by a recording encoding means, means for outputting a reproduction signal from the recording medium, means for performing maximum likelihood sequence estimation by partial response equalization and Viterbi detection from the reproduction signal, and recording and decoding means, In a magnetic recording / reproducing circuit comprising a means for restoring digital information by an error correction decoding means, an ACS (Add, Comp) in the Viterbi detection means is detected by the Viterbi detection.
(are, Select) operation means for detecting the erasure error bit of the maximum likelihood decoded data by providing means for obtaining the 2nd sequence together with the best sequence, and performing erasure error correction using this. Digital magnetic recording and reproducing circuit. 2. A maximum likelihood decoded data and an erasure error bit detection signal are output from Viterbi detection, and the recording / decoding means outputs an erasure byte error detection signal from the erasure error bit detection signal together with the recording and decoding data. 2. The digital magnetic recording / reproducing circuit according to claim 1, wherein the error correction decoding means performs erasure error correction using the erasure error byte detection signal. 3. The erasure error bit of data which has been subjected to maximum likelihood decoding by Viterbi detection, wherein the recording encoding means and the recording / decoding means are replaced by second error correction encoding means and second error correction decoding means, respectively. 2. The digital magnetic recording / reproducing circuit according to claim 1, wherein the second error correction decoding means performs erasure error correction by using the detection result. 4. A Viterbi detecting means for obtaining a second sequence (a sequence that is most likely next to the best sequence) together with a best sequence (a sequence subjected to maximum likelihood estimation),
means for detecting an erasure error by taking the exclusive OR of the st and 2nd sequences and outputting an erasure error bit detection flag, and recording and decoding the data traced back from the path memory and the erasure error bit detection flag 3. The digital magnetic recording / reproducing circuit according to claim 2, wherein the digital magnetic recording / reproducing circuit outputs the signal to a recording device. 5. An ACS calculating means in the Viterbi detecting means calculates a likelihood difference to be compared, compares the likelihood difference with a threshold value, and obtains a second sequence together with a best sequence according to the magnitude relation. 3. The digital magnetic recording / reproducing circuit according to claim 2, wherein: 6. The ACS operation means in the Viterbi detection means includes means for obtaining a second sequence together with the best sequence, and decoding error detection means as second error correction decoding means. 3. The digital magnetic recording / reproducing circuit according to 3. 7. The ACS operation means in the Viterbi detection means includes means for obtaining a second sequence together with a best sequence, and means and a decoding error detection means as second error correction decoding means are provided. 7. The de-digital magnetic recording / reproducing circuit according to claim 6, wherein: 8. The ACS operation means in the Viterbi detection means, wherein means for obtaining the second sequence together with the best sequence is provided, and decoding error detection means is provided as second error correction decoding means. A digital magnetic recording / reproducing circuit according to claim 6. 9. The digital information is encoded by error correction coding means,
Means for recording on a recording medium by a recording encoding means, means for outputting a reproduction signal from the recording medium, means for performing maximum likelihood sequence estimation by partial response equalization and Viterbi detection from the reproduction signal, and recording and decoding means, In a magnetic recording / reproducing apparatus comprising a means for restoring digital information by an error correction decoding means, an ACS (Add, Comp) in the Viterbi detection means is detected by the Viterbi detection.
(are, Select) calculating means, a means for obtaining the second sequence together with the best sequence is provided to detect the erasure error bit of the maximum likelihood decoded data, and a circuit for performing erasure error correction using the detected error bit is provided. Digital magnetic recording / reproducing apparatus characterized by the following. 10. A maximum likelihood decoded data and an erasure error bit detection signal are output from Viterbi detection, and the recording / decoding means outputs an erasure byte error detection signal from the erasure error bit detection signal.
10. The digital magnetic recording / reproducing apparatus according to claim 9, wherein the error correction decoding means outputs a signal together with the recording / decoding data, and the error correction decoding means has a circuit for performing erasure error correction using the erasure error byte detection signal. 11. A recording encoding means and a recording / decoding means,
Each is replaced by a second error correction encoding unit and a second error correction decoding unit, and the erasure error bit of the data that has been subjected to maximum likelihood decoding by Viterbi detection is detected.
10. The digital magnetic recording / reproducing circuit according to claim 9, further comprising a circuit for performing erasure error correction by said second error correction decoding means. 12. Viterbi detecting means for obtaining a 2nd sequence (the most likely sequence next to the best sequence) together with a best sequence (a sequence subjected to maximum likelihood estimation);
means for detecting an erasure error by taking the exclusive OR of the est and the 2nd sequence and outputting an erasure error bit detection flag, and recording and decoding the data traced back from the path memory and the erasure error bit detection flag 11. The digital magnetic recording / reproducing apparatus according to claim 10, further comprising a circuit for outputting to the recorder. 13. An ACS calculating means of the Viterbi detecting means calculates a likelihood difference to be compared, compares the likelihood difference with a threshold value, and obtains a best sequence and a second sequence based on the magnitude relation. The digital magnetic recording / reproducing apparatus according to claim 10, further comprising a circuit. 14. A circuit provided with means for obtaining the second sequence together with the best sequence in the ACS operation means of the Viterbi detection means, and a circuit provided with decoding error detection means as second error correction decoding means. Claim 11
A digital magnetic recording / reproducing apparatus according to claim 1. 15. An ACS operation means in a Viterbi detection means, comprising means for obtaining a second sequence together with a best sequence, and a circuit having a decoding error detection means as a second error correction decoding means. 15. The de-digital magnetic recording / reproducing apparatus according to claim 14, wherein: 16. A circuit provided with means for obtaining a second sequence together with a best sequence in ACS calculation means in Viterbi detection means, and a circuit provided with decoding error detection means as second error correction decoding means. Claim 14
A digital magnetic recording / reproducing apparatus according to claim 1.