JP3759525B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and relates to a wiring formation method in a blanket-tungsten CVD method in connection holes of via holes and contact holes.

  As a technique for embedding fine contact holes and via holes, formation of a blanket-tungsten (W) CVD method plug having good coverage and low resistance has been put into practical use. This blanket-tungsten (W) CVD method is a method of forming a W plug by filling a tungsten (W) layer 102 in a via hole and a contact hole in an interlayer insulating layer 101 as shown in FIG.

  However, as shown in FIG. 4, before the W layer 102 is completely filled in the hole, there is a problem that the void 103 is formed in the W layer 102 inside the hole by closing the hole opening end first. It was. This is due to the influence of the overhang shape of the adhesion layer 104 formed in the hole opening before filling the W layer 102, and the swelling inside the hole generated when the hole opening is formed in the interlayer insulating layer 101 by dry etching. In addition, since the supply amount of the deposition reaction gas entering from the hole opening portion is different between the hole opening portion and the bottom portion, the growth rate of the W layer 102 depends on the supply amount. Therefore, it is considered that the vicinity of the hole opening is closed first, and as a result, the void 103 is generated inside the hole.

  This void 103 is formed when a blanket-W layer is formed and a unnecessary portion of the W layer is polished and removed by CMP to form a plug leaving the W layer 102 only inside the hole. If it is large, it will be exposed on the plug surface. The exposure of the void 103 tends to include foreign matter inside the plug, and when a new film is formed on the W plug and the temperature rises, not only does it cause a contact failure, but also moisture adhering to the inner surface of the void 103 It causes film bulging or film peeling that occurs by evaporation at once. In view of this, the manufacturing method shown in FIG. 5 has been considered (for example, see Patent Document 1).

  As shown in FIG. 5A, after a first adhesion layer (TiN film) 106 is formed on the entire surface of the interlayer insulating layer 105 formed on the Si substrate 111, a photoresist film 107 is formed on the entire surface thereof. Then, an opening 109 is formed in the photoresist film 107, and a hole forming mask for the interlayer insulating layer 105 is formed. Next, the first adhesion layer 106 is selectively etched by isotropic etching, whereby the edge of the opening 108 formed in the first adhesion layer 106 is recessed outward from the opening edge of the photoresist film 107. Yes. Next, a hole opening 110 is formed in the interlayer insulating layer 105 by anisotropic etching.

  Next, as shown in FIG. 5B, with the photoresist film 107 attached, the Ti film 112 as a contact metal with the Si substrate 111 in the diffusion layer region, and the reaction between tungsten (W) and the Si substrate 111. A TiN film 113 is formed by sputtering as a barrier metal that suppresses the above.

  Next, as shown in FIG. 5C, the photoresist film 107 and the Ti film 112 and the TiN film 113 on the photoresist film 107 are removed. Thereafter, although not shown, after depositing a tungsten (W) layer by blanket-CVD and filling the hole opening 110, unnecessary portions of the W layer and the first adhesion layer 106 are removed to remove W. A plug is formed.

According to the above wiring formation method, since the opening diameter of the first adhesion layer 106 recedes outward from the hole opening diameter formed in the interlayer insulating layer 105, the W layer grows near the hole opening end. Since there is no TiN film (first adhesion layer 106) serving as a nucleus, the growth of the W layer is suppressed near the hole opening end, and the W layer grows uniformly from the bottom of the contact hole to the entire hole. Generation of voids in the W layer can be suppressed, and the Ti film 112 and TiN film 113 deposited as a barrier metal with the photoresist film 107 still attached. Since the Ti film 112 and the TiN film 113 are formed to be overhanged in the vicinity of the opening of the photoresist film 107, after the photoresist film 107 is removed, In the vicinity of the hole opening edge of the inter-layer insulating layer 105, the opening edge of the first adhesion layer 106 recedes outward, and there is no overhanging shape of the TiN film that becomes the nucleus when the W layer is grown. This means that the influence on the void generation in the W layer due to the hang can be suppressed.
JP-A-8-172058

  However, when the hole diameter is further miniaturized and the film thickness of the interlayer insulating layer is increased and the aspect ratio is increased, the above-described wiring formation technique removes the TiN film at the hole opening edge portion and opens the opening edge portion. If the growth rate of the W layer on the (interlayer insulating layer surface) is suppressed, the effect does not occur. This is because, in the coverage property of the W film in the blanket-CVD method, if the aspect ratio increases inside the hole, a difference in the coverage property between the side wall portion near the hole opening end and the bottom portion is significantly generated. As a result, only by removing the TiN film near the hole opening edge, the TiN film exists on the entire surface of the hole side wall, so that the growth of the W layer near the hole opening end advances earlier than the hole bottom as described above. As a result, the hole opening end is closed before the W layer is sufficiently filled in the hole, and voids are generated in the W layer.

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the reliability by suppressing generation of voids in a W layer filled in a hole even when the hole diameter is further miniaturized. Yes.

According to the method for manufacturing a semiconductor device of the present invention, a step of forming an interlayer insulating layer on a semiconductor substrate having a lower conductor layer formed on or above the substrate surface, and opening the lower conductor layer in the interlayer insulating layer Forming a hole opening, forming a first adhesion layer on the interlayer insulating layer and on the sidewall and bottom of the hole opening, and on the first adhesion layer on the sidewall of the upper portion of the hole opening. A step of forming the second adhesion layer only, and a step of filling the hole opening with the tungsten layer by forming a tungsten layer by blanket CVD after forming the second adhesion layer, The tungsten layer formed so that the growth rate of the tungsten layer formed on the adhesion layer is slower than the growth rate of the tungsten layer formed on the first adhesion layer, or on the second adhesion layer of Forming the first adhesion layer and the second adhesion layer so that the incubation time until the long start is longer than the incubation time until the start of growth of the tungsten layer formed on the first adhesion layer; It is characterized by.

  According to this manufacturing method, when the W layer is formed, the first and second adhesion layers having different growth characteristics of the W layer are formed on the exposed surface in the hole opening portion above and below the hole opening portion. The growth process of the W layer at the upper part of the opening is slower than the lower part of the hole opening, and the opening end of the hole opening is blocked early, and voids are generated in the W layer inside the hole opening. Can be suppressed.

  In the manufacturing method of the semiconductor device described above, the first adhesion layer deposited in the vicinity of the opening end in the hole opening after the first adhesion layer is formed in the hole opening and before the second adhesion layer is formed. It is preferable to remove the deposited film thickness of the second adhesion layer by dry etching.

  Thereby, the overhang at the time of forming the second adhesion layer can be suppressed, and the generation of voids at the time of forming the W layer can be further suppressed.

In the semiconductor device manufacturing method, the first adhesion layer is a TiN film formed by a thermal CVD method using a TiCl ₄ and NH ₃ source, and the second adhesion layer is an MOCVD using an organic source of TDMAT. A TiN film formed by the method is preferred.

This makes it easy to place the first and second adhesion layers above and below the hole opening by utilizing the fact that the MOCVD-TiN film has poor coverage compared to the TiCl ₄ -TiN film having excellent coverage. Since the incubation time until the start of the growth of the W film on the MOCVD-TiN film is longer than that on the TiCl ₄ -TiN film, the growth in the hole opening of the W layer is selectively performed. It can be carried out.

  In the semiconductor device manufacturing method described above, it is preferable that after the first adhesion layer is formed, the semiconductor substrate is continuously released to the atmosphere until the second adhesion layer is formed.

  Thereby, the influence on the throughput can be suppressed.

  As described above, according to the present invention, W nucleus growth formation in the blanket-tungsten CVD method is performed by forming the first and second adhesion layers having different W layer growth properties in the hole opening portion above and below the hole opening portion. When the coverage of the film is improved, the generation of voids in the W plug is suppressed, and unnecessary W layers are removed by subsequent CMP to leave the W layer only in the hole openings, voids are formed on the surface of the W plug. The generation of the opening hole can be suppressed and the reliability can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a process cross-sectional view illustrating a contact plug wiring forming process according to an embodiment of the present invention.

  As shown in FIG. 1A, a silicon oxide film such as BPSG is formed on the entire surface of the semiconductor substrate 2 on which the lower conductor layer 1 composed of the impurity diffusion region on the surface is formed by the plasma CVD method, and then by the CMP method. Planarization is performed to form an interlayer insulating layer 3 having a thickness of 1.5 μm. Subsequently, a photoresist pattern (not shown) having an opening for forming a contact hole is formed on the interlayer insulating layer 3 by a lithography process, and the interlayer insulating layer 3 is dry-etched using the photoresist pattern as a mask. A hole opening 4 (hole opening diameter: about 0.2 μm) for communicating an upper layer wiring (not shown) and the lower conductor layer 1 is formed at a predetermined position of the layer 3, and the photoresist pattern is removed. .

Next, as shown in FIG. 1B, after forming the hole opening 4 and removing the photoresist pattern, interdiffusion between the W layer to be filled in the hole opening 4 and Si is prevented, For the purpose of obtaining contact resistance with the lower conductor layer 1, the Ti film 5 is deposited in the hole opening 4 under the condition that the film thickness is 25 nm on the surface of the interlayer insulating layer 3 by argon sputtering. At this time, the Ti film 5 is deposited on the side wall of the hole opening 4 on the order of several nanometers, and the coverage at the bottom of the hole opening 4 is influenced by the characteristics of the flying direction of the target molecules and the probability of the number of flying. Since the hole depth is 1.5 μm from the characteristics of the property, the deposition is about 2 to 4 nm. Subsequently, a TiN film having a thickness of 10 nm is deposited on the Ti film 5 by a thermal CVD method using TiCl ₄ and NH ₃ as sources as a first adhesion layer 6 for achieving adhesion with the W layer. Here, the TiN ₄ source TiN film is excellent in coverage, and even in the experiment, the bottom coverage of TiCl ₄ -TiN with respect to a contact hole having a hole diameter of 0.2 μm in an interlayer insulating layer having a thickness of 1.6 μm is demonstrated. As a result of the confirmation, the film thickness at the bottom of the hole has a coverage of 95% or more with respect to the film thickness at the end of the hole opening.

Next, as shown in FIG. 1C, the TiN film of the TiCl ₄ source, which is the first adhesion layer 6 of the edge portion 8 at the hole opening end, is etched back by Ar sputtering to be deposited next. About the thickness of the second adhesion layer 7 deposited is removed.

Next, as shown in FIG. 1D, a TiN film is formed as the second adhesion layer 7 by MOCVD using TDMAT as an organic source, and the film thickness is 2 to 5 nm on the surface of the first adhesion layer 6. The film is formed by setting the time so as to deposit. The film formation conditions at this time are pressure: 1.5 × 133 Pa (1.5 Torr), heater temperature: 450 ° C., and carrier gas flow rate: 225 sccm. The coverage of the TiN film formed by the MOCVD method is not as good as that of the TiN film of the TiCl ₄ source (first adhesion layer 6).

  Here, FIG. 2 shows the hole diameter when the bottom coverage property of the TiN film by the MOCVD method is confirmed for the contact hole having the hole diameter of 0.15 to 0.35 μm in the 0.6 μm-thick interlayer insulating layer. It is the graph which plotted the correlation. As is clear from this graph, the bottom coverage property decreases linearly as the hole diameter decreases. This is because the flow rate of the reaction gas from the opening to the inside of the hole decreases in proportion to the opening area, and the film thickness at the opening end is reaction-controlled against the difference in hole diameter. However, it is considered that the deposition rate at the bottom of the hole decreases in proportion to the amount of supply from the opening in the depth direction of the hole. Similarly, the coverage is further reduced as the hole depth increases. This is because the amount of reaction gas supplied to the bottom of the hole further decreases as the depth of the hole increases, so that the film thickness at the bottom of the hole decreases as in the proportional relationship between the hole diameter and the coverage described above. It is thought to do.

  In an experiment in which a TiN film of 7 nm was deposited on the surface of an interlayer insulating layer by a MOCVD method in a contact hole having a hole diameter of 0.2 μm on an interlayer insulating layer having a thickness of 1.5 μm, the TiN film was 1.0 to Only the depth of 1.4 μm is deposited on the side wall of the hole. From this result, if the time is set so that the TiN film by MOCVD is deposited on the surface of the interlayer insulating film by 2 to 5 nm, It becomes possible to deposit a TiN film only on the side wall of the hole up to a depth of about ½ with respect to the depth direction. As a result, as shown in FIG. However, it is possible to form adhesive layers having different characteristics in the upper and lower sides where the first adhesive layer 6 and the upper half of the hole opening 4 become the second adhesive layer 7.

Here, as shown in FIG. 1C, after a TiN ₄ source TiN film as the first adhesion layer 6 is deposited, the TiN film (TiCl ₄ source) at the edge 8 at the hole opening end is formed by Ar sputtering. Is etched back to remove the film thickness of the second adhesion layer 7 of 3 to 5 nm, even if the TiN film (by the MOCVD method) of the second adhesion layer 7 is deposited. Since the hole opening end is cut by the back, the overhang shape of the hole opening 4 by the first and second adhesion layers (6, 7) can be suppressed, and further, void formation can be suppressed. is there. In these adhesion layer forming apparatuses, if the first adhesion layer 6 formation chamber to the second adhesion layer 7 formation chamber are connected to the transfer chamber of the semiconductor substrate 2 in the semiconductor manufacturing apparatus, the first Since the process up to the formation of the second adhesion layer 7 can be continuously performed after the formation of the first adhesion layer 6 without releasing the semiconductor substrate 2 to the atmosphere, the processing time of the semiconductor device can be greatly increased. Therefore, it is possible to suppress the influence on the throughput while improving the reliability.

Next, as shown in FIG. 1E, after the second adhesion layer 7 is formed, a tungsten (W) layer 9 is filled into the hole opening 4 by a blanket-CVD method. In the formation of the W layer 9, a nucleation growth forming film is initially formed with a thickness of about 20 nm. The film forming conditions in this case are as follows: pressure: 30 × 133 Pa (30 Torr), heater temperature: 450 ° C., and reactive gas flow rates of 42 sccm for WF ₆ , 5 sccm for SiH ₄ , and 500 sccm for H ₂ . Thereafter, the pressure is 90 × 133 Pa (90 Torr), the heater temperature is 450 ° C., the reaction gas flow rate is 120 sccm for WF ₆ , and 500 sccm for H ₂ to deposit on the surface of the nucleation growth film by about 180 nm. Fill the space. Here, in an experiment in which a W layer was filled under the above-described conditions into a contact hole in which a hole diameter of 0.2 μm was deposited on a 1.5 μm thick interlayer insulating layer and a TiN ₄ source TiN film of 10 nm was deposited on an adhesion layer, W layer growth by ₆ + H ₂ gas reduction has a coverage of about 90% or more, but a W nucleus growth film by WF ₆ + SiH ₄ gas reduction has a coverage of about 60 to 80%.

  Thereafter, as shown in FIG. 1 (f), unnecessary portions of the W layer 9, the second adhesion layer 7, the first adhesion layer 6 and the Ti film 5 are removed by the CMP method to thereby form the inside of the hole opening 4. Only the W layer 9, the second adhesion layer 7, the first adhesion layer 6, and the Ti film 5 are left to form a W plug.

According to the above-described manufacturing method, if a TiN ₄ source TiN film and a MOCVD-TiN film are selected for the first adhesion layer 6 and the second adhesion layer 7, respectively, the W layer 9 as shown in the graph of FIG. Incubation time until deposition begins depends on the adhesion layer, so when trying to deposit 20 nm of W nucleus growth film on TiN film of TiCl ₄ source, on MOCVD-TiN film (with plasma treatment) The W nucleus growth film deposits only 15 nm, and the difference is 5 nm.

As a result, when the W layer is to be deposited with a thickness of 20 nm, the coverage of the W nucleus growth film is formed in the first adhesion layer 6 of the TiN ₄ source TiN film deposited below the hole opening 4 as described above. Although only 12 to 16 nm is deposited at the bottom of the hole, the W nucleus growth film is deposited to a thickness of 15 nm on the MOCVD-TiN film, which is the second adhesion layer 7 above the hole opening 4. The coverage of the bottom with respect to the hole opening end is 80% or more. As a result, the W nucleus growth film is deposited with a substantially uniform film thickness from the hole opening end to the bottom. Furthermore, as shown in the graph of FIG. 3, if the plasma treatment treatment of the MOCVD-TiN film is not performed, the incubation time until the W layer deposition starts further increases, so that the coverage of the W nucleation film is almost 100% or It will exceed 100%. Therefore, it is possible to suppress the generation of voids generated from the difference in the film thickness of the W nucleation film between the vicinity of the hole opening end and the vicinity of the bottom due to the poor coverage of the W nucleation formation film.

  As described above, according to the present embodiment, the second adhesion layer 7 has a longer incubation time until the start of the growth of the W layer than the first adhesion layer 6. , The growth of the W layer on the first adhesion layer 6 above the hole is slower than the growth of the W layer on the second adhesion layer 7 below the hole. The occurrence of voids in the W plug due to early plugging can be suppressed, and the reliability can be improved.

  The first adhesion layer 6 and the second adhesion layer 7 may have a relationship in which the second adhesion layer 7 has a slower growth rate of the W layer than the first adhesion layer 6.

  Further, the second adhesion layer 7 is formed from the opening end of the hole opening 4 to a depth of about ½ of the depth of the hole opening 4 in the depth direction, but only on the upper part than that. You may have been. For example, depending on the case, it may be formed from the opening end of the hole opening 4 to a depth of about 1/3 or 1/4 of the depth of the hole opening 4 in the depth direction.

  In the present embodiment, the lower conductor layer 1 below the W plug is an impurity diffusion region formed on the surface of the semiconductor substrate 2, but is made of a conductor such as polysilicon or metal formed on the semiconductor substrate. It may be a wiring or an electrode.

  The method for manufacturing a semiconductor device according to the present invention can suppress the generation of void opening holes on the surface of the W plug, and is useful for improving the reliability of the semiconductor device.

Sectional drawing which shows the manufacturing method of the semiconductor device in embodiment of this invention in order of a process The figure which shows the coverage confirmation result of the MOCVD-TiN film | membrane in embodiment of this invention The figure which shows the film-forming speed | rate of W nucleation film | membrane by the contact | glue layer difference in embodiment of this invention Sectional view at the time of void formation in a conventional W plug Sectional drawing which shows the manufacturing method by another prior art example in order of a process

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower conductor layer 2 Semiconductor substrate 3 Interlayer insulating layer 4 Hole opening part 6 First adhesion layer 7 Second adhesion layer 9 Tungsten layer

Claims (4)

Forming an interlayer insulating layer on a semiconductor substrate on which a lower conductor layer is formed on the substrate surface portion or above the substrate surface;
Forming a hole opening that opens on the lower conductor layer in the interlayer insulating layer;
Forming a first adhesion layer on the interlayer insulating layer and on the side wall and bottom in the hole opening;
Forming a second adhesion layer only on the first adhesion layer on the side wall of the upper portion of the hole opening;
Filling the tungsten layer in the hole opening by forming a tungsten layer by blanket CVD after forming the second adhesion layer,
The growth rate of the tungsten layer formed on the second adhesion layer has a characteristic of being slower than the growth rate of the tungsten layer formed on the first adhesion layer, or the second adhesion layer Incubation time until the start of growth of the tungsten layer formed on the layer is longer than the incubation time until start of growth of the tungsten layer formed on the first adhesion layer. A method for manufacturing a semiconductor device, comprising: forming a second adhesion layer and the second adhesion layer.   After forming the first adhesion layer in the hole opening, and before forming the second adhesion layer, dry etching the first adhesion layer deposited near the opening end in the hole opening. The method of manufacturing a semiconductor device according to claim 1, wherein the deposited film thickness of the second adhesion layer is removed. The first adhesion layer is a TiN film formed by a thermal CVD method using TiCl ₄ and NH ₃ sources, and the second adhesion layer is a TiN film formed by an MOCVD method using an organic source of TDMAT. The method of manufacturing a semiconductor device according to claim 1, wherein:   4. The method according to claim 1, wherein after the first adhesion layer is formed, the semiconductor substrate is continuously released to the atmosphere until the second adhesion layer is formed. 5. The manufacturing method of the semiconductor device of description.

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