JP3755345B2 - Color conversion circuit - Google Patents

Description

【００５６】
図１に戻って、色変換回路の説明を続ける。アドレス発生ブロック１１ｘ（ｘ＝ａ、ｂ）は、頂点Ｐ０〜Ｐ７に対応付けられる８個の色データ（以下、補間計算用色データと表記する）をメモリ部１４に出力させるためのアドレス信号ＡＤＲＳｘを発生するブロックである。アドレス発生ブロック１１ｘは、図示したように、２つのアンドゲート２１ｘ、２２ｘとオアゲート２３ｘとバッファ２４ｘ（ラッチ）とアドレス発生部２５ｘとを備える。
【００５７】
アンドゲート２１ｘ、２２ｘは、共に、２４ビット幅の信号を入力とする２入力ゲートであり、アンドゲート２１ｘには、色変換回路に供給されているＲＧＢ信号（ＲＧＢデータ）と制御信号ＥＮＡｘとが供給されている。なお、色変換回路に供給されるＲＧＢ信号は、入力周期Ｔでその内容（信号が表すＲＧＢデータ）が変わる信号となっており、制御信号ＥＮＡｘは、全てのビットが“０”である状態と、全てのビットが“１”である状態とを交互にとる周期２Ｔの２４ビット幅の信号となっている。また、色変換回路に含まれる各バッファには、図示していない、周期Ｔのクロック信号ＣＬＫが供給されている。各信号が変化するタイミングについては後述する。
【００５８】
アンドゲート２２ｘには、バッファ２４ｘの出力と、ＥＮＡｘを反転した信号が入力されている。このアンドゲート２２ｘの出力と、アンドゲート２１ｘの出力は、２入力ゲートであるオアゲート２３ｘに入力されている。オアゲート２３ｘの出力は、図示せぬクロック信号ＣＬＫに従って動作するバッファ２４ｘに入力されており、このバッファ２４ｘの出力がアンドゲート２２ｘに帰還されている。
【００５９】
そして、バッファ２４ｘの出力に含まれるｒ、ｇ、ｂ、ｕＲ[０]（ｕＲの最下位ビット）、ｕＧ[０]、及びｕＢ[０]が、信号ＢＵＦＦ１ｘとして、アドレス発生ブロック１１ｘから出力されている。すなわち、ＲＧＢ信号（ＲＧＢデータ）のＲ成分の下位４ビット、Ｇ成分の下位４ビット、及び、Ｂ成分の下位４ビットからなる１２ビット幅の信号が、ＢＵＦＦ１ｘとして出力されている。
【００６０】
バッファ２４ｘの出力に含まれるｕＲ、ｕＧ、ｕＢ（Ｒ、Ｇ、Ｂ成分の上位５ビット）からなる１５ビット幅の信号ＢＵＦＦ０ｘは、アドレス発生部２５ｘに入力されている。アドレス発生部２５ｘは、補間計算用色データをメモリ部１４に出力させるためのアドレス信号ＡＤＲＳｘを実際に発生する回路である。
【００６１】
以下、図６ないし図８を用いて、アドレス発生部２５ｘ（ｘ＝ａ、ｂ）の構成、動作を詳細に説明する。なお、図６は、アドレス発生部２５ｘの全体構成を示した図であり、図７は、アドレス発生部２５ｘ内に設けられているアドレスセレクタ４２₀の構成図である。また、図８は、アドレス発生部２５ｘ内に設けられているアドレスセレクタ４２₁〜４２₇の構成の説明図である。
【００６２】
図６に示したように、アドレス発生部２５ｘは、アドレス演算部４１と８個のアドレスセレクタ４２₀〜４２₇とからなる。バッファ２４ｘからのＢＵＦＦｘ０（すなわち、ｕＲ、ｕＧ及びｕＢ）は、アドレス演算部４１に供給されている。また、ＢＵＦＦｘ０に含まれるｕＲ［０］、ｕＧ［０］、ｕＢ［０］は、アドレスセレクタ４２₀〜４２₇にも供給されている。
【００６３】
アドレス演算部４１は、供給されたｕＲ、ｕＧ、ｕＢ（注目単位格子の頂点Ｐ０の座標値）に基づき、それぞれ、１３ビット幅の信号であり、ｕＲ、ｕＧ、ｕＢとの関係が、以下の（１）〜（８）式で表せるアドレス信号ＡＤＰ０〜ＡＤＰ７を、出力する。
【００６４】
【数１】

【００６５】
すなわち、アドレス演算部４１は、頂点Ｐ０〜Ｐ７の色データのアドレスを表すアドレス信号ＡＤＰ０〜ＡＤＰ７を出力する回路となっている。ただし、アドレス演算部４１の出力するアドレス信号ＡＤＰ０〜ＡＤＰ７は、それぞれをメモリ＃０〜＃７に供給しても、頂点Ｐ０〜Ｐ７の色データを読み出すことができるとは限らない信号（補間計算用色データを出力させるためのＡＤＭＯ〜ＡＤＭ７とするためには並べ替えが必要とされる信号）となっている。
【００６６】
ここで、上記式によって表されるＡＤＰｋ（ｋ＝０〜７）が、注目単位格子の頂点Ｐｋに関する色データが記憶されているメモリのアドレスとなっていること、並びに、各メモリにｘ、ｙ、ｚのいずれかが“３３”である、実際に使用されることがない色データＤ(ｘ、ｙ、ｚ)の記憶領域が用意されている理由を簡単に説明しておく。
【００６７】
メモリ部１４内の各メモリは、既に説明したような形態（図３、４、表１参照）で使用されている。すなわち、メモリ＃Ｋ（Ｋ＝０〜７）には、ｘ、ｙ、ｚが、それぞれ、０〜３３の範囲にあり、かつ、ｘ、ｙ、ｚの奇遇の組み合わせが等しい色データＤ(ｘ、ｙ、ｚ)が、ｘ、ｙ、ｚの昇順でソートされて記憶されている。このように、ｘ、ｙ、ｚのいずれかが“３３”である、実際に使用されることがない色データＤ(ｘ、ｙ、ｚ)の記憶領域が用意されているため、メモリ＃Ｋのｉ番目の記憶領域に記憶された色データのｚ値と、“ｉ＋１７”番目の記憶領域に記憶されたの色データのｚ値が等しくなっている。また、メモリ＃Ｋのｉ番目の記憶領域に記憶された色データのｙ値と、“ｉ＋１７×１７”番目の記憶領域に記憶されたの色データのｙ値が等しくなっている。
【００６８】
従って、メモリ＃０に記憶されている、ｕＲ、ｕＧ、ｕＢがいずれも偶数である色データＤ(ｕＲ、ｕＧ、ｕＢ）のアドレスＡＤは、次式で表せることになる。
【００６９】
【数２】

【００７０】
ｕＤ(＝ｕＲ、ｕＧ、or ｕＢ）が偶数である場合、ｕＤ／２＝INT(ｕＤ／２)が成立するので、この（９）式で算出されるＡＤは、上記した（１）式で算出されるＡＤＰ０と一致する。すなわち、（１）式は、ｕＲ、ｕＧ、ｕＢが偶数であった場合に、Ｄ(ｕＲ、ｕＧ、ｕＢ)が記憶されているメモリ（この場合、メモリ＃０）のアドレスを示す式となっている。
【００７１】
次に、ｕＲ、ｕＧが偶数であり、ｕＢが奇数であった場合を考える。この場合、Ｄ(ｕＲ、ｕＧ、ｕＢ）は、メモリ＃１に記憶されており、そのアドレスＡＤは次式で表せる。
【００７２】
【数３】

【００７３】
ｕＲ、ｕＧが偶数である場合、ｕＲ／２＝INT(ｕＲ／２)、ｕＧ／２＝INT(ｕＧ／２)が成立し、ｕＢが奇数である場合、(ｕＢ−１)／２＝INT(ｕＢ／２)が成立する。従って、上記した（１）式は、ｕＲ、ｕＧが偶数であり、ｕＢが奇数であった場合に、Ｄ(ｕＲ、ｕＧ、ｕＢ）が記憶されているメモリ（この場合、メモリ＃１）のアドレスを示す式ともなっている。
【００７４】
Ｄ(ｕＲ、ｕＧ、ｕＢ）が、メモリ＃２〜＃７に記憶されている場合におけるアドレスＡＤとｕＲ、ｕＧ、ｕＢとの関係も、（１０)式のような、（９）式の一種以上の変数（ｕＲ等）を、その変数から“１”を減じたもの（“ｕＲ−１”等）に置換した式で表せる。そして、ｕＤ(＝ｕＲ、ｕＧ、or ｕＢ）が偶数である場合、(ｕＤ／２)＝INT(ｕＤ／２)が成立し、ｕＤが奇数である場合、(ｕＤ／２)＝INT((ｕＤ−１)／２)が成立するので、結局、（１）式によって、ｕＲ、ｕＧ、ｕＢの奇偶によらず（任意のｕＲ、ｕＧ、ｕＢの組合せに対して）、色データＤ(ｕＲ、ｕＧ、ｕＢ)が記憶されているメモリ（メモリ＃０〜＃７のいずれか）のアドレスが表せることになる。
【００７５】
また、（２）式は、（１）式におけるｕＲ、ｕＧ、ｕＢを、それぞれ、ｕＲ＋１、ｕＧ、ｕＢで置換したものとなっており、（ｕＲ＋１、ｕＧ、ｕＢ）は、頂点Ｐ１の座標（図５参照）である。そして、（１）式は、上記したように、任意のｕＲ、ｕＧ、ｕＢの組合せに対して、色データＤ(ｕＲ、ｕＧ、ｕＢ)が記憶されているメモリ（メモリ＃０〜＃７のいずれか）のアドレスを表す式となっているので、（２）式によって、頂点Ｐ１に関する色データＤ(ｕＲ＋１、ｕＧ、ｕＢ）が記憶されているメモリ（メモリ＃０〜＃７のいずれか）のアドレスが表せることになる。
【００７６】
（３）〜（８）式の各式も、同様に、（１）式において頂点ＰＯの座標の代わりに頂点Ｐ２〜Ｐ７の座標を用いた式となっている。従って、アドレス演算部４１から出力される、上記した（１）〜（８）式でその値が表せるＡＤＰ０〜ＡＤＰ７は、それぞれ、Ｄ(Ｐ０）〜Ｄ(Ｐ７)を読み出すために使用できるアドレス信号となっていることになる。
【００７７】
そして、（１）〜（８）式で色データのアドレスを表せるようにすれば、アドレス演算部４１を簡単な構成の論理回路で実現できるので、ｘ、ｙ、ｚのいずれかが“３３”である、実際に使用されることがない色データＤ(ｘ、ｙ、ｚ)の記憶領域を各メモリ内に用意しているのである。
【００７８】
アドレス演算部４１が出力するＡＤＰ０〜ＡＤＰ７は、図６に示してあるように、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］が供給されている各アドレスセレクタ４２_k（ｋ＝０〜７）に入力されている。
【００７９】
図７に示したように、アドレスセレクタ４２₀は、８つのアンドゲート４５₀〜４５₇と８つのセレクタ４６₀〜４６₇とオアゲート４７とを備える。アンドゲート４５₀〜４５₇は、いずれも、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］が入力されている３入力ゲートである。ただし、アンドゲート４５₀〜４５₇は、それぞれ、入力されたｕＲ［０］、ｕＧ［０］、ｕＢ［０］に対して、以下のように機能するものとなっている。
【００８０】
アンドゲート４５₀は、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］が全て“０”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート４５₁は、ｕＲ［０］とｕＧ［０］が“０”であり、ｕＢ［０］が“１”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート４５₂は、ｕＲ［０］とｕＢ［０］が“０”であり、ｕＧ［０］が“１”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート４５₃は、ｕＲ［０］が“０”であり、ｕＧ［０］とｕＢ［０］が“１”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。
【００８１】
アンドゲート４５₄は、ｕＲ［０］が“１”であり、ｕＧ［０］及びｕＢ［０］が“０”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート４５₅は、ｕＲ［０］及びｕＢ［０］が“１”であり、ｕＧ［０］が“０”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート４５₆は、ｕＲ［０］及びｕＧ［０］が“１”であり、ｕＢ［０］が“０”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート４５₇は、ｕＲ［０］、ｕＢ［０］、ｕＧ［０］が全て“１”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。
【００８２】
アンドゲート４５_k（ｋ＝０〜７）の出力は、セレクタ４６ｋに制御信号として入力されている。セレクタ４６_kには、さらに、アドレス演算部４１からのアドレス信号ＡＤＰｋと、各ビットが“０”である１３ビット幅の信号ＺＥＲＯとが入力されており、セレクタ４６_kは、制御信号が“１”（“Ｈ”）であるときには、ＡＤＰｋを出力し、制御信号が“０”（“Ｌ”）であるときには、ＺＥＲＯを出力する。
【００８３】
オアゲート４７は、８種の１３ビット幅の信号の各ビットの論理和をとった１３ビット幅の信号を出力するゲートである。オアゲート４７には、セレクタ４６₁〜４６₇の出力が入力されており、オアゲート４７の出力がアドレスセレクタ４２₀の出力ＡＤＭ０とされている。
【００８４】
すなわち、アドレスセレクタ４２₀は、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］値に応じて、ＡＤＰ０〜ＡＤＰ７のいずれかをＡＤＭ０として出力する回路となっている。より具体的には、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］がいずれも“０”である場合（ｕＲ、ｕＧ、ｕＢがいずれも偶数である場合）、アンドゲート４５₀のみが“１”を出力するので、アドレスセレクタ４２₀（オアゲート４７）からは、ＡＤＰ０がＡＤＭ０として出力される。すなわち、ｕＲ、ｕＧ、ｕＢがいずれも偶数である場合（メモリ＃０に頂点Ｐ０に関する色データが記憶されている場合；表１参照）、アドレスセレクタ４２₀は、頂点Ｐ０に関する色データが記憶されているアドレスを表すアドレス信号ＡＤＰ０を、ＡＤＭ０として出力する。
【００８５】
また、ｕＲ［０］とｕＧ［０］が“０”であり、ｕＢ［０］が“１”である場合（ｕＲ、ｕＧが偶数であり、ｕＢが奇数である場合）、アンドゲート４５₁のみが“１”を出力するので、アドレスセレクタ４２₀からは、ＡＤＰ１が出力される。すなわち、ｕＲ、ｕＧが偶数であり、ｕＢが奇数である場合、アドレスセレクタ４２₀は、色データＤ(Ｐ１）（Ｄ（Ｐ０）がメモリ＃１に記憶されている場合、メモリ＃０にはＤ(Ｐ１)が記憶されている；表１参照）に関するアドレス信号ＡＤＰ１を、ＡＤＭ０として出力する。
【００８６】
また、ｕＲ、ｕＢが偶数であり、ｕＧが奇数である場合（Ｄ(Ｐ０)がメモリ＃３に記憶されている場合）、アドレスセレクタ４２₀は、色データＤ(Ｐ２）に関するアドレス信号ＡＤＰ２を、ＡＤＭ０として出力する。ｕＲ、ｕＧ、ｕＢの他の奇偶の組み合わせに対しても、アドレスセレクタ４２₀は同様に機能する。
【００８７】
すなわち、アドレスセレクタ４２₀は、アドレス演算部４１が出力する８つのアドレス信号ＡＤＰ０〜ＡＤＰ７の中から、メモリ＃０に対して供給すべき（メモリ＃０に記憶されている注目単位格子に関する色データを読み出すための）アドレス信号を選択して出力する回路となっている。
【００８８】
アドレス発生部２５ｘ内の他のアドレスセレクタ４２₁〜４２₇は、それぞれ、図８（１）〜（７）に示したような信号が、各アンドゲート４５に入力されるようにアドレスセレクタ４２₀を変形した回路となっている。すなわち、アドレスセレクタ４２_k（ｋ＝１〜７）は、アドレス演算部４１が出力する８つのアドレス信号ＡＤＰ０〜ＡＤＰ７から、メモリ＃ｋに対して供給すべきアドレス信号を選択して出力する回路となっている。
【００８９】
そして、図６に示してあるように、アドレスセレクタ４２₀〜４２₇が出力するＡＤＭ０〜ＡＤＭ７からなる１３×８＝１０４ビット幅の信号（ＡＤＰ０〜ＡＤＰ７を、ｕＲ、ｕＧ、ｕＢの奇偶の組合せに応じて並べ替えた信号）が、アドレス発生部２５ｘの出力ＡＤＲＳｘとされている。
【００９０】
図１に戻って色変換回路の説明を続ける。アドレス発生ブロック１１ｘからは、アドレス発生部２５ｘの出力が、そのまま出力されている。そして、アドレス発生ブロック１１ａの出力ＡＤＲＳａと、アドレス発生ブロック１１ｂの出力ＡＤＲＳｂが、アドレス切替部１２に入力されている。アドレス切替部１２は、制御信号ＡＤＳＥＬ（詳細は後述）に応じてＡＤＲＳａ、ＡＤＲＳｂのいずれか一方を出力する回路であり、このアドレス切替部１２の出力がアドレスバッファ１３を介してメモリ部１４に供給されている。そして、メモリ＃０〜＃７の出力Ｄ０〜Ｄ７からなる２５６ビット幅の信号ＤＡＴＡがデータバッファ１５（図２）に供給され、データバッファ１５の出力ＤＢＵＦＦが補間演算ブロック１６ａ、１６ｂに供給されている。
【００９１】
ここで、図９に示したタイミング図を用いて、ここまで説明してきた各部の総合的な動作を説明する。
【００９２】
図９（１）、（２）に示したように、本色変換回路は、クロックＣＬＫの周期Ｔと等しい周期でその内容が変わるＲＧＢ信号が入力されて使用される。また、アドレス発生ブロック１１ａに入力されているＥＮＡａは、図９(３)に示してあるように、ＲＧＢデータの入力周期に同期した形で、“Ｈ”状態（全てのビットが“１”の状態）、“Ｌ”状態（全てのビットが“０”の状態）とを交互に取る信号となっている。一方、アドレス発生ブロック１１ｂに入力されているＥＮＡｂは、図９(６)に示してあるように、ＥＮＡａが“Ｈ”状態をとっているときに、“Ｌ”状態をとり、ＥＮＡａが“Ｌ”状態をとっているときに、“Ｈ”状態をとる信号となっている。また、図９（９）に示したように、ＡＤＳＥＬは、ＥＮＡａと、同位相の信号となっている。
【００９３】
すなわち、アドレス発生ブロック１１ａ、１１ｂからデータバッファ１５までの部分は、以下のように動作する。
【００９４】
既に説明した構成（図１）から明らかなように、アドレス発生ブロック１１ａ内のオアゲート２３ａは、ＥＮＡａが“Ｈ”である場合、色変換回路に入力されているＲＧＢ信号を出力している。
【００９５】
従って、図９に示してあるように、時刻ｔ１において、ＲＧＢ信号がＲＧＢデータ▲１▼を表しており、かつ、ＥＮＡａが“Ｈ”であった場合、バッファ２４ａは、オアゲート２３ａから出力されているＲＧＢデータ▲１▼を取り込み、取り込んだデータの出力を開始する。その後、時刻ｔ２（＝ｔ１＋Ｔ）に、バッファ２４ａは、オアゲート２３ａの出力を再度取り込むが、この時点では、ＥＮＡａが“Ｌ”となっているので、オアゲート２３ａからは、バッファ２４ａの出力、すなわち、ＲＧＢデータ▲１▼が出力されている。このため、バッファ２４ａは、同じ内容のデータ（ＲＧＢデータ▲１▼）を出力し続けることになる。そして、ＣＬＫの次の立ち上がり時（ｔ＝ｔ３）には、ＥＮＡａが“Ｈ”となっているので、バッファ２４ａは、その時点において色変換回路に入力されているＲＧＢ信号が表しているＲＧＢデータ▲３▼を取り込み、その出力を開始する。
【００９６】
アドレス発生ブロック１１ａ内のバッファ２４ａまでの部分は、このような動作を繰り返すため、結局、バッファ２４ａからは、図９（４）に示したように、ＢＵＦＦ１ａとして、時間２Ｔ周期で、内容（信号が表すデータ）が変わる信号であって、各データがＲＧＢ信号によって色変換回路に供給された一個おきのＲＧＢデータ（図示したケースでは、奇数番号が付してあるＲＧＢデータ）の一部（ｕＲ［０］、ｕＧ［０］、ｕＢ［０］、ｒ、ｇ、ｂ）となった信号が、出力される。また、ＢＵＦＦ０ａ（図示せず）として、ＢＵＦＦ１ａと同様の時間変化をする信号が出力される。
【００９７】
そして、アドレス発生ブロック１１ｂには、ＥＮＡａを反転した（ＥＮＡａと位相が１８０°異なった）信号ＥＮＡｂが供給されている。このため、アドレス発生ブロック１１ｂのバッファ２４ｂからは、図９（７）に示したように、時間２Ｔ周期で、内容（データ）が変わる信号であって、各データが色変換回路に供給された一個おきのＲＧＢデータ（図示したケースでは、偶数番号が付してあるＲＧＢデータ）の一部となった信号ＢＵＦＦ１ｂが、出力される。また、ＢＵＦＦ０ｂ（図示せず）としても、ＢＵＦＦ１ｂと同様の時間変化をする信号が出力される。
【００９８】
さらに、各アドレス発生ブロック１１ｘにおいては、ＢＵＦＦ０ｘ（ｕＲ、ｕＧ、ｕＢ）を基にした演算処理によりＡＤＰ０〜ＡＤＰ７が生成され、それらが、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］の組み合わせに応じて並べ替えられて、ＡＤＲＳｘが生成されている。
【００９９】
アドレス発生部２５ｘは、このＡＤＲＳｘの生成に、時間Ｔ以上の時間が必要とされる回路となっている。このため、アドレス発生ブロック１１ａからは、図９（５）に示してあるように、バッファ２４ａの出力（図９（４）参照）が安定（確定）した後、所定時間（＞Ｔ）遅れてＡＤＲＳａの出力が開始される。また、アドレス発生ブロック１１ｂからは、図９（８）に示してあるように、バッファ２４ｂの出力（図９（７）参照）が安定した後、所定時間遅れてＡＤＲＳｂの出力が開始される。
【０１００】
ＡＤＲＳａ、ＡＤＲＳｂが供給されているアドレス切替部１２は、ＡＤＳＥＬが“Ｈ”であるときには、ＡＤＲＳａを出力し、ＡＤＳＥＬが“Ｌ”であるときには、ＡＤＲＳｂを出力する。ＡＤＳＥＬは、ＥＮＡａと同位相の信号となっており、アドレスバッファ１３は、アドレス切替部１２の出力をＣＬＫの立ち上がり時に取り込むので、アドレスバッファ１３からは、図９（１０）に示したように、表すデータが時間Ｔ毎に変化する信号であって、各データが略２Ｔ時間前に色変換回路に入力されたＲＧＢデータの補間計算用色データのアドレスとなった信号ＡＤＲＳが、出力される。
【０１０１】
そして、そのＡＤＲＳがアドレス信号として入力されているメモリ部１４からは、図９（１１）に示したようなタイミングでその内容が変化する信号ＤＡＴＡが出力される。データバッファ１５は、ＣＬＫに従って、信号ＤＡＴＡを取り込むので、結局、データバッファ１５からは、図９（１２）に示したように、色変換回路に入力された各ＲＧＢデータに関する補間計算用色データを、当該ＲＧＢデータの入力から一定時間後に表す信号ＤＢＵＦＦが出力される。
【０１０２】
図２に戻って、色変換回路の説明を続ける。
【０１０３】
データバッファ１５の出力ＤＢＵＦＦは、補間演算ブロック１６ａ，１６ｂに入力されている。補間演算ブロック１６ｘ（ｘ＝ａ、ｂ）は、図示してあるように、２つのアンドゲート３１ｘ、３２ｘ、オアゲート３３ｘ、バッファ３４ｘ、補間演算部３５ｘ、及び、４つのバッファ３６ｘ〜３９ｘを備える。アンドゲート３１ｘ、３２ｘは、共に、２５６ビット幅の信号を入力とする２入力ゲートであり、アンドゲート３１ｘには、データバッファ１５からのＤＢＵＦＦと、全てのビットが“０”である状態と全てのビットが“１”である状態のいずれかを取る２５６ビット幅の信号である制御信号ＤＥＮＡｘが入力されている。一方、アンドゲート３２ｘには、バッファ３４ｘの出力とＤＥＮＡｘを反転した信号が入力されている。そして、アンドゲート３１ｘの出力とアンドゲート３２ｘの出力が、２５６ビット幅の信号を入力とする２入力ゲートであるオアゲート３３ｘに入力されている。
【０１０４】
オアゲート３３ｘの出力は、ＣＬＫ（図示せず）に従って動作するバッファ３４ｘに入力されており、このバッファ３４ｘの出力ＤＢＵＦＦｘがアンドゲート３２ｘと補間演算部３５ｘの双方に供給されている。
【０１０５】
また、アドレス発生ブロック１１ｘの出力であるＢＵＦＦ１ｘ（ｕＲ［０］、ｕＧ［０］、ｕＢ［０］、ｒ、ｇ、ｂ）は、バッファ３６ｘに入力されている。バッファ３６ｘの出力ＢＵＦＦ２ｘは、バッファ３７ｘに入力されており、バッファ３７ｘの出力ＢＵＦＦ３ｘは、バッファ３８ｘに入力されている。そして、バッファ３９ｘには、バッファ３８ｘの出力ＢＵＦＦ４ｘが入力されており、バッファ３９ｘの出力ＢＵＦＦ５ｘが補間演算部３５ｘに入力されている。なお、これらのバッファ３６ｘ〜３９ｘは、補間演算部３５ｘにＢＵＦＦ５ｘとして供給される、ＲＧＢデータの下位データ（ｕＲ［０］、ｕＧ［０］、ｕＢ［０］、ｒ、ｇ、ｂ）を、バッファ３４ｘからＤＢＵＦＦｘとして供給される色データＤ０〜Ｄ７の元となったＲＧＢデータの下位データと一致させるための回路となっている。すなわち、補間演算部３５ｘは、あるＲＧＢデータのｕＲ［０］、ｕＧ［０］、ｕＢ［０］、ｒ、ｇ、ｂと、そのＲＧＢデータのｕＲ、ｕＧ、ｕＢに基づき読み出された補間計算用色データＤ０〜Ｄ７の入力を受けて動作する。
【０１０６】
図１０に、補間演算部３５ｘ（ｘ＝ａ，ｂ）の構成を示す。図示したように、補間演算部３５ｘは、データセレクタ５１₀〜５１₇とモード判定・係数演算部５２と演算用データセレクタ５３と出力演算部５４とを備える。バッファ３４ｘからのＤＢＵＦＦｘは、各データセレクタ５１に供給されている。また、ＢＵＦＦｘ５に含まれているｕＲ［０］、ｕＧ［０］、ｕＢ［０］は、各データセレクタ５１₀〜５１₇に供給されており、ＢＵＦＦｘ５に含まれるｒ、ｇ、ｂは、モード判定・係数演算部５２に供給されている。
【０１０７】
まず、補間演算部３５ｘに含まれているデータセレクタ５１₀〜５１₇の構成、動作を説明する。図１１に示したように、データセレクタ５１₀は、ＡＤＰ０〜ＡＤＰ７の代わりにＤ０〜Ｄ７が用いられるように、アドレスセレクタ２６₀（図７）を変形した回路となっている。
【０１０８】
すなわち、データセレクタ５１₀内のアンドゲート５５₀は、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］が全て“０”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート５５₁は、ｕＲ［０］とｕＧ［０］が“０”であり、ｕＢ［０］が“１”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート５５₂は、ｕＲ［０］とｕＢ［０］が“０”であり、ｕＧ［０］が“１”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート５５₃は、ｕＲ［０］が“０”であり、ｕＧ［０］とｕＢ［０］が“１”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。
【０１０９】
アンドゲート５５₄は、ｕＲ［０］が“１”であり、ｕＧ［０］及びｕＢ［０］が“０”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート５５₅は、ｕＲ［０］及びｕＢ［０］が“１”であり、ｕＧ［０］が“０”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート５５₆は、ｕＲ［０］及びｕＧ［０］が“１”であり、ｕＢ［０］が“０”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。アンドゲート５５₇は、ｕＲ［０］、ｕＢ［０］、ｕＧ［０］が全て“１”である場合に“１”を出力し、それ以外の場合には、“０”を出力する。
【０１１０】
そして、データセレクタ５１₀内のセレクタ５６_k（ｋ＝０〜７）は、アンドゲート５５_kの出力と、色データＤｋと、各ビットが“０”である３２ビット幅の信号ＺＥＲＯの入力を受け、アンドゲート５５_kから“１”が入力されているときには、ＡＤＰｋを出力し、アンドゲート５５_kから“０”が入力されているときには、ＺＥＲＯを出力する。セレクタ５６₁〜５６₇の出力（３２ビット幅の信号）は、オアゲート５７に入力されており、オアゲート５７の出力がデータセレクタ５１₀の出力Ｄ(Ｐ０）とされている。
【０１１１】
すなわち、データセレクタ５１₀は、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］値に応じて、以下のように動作する。
【０１１２】
ｕＲ［０］、ｕＧ［０］、ｕＢ［０］がいずれも“０”である場合（ｕＲ、ｕＧ、ｕＢがいずれも偶数である場合）、データセレクタ５１₀（オアゲート５７）は、Ｄ０をＤ(Ｐ０）として出力する。すなわち、頂点Ｐ０に関する色データがメモリ＃０に記憶されている場合、データセレクタ５１₀は、メモリ＃０から読み出されたデータである色データＤＯをＤ(Ｐ０）として出力する。
【０１１３】
また、ｕＲ［０］とｕＧ［０］が“０”であり、ｕＢ［０］が“１”である場合（ｕＲ、ｕＧが偶数であり、ｕＢが奇数である場合）、データセレクタ５１₀は、Ｄ１をＤ(Ｐ０）として出力する。すなわち、頂点Ｐ０に関する色データがメモリ＃１に記憶されている場合、データセレクタ５１₀は、メモリ＃１から読み出されたデータである色データＤ１をＤ(Ｐ０）として出力する。
【０１１４】
また、ｕＲ、ｕＢが偶数であり、ｕＧが奇数である場合（頂点Ｐ０に関する色データがメモリ＃２に記憶されている場合）、データセレクタ５１₀は、メモリ＃２から読み出された色データＤ２をＤ(Ｐ０）として出力する。
【０１１５】
ｕＲ、ｕＧ、ｕＢの他の奇偶の組み合わせに対しても、データセレクタ５１₀は同様に機能する。すなわち、データセレクタ５１₀は、メモリ部１４から読み出された８つのデータＤ０〜Ｄ７の中から、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］値に基づき頂点Ｐ０に関するデータ（頂点Ｐ０に関するデータが記憶されているメモリの出力）を選択して出力する回路となっている。
【０１１６】
補間演算部３５ｘ内のデータセレクタ５１₁〜５１₇は、それぞれ、図１２（１）〜（７）に示したような信号が各アンドゲート５５に入力されるようにデータセレクタ５１₀を変形した回路となっている。すなわち、データセレクタ５１_k（ｋ＝１〜７）は、メモリ部１４から読み出された８つの色データＤ０〜Ｄ７から、頂点Ｐｋに関する色データを選択して出力することができる構成を有している。
【０１１７】
図１０に示してあるように、データセレクタ５１₀の出力Ｄ(Ｐ０）と、データセレクタ５１₇の出力Ｄ(Ｐ７）は、補間計算を実際に行う回路である出力演算部５４に入力されている。一方、データセレクタ５１₁〜５１₆の出力Ｄ(Ｐ１）〜Ｄ(Ｐ６）は、演算用データセレクタ５３に入力されている。
【０１１８】
そして、ｒ、ｇ、ｂが入力されているモード判定・係数演算部５２は、それらの値に応じた内容の信号modeと信号ｂ０〜ｂ３を出力する。具体的には、モード判定・係数演算部５２は、ｒ、ｇ、ｂに応じて表２に示したように機能する。
【０１１９】
【表２】

【０１２０】
すなわち、モード判定・係数演算部５２は、ｒ＜ｇ＜ｂが成立している場合には、“１”を表す信号modeと、それぞれ、“８−ｂ”、“ｇ−ｒ”、“ｂ−ｇ”、“ｒ”を表す信号ｂ０〜ｂ３とを出力する。また、ｒ＜ｂ≦ｇが成立している場合には、“２”を表す信号modeと、それぞれ、“８−ｇ”、“ｇ−ｂ”、“ｂ−ｒ”、“ｒ”を表す信号ｂ０〜ｂ３を出力する。
【０１２１】
ｇ≦ｒ＜ｂが成立している場合、モード判定・係数演算部５２は、“３”を表す信号modeを出力し、それぞれ、“８−ｂ”、“ｂ−ｇ”、“ｒ−ｇ”、“ｇ”を表す信号ｂ０〜ｂ３を出力する。また、ｂ≦ｒ＜ｇが成立している場合には、“４”を表す信号modeと、それぞれ、“８−ｇ”、“ｒ−ｂ”、“ｒ−ｂ”、“ｂ”を表す信号ｂ０〜ｂ３を出力する。
【０１２２】
ｇ＜ｂ≦ｒが成立している場合、モード判定・係数演算部５２は、“５”を表す信号modeと、それぞれ、“８−ｒ”、“ｂ−ｇ”、“ｒ−ｂ”、“ｇ”を表す信号ｂ０〜ｂ３とを出力する。また、ｂ≦ｇ＜ｒが成立している場合には、“４”を表す信号modeと、それぞれ、“８−ｒ”、“ｒ−ｇ”、“ｇ−ｂ”、“ｂ”を表す信号ｂ０〜ｂ３とを出力する。
【０１２３】
モード判定・係数演算部５２が出力する信号modeは、演算用データセレクタ５３に入力されている。
【０１２４】
そして、演算用データセレクタ５３は、データセレクタ５１₁〜５１₆から供給されているＤ(Ｐ１)〜Ｄ(Ｐ６)の中の、信号modeに応じた２つの信号をＤＡ、ＤＢとして出力する。具体的には、演算用データセレクタ５３は、信号modeに応じて、表３に示したように機能する。
【０１２５】
【表３】

【０１２６】
すなわち、演算用データセレクタ５３は、信号modeが“１”を表すものであった場合、信号ＤＡとしてＤ(Ｐ３）を出力し、信号ＤＢとしてＤ(Ｐ１）を出力する。また、modeが“２”であった場合、信号ＤＡとしてＤ(Ｐ２）を出力し、信号ＤＢとしてＤ(Ｐ３）を出力する。
【０１２７】
また、modeが“３”であった場合、演算用データセレクタ５３は、信号ＤＡとしてＤ(Ｐ１）を出力し、信号ＤＢとしてＤ(Ｐ５）を出力する。modeが“４”であった場合には、信号ＤＡとしてＤ(Ｐ６）を出力し、信号ＤＢとしてＤ(Ｐ２）を出力する。
【０１２８】
modeが“５”であった場合、信号ＤＡとしてＤ(Ｐ５）を出力し、信号ＤＢとしてＤ(Ｐ４）を出力する。そして、演算用データセレクタ５３は、modeが“６”を表すものであった場合には、信号ＤＡとしてＤ(Ｐ４）を出力し、信号ＤＢとしてＤ(Ｐ６）を出力する。
【０１２９】
演算用データセレクタ５３が出力するＤＡ、ＤＢと、モード判定・係数演算部５２が出力するｂ０〜ｂ３と、データセレクタ５１₀、５１₇の出力Ｄ(Ｐ０)、Ｄ(Ｐ７)とが入力されている出力演算部５４は、次式でその内容（値）が表される３２ビットの信号ＯＵＴｘを出力する。
【０１３０】
【数４】

【０１３１】
ここで、図１３を用いて、モード判定・係数演算部５２、演算用データセレクタ５３及び出力演算部５４の上記した動作の物理的な意味を説明しておくことにする。
【０１３２】
モード判定・係数演算部５２が出力している信号modeは、座標（ｕＲ＋ｒ／８、ｕＧ＋ｇ／８、ｕＢ＋ｂ／８）によってその位置が示される点Ｐ_RGB（図５参照）が、注目単位格子の分割により得られる、図１３（１）〜（６）に示した６つの４面体のいずれに含まれるかを表す信号となっている。具体的には、モード判定・係数演算部５２は、点Ｐ_RGBが、図１３（１）〜（６）に示した４面体内に含まれるときに、それぞれ、“１”〜“６”を示す信号modeを出力するように構成されている。
【０１３３】
演算用データセレクタ５３において行なわれている、modeに応じた色データの選択出力は、頂点Ｐ１〜Ｐ６に関する色データの中から、点Ｐ_RGBが含まれている４面体の４つの頂点の中の頂点Ｐ０、Ｐ７を除く２頂点に関する色データ（すなわち、補間計算に用いる色データ）を選択して出力する処理となっている。なお、Ｄ(Ｐ０)、Ｄ(Ｐ７)が信号modeに応じて選択される色データとなっていないのは、図１３に示してあるように、本色変換回路では、注目単位格子が、いずれも、頂点Ｐ０、Ｐ７を含む６つの四面体に分割されているからである。
【０１３４】
そして、モード判定・係数演算部５２が出力するｂ０〜ｂ３は、それぞれ、１／８を乗ずることによって補間演算の重み係数として用いることができるデータを表す信号となっているため、出力演算部５４の上記した（１１）式に従った演算により、ＲＧＢデータの変換結果であるＣＭＹＫデータが得られているのである。
【０１３５】
図２に戻って、色変換回路の残りの構成の説明を行う。図示してあるように、補間演算ブロック１６ａ、１６ｂから出力される信号ＯＵＴａ，ＯＵＴｂは、データ切替部１７に入力されている。データ切替部１７は、制御信号ＤＡＴＡＳＥＬに応じてＯＵＴａ、ＯＵＴｂのいずれか一方を出力する回路である。データ切替部１７の出力は、出力バッファ１８に入力されており、出力バッファ１８の出力が、色変換回路の出力である信号ＯＵＴとされている。
【０１３６】
以下、図９を用いて、色変換回路の補間演算ブロック１６ａ，ｂ以降の部分の総合的な動作を説明する。
【０１３７】
補間演算ブロック１６ａに供給されている制御信号ＤＥＮＡａは、図９（１３）に示したように、制御信号ＥＮＡａと同位相の信号となっている。一方、補間演算ブロック１６ｂに供給されている制御信号ＤＥＮＡｂは、図９（２０）に示したように、ＤＥＮＡｂを反転した信号となっている。また、データ切替部１７に供給されている制御信号ＯＵＴＳＥＬは、図９（２７）に示したように、ＤＥＮＡａと同位相の信号となっている。
【０１３８】
そして、補間演算ブロック１６ａ内のアンドゲート３１ａ、３２ａ、オアゲート３３ａ、バッファ３４ａからなる回路は、アドレス発生ブロック１１ｘ内のアンドゲート２１ｘ、２２ｘ、オアゲート２３ｘ、バッファ２４ｘからなる回路と同様の構成を有している。このため、バッファ３４ａからは、図９（１４）に示したように、時間２Ｔ毎に、その内容（信号が表すデータ）が変わる信号であって、各データが奇数番目のＲＧＢデータに関する補間計算用色データとなった信号ＤＢＵＦＦａが出力される。
【０１３９】
一方、ＢＵＦＦ１ａ（図９（４））が入力されているバッファ３６ａは、ＣＬＫに応じてＢＵＦＦ１ａを取り込む。従って、バッファ３６ａの出力ＢＵＦＦ２ａは、図９（１５）に示したように、ＢＵＦＦ１ａを時間Ｔだけ遅らせた信号となる。また、ＢＵＦＦ２ａが入力されているバッファ３７ａの出力ＢＵＦＦ３ａは、図９（１６）に示したように、ＢＵＦＦ２ａを時間Ｔだけ遅らせた信号となり、ＢＵＦＦ３ａが入力されているバッファ３８ａの出力ＢＵＦＦ４ａは、図９（１７）に示したように、ＢＵＦＦ３ａを時間Ｔだけ遅らせた信号となる。
【０１４０】
その結果、ＢＵＦＦ４ａが入力されているバッファ３９ａの出力ＢＵＦＦ５ａ、すなわち、補間演算部３５ａに入力されるＢＵＦＦ５ａは、図９（１８）に示したように、ＢＵＦＦ１ａを時間５Ｔだけ遅らせた信号となる。すなわち、バッファ３６ｘ〜３９ｘによって、あるＲＧＢデータに関するｒ、ｇ、ｂ、ｕＲ［０］、ｕＧ［０］及びｕＢ［０］が、そのＲＧＢデータに関する補間計算用色データ（図９（１４））と同時に補間演算部３５ｘに供給されるように制御されている。
【０１４１】
そして、補間演算部３５ａでは、同時に入力された、あるＲＧＢデータに関するｒ、ｇ、ｂ、ｕＲ［０］、ｕＧ［０］、ｕＢ［０］、補間計算用色データに基づき、そのＲＧＢデータに対応するＣＭＹＫデータが補間演算によって求められる。従って、補間演算部３５ａから出力される信号ＯＵＴａは、図９（１９）に示してあるように、入力された各ＲＧＢデータ（奇数番目のＲＧＢデータ）の変換結果を表す信号であって、補間演算部３５ａへの新たなデータ（図９（１４）、（１８））の入力後、演算に要する時間が経過したときに、その内容が確定する信号となる。
【０１４２】
補間演算ブロック１６ｂにおいては、補間演算ブロック１６ａと同様の処理が、アドレス発生ブロック１１ｂからの信号ＢＵＦＦ０ａとデータバッファ１５からの信号ＤＢＵＦＦに対して行なわれる。すなわち、補間演算ブロック１６ｂ内のバッファ３６ｂ〜３９ｂの出力ＢＵＦＦ２ｂ〜ＢＵＦＦ５ｂは、それぞれ、図９（２２）〜（２５）に示したように変化する。そして、補間演算部３５ｂでは、ＢＵＦＦ５ｂとＤＢＵＦＦｂとを基に、ＯＵＴｂが生成されるので、結局、補間演算ブロック１６ｂから出力されるＯＵＴｂは、図９（２６）に示したように、入力された各ＲＧＢデータ（偶数番目のＲＧＢデータ）の変換結果を、表す信号であって、補間演算部３５ｂへの新たなデータ（図９（２１）、（２５））の入力後、演算に要する時間が経過したときに、その内容が確定する信号となる。
【０１４３】
そして、ＯＵＴａ、ＯＵＴｂが入力されているデータ切替部１７には、図（２７）に示したように、ＣＬＫの倍の周期で変化する制御信号ＯＵＴＳＥＬであって、ＯＵＴａが遷移状態から安定状態に変化した際に“Ｈ”状態を取っており、ＯＵＴｂが遷移状態から安定状態に変化した際に“Ｌ”状態を取っているようにその位相が制御された制御信号ＯＵＴＳＥＬが入力されている。
【０１４４】
そのようなＯＵＴＳＥＬが供給されているデータ切替部１７の出力が出力バッファ１８に供給されているので、出力バッファ１８からは、図９（２８）に示したように、入力された各ＲＧＢデータの変換結果を表す信号ＯＵＴが出力されることになる。
【０１４５】
以上、詳細に説明したように、実施形態に係る色変換回路は、全てのＲＧＢデータに対して補間計算が行える数のＣＭＹＫデータを記憶した、補間計算に必要とされる複数のＣＭＹＫデータを同時に読み出せるメモリ部１４を、備えている。従って、ＲＧＢデータを、その内容によらず、ＣＭＹＫデータに高速に変換できることになる。また、色変換回路は、ＣＭＹＫデータが記憶された“３×５−２”ビットのアドレスでアクセスされる８個のメモリからなるメモリ部１４と、それらのメモリに供給する“３×５−２”ビットの８種のアドレスを、ＲＧＢデータのｕＲ、ｕＧ、ｕＢから生成するアドレス発生部２５とを備えている。従って、色変換回路は、被変換色データの成分毎に、独立して、目的色データを読み出すためのアドレスの一部（特定の複数ビット）が作成されている従来の色変換回路（図１５参照）よりも、少ない記憶容量のメモリを用いて製造できる回路となっている。
【０１４６】
また、実施形態に係る色変換回路は、２つのアドレス発生部２５ａ、２５ｂと、２つの補間演算部３５ａ、３５ｂと、アドレス発生部２５ａ、２５ｂを交互に機能させるための回路（バッファ２４、アドレス切替部１２等）、補間演算部３５ａ、３５ｂを交互に機能させるための回路（バッファ３４、データ切替部１７等）を備えている。このため、実施形態に係る色変換回路は、アドレス発生部２５、補間演算部３５のスループット（単位時間当たりの処理量）よりも高いスループットで、ＲＧＢデータを変換できる回路となっている。
【０１４７】
換言すれば、色変換回路に必要とされているスループット（要求されているＲＧＢデータの変換速度）が、アドレス発生部２５のスループット、補間演算部３５のスループットのいずれよりも高いものであったため、実施形態に係る色変換回路は、上記のような構成を採用しているのである。
【０１４８】
従って、色変換回路のスループットが、アドレス発生部２５スループット、補間演算部３５スループットのいずれよりも低くてよい場合（高いＲＧＢデータの変換速度が必要とされていない場合）には、１個のアドレス発生部２５と、一個の補間演算部３５と、メモリ部１４と、バッファ３６〜３９のようなタイミング調節用のバッファだけで色変換回路を構成することができる。
【０１４９】
また、要求されているスループットが、アドレス発生部２５のスループットよりも高く、補間演算部３５のスループットよりも低い場合には、メモリ部１４よりも前段にある回路を、一個のアドレス発生部２５を用いた回路とすることができる。逆に、所望のスループットが、アドレス発生部２５のスループットよりも低く、補間演算部３５のスループットよりも高い場合には、メモリ部１４よりも後段にある回路を、一個の補間演算部３６を用いた回路とすることができる。
【０１５０】
なお、アドレス発生部２５のスループットと、補間演算部３５のスループットのいずれの方が高いかは、アドレス発生部２５、補間演算部３５の実際の回路構成に依る。本実施形態に係る色変換回路では、アドレス発生部２５、補間演算部３５を、基本的な演算回路の組み合わせで実現しているため、双方のスループットがほぼ同程度のものとなっている（処理の遅延時間がほぼ同じものとなっている）が、例えば、アドレス発生部２５をメモリを用いて実現した場合や、アドレス発生部２５をパイプライン化した場合には、アドレス発生部２５のスループットが、補間演算部３５のスループットよりも高くなる（メモリのスループットと同程度のものとなる）。また、補間演算部３５のみをパイプライン化してそのスループットを高くした場合には、アドレス発生部２５のスループットの方が、補間演算部３５のスループットよりも低くなる。従って、要求されるスループットと、アドレス発生部２５、補間演算部３５のスループットの関係によって、上記したいずれの構成を色変換回路に採用するかを決定すべきである。
【０１５１】
また、実施形態に係る色変換回路は、点Ｐ_RGBを含む四面体の４頂点の色データを基にした補間演算により最終出力が得られる回路であったが、メモリ部１４から同時に読み出される８個の色データを全てを用いて補間演算が行なわれるように色変換回路を変形しても良いことは当然である。
【０１５２】
さらに、メモリ部１４の代わりに、メモリ＃０とメモリ＃７に記憶されたＣＭＹＫデータ、メモリ＃１とメモリ＃６に記憶されたＣＭＹＫデータ、メモリ＃２とメモリ＃５に記憶されたＣＭＹＫデータ、メモリ＃３とメモリ＃４に記憶されたＣＭＹＫデータを、それぞれ、記憶した１４ビットのアドレスでアクセスされる４つのメモリを備えるメモリ部が用いられ、補間演算部３５として、対角の頂点を含まないように注目単位格子を分割した四面体の中から選択された点Ｐ_RGBを含む四面体の４頂点に関するＹＭＣＫデータを基に補間演算を行うものが用いられるように色変換回路を変形することもできる。
【０１５３】
【発明の効果】
本発明によれば、色データを、その内容によらず、他方式の色データに高速に変換でき、少容量のメモリしか必要としない色変換回路が得られることになる。
【図面の簡単な説明】
【図１】本発明の一実施形態に係る色変換回路の前半部分の構成を示した回路図である。
【図２】実施形態に係る色変換回路の後半部分の構成を示した回路図である。
【図３】実施形態に係る色変換回路内に設けられたメモリ＃０〜＃３の利用形態の説明図である。
【図４】実施形態に係る色変換回路内に設けられたメモリ＃４〜＃７の利用形態の説明図である。
【図５】実施形態に係る色変換回路によって行われる色変換手順を説明するための図である。
【図６】実施形態に係る色変換回路内に設けられたアドレス発生部の全体構成を示した回路図である。
【図７】アドレス発生部内に設けられているアドレスセレクタの構成を示す回路図である。
【図８】アドレス発生部内に設けられている他のアドレスセレクタの構成の説明図である。
【図９】実施形態に係る色変換回路の全体的な動作を説明するためのタイミング図である。
【図１０】実施形態に係る色変換回路内に設けられている補間演算部の全体構成を示した回路図である。
【図１１】補間演算部内に設けられているデータセレクタの構成を示す回路図である。
【図１２】補間演算部内に設けられている他のデータセレクタの構成の説明図である。
【図１３】補間演算部の動作の説明図である。
【図１４】従来の色変換回路に備えられたメモリの使用形態の説明図である。
【図１５】米国特許第4,837,722号明細書に開示されているデジタル式高速３次元補間装置の構成を示した図である。
【符号の説明】
１１ アドレス発生ブロック
１２ アドレス切替部
１３ アドレスバッファ
１４ メモリ部
１５ データバッファ
１６ 補間演算ブロック
１７ データ切替部
１８ 出力バッファ
２５ アドレス発生部
３５ 補間演算部
４１ アドレス演算部
４２ アドレスセレクタ
５１ データセレクタ
５２ モード判定・係数演算部
５３ 演算用データセレクタ
５４ 出力演算部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a color conversion circuit that converts color data of a certain format into color data of another format, for example, a color conversion circuit that converts RGB data to CMYK data.
[0002]
[Prior art]
As is well known, there are various data such as RGB data, CMYK data, and CMY data as color data (hereinafter referred to as color data), and the color data of each format is properly used according to the application. ing. For example, in data mainly intended for display on a computer monitor, RGB data is often used as color data. In a color printing apparatus, printing is performed by mixing C (cyan), M (magenta), and Y (yellow) ink (or using K (black) ink). In data, CMY and CMYK data are often used as color data. However, since data whose color is indicated by RGB data may be supplied, a color printing apparatus is usually equipped with a semiconductor circuit for converting RGB data into CMYK (or CMY) data.
[0003]
Such a circuit for converting color data in one format into color data in another format (hereinafter referred to as a color conversion circuit) is basically converted to each color data that needs to be converted. It is configured using a memory that stores color data. For example, a ROM (or RAM) in which CMYK data to be used instead of each RGB data is stored at an address indicated by the RGB data functions as a color conversion circuit for converting the RGB data into CMYK data. Become.
[0004]
However, when the color conversion circuit is configured with only the memory, for example, in order to obtain a color conversion circuit capable of converting 24-bit RGB data into 32-bit (4 bytes) YMCK data, approximately 67 Mbytes are obtained. (= 4 bytes x 2 ^{twenty four} ) Is required. Since it is not practical to use such a large-capacity memory, in a general color conversion circuit, only the second type color data corresponding to the representative first type color data is stored in the memory. Second type data corresponding to each first type color data can be calculated by interpolation based on some (usually four or eight) second type data stored in the memory. It is done.
[0005]
Specifically, as a color conversion circuit for converting 24-bit RGB data into CMYK data, coordinates (0, 0, 0) to (32, 32, 32) are schematically shown in FIG. It is known to have a memory in which a total of 33 × 33 × 33 CMYK data associated with is stored. The CMYK data stored in this memory and associated with coordinates (x, y, z) where x, y, z are all 31 or less are all in the lower 3 bits of the R, G, B components. It is “0”, and CMYK data (CMYK data indicating the same color as the RGB data) corresponding to RGB data in which the upper 5 bits of the R, G, and B components are x, y, and z, respectively. In CMYK data associated with coordinates (x, y, z) where any of x, y, z is 32, the lower 3 bits of each of the R, G, B components are all “0”. CMYK data corresponding to virtual RGB data (the maximum value of x, y, z is 31 and cannot be 32) in which the upper 5 bits of the R, G, B components are x, y, z, respectively It has become.
[0006]
When converting RGB data to CMYK data, coordinates (x, y, z), (x + 1, y, z), (x, y + 1, z) are based on the x, y, z values of the RGB data to be converted. ), (X + 1, y + 1, z), (x, y, z + 1), (x + 1, y, z + 1), (x, y + 1, z + 1), and (x + 1, y + 1, z + 1) 8 CMYK data from the memory Read out. An average value obtained by multiplying each YMCK data by a weighting coefficient calculated from the values r, g, and b of the lower 3 bits of the R, G, and B components is output as a conversion result.
[0007]
It should be noted that any point (or plane) of the tetrahedron obtained by dividing the cube composed of the eight lattice points having the eight coordinates as described above is a point having coordinates (x + r / 8, y + g / 8, z + b / 8). There is also known a color conversion circuit in which it is determined whether the point exists in the upper part) and an interpolation operation is performed using only YMCK data relating to the vertices of the tetrahedron in which the point exists.
[0008]
As described above, if the final output is obtained by the interpolation calculation, the color conversion circuit can be realized using a memory having a relatively small storage capacity. However, since such a color conversion circuit reads a plurality (4 or 8) of data from the memory at the time of data conversion, how many times it takes to read one data from the memory to convert one data. Such time is required, that is, high-speed conversion cannot be performed.
[0009]
For this reason, a technique that enables color data conversion at high speed by dispersing and holding color data used for interpolation calculation in a plurality of memories has been proposed. For example, US Pat. No. 4,837,722 discloses a digital high-speed three-dimensional interpolation device that converts a television signal (converted color data comprising 8-bit X, Y, and Z components) into RGB data (target color data). (Hereinafter simply referred to as an interpolator).
[0010]
This interpolator uses eight pieces of RGB data when obtaining RGB data from the color data to be converted. As shown in FIG. 15, RAMs 61 to 68 (RAMs # 0 to # 7) are added. Units 69 to 71, ROMs 72 to 79, multipliers 80 to 87, and adders 88 to 97. In the following description and drawings, XH4, YH4, and ZH4 indicate the upper 4 bits of the X, Y, and Z components of the luminance data to be converted, respectively. Also, XL1, YL1, and ZL1 indicate the fifth bit data of the luminance data to be converted (the least significant bit data of the upper 5-bit data), respectively. XF, YF, and ZF represent the lower 3 bits of the luminance data to be converted.
[0011]
The RAMs 61 to 68 (RAM # 0 to # 7) constituting the interpolation device are all accessed by a 12-bit address. In the RAMs # 0 to # 7, 32 × 32 × 32 pieces of RGB data are distributed and stored as follows. The RGB data stored in the RAMs # 0 to # 7 are all “0” in XF, YF, and ZF, and 2 × XH4 + XL1, 2 × YH4 + YL1, 2 × ZH4 + ZL1 (ie, X, Y , The upper 5-bit value of the Z component) is data that can be used as the conversion result of the color data to be converted, each of which is a value in the range of 0 to 31, and is associated with XL1, YL1, and ZL1. It has become.
[0012]
The RAM # 0 stores only RGB data related to the converted color data in which XL1, YL1, and ZL1 are all “0”. The RAM # 1 stores only RGB data related to converted color data in which XL1 is “1” and YL1 and ZL1 are both “0”. The RAM # 2 stores only RGB data related to converted color data in which YL1 is “1” and both XL1 and ZL1 are “0”. The RAM # 3 stores only RGB data relating to the color data to be converted in which XL1 and YL1 are “1” and ZL1 is “0”.
[0013]
The RAM # 4 stores only RGB data related to the converted color data in which XL1 and YL1 are “0” and ZL1 is “1”. The RAM # 5 stores only RGB data related to the converted color data in which XL1 and ZL1 are “1” and YL1 is “0”. The RAM # 6 stores only RGB data related to the converted color data in which YL1 and ZL1 are “1” and XL1 is “0”. The RAM # 7 stores only RGB data related to the converted color data in which XL1, YL1, and ZL1 are all “1”.
[0014]
That is, the RAM # 0 to # 7 include color data corresponding to the color data to be converted whose upper 5 bit values of X, Y, and Z are x, y, and z, and upper 5 bit values of X, Y, and Z. Color data corresponding to the converted color data for which x, y, z is x + 1, y, z; color data corresponding to the converted color data for which the upper 5 bit values of X, Y, Z are x, y + 1, z; Color data corresponding to converted color data whose upper 5 bit values of Y, Z are x + 1, y + 1, z and converted color data whose upper 5 bit values of X, Y, Z are x, y, z + 1 The corresponding color data, the color data corresponding to the color data to be converted whose X, Y, and Z upper 5 bit values are x + 1, y, and z + 1, and the upper 5 bit values of X, Y, and Z are x, y + 1, The color data corresponding to the converted color data that is z + 1, and the upper 5 bit values of X, Y, and Z are x + 1, y 1, in the form and color data corresponding to the converted color data is z + 1 can be read at the same time, total 32 × 32 × 32 pieces of color data are stored.
[0015]
As shown in the figure, in RAM # 0, “ZH4 + ZL1” (output of adder 69), “YH4 + YL1” (output of adder 70), and “XH4 + XL1” (output of adder 71) are combined. In addition, a 12-bit signal (arranged) is provided as an address signal. In addition, a signal obtained by combining “ZH4 + ZL1”, “YH4 + YL1”, and “XH4” is given to the RAM # 1 as an address signal. A signal obtained by combining “ZH4 + ZL1”, “YH4”, and “XH4 + XL1” is given to the RAM # 2 as an address signal. A signal obtained by combining “ZH4 + ZL1”, “YH4”, and “XH4” is supplied to the RAM # 3 as an address signal.
[0016]
In addition, a signal combining “ZH4”, “YH4 + YL1”, and “XH4 + XL1” is given to the RAM # 4 as an address signal. A signal obtained by combining “ZH4”, “YH4 + YL1”, and “XH4” is given to the RAM # 5 as an address signal. A signal obtained by combining “ZH4”, “YH4”, and “XH4 + XL1” is given to the RAM # 6 as an address signal. A signal obtained by combining “ZH4”, “YH4”, and “XH4” is given to the RAM # 7 as an address signal.
[0017]
Whether each bit of the signal related to XH4, YH4, and ZH4 is supplied to which bit of the address signal depends on the specific usage of each RAM, but according to the illustrated configuration, eight bits used for interpolation calculation RGB data can be output from the RAMs # 0 to # 7. For example, the RGB data related to each color data to be converted is stored at the address “16 × 16 × ZH4 + 16 × YH4 + XH4” obtained from XH4, YH4, ZH4 of the RAM determined as described above according to XL1, YL1, and ZL1. If stored, the signals related to XH4, YH4, and ZH4 are the lower, middle, and upper 4 bits of the address signal, respectively. RGB data is simultaneously output from RAM # 0 to RAM # 7.
[0018]
In the ROM #k (k = 0 to 7) provided in the interpolation device, the proportional coefficient to be multiplied by the output of the RAM #k is associated with XF, YF, ZF, XL1, YL1, and ZL1 (the 12-bit data). Is stored in the address). It should be noted that although a set of proportional coefficients (eight proportional coefficients) necessary for the interpolation calculation is data that can be calculated only from XF, YF, and ZF, they are also associated with XL1, YL1, and ZL1. This is because the RAM output to which the eight proportional coefficients obtained from XF, YF, and ZF are to be multiplied depends on the combination of XL1, YL1, and ZL1.
[0019]
As shown in the figure, the outputs of ROMs # 0 to # 7 are multiplied by the outputs of RAMs # 0 to # 7 by multipliers 80 to 87, respectively. The outputs of the multipliers 80 to 87 are added by a circuit including adders 88 to 94, and the addition result is output as a conversion result.
[0020]
U.S. Pat. No. 4,837,722, which discloses this interpolation device, describes RGB data stored in RAM # 0 and RAM # 7, RGB data stored in RAM # 1 and RAM # 6, and RAM #. 2 and RGB data stored in RAM # 5, and RGB data stored in RAM # 3 and RAM # 4, respectively, are provided with four memories, and four RGB data read from these memories are stored. An interpolator that performs the interpolation calculation used is also disclosed.
[0021]
[Problems to be solved by the invention]
According to the interpolating apparatus shown in FIG. 15, since eight data necessary for the interpolation calculation can be obtained simultaneously, the data can be converted at high speed. However, in this color conversion circuit, three types of 4-bit data (ZH4, ZH4 + ZL1, YH4, YH4 + ZL1, etc.) determined according to the color components X, Y, and Z are used as specific bits of addresses supplied to the RAM. ing. For this reason, for example, if a color conversion circuit for converting 24-bit converted color data into target color data, which is color data of another method, is configured using this technique, all converted colors Data conversion cannot be performed.
[0022]
That is, since such a color conversion circuit is provided with eight RAMs that are accessed by a 12-bit address signal, the color conversion circuit includes two RAMs. ¹² * 8 (= 32 * 32 * 32) pieces of target color data can be held. However, the target color data necessary for converting all the converted color data is the target color data related to the coordinates (0, 0, 0) to (32, 32, 32), that is, 33 × 33 × 33 in total. Therefore, converted color data that cannot be converted regardless of how the RAMs # 0 to # 7 are used will be generated.
[0023]
If the above color conversion circuit is modified so that 5-bit data used as part of the address is output for each color component X, Y, Z, all the converted color data is converted. Although a circuit that can be obtained is obtained, the color conversion circuit obtained by such modification is a circuit that requires mounting of a memory accessed by a 15-bit address.
[0024]
Accordingly, an object of the present invention is to provide a color conversion circuit that can convert color data to color data of other methods at high speed regardless of the content thereof, and can be manufactured using a small-capacity memory. There is to do.
[0025]
[Means for Solving the Problems]
In order to solve the above problems, the present invention employs the following configuration for the color conversion circuit.
[0026]
The color conversion circuit according to the first aspect of the present invention is a color conversion circuit for converting the color data to be converted, which is composed of n + m-bit first to third element data, into target color data representing the same color. And information (0, 0, 0) to (2) each consisting of three integer values. ⁿ 2 ⁿ 2 ⁿ (2) ⁿ +1) x (2 ⁿ +1) x (2 ⁿ +1) First to eighth memories, each of which is stored in a distributed manner and is accessed by an address signal of “3 × n−2” bits, are associated with each memory. First to eighth memories in which a plurality of target color data having equal combinations of three kinds of integer values constituting information are stored, and first to third element data constituting converted color data Information (x, y, z), (x, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1) based on the upper n-bit values x, y, z, respectively. , Y, z), (x + 1, y, z + 1), (x + 1, y + 1, z), and eight target color data associated with (x + 1, y + 1, z + 1) from the first to eighth memories. An address that generates eight "3xn-2" bit addresses for reading. The address generation circuit, at least four target color data among the eight target color data stored in the addresses generated by the address generation circuit in the first to eighth memories, and the first of the converted color data. Or a target color data generation / output circuit that generates and outputs target color data corresponding to the color data to be converted by interpolation using lower m bits of the third element data.
[0027]
That is, in the color conversion circuit according to the first aspect of the present invention, as means for storing target color data which is color data to be output as a conversion result, it is accessed with an address signal of “3 × n−2” bit width. Eight memories (first to eighth memories) are used. These memories include (0, 0, 0) to (2 ⁿ 2 ⁿ 2 ⁿ (2) ⁿ +1) x (2 ⁿ +1) x (2 ⁿ +1) target color data are (x, y, z), (x, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), ( 8 target color data associated with (x + 1, y, z + 1), (x + 1, y + 1, z), (x + 1, y + 1, z + 1) are stored in a form that can be read simultaneously regardless of x, y, z. The
[0028]
When the color data to be converted is converted to the target color data, the address generation circuit converts the values n, x, y, and z of the upper n bits of the first to third element data constituting the color data to be converted. Based on the information (x, y, z), (x, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), (x + 1, y, z + 1), (x + 1, y + 1, z), eight target color data corresponding to (x + 1, y + 1, z + 1) are read out from eight types of “3 × n−” A 2 "-bit address is generated, and the target color data generation / output circuit generates at least four target color data out of the eight target color data specified by the address generated by the address generation circuit, and is converted First to third element data of color data By interpolation calculation using the lower m bits of data the data is performed, target color data corresponding to the converted color data is generated and outputted.
[0029]
As described above, the color conversion circuit according to the first aspect of the present invention obtains a number of target color data that can be interpolated for all the converted color data, and a plurality of target color data required for the interpolation calculation. Since the data is stored in a form that can be read from the memory at the same time, the color data (converted color data) can be converted to color data (target color data) of another method at high speed regardless of the contents. Further, the present color conversion circuit includes eight memories that are accessed by “3 × n−2” bit addresses in which color data is stored, and “3 × n−2” bit 8 that is supplied to these memories. There is provided an address generation circuit for generating seed addresses from three kinds of components (first to third element data) of the color data to be converted and the upper n-bit data of each. Therefore, this color conversion circuit is a conventional color conversion circuit in which a part of the address (specific multiple bits) for reading the target color data is created independently for each component of the color data to be converted (FIG. 15). It is possible to manufacture using a memory having a smaller storage capacity than that of (see).
[0030]
The address generation circuit used in the color conversion circuit according to the first aspect of the present invention may be a memory or an arithmetic circuit (a circuit that generates an address by calculation).
[0031]
However, when the address generation circuit is realized by an arithmetic circuit, the operation speed of the arithmetic circuit is slower than the operation speed of the memory. Therefore, the conversion speed of the color data to be converted by the color conversion circuit is equal to the operation speed of the address generation circuit (or The operation speed of the target color data generation / output circuit) is limited. Accordingly, when conversion of the color data to be converted at a speed higher than the operation speed of the address generation circuit (or target color data generation / output circuit) is required, the second and third aspects of the present invention described below are used. It is desirable to use the color conversion circuit of the aspect.
[0032]
In the color conversion circuit of the second aspect of the present invention, the color data to be converted, each of which is input every time T and is composed of n + m-bit first to third element data, sequentially represents the same color. Each of which is a color conversion circuit for converting to information (0, 0, 0)-(2 ⁿ 2 ⁿ 2 ⁿ (2) ⁿ +1) x (2 ⁿ +1) x (2 ⁿ +1) First to eighth memories, each of which is stored in a distributed manner and is accessed by an address signal of “3 × n−2” bits, are associated with each memory. First to eighth memories in which a plurality of target color data having the same odd combination of three kinds of integer values constituting information are stored, and inputted converted color data are fetched every 2T. A first capture circuit that outputs the converted color data, and a second capture circuit that captures the input converted color data every time 2T and outputs the captured converted color data. After the conversion color data is acquired by the one acquisition circuit, the second acquisition circuit that acquires the conversion color data after time T and the conversion color data output from the first acquisition circuit are configured. Value n of upper n bits of first to third element data Based on y and z, information (x, y, z), (x, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), ( x + 1, y, z + 1), (x + 1, y + 1, z), and eight target color data corresponding to (x + 1, y + 1, z + 1) are read out from the first to eighth memories. A first address generation circuit for generating an address of 3 × n−2 ″ bits, and a value x of upper n bits of the first to third element data constituting the color data to be converted output from the second fetch circuit , Y, z, information (x, y, z), (x, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), respectively. (X + 1, y, z + 1), (x + 1, y + 1, z), (x + 1, y + 1, z + 1) A second address generation circuit for generating eight types of “3 × n−2” bit addresses for reading out eight target color data from the first to eighth memories, and a first address generation circuit or a second address generation circuit; When an address is generated by the address generation circuit, at least four types of target color data among the target color data stored in the generated addresses of the first to eighth memories and the addresses are generated. Generate target color data corresponding to the color data to be converted and output the target color data by interpolation using the lower m bits of the three types of color element data of the color data to be converted And an output circuit.
[0033]
That is, in the color conversion circuit according to the second aspect of the present invention, as in the color conversion circuit according to the first aspect, “3 ×” is used as means for storing target color data that is color data to be output as a conversion result. Eight memories (first to eighth memories) accessed by an address signal having an n-2 "bit width are used. These memories include (0, 0, 0) to (2 ⁿ 2 ⁿ 2 ⁿ (2) ⁿ +1) x (2 ⁿ +1) x (2 ⁿ +1) target color data are (x, y, z), (x, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), ( 8 target color data associated with (x + 1, y, z + 1), (x + 1, y + 1, z), (x + 1, y + 1, z + 1) are stored in a form that can be read simultaneously regardless of x, y, z. The
[0034]
In addition, the circuit composed of the first capture circuit and the first address generation circuit, and the circuit composed of the second capture circuit and the second address generation circuit alternately process the color data to be converted input to the color conversion circuit. The eight “3 × n−2” bit addresses for reading out the eight target color data that can be used to convert the color data to be converted from the first to eighth memories. Generate. The target color data generation / output circuit generates at least four target color data out of the eight target color data specified by the address generated by the first or second address generation circuit and its address. The target color data corresponding to the converted color data is generated and output by performing an interpolation operation using the lower m bits of the first to third element data of the converted color data used for the conversion. .
[0035]
Accordingly, the color conversion circuit according to the second aspect of the present invention, as with the color conversion circuit according to the first aspect, converts color data (converted color data) into color data (objective) of any other type regardless of the content. Color data) at a high speed, and can be manufactured using a memory having a smaller storage capacity than a conventional color conversion circuit.
[0036]
The color conversion circuit according to the second aspect of the present invention includes two systems corresponding to the address generation circuit used in the color conversion circuit according to the first aspect, and the circuit to be supplied to the color conversion circuit by them. Since the addresses corresponding to the conversion color data are generated alternately, the conversion of the color data to be converted can be performed at a higher speed (at a speed not limited by the operation speed of each address generation circuit).
[0037]
When realizing the color conversion circuit according to the second aspect, as the target color data generation / output circuit, either the address generated by the first address generation circuit or the address generated by the second address generation circuit is used. An address selection supply circuit for supplying to the first to eighth memories, and when an address is generated by the first address generation circuit, supply of the address to the first to eighth memories is started. When an address is generated by the 2-address generation circuit, an address selection supply circuit that starts supplying the address to the first to eighth memories, and eight target colors output from the first to eighth memories Interpolation calculation data, which is data consisting of data, is fetched every 2T, and the first interpolation calculation data fetch circuit that outputs the fetched interpolation calculation data , A second interpolation calculation data fetching circuit for fetching interpolation calculation data every time 2T and outputting the fetched interpolation calculation data, wherein the interpolation calculation data by the first interpolation calculation data fetching circuit Interpolation calculation output by the second interpolation calculation data fetch circuit that fetches the interpolation calculation data after time T and the first interpolation calculation data fetch circuit of the first to eighth memories after the fetch. By performing an interpolation operation using at least four types of target color data included in the image data and lower m-bit data of the three types of color element data of the converted color data that is the source of the interpolation calculation data, Included in the interpolation calculation data output from the first interpolation color data generation circuit for generating the target color data corresponding to the color data to be converted and the second interpolation calculation data fetch circuit of the first to eighth memories. At least 4 Corresponding to the converted color data by interpolation using the target color data and the lower m-bit data of the first to third color element data of the converted color data that is the basis of the interpolation calculation data A second target color data generation circuit for generating target color data to be output, target color data generated by the first target color data generation circuit, or target color data generated by the second target color data generation circuit When the target color data is generated by the first target color data generation circuit, the output of the target color data is started, and the target color data is generated by the first target color data generation circuit. And a selection output circuit for starting output of the target color data can be used.
[0038]
That is, the color conversion circuit of the second aspect may be configured so that the processing after the target color data is read out is alternately realized by two systems of circuits. According to the color conversion circuit having this configuration, the conversion of the color data to be converted is not limited by the operation speed of the address generation circuit and the target color data generation circuit (in practice, the speed is the same as the data read speed from the memory). It can be done with.
[0039]
In the color conversion circuit of the fourth aspect of the present invention, the target color data representing the same color in turn for the converted color data composed of the first to third element data of n + m bits, which are input every time T, respectively. Each of which is a color conversion circuit for converting to information (0, 0, 0)-(2 ⁿ 2 ⁿ 2 ⁿ (2) ⁿ +1) x (2 ⁿ +1) x (2 ⁿ +1) First to eighth memories, each of which is stored in a distributed manner and is accessed by an address signal of “3 × n−2” bits, are associated with each memory. First to eighth memories in which a plurality of target color data having the same odd combination of three kinds of integer values constituting information are stored, and first to second memories constituting input converted color data Information (x, y, z), (x, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1) based on the upper n-bit values x, y, z of the three element data, respectively. ), (X + 1, y, z), (x + 1, y, z + 1), (x + 1, y + 1, z), (x + 1, y + 1, z + 1), the first to first 8 "3xn-2" bit addresses to read from 8 memories Interpolating calculation data, which is data composed of eight target color data output from the first to eighth memories by supplying an address generated by the address generating circuit and an address generated by the address generating circuit, for a time 2T. First interpolation calculation data fetching circuit that fetches every time and fetches the fetched interpolation calculation data, and second interpolation calculation that fetches the interpolation calculation data every 2T and outputs the fetched interpolation calculation data A data acquisition circuit, a second interpolation calculation data acquisition circuit for acquiring the interpolation calculation data after time T after the interpolation calculation data is acquired by the first interpolation calculation data acquisition circuit; At least four types of target color data included in the interpolation calculation data output from the first interpolation calculation data fetch circuit in the first to eighth memories and the source of the interpolation calculation data A first target color data generation circuit that generates target color data corresponding to the color data to be converted by interpolation using the lower m bits of the three types of color element data of the color data to be converted; Or at least four types of target color data included in the interpolation calculation data output from the second interpolation calculation data fetch circuit in the eighth memory, and the converted color data that is the basis of the interpolation calculation data. A second target color data generation circuit for generating target color data corresponding to the color data to be converted by interpolation using the lower m bits of the first to third color element data; and first target color data A selection output circuit that outputs either target color data generated by the generation circuit or target color data generated by the second target color data generation circuit, the first target color data generation circuit Selective output circuit that starts output of the target color data when the target color data is generated, and starts output of the target color data when the target color data is generated by the first target color data generation circuit With.
[0040]
That is, the color conversion circuit according to the third aspect of the present invention has a configuration in which only the processing after the target color data is read out is realized alternately by two circuits. According to the color conversion circuit having this configuration, the color data to be converted can be converted at a speed that is not limited by the operation speed of the target color data generation circuit.
[0041]
When the color conversion circuit of each aspect of the present invention is realized in the form of n = 5, each of the first to eighth memories is associated with information (a, b, c). The color data can be stored in the address “17 × 17 × INT (a / 2) + 17 × INT (b / 2) + INT (c / 2)”. In this way, the address generation circuit can be realized with a relatively simple arithmetic circuit.
[0042]
In addition, the color conversion circuit according to the fourth aspect of the present invention is a color conversion circuit for converting the color data to be converted comprising the first to third element data of n + m bits into the target color data representing the same color. These are first to fourth memories accessed by an address signal of “3 × n−1” bits, and information (0, 0, 0) to (2) consisting of three kinds of integer values. ⁿ 2 ⁿ 2 ⁿ (2) ⁿ +1) x (2 ⁿ +1) x (2 ⁿ +1) target color data constitutes first to fourth memory in which four color data that may be used simultaneously for interpolation calculation are stored in a form that can be read simultaneously, and converted color data Four types of “3 × n−1” bits for reading out the four target color data used for the interpolation calculation from the first to fourth memories based on the upper n bits of the first to third element data An address generation circuit for generating the addresses, four target color data stored in the addresses generated by the address generation circuit in the first to fourth memories, and first to third element data of the converted color data And a target color data generation / output circuit for generating and outputting target color data corresponding to the color data to be converted by interpolation using the lower-order m-bit data.
[0043]
As described above, the color conversion circuit according to the fourth aspect of the present invention holds the number of target color data that can be interpolated for all the converted color data in four memories. For this reason, color data (converted color data) can be converted to color data (target color data) of another method at high speed regardless of the content. Further, this color conversion circuit includes four memories that are accessed by “3 × n + 2” bit addresses in which the color data to be converted is stored, and four types of “3 × n + 2” bits that are supplied to these memories. Are generated from the upper n-bit data of the three types of components (first to third element data) of the color data to be converted. Therefore, this color conversion circuit is a conventional color conversion circuit in which a part of the address (specific multiple bits) for reading the target color data is created independently for each component of the color data to be converted (FIG. 15). It is possible to manufacture using a memory having a smaller storage capacity than that of (see).
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be specifically described below with reference to the drawings.
[0045]
A color conversion circuit according to an embodiment of the present invention converts 24-bit RGB data composed of 8-bit R, G, and B components into 32-bit CMYK data (hereinafter referred to as color data). It is a circuit for.
[0046]
As shown in FIGS. 1 and 2, the color conversion circuit includes two address generation blocks 11a and 11b, an address switching unit 12, an address buffer 13, a memory unit 14, a data buffer 15, and two interpolation operation blocks 16a and 16b. A data switching unit 17 and an output buffer 18 are provided.
[0047]
The memory unit 14 (FIG. 1) is a unit that stores 33 × 33 × 33 pieces of color data D (0, 0, 0) to (32, 32, 32) used for interpolation calculation, and includes eight memories (MEM). ) # 0 to # 7. Each memory #k (k = 0 to 7) is a memory accessed by an address signal having a 13-bit width, and each of the memories # 0 to # 7 is a part of the output ADRS of the address buffer 13. Some address signals ADM0 to ADM7 are supplied.
[0048]
The color data D (x, y, z) stored in the memory unit 14 includes the lower 3 bits of the R component (hereinafter referred to as r), the lower 3 bits of the G component (hereinafter referred to as g), The lower 3 bits of the B component (hereinafter referred to as b) are all “0”, the upper 5 bits of the R component (hereinafter referred to as uR), and the upper 5 bits of the G component (hereinafter referred to as uG). The upper 5 bits of the B component (hereinafter referred to as uB) are CMYK data corresponding to RGB data of x, y, and z, respectively. However, the color data D (x, y, z) in which any of x, y, z is “32”, r, g, b are all “0”, and uR, uG, uB are respectively , X, y, and z are CMYK data corresponding to virtual RGB data (uR, uG, and uB cannot take 32). That is, the color data D (x, y, z) whose x, y, z is “32” is not CMYK data corresponding to existing RGB data, and any of uR, uG, uB is “ This is CMYK data prepared to obtain CMYK data corresponding to RGB data of 31 ″ by interpolation calculation.
[0049]
Each memory in the memory unit 14 stores these color data in the form as shown in FIGS.
[0050]
That is, as shown in FIG. 3, the memory # 0 includes 17 × 17 × 17 pieces of color data D (x, y, z) in which x, y, and z are all even numbers of 0 or more and 33 or less. z) are stored in the form sorted in ascending order of x, ascending order of y, and ascending order of z. In the memory # 1, 17 × 17 × 17 color data D (x, y, x, y are even numbers of 0 or more and 33 or less, and z is an odd number of 0 or more and 33 or less. z) is stored in the form sorted in ascending order of x, y, z. In the memory # 2, color data D (x, y, z) where x and z are even numbers of 0 or more and 33 or less and y is an odd number of 0 or more and 33 or less is x, y, z Are stored in an ascending order. In the memory # 3, color data D (x, y, z) where x is an even number of 0 to 33 and y and z are odd numbers of 0 to 33 is stored in x, y, z. Are stored in an ascending order.
[0051]
Further, as shown in FIG. 4, the memory # 4 includes color data (x, y, x) in which x is an odd number from 0 to 33 and y and z are even numbers from 0 to 33. z) is stored in the form sorted in ascending order of x, y, z. In the memory # 5, color data D (x, y, z) in which x and z are odd numbers from 0 to 33 and y is an even number from 0 to 33 is stored in x, y, z Are stored in an ascending order. In the memory # 6, color data D (x, y, z) in which x and y are odd numbers from 0 to 33 and z is an even number from 0 to 33 is stored in x, y, z Are stored in ascending order. In the memory # 7, color data D (x, y, z) in which x, y, z are all odd numbers from 0 to 33 are sorted in ascending order of x, y, z. It is remembered.
[0052]
That is, only the color data D (0, 0, 0) to D (32, 32, 32) is necessary for the conversion of RGB data, but the data is stored in the memory unit 14 (memory # 0 to # 7). A storage area for color data D (x, y, z) that is not actually used and any of x, y, z is “33” is also prepared. The reason why these storage areas are prepared will be described later.
[0053]
The memory unit 14 includes D (uR, uG, uB), D (uR, uG, uB + 1), D (uR, uG + 1, uB), D (uR, uG + 1, uB + 1), D (uR + 1, uG, uB), D (uR + 1, uG, uB + 1), D (uR + 1, uG + 1, uB), and D (uR + 1, uG + 1, uB + 1) for any uR, uG, uB combination memory # 0- # 7 Color data D (0, 0, 0) to (the color data is stored in different memories because the odd / even combinations of uR, uG, and uB are different from each other). D (32, 32, 32) is stored.
[0054]
In other words, when the memory unit 14 considers lattice points whose coordinate values are integers in a three-dimensional space having R / 8, G / 8, and B / 8 coordinate axes, as shown in FIG. Eight lattice points P0 to P7 in a positional relationship, that is, points P whose positions are represented by coordinates (uR + r / 8, uG + g / 8, uB + b / 8). _RGB 8 units of color data associated with the coordinates of the eight vertices P0 to P7 of a unit grid including the following (hereinafter referred to as the unit cell of interest) can be read simultaneously from the memories # 0 to # 7, and the vertex P0 As shown in Table 1, the memory in which the color data related to .about.P7 is stored is a unit determined according to the odd / even of uR, uG, uB (coordinates of the lattice point P0).
[0055]
[Table 1]

[0056]
Returning to FIG. 1, the description of the color conversion circuit will be continued. The address generation block 11x (x = a, b) is an address signal ADRSx for causing the memory unit 14 to output eight color data (hereinafter referred to as interpolation calculation color data) associated with the vertices P0 to P7. Is a block that generates As illustrated, the address generation block 11x includes two AND gates 21x and 22x, an OR gate 23x, a buffer 24x (latch), and an address generation unit 25x.
[0057]
Each of the AND gates 21x and 22x is a two-input gate that receives a signal having a width of 24 bits. The AND gate 21x includes an RGB signal (RGB data) supplied to the color conversion circuit and a control signal ENAx. Have been supplied. The RGB signal supplied to the color conversion circuit is a signal whose contents (RGB data represented by the signal) change in the input period T, and the control signal ENAx is in a state where all bits are “0”. The signal is a 24-bit width signal having a period 2T that alternately takes a state in which all bits are “1”. A clock signal CLK having a period T (not shown) is supplied to each buffer included in the color conversion circuit. The timing at which each signal changes will be described later.
[0058]
The AND gate 22x receives an output of the buffer 24x and a signal obtained by inverting ENAx. The output of the AND gate 22x and the output of the AND gate 21x are input to an OR gate 23x that is a two-input gate. The output of the OR gate 23x is input to a buffer 24x that operates according to a clock signal CLK (not shown), and the output of the buffer 24x is fed back to the AND gate 22x.
[0059]
Then, r, g, b, uR [0] (the least significant bit of uR), uG [0], and uB [0] included in the output of the buffer 24x are output from the address generation block 11x as the signal BUFF1x. ing. That is, a 12-bit width signal composed of the lower 4 bits of the R component of the RGB signal (RGB data), the lower 4 bits of the G component, and the lower 4 bits of the B component is output as BUFF1x.
[0060]
A 15-bit width signal BUFF0x consisting of uR, uG, uB (upper 5 bits of R, G, B components) included in the output of the buffer 24x is input to the address generator 25x. The address generation unit 25x is a circuit that actually generates an address signal ADRSx for causing the memory unit 14 to output interpolation calculation color data.
[0061]
Hereinafter, the configuration and operation of the address generator 25x (x = a, b) will be described in detail with reference to FIGS. FIG. 6 is a diagram showing the overall configuration of the address generator 25x, and FIG. 7 shows an address selector 42 provided in the address generator 25x. ₀ FIG. FIG. 8 shows an address selector 42 provided in the address generator 25x. ₁ ~ 42 ₇ It is explanatory drawing of this structure.
[0062]
As shown in FIG. 6, the address generator 25x includes an address calculator 41 and eight address selectors 42. ₀ ~ 42 ₇ It consists of. BUFFx0 (that is, uR, uG, and uB) from the buffer 24x is supplied to the address calculation unit 41. Further, uR [0], uG [0], and uB [0] included in BUFFx0 are address selectors 42. ₀ ~ 42 ₇ Has also been supplied.
[0063]
The address calculation unit 41 is a 13-bit signal based on the supplied uR, uG, uB (coordinate values of the vertex P0 of the unit cell of interest), and the relationship with uR, uG, uB is as follows: Address signals ADP0 to ADP7 that can be expressed by equations (1) to (8) are output.
[0064]
[Expression 1]

[0065]
That is, the address calculation unit 41 is a circuit that outputs address signals ADP0 to ADP7 representing the color data addresses of the vertices P0 to P7. However, even if the address signals ADP0 to ADP7 output from the address calculation unit 41 are supplied to the memories # 0 to # 7, the color data of the vertices P0 to P7 may not be read (interpolation calculation). The signal is required to be rearranged in order to obtain ADMO to ADM7 for outputting the color data for use.
[0066]
Here, ADPk (k = 0 to 7) represented by the above formula is an address of a memory in which color data related to the vertex Pk of the unit cell of interest is stored, and x, y are stored in each memory. The reason why a storage area for color data D (x, y, z) that is not actually used and any of z and “z” is “33” will be briefly described.
[0067]
Each memory in the memory unit 14 is used in the form already described (see FIGS. 3 and 4 and Table 1). That is, in the memory #K (K = 0 to 7), color data D (x, x, y, z are in the range of 0-33, respectively, and the odd combinations of x, y, z are equal. , Y, z) are sorted and stored in ascending order of x, y, z. As described above, since the storage area for the color data D (x, y, z) that is not actually used and any of x, y, z is “33” is prepared, the memory #K The z value of the color data stored in the i th storage area is equal to the z value of the color data stored in the “i + 17” th storage area. Further, the y value of the color data stored in the i-th storage area of the memory #K is equal to the y value of the color data stored in the “i + 17 × 17” -th storage area.
[0068]
Accordingly, the address AD of the color data D (uR, uG, uB) stored in the memory # 0 and having all even numbers of uR, uG, uB can be expressed by the following equation.
[0069]
[Expression 2]

[0070]
When uD (= uR, uG, or uB) is an even number, since uD / 2 = INT (uD / 2) holds, AD calculated by this equation (9) is expressed by the above equation (1). It matches the calculated ADP0. That is, equation (1) is an equation indicating the address of the memory (in this case, memory # 0) in which D (uR, uG, uB) is stored when uR, uG, uB are even numbers. ing.
[0071]
Next, consider a case where uR and uG are even and uB is odd. In this case, D (uR, uG, uB) is stored in the memory # 1, and the address AD can be expressed by the following equation.
[0072]
[Equation 3]

[0073]
When uR and uG are even numbers, uR / 2 = INT (uR / 2) and uG / 2 = INT (uG / 2) hold, and when uB is odd, (uB-1) / 2 = INT (uB / 2) is established. Therefore, in the above equation (1), when uR and uG are even and uB is odd, the memory (in this case, memory # 1) in which D (uR, uG, uB) is stored is stored. It is also an expression indicating an address.
[0074]
The relationship between the address AD and uR, uG, uB when D (uR, uG, uB) is stored in the memories # 2 to # 7 is also a kind of the equation (9), such as the equation (10). The above variables (uR and the like) can be expressed by an expression in which the variables are subtracted by “1” (such as “uR-1”). When uD (= uR, uG, or uB) is an even number, (uD / 2) = INT (uD / 2) is established, and when uD is an odd number, (uD / 2) = INT (( Since uD-1) / 2) is established, the color data D (uR) is eventually obtained from the equation (1) regardless of the odd / even of uR, uG, uB (for any combination of uR, uG, uB). , UG, uB) can represent the address of the memory (any one of the memories # 0 to # 7).
[0075]
Further, the expression (2) is obtained by replacing uR, uG, and uB in the expression (1) with uR + 1, uG, and uB, respectively, and (uR + 1, uG, uB) is the coordinates of the vertex P1 ( FIG. 5). Then, as described above, the expression (1) is obtained by storing the color data D (uR, uG, uB) for any combination of uR, uG, uB (memory # 0 to # 7). Any one address), so that the memory (any one of the memories # 0 to # 7) in which the color data D (uR + 1, uG, uB) relating to the vertex P1 is stored according to the expression (2). The address of can be expressed.
[0076]
Similarly, the expressions (3) to (8) are also expressions using the coordinates of the vertices P2 to P7 in place of the coordinates of the vertex PO in the expression (1). Therefore, ADP0 to ADP7, which are output from the address calculation unit 41 and whose values can be expressed by the above-described equations (1) to (8), can be used to read D (P0) to D (P7), respectively. It will be.
[0077]
If the address of the color data can be expressed by the equations (1) to (8), the address calculation unit 41 can be realized by a logic circuit with a simple configuration, and any of x, y, and z is “33”. A storage area for color data D (x, y, z) that is not actually used is prepared in each memory.
[0078]
As shown in FIG. 6, ADP0 to ADP7 output by the address calculation unit 41 are address selectors 42 to which uR [0], uG [0], uB [0] are supplied. _k (K = 0 to 7).
[0079]
As shown in FIG. 7, the address selector 42 ₀ The eight AND gates 45 ₀ ~ 45 ₇ And eight selectors 46 ₀ ~ 46 ₇ And an OR gate 47. ANDGATE 45 ₀ ~ 45 ₇ Are three-input gates to which uR [0], uG [0], and uB [0] are input. However, ANDGATE 45 ₀ ~ 45 ₇ Respectively function as follows with respect to the input uR [0], uG [0], and uB [0].
[0080]
ANDGATE 45 ₀ Outputs “1” when uR [0], uG [0], and uB [0] are all “0”, and outputs “0” otherwise. ANDGATE 45 ₁ Outputs “1” when uR [0] and uG [0] are “0” and uB [0] is “1”, and outputs “0” otherwise. . ANDGATE 45 ₂ Outputs “1” when uR [0] and uB [0] are “0” and uG [0] is “1”, and outputs “0” otherwise. . ANDGATE 45 _Three Outputs “1” when uR [0] is “0” and uG [0] and uB [0] are “1”, and outputs “0” otherwise. .
[0081]
ANDGATE 45 _Four Outputs “1” when uR [0] is “1” and uG [0] and uB [0] are “0”, and outputs “0” otherwise. . ANDGATE 45 _Five Outputs “1” when uR [0] and uB [0] are “1” and uG [0] is “0”, otherwise outputs “0”. . ANDGATE 45 ₆ Outputs “1” when uR [0] and uG [0] are “1” and uB [0] is “0”, otherwise outputs “0”. . ANDGATE 45 ₇ Outputs “1” when uR [0], uB [0], and uG [0] are all “1”, and outputs “0” otherwise.
[0082]
ANDGATE 45 _k The output of (k = 0 to 7) is input as a control signal to the selector 46k. Selector 46 _k Further, an address signal ADPk from the address calculation unit 41 and a 13-bit width signal ZERO each bit of which is “0” are input to the selector 46. _k Outputs ADPk when the control signal is “1” (“H”), and outputs ZERO when the control signal is “0” (“L”).
[0083]
The OR gate 47 is a gate that outputs a 13-bit width signal obtained by ORing each bit of 8 types of 13-bit width signals. The OR gate 47 has a selector 46 ₁ ~ 46 ₇ The output of the OR gate 47 is the address selector 42. ₀ Output ADM0.
[0084]
That is, the address selector 42 ₀ Is a circuit that outputs any one of ADP0 to ADP7 as ADM0 according to the values of uR [0], uG [0], and uB [0]. More specifically, when uR [0], uG [0], and uB [0] are all “0” (when uR, uG, and uB are all even numbers), the AND gate 45 is used. ₀ Since only "1" is output, the address selector 42 ₀ From (OR gate 47), ADP0 is output as ADM0. That is, when uR, uG, and uB are all even numbers (when color data related to the vertex P0 is stored in the memory # 0; see Table 1), the address selector 42 ₀ Outputs, as ADM0, an address signal ADP0 representing an address where color data relating to the vertex P0 is stored.
[0085]
When uR [0] and uG [0] are “0” and uB [0] is “1” (when uR and uG are even and uB is odd), the AND gate 45 ₁ Since only "1" is output, the address selector 42 ₀ Outputs ADP1. That is, when uR and uG are even and uB is odd, the address selector 42 ₀ Is the address signal ADP1 relating to the color data D (P1) (when D (P0) is stored in the memory # 1, D (P1) is stored in the memory # 0; see Table 1). Output as.
[0086]
Further, when uR and uB are even numbers and uG is an odd number (when D (P0) is stored in the memory # 3), the address selector 42 ₀ Outputs the address signal ADP2 relating to the color data D (P2) as ADM0. The address selector 42 also applies to other odd / even combinations of uR, uG, and uB. ₀ Works the same way.
[0087]
That is, the address selector 42 ₀ Are addresses to be supplied to the memory # 0 from among the eight address signals ADP0 to ADP7 output from the address calculation unit 41 (for reading color data relating to the target unit cell stored in the memory # 0). This circuit selects and outputs a signal.
[0088]
Another address selector 42 in the address generator 25x ₁ ~ 42 ₇ The address selector 42 so that signals as shown in FIGS. 8 (1) to (7) are input to the AND gates 45, respectively. ₀ Is a modified circuit. That is, the address selector 42 _k (K = 1 to 7) is a circuit that selects and outputs an address signal to be supplied to the memory #k from the eight address signals ADP0 to ADP7 output by the address calculation unit 41.
[0089]
Then, as shown in FIG. 6, the address selector 42 ₀ ~ 42 ₇ 13 × 8 = 104 bit width signals (signals in which ADP0 to ADP7 are rearranged according to the odd / even combinations of uR, uG, and uB) output from the address generator 25x and the output ADRSx Has been.
[0090]
Returning to FIG. 1, the description of the color conversion circuit will be continued. From the address generation block 11x, the output of the address generation unit 25x is output as it is. The output ADRSa of the address generation block 11a and the output ADRSb of the address generation block 11b are input to the address switching unit 12. The address switching unit 12 is a circuit that outputs either ADRSa or ADRSb in response to a control signal ADSEL (details will be described later). The output of the address switching unit 12 is supplied to the memory unit 14 via the address buffer 13. Has been. Then, a 256-bit signal DATA consisting of outputs D0 to D7 of the memories # 0 to # 7 is supplied to the data buffer 15 (FIG. 2), and an output DBUFF of the data buffer 15 is supplied to the interpolation operation blocks 16a and 16b. Yes.
[0091]
Here, the overall operation of each unit described so far will be described with reference to the timing chart shown in FIG.
[0092]
As shown in FIGS. 9A and 9B, the present color conversion circuit is used by receiving an RGB signal whose contents change at a period equal to the period T of the clock CLK. As shown in FIG. 9 (3), ENAa input to the address generation block 11a is in an “H” state (all bits are “1”) in synchronization with the input period of RGB data. State) and “L” state (a state in which all bits are “0”). On the other hand, as shown in FIG. 9 (6), ENAb input to the address generation block 11b takes "L" state when ENAa is in "H" state, and ENAa is "L". When the signal is in the “state”, the signal takes the “H” state. Further, as shown in FIG. 9 (9), ADSEL is a signal having the same phase as ENAa.
[0093]
That is, the portions from the address generation blocks 11a and 11b to the data buffer 15 operate as follows.
[0094]
As is apparent from the configuration described above (FIG. 1), the OR gate 23a in the address generation block 11a outputs the RGB signal input to the color conversion circuit when ENAa is “H”.
[0095]
Therefore, as shown in FIG. 9, when the RGB signal represents RGB data (1) and ENAa is “H” at time t1, the buffer 24a is output from the OR gate 23a. RGB data {circle around (1)} is fetched and output of the fetched data is started. Thereafter, at time t2 (= t1 + T), the buffer 24a takes in the output of the OR gate 23a again. At this time, since ENAa is “L”, the output from the OR gate 23a, that is, the output of the buffer 24a, that is, RGB data (1) is output. For this reason, the buffer 24a continues to output data (RGB data (1)) having the same contents. Since ENAa is “H” at the next rising edge of CLK (t = t3), the buffer 24a stores the RGB data represented by the RGB signal input to the color conversion circuit at that time. Capture (3) and start outputting.
[0096]
Since the portion up to the buffer 24a in the address generation block 11a repeats such an operation, as shown in FIG. 9 (4), the buffer 24a eventually has the contents (signals) in the period of 2T as BUFF 1a. (Data represented by), and a part (uR) of every other RGB data (in the illustrated case, odd-numbered RGB data) in which each data is supplied to the color conversion circuit by an RGB signal. [0], uG [0], uB [0], r, g, b) are output. Further, as BUFF0a (not shown), a signal that changes in time similar to BUFF1a is output.
[0097]
The address generation block 11b is supplied with a signal ENAb obtained by inverting ENAa (which is 180 ° out of phase with ENAa). Therefore, as shown in FIG. 9 (7), the buffer 24b of the address generation block 11b is a signal whose contents (data) change in a cycle of 2T, and each data is supplied to the color conversion circuit. A signal BUFF1b that is a part of every other RGB data (in the illustrated case, RGB data with even numbers) is output. Also, as BUFF0b (not shown), a signal that changes in time similar to BUFF1b is output.
[0098]
Further, in each address generation block 11x, ADP0 to ADP7 are generated by arithmetic processing based on BUFF0x (uR, uG, uB), and these are generated as uR [0], uG [0], uB [0]. Rearranged according to the combination, ADRSx is generated.
[0099]
The address generator 25x is a circuit that requires time T or longer to generate this ADRSx. For this reason, as shown in FIG. 9 (5), the address generation block 11a is delayed by a predetermined time (> T) after the output of the buffer 24a (see FIG. 9 (4)) is stabilized (determined). Output of ADRSa is started. Further, as shown in FIG. 9 (8), after the output of the buffer 24b (see FIG. 9 (7)) is stabilized, the address generation block 11b starts outputting ADRSb with a predetermined time delay.
[0100]
The address switching unit 12 to which ADRSa and ADRSb are supplied outputs ADRSa when ADSEL is “H”, and outputs ADRSb when ADSEL is “L”. ADSEL is a signal having the same phase as ENAa, and the address buffer 13 takes in the output of the address switching unit 12 at the rising edge of CLK, and therefore, from the address buffer 13, as shown in FIG. A signal ADRS in which the data to be represented changes every time T and each data becomes the address of color data for interpolation calculation of RGB data input to the color conversion circuit approximately 2T hours before is output.
[0101]
Then, from the memory unit 14 to which the ADRS is input as an address signal, a signal DATA whose contents change at a timing as shown in FIG. 9 (11) is output. Since the data buffer 15 takes in the signal DATA in accordance with CLK, eventually, the data buffer 15 receives the interpolation calculation color data relating to each RGB data input to the color conversion circuit as shown in FIG. 9 (12). Then, a signal DBUFF expressed after a certain time from the input of the RGB data is output.
[0102]
Returning to FIG. 2, the description of the color conversion circuit will be continued.
[0103]
The output DBUFF of the data buffer 15 is input to the interpolation calculation blocks 16a and 16b. As illustrated, the interpolation calculation block 16x (x = a, b) includes two AND gates 31x and 32x, an OR gate 33x, a buffer 34x, an interpolation calculation unit 35x, and four buffers 36x to 39x. Each of the AND gates 31x and 32x is a two-input gate that receives a 256-bit width signal. The AND gate 31x includes a DBUFF from the data buffer 15 and a state in which all bits are “0”. The control signal DENax, which is a 256-bit width signal that takes one of the states of “1”, is input. On the other hand, the AND gate 32x is supplied with a signal obtained by inverting the output of the buffer 34x and DENAx. The output of the AND gate 31x and the output of the AND gate 32x are input to an OR gate 33x which is a two-input gate that receives a 256-bit width signal.
[0104]
The output of the OR gate 33x is input to a buffer 34x that operates according to CLK (not shown), and the output DBUFFx of the buffer 34x is supplied to both the AND gate 32x and the interpolation calculation unit 35x.
[0105]
Also, BUFF1x (uR [0], uG [0], uB [0], r, g, b), which is the output of the address generation block 11x, is input to the buffer 36x. The output BUFF2x of the buffer 36x is input to the buffer 37x, and the output BUFF3x of the buffer 37x is input to the buffer 38x. Then, the output BUFF 4x of the buffer 38x is input to the buffer 39x, and the output BUFF 5x of the buffer 39x is input to the interpolation calculation unit 35x. Note that these buffers 36x to 39x receive lower-order data (uR [0], uG [0], uB [0], r, g, b) of RGB data supplied as BUFF 5x to the interpolation calculation unit 35x, This is a circuit for matching the lower data of the RGB data that is the source of the color data D0 to D7 supplied as DBUFFx from the buffer 34x. That is, the interpolation calculation unit 35x performs interpolation read based on uR [0], uG [0], uB [0], r, g, b of certain RGB data and uR, uG, uB of the RGB data. Operates in response to input of calculation color data D0 to D7.
[0106]
FIG. 10 shows a configuration of the interpolation calculation unit 35x (x = a, b). As shown in the figure, the interpolation calculation unit 35x includes a data selector 51. ₀ ~ 51 ₇ A mode determination / coefficient calculation unit 52, a calculation data selector 53, and an output calculation unit 54. DBUFFx from the buffer 34x is supplied to each data selector 51. Also, uR [0], uG [0], and uB [0] included in BUFFx5 are the data selectors 51. ₀ ~ 51 ₇ R, g, and b included in BUFFx5 are supplied to the mode determination / coefficient operation unit 52.
[0107]
First, the data selector 51 included in the interpolation calculation unit 35x. ₀ ~ 51 ₇ The configuration and operation will be described. As shown in FIG. 11, the data selector 51 ₀ Address selector 26 so that D0 to D7 are used instead of ADP0 to ADP7. ₀ The circuit is a modification of FIG.
[0108]
That is, the data selector 51 ₀ Andgate 55 in ₀ Outputs “1” when uR [0], uG [0], and uB [0] are all “0”, and outputs “0” otherwise. Andgate 55 ₁ Outputs “1” when uR [0] and uG [0] are “0” and uB [0] is “1”, and outputs “0” otherwise. . Andgate 55 ₂ Outputs “1” when uR [0] and uB [0] are “0” and uG [0] is “1”, and outputs “0” otherwise. . Andgate 55 _Three Outputs “1” when uR [0] is “0” and uG [0] and uB [0] are “1”, and outputs “0” otherwise. .
[0109]
Andgate 55 _Four Outputs “1” when uR [0] is “1” and uG [0] and uB [0] are “0”, and outputs “0” otherwise. . Andgate 55 _Five Outputs “1” when uR [0] and uB [0] are “1” and uG [0] is “0”, otherwise outputs “0”. . Andgate 55 ₆ Outputs “1” when uR [0] and uG [0] are “1” and uB [0] is “0”, otherwise outputs “0”. . Andgate 55 ₇ Outputs “1” when uR [0], uB [0], and uG [0] are all “1”, and outputs “0” otherwise.
[0110]
Then, the data selector 51 ₀ Selector 56 in _k (K = 0 to 7) is AND gate 55 _k And the input of the color data Dk and a 32-bit wide signal ZERO each bit of which is “0”. _k ADPk is output when “1” is input from the AND gate 55 _k When “0” is input from ZERO, ZERO is output. Selector 56 ₁ ~ 56 ₇ (32-bit width signal) is input to the OR gate 57, and the output of the OR gate 57 is the data selector 51. ₀ Output D (P0).
[0111]
That is, the data selector 51 ₀ Operates as follows according to uR [0], uG [0], uB [0] values.
[0112]
When uR [0], uG [0], and uB [0] are all “0” (when uR, uG, and uB are even numbers), the data selector 51 ₀ (OR gate 57) outputs D0 as D (P0). That is, when the color data relating to the vertex P0 is stored in the memory # 0, the data selector 51 ₀ Outputs the color data DO read from the memory # 0 as D (P0).
[0113]
When uR [0] and uG [0] are “0” and uB [0] is “1” (when uR and uG are even numbers and uB is odd numbers), the data selector 51 ₀ Outputs D1 as D (P0). That is, when color data relating to the vertex P0 is stored in the memory # 1, the data selector 51 ₀ Outputs the color data D1 read from the memory # 1 as D (P0).
[0114]
When uR and uB are even numbers and uG is an odd number (when color data relating to the vertex P0 is stored in the memory # 2), the data selector 51 ₀ Outputs the color data D2 read from the memory # 2 as D (P0).
[0115]
The data selector 51 also applies to other odd / even combinations of uR, uG, and uB. ₀ Works the same way. That is, the data selector 51 ₀ Is the data related to the vertex P0 (the data related to the vertex P0 is stored based on the values of uR [0], uG [0], uB [0] among the eight data D0 to D7 read from the memory unit 14). This is a circuit that selects and outputs the output of the memory.
[0116]
Data selector 51 in the interpolation calculator 35x ₁ ~ 51 ₇ Respectively, so that the signals as shown in FIGS. 12 (1) to (7) are input to the AND gates 55, respectively. ₀ Is a modified circuit. That is, the data selector 51 _k (K = 1 to 7) has a configuration capable of selecting and outputting color data related to the vertex Pk from the eight color data D0 to D7 read from the memory unit 14.
[0117]
As shown in FIG. 10, the data selector 51 ₀ Output D (P0) and the data selector 51 ₇ The output D (P7) is input to the output calculation unit 54, which is a circuit that actually performs the interpolation calculation. On the other hand, the data selector 51 ₁ ~ 51 ₆ The outputs D (P1) to D (P6) are input to the calculation data selector 53.
[0118]
The mode determination / coefficient operation unit 52 to which r, g, and b are input outputs a signal mode and signals b0 to b3 having contents corresponding to those values. Specifically, the mode determination / coefficient calculation unit 52 functions as shown in Table 2 according to r, g, and b.
[0119]
[Table 2]

[0120]
That is, when r <g <b is satisfied, the mode determination / coefficient calculation unit 52 sets the signal mode indicating “1” and “8-b”, “gr”, “b”, respectively. The signals b0 to b3 representing -g "and" r "are output. When r <b ≦ g is satisfied, the signal mode indicating “2” and “8-g”, “gb”, “br”, and “r” are respectively indicated. Signals b0 to b3 are output.
[0121]
When g ≦ r <b is satisfied, the mode determination / coefficient calculation unit 52 outputs a signal mode representing “3”, and “8-b”, “b-g”, “r-g”, respectively. The signals b0 to b3 representing “,” “g” are output. When b ≦ r <g is established, the signal mode indicating “4” and “8-g”, “r-b”, “r-b”, and “b”, respectively, are expressed. Signals b0 to b3 are output.
[0122]
When g <b ≦ r is satisfied, the mode determination / coefficient calculation unit 52 determines the signal mode indicating “5” and “8-r”, “b-g”, “r-b”, Signals b0 to b3 representing “g” are output. When b ≦ g <r is satisfied, the signal mode indicating “4” and “8-r”, “r-g”, “g-b”, and “b”, respectively, are expressed. Signals b0 to b3 are output.
[0123]
The signal mode output from the mode determination / coefficient calculation unit 52 is input to the calculation data selector 53.
[0124]
The calculation data selector 53 is connected to the data selector 51. ₁ ~ 51 ₆ The two signals corresponding to the signal mode among D (P1) to D (P6) supplied from are output as DA and DB. Specifically, the calculation data selector 53 functions as shown in Table 3 according to the signal mode.
[0125]
[Table 3]

[0126]
That is, when the signal mode represents “1”, the calculation data selector 53 outputs D (P3) as the signal DA and outputs D (P1) as the signal DB. When the mode is “2”, D (P2) is output as the signal DA and D (P3) is output as the signal DB.
[0127]
When the mode is “3”, the calculation data selector 53 outputs D (P1) as the signal DA and outputs D (P5) as the signal DB. When the mode is “4”, D (P6) is output as the signal DA and D (P2) is output as the signal DB.
[0128]
When the mode is “5”, D (P5) is output as the signal DA and D (P4) is output as the signal DB. If the mode represents “6”, the calculation data selector 53 outputs D (P4) as the signal DA and outputs D (P6) as the signal DB.
[0129]
DA and DB output from the calculation data selector 53, b0 to b3 output from the mode determination / coefficient calculation unit 52, and the data selector 51 ₀ , 51 ₇ The output calculation unit 54 to which the outputs D (P0) and D (P7) are input outputs a 32-bit signal OUTx whose content (value) is expressed by the following equation.
[0130]
[Expression 4]

[0131]
Here, the physical meaning of the above-described operations of the mode determination / coefficient calculation unit 52, the calculation data selector 53, and the output calculation unit 54 will be described with reference to FIG.
[0132]
The signal mode output from the mode determination / coefficient calculation unit 52 is a point P whose position is indicated by coordinates (uR + r / 8, uG + g / 8, uB + b / 8). _RGB (See FIG. 5) is a signal indicating which of the six tetrahedrons shown in FIGS. 13 (1) to (6) is obtained by dividing the unit cell of interest. Specifically, the mode determination / coefficient calculation unit 52 _RGB Are included in the tetrahedron shown in FIGS. 13 (1) to (6), and signal modes indicating "1" to "6" are output, respectively.
[0133]
The selection output of the color data corresponding to the mode performed in the calculation data selector 53 is the point P out of the color data related to the vertices P1 to P6. _RGB Is selected and output for color data relating to two vertices excluding the vertices P0 and P7 among the four vertices of the tetrahedron in which the. Note that D (P0) and D (P7) are not the color data selected according to the signal mode, as shown in FIG. This is because it is divided into six tetrahedrons including vertices P0 and P7.
[0134]
Since b0 to b3 output from the mode determination / coefficient calculation unit 52 are signals representing data that can be used as weighting coefficients for interpolation calculation by multiplying by 1/8, the output calculation unit 54 Thus, the CMYK data, which is the conversion result of the RGB data, is obtained by the calculation according to the above equation (11).
[0135]
Returning to FIG. 2, the remaining configuration of the color conversion circuit will be described. As illustrated, the signals OUTa and OUTb output from the interpolation calculation blocks 16 a and 16 b are input to the data switching unit 17. The data switching unit 17 is a circuit that outputs either OUTa or OUTb in response to the control signal DATASEL. The output of the data switching unit 17 is input to the output buffer 18, and the output of the output buffer 18 is a signal OUT that is the output of the color conversion circuit.
[0136]
The overall operation of the color conversion circuit after the interpolation operation blocks 16a and 16b will be described below with reference to FIG.
[0137]
As shown in FIG. 9 (13), the control signal DENAa supplied to the interpolation calculation block 16a is a signal having the same phase as the control signal ENAa. On the other hand, the control signal DENAb supplied to the interpolation calculation block 16b is a signal obtained by inverting DENAb as shown in FIG. 9 (20). Further, the control signal OUTSEL supplied to the data switching unit 17 is a signal having the same phase as DENAa as shown in FIG. 9 (27).
[0138]
The circuit composed of the AND gates 31a and 32a, the OR gate 33a, and the buffer 34a in the interpolation calculation block 16a has the same configuration as the circuit composed of the AND gates 21x and 22x, the OR gate 23x, and the buffer 24x in the address generation block 11x. is doing. Therefore, as shown in FIG. 9 (14), the buffer 34a is a signal whose contents (data represented by the signal) change every 2T, and each data is an interpolation calculation regarding odd-numbered RGB data. The signal DBUFFa that has become color data is output.
[0139]
On the other hand, the buffer 36a to which the BUFF 1a (FIG. 9 (4)) is input takes in the BUFF 1a according to CLK. Therefore, the output BUFF2a of the buffer 36a is a signal obtained by delaying the BUFF1a by the time T as shown in FIG. Further, the output BUFF 3a of the buffer 37a to which the BUFF 2a is input is a signal obtained by delaying the BUFF 2a by the time T as shown in FIG. 9 (16), and the output BUFF 4a of the buffer 38a to which the BUFF 3a is input is 9 (17), the signal is a signal obtained by delaying BUFF 3a by time T.
[0140]
As a result, the output BUFF 5a of the buffer 39a to which the BUFF 4a is input, that is, the BUFF 5a input to the interpolation calculation unit 35a, is a signal obtained by delaying the BUFF 1a by time 5T as shown in FIG. 9 (18). That is, r, g, b, uR [0], uG [0], and uB [0] related to a certain RGB data are converted into color data for interpolation calculation related to the RGB data (FIG. 9 (14)). At the same time, it is controlled so as to be supplied to the interpolation calculation unit 35x.
[0141]
The interpolation calculation unit 35a converts r, g, b, uR [0], uG [0], uB [0], and interpolation calculation color data related to certain RGB data, which are simultaneously input, to the RGB data. Corresponding CMYK data is obtained by interpolation calculation. Therefore, as shown in FIG. 9 (19), the signal OUTa output from the interpolation calculation unit 35a is a signal representing the conversion result of each input RGB data (odd-numbered RGB data), and is interpolated. After the input of new data (FIGS. 9 (14) and (18)) to the calculation unit 35a, the content becomes a signal that is finalized when the time required for the calculation has elapsed.
[0142]
In the interpolation calculation block 16b, the same processing as the interpolation calculation block 16a is performed on the signal BUFF0a from the address generation block 11b and the signal DBUFF from the data buffer 15. That is, the outputs BUFF2b to BUFF5b of the buffers 36b to 39b in the interpolation calculation block 16b change as shown in FIGS. 9 (22) to (25), respectively. Then, since the interpolation calculation unit 35b generates OUTb based on the BUFF 5b and DBUFFb, the OUTb output from the interpolation calculation block 16b is eventually input as shown in FIG. 9 (26). Time required for calculation after input of new data (FIG. 9 (21), (25)) to the interpolation calculation unit 35b, which is a signal representing the conversion result of each RGB data (even-numbered RGB data) When the time elapses, the signal becomes a finalized signal.
[0143]
Then, as shown in FIG. 27, the data switching unit 17 to which OUTa and OUTb are input is a control signal OUTSEL that changes at a cycle twice that of CLK, and OUTa changes from a transition state to a stable state. A control signal OUTSEL whose phase is controlled so that it takes the “H” state when it changes and takes the “L” state when OUTb changes from the transition state to the stable state is input.
[0144]
Since the output of the data switching unit 17 to which such OUTSEL is supplied is supplied to the output buffer 18, from the output buffer 18, as shown in FIG. A signal OUT representing the conversion result is output.
[0145]
As described above in detail, the color conversion circuit according to the embodiment stores a plurality of CMYK data necessary for interpolation calculation, storing a number of CMYK data that can be subjected to interpolation calculation for all RGB data. A memory unit 14 that can be read is provided. Therefore, RGB data can be converted to CMYK data at high speed regardless of the contents. The color conversion circuit also includes a memory unit 14 composed of eight memories accessed by “3 × 5-2” bit addresses in which CMYK data is stored, and “3 × 5-2” supplied to these memories. An address generation unit 25 that generates eight types of addresses of bits from RGB data uR, uG, and uB. Therefore, the color conversion circuit is a conventional color conversion circuit in which a part of the address (specific multiple bits) for reading the target color data is created independently for each component of the color data to be converted (FIG. 15). The circuit can be manufactured using a memory having a smaller storage capacity than that of the reference).
[0146]
In addition, the color conversion circuit according to the embodiment includes a circuit (buffer 24, address for alternately functioning the two address generation units 25a and 25b, the two interpolation calculation units 35a and 35b, and the address generation units 25a and 25b. A switching unit 12 and the like, and circuits (buffer 34, data switching unit 17 and the like) for causing the interpolation calculation units 35a and 35b to function alternately. For this reason, the color conversion circuit according to the embodiment is a circuit that can convert RGB data with a throughput higher than the throughput (processing amount per unit time) of the address generation unit 25 and the interpolation calculation unit 35.
[0147]
In other words, the throughput required for the color conversion circuit (required RGB data conversion speed) is higher than both the throughput of the address generator 25 and the throughput of the interpolation calculator 35. The color conversion circuit according to the embodiment employs the configuration as described above.
[0148]
Therefore, when the color conversion circuit throughput may be lower than either the address generation unit 25 throughput or the interpolation calculation unit 35 throughput (when a high RGB data conversion speed is not required), one address is used. A color conversion circuit can be configured with only the generation unit 25, one interpolation calculation unit 35, the memory unit 14, and buffers for timing adjustment such as buffers 36 to 39.
[0149]
Further, when the requested throughput is higher than the throughput of the address generator 25 and lower than the throughput of the interpolation calculator 35, a circuit in the previous stage than the memory unit 14 is connected to one address generator 25. The circuit used can be used. On the other hand, when the desired throughput is lower than the throughput of the address generation unit 25 and higher than the throughput of the interpolation calculation unit 35, a circuit at a later stage than the memory unit 14 is used as a single interpolation calculation unit 36. Circuit.
[0150]
Note that which of the throughput of the address generator 25 and the interpolation calculator 35 is higher depends on the actual circuit configuration of the address generator 25 and the interpolation calculator 35. In the color conversion circuit according to the present embodiment, since the address generation unit 25 and the interpolation calculation unit 35 are realized by a combination of basic calculation circuits, the throughputs of both are almost the same (processing) For example, when the address generator 25 is implemented using a memory, or when the address generator 25 is pipelined, the throughput of the address generator 25 is high. , It becomes higher than the throughput of the interpolation calculation unit 35 (similar to the throughput of the memory). Further, when only the interpolation calculation unit 35 is pipelined to increase the throughput, the throughput of the address generation unit 25 is lower than the throughput of the interpolation calculation unit 35. Therefore, which of the above-described configurations should be determined for the color conversion circuit is determined according to the relationship between the required throughput and the throughput of the address generation unit 25 and the interpolation calculation unit 35.
[0151]
The color conversion circuit according to the embodiment includes a point P _RGB In this circuit, the final output is obtained by the interpolation calculation based on the color data of the four vertices of the tetrahedron including, but the interpolation calculation is performed using all the eight color data simultaneously read from the memory unit 14. Of course, the color conversion circuit may be modified as described above.
[0152]
Further, instead of the memory unit 14, CMYK data stored in the memory # 0 and the memory # 7, CMYK data stored in the memory # 1 and the memory # 6, and CMYK data stored in the memory # 2 and the memory # 5. A memory unit including four memories that are accessed by 14-bit addresses respectively storing CMYK data stored in the memory # 3 and the memory # 4 is used. Point P selected from tetrahedrons obtained by dividing the unit cell of interest so as not to include it _RGB It is also possible to modify the color conversion circuit so that the one that performs the interpolation calculation based on the YMCK data relating to the four vertices of the tetrahedron including.
[0153]
【The invention's effect】
According to the present invention, it is possible to obtain a color conversion circuit that can convert color data into other types of color data at a high speed regardless of the content thereof and requires only a small capacity memory.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a first half of a color conversion circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a latter half of the color conversion circuit according to the embodiment.
FIG. 3 is an explanatory diagram of a usage pattern of memories # 0 to # 3 provided in the color conversion circuit according to the embodiment.
FIG. 4 is an explanatory diagram of a usage form of memories # 4 to # 7 provided in the color conversion circuit according to the embodiment.
FIG. 5 is a diagram for explaining a color conversion procedure performed by the color conversion circuit according to the embodiment.
FIG. 6 is a circuit diagram illustrating an overall configuration of an address generation unit provided in the color conversion circuit according to the embodiment.
FIG. 7 is a circuit diagram showing a configuration of an address selector provided in an address generator.
FIG. 8 is an explanatory diagram of a configuration of another address selector provided in the address generation unit.
FIG. 9 is a timing chart for explaining the overall operation of the color conversion circuit according to the embodiment.
FIG. 10 is a circuit diagram illustrating an overall configuration of an interpolation calculation unit provided in the color conversion circuit according to the embodiment.
FIG. 11 is a circuit diagram showing a configuration of a data selector provided in the interpolation calculation unit.
FIG. 12 is an explanatory diagram of a configuration of another data selector provided in the interpolation calculation unit.
FIG. 13 is an explanatory diagram of an operation of an interpolation calculation unit.
FIG. 14 is an explanatory diagram of a usage pattern of a memory provided in a conventional color conversion circuit.
FIG. 15 is a diagram showing a configuration of a digital high-speed three-dimensional interpolation device disclosed in US Pat. No. 4,837,722.
[Explanation of symbols]
11 Address generation block
12 Address switching part
13 Address buffer
14 Memory part
15 Data buffer
16 Interpolation calculation block
17 Data switching part
18 Output buffer
25 Address generator
35 Interpolation calculator
41 Address calculator
42 Address selector
51 Data selector
52 Mode judgment / coefficient calculation section
53 Data selector for calculation
54 Output calculator

Claims (6)

Each of the color conversion circuits for converting the color data to be converted comprising first to third element data of n + m bits into target color data representing the same color,
(2 ⁿ +1) × (2 ⁿ +1) × (2 ⁿ +1) associated with information (0, 0, 0) to (2 ⁿ , 2 ⁿ , 2 ⁿ ) each consisting of three integer values 1st to 8th memory, each of which is accessed by an address signal of “3 × n−2” bits, in which a plurality of target color data are stored in a distributed manner. First to eighth memories in which a plurality of target color data having equal combinations of three kinds of integer values constituting the same are stored;
Information (x, y, z), (x, y, z + 1) based on the upper n-bit values x, y, z of the first to third element data constituting the color data to be converted, respectively. , (X, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), (x + 1, y, z + 1), (x + 1, y + 1, z), (x + 1, y + 1, z + 1) An address generation circuit for generating eight types of “3 × n−2” -bit addresses for reading the eight target color data attached from the first to eighth memories;
At least four target color data among the eight target color data stored in the addresses generated by the address generation circuit in the first to eighth memories, and the first to eighth colors of the converted color data. And a target color data generation / output circuit for generating and outputting target color data corresponding to the color data to be converted by interpolation using lower m-bit data of the third element data. Conversion circuit. A color conversion circuit for sequentially converting converted color data composed of first to third element data of n + m bits, which is input every time T, into target color data representing the same color,
(2 ⁿ +1) × (2 ⁿ +1) × (2 ⁿ +1) associated with information (0, 0, 0) to (2 ⁿ , 2 ⁿ , 2 ⁿ ) each consisting of three integer values 1st to 8th memory, each of which is accessed by an address signal of “3 × n−2” bits, in which a plurality of target color data are stored in a distributed manner. First to eighth memories in which a plurality of target color data having equal combinations of three kinds of integer values constituting the same are stored;
A first capture circuit that captures input converted color data every time 2T and outputs the captured converted color data;
A second capture circuit that captures input converted color data every time 2T and outputs the captured converted color data after the conversion color data is captured by the first capture circuit; A second capture circuit for capturing the converted color data after time T;
Information (x, y, z) based on values x, y, z of upper n bits of the first to third element data constituting the color data to be converted output from the first fetch circuit, respectively. , (X, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), (x + 1, y, z + 1), (x + 1, y + 1, z), ( First address for generating eight types of “3 × n−2” bit addresses for reading out the eight target color data associated with x + 1, y + 1, z + 1) from the first to eighth memories A generation circuit;
Information (x, y, z) based on the values x, y, z of the upper n bits of the first to third element data constituting the color data to be converted output from the second fetch circuit, respectively. , (X, y, z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), (x + 1, y, z + 1), (x + 1, y + 1, z), ( a second address for generating eight types of “3 × n−2” bit addresses for reading out the eight target color data associated with x + 1, y + 1, z + 1) from the first to eighth memories. A generation circuit;
When an address is generated by the first address generation circuit or the second address generation circuit, at least four types of target color data stored in the generated addresses of the first to eighth memories are used. Object corresponding to the converted color data by interpolation using the target color data and the lower m bits of the three color element data of the converted color data used to generate the address A color conversion circuit comprising a target color data generation / output circuit for generating and outputting color data. The target color data generation / output circuit includes:
An address selection / supply circuit that supplies either the address generated by the first address generation circuit or the address generated by the second address generation circuit to the first to eighth memories, the first address When the address is generated by the generation circuit, supply of the address to the first to eighth memories is started, and when the address is generated by the second address generation circuit, the address is changed to the first address. Or an address selection supply circuit for starting supply to the eighth memory;
Interpolation calculation data, which is data composed of eight target color data output from the first to eighth memories, is fetched every 2T, and the first interpolation calculation data is output to output the interpolated calculation data. Embedded circuit,
A second interpolation calculation data fetch circuit that fetches the interpolation calculation data every 2T and outputs the fetched interpolation calculation data, the interpolation calculation data by the first interpolation calculation data fetch circuit A second interpolation calculation data fetch circuit for fetching interpolation calculation data after time T after fetching
At least four types of target color data included in the interpolation calculation data output from the first interpolation calculation data fetch circuit in the first to eighth memories, and the subject data from which the interpolation calculation data is based. A first target color data generation circuit that generates target color data corresponding to the color data to be converted by interpolation using the lower m bits of the three types of color element data of the converted color data;
At least four types of target color data included in the interpolation calculation data output from the second interpolation calculation data fetch circuit in the first to eighth memories, and the subject data from which the interpolation calculation data is based. A second target color data generation circuit for generating target color data corresponding to the color data to be converted by interpolation using the lower m bits of the first to third color element data of the converted color data;
A selection output circuit for outputting either target color data generated by the first target color data generation circuit or target color data generated by the second target color data generation circuit, wherein the first target color data When target color data is generated by the generation circuit, output of the target color data is started. When target color data is generated by the first target color data generation circuit, output of the target color data is started. 3. The color conversion circuit according to claim 2, further comprising a selection output circuit that performs the selection. A color conversion circuit for sequentially converting converted color data composed of first to third element data of n + m bits, which is input every time T, into target color data representing the same color,
(2 ⁿ +1) × (2 ⁿ +1) × (2 ⁿ +1) associated with information (0, 0, 0) to (2 ⁿ , 2 ⁿ , 2 ⁿ ) each consisting of three integer values 1st to 8th memory, each of which is accessed by an address signal of “3 × n−2” bits, in which a plurality of target color data are stored in a distributed manner. First to eighth memories in which a plurality of target color data having equal combinations of three kinds of integer values constituting the same are stored;
Information (x, y, z), (x, y, respectively) based on the upper n-bit values x, y, z of the first to third element data constituting the input color data to be converted. , Z + 1), (x, y + 1, z), (x, y + 1, z + 1), (x + 1, y, z), (x + 1, y, z + 1), (x + 1, y + 1, z), (x + 1, y + 1, z + 1) 8) address generation circuits for generating eight types of “3 × n−2” bit addresses for reading out the eight target color data associated with the first to eighth memories,
Interpolation calculation data, which is data composed of eight target color data output from the first to eighth memories, is taken every time 2T by supplying an address generated by the address generation circuit. A first interpolation calculation data fetch circuit for outputting calculation data;
A second interpolation calculation data fetch circuit that fetches the interpolation calculation data every 2T and outputs the fetched interpolation calculation data, the interpolation calculation data by the first interpolation calculation data fetch circuit A second interpolation calculation data fetch circuit for fetching interpolation calculation data after time T after fetching
At least four types of target color data included in the interpolation calculation data output from the first interpolation calculation data fetch circuit in the first to eighth memories, and the subject data from which the interpolation calculation data is based. A first target color data generation circuit that generates target color data corresponding to the color data to be converted by interpolation using the lower m bits of the three types of color element data of the converted color data;
At least four types of target color data included in the interpolation calculation data output from the second interpolation calculation data fetch circuit in the first to eighth memories, and the subject data from which the interpolation calculation data is based. A second target color data generation circuit for generating target color data corresponding to the color data to be converted by interpolation using the lower m bits of the first to third color element data of the converted color data;
A selection output circuit for outputting either target color data generated by the first target color data generation circuit or target color data generated by the second target color data generation circuit, wherein the first target color data When target color data is generated by the generation circuit, output of the target color data is started. When target color data is generated by the first target color data generation circuit, output of the target color data is started. A color conversion circuit comprising: a selection output circuit that performs the selection. n = 5,
In each of the first to eighth memories, the color data associated with the information (a, b, c) has an address “17 × 17 × INT (a / 2) + 17 × INT (b / 2) + INT. The color conversion circuit according to claim 1, wherein the color conversion circuit is stored in (c / 2) ″. Each of the color conversion circuits for converting the color data to be converted comprising first to third element data of n + m bits into target color data representing the same color,
Each of the first to fourth memories is accessed by an address signal of “3 × n−1” bits, and includes information (0, 0, 0) to (2 ⁿ , 2 ⁿ , three kinds of integer values). associated with the ^{2 n) (2 n +1)} × (2 n +1) × (2 n +1) pieces of target color data, the four color data that may be used simultaneously for interpolation calculation can be read at the same time First to fourth memories stored in the form;
To read four target color data used for interpolation calculation from the first to fourth memories based on the upper n bits of the first to third element data constituting the converted color data An address generation circuit for generating four types of “3 × n−1” bit addresses;
Four target color data stored at addresses generated by the address generation circuit in the first to fourth memories, and lower m-bit data of the first to third element data of the converted color data And a target color data generation / output circuit for generating and outputting target color data corresponding to the color data to be converted by an interpolation operation using the color conversion circuit.

Images