JP3750503B2 - Image data transmission apparatus and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image data transmission apparatus that transmits image data to a local area network (LAN) and a control method therefor, and more particularly, to an apparatus that transmits continuous stream data such as a moving image captured by a camera in real time.
[0002]
[Prior art]
As shown in FIG. 9, the network image transmission system includes a transmission apparatus (server) 101, a reception apparatus (client) 103, and a network bus (for example, an Ethernet network bus, hereinafter referred to as “Ethernet”) that interconnects them. 102. The server 101 compresses the video signal captured by the camera with MPEG (Motion Picture Expert Group) 1 and packetizes it, and sends it to the Ethernet 102. The client 103 receives this data, decompresses it, and displays it on the display monitor 104. The configuration of the server 101 will be described below.
[0003]
(1) Configuration of transmission apparatus (server) 101
FIG. 10 shows the circuit configuration of the server 101. The server 101 performs software processing on the entire MPEG encoder circuit 111 that performs information compression processing on the input video signal in accordance with MPEG1, and an Ethernet circuit 114 that transmits the compressed data (elementary stream) to the Ethernet. A CPU (Central Processing Unit) 112 that performs control, a DRAM (Dynamic Random Access Memory) 113, and a data bus 115 are configured.
[0004]
Among these, the MPEG encoder circuit 111 mainly includes an A / D converter (including a sync separator and a synchronization circuit) 121, an MPEG1 encoder LSI 122, a FIFO (First In First Out) memory 123, and an MPEG interface circuit 124. Is done.
[0005]
(2) Flow of video data
Here, a process until the input video signal is transmitted to the Ethernet 102 will be briefly described.
In the circuit configuration of the server 101 shown in FIG. 10, the input video signal is converted into digital data, then compressed by the MPEG1 encoder LSI 122, and output in the format of the elementary stream ES. This data is temporarily held in the FIFO memory 123 and written to the DRAM 113 via the data bus 115 under the control of the CPU 112. Further, information such as a header of UDP (User Datagram Protocol) or IP (Internet Protocol) is added here and sent to the Ethernet circuit 114, and sent out on the Ethernet 102 for each packet. The above is the flow of video data in the server 101.
[0006]
(3) FIFO memory 123 write / read operations
Here, writing / reading operations of the FIFO memory 123 of the MPEG encoder circuit 111 will be described.
The elementary stream ES output from the MPEG1 encoder LSI 122 is controlled by the write reset signal WR and the write enable signal WE output from the LSI 122 and is written in the FIFO memory 123.
[0007]
The data written in the FIFO memory 123 is read out under the control of the read reset signal RR and the read enable signal RE output from the MPEG interface circuit 124. The MPEG interface circuit 124 is connected to the data bus 115 of the CPU 112, and the output of the read reset signal RR and the read enable signal RE is executed according to instructions of the CPU (software) 112.
[0008]
Hereinafter, the read operation of the FIFO memory 123 will be described with reference to the timing chart of FIG.
The frame pulse FP shown in FIG. 11A is a signal that switches at the frame period of the input video signal. The MPEG interface circuit 124 (see FIG. 10) generates an MPEG interrupt request pulse MIRQ from the frame pulse FP and outputs it. The MPEG interrupt request pulse MIRQ is input to the hardware interrupt terminal of the CPU 112 and requests the CPU 112 for a hardware interrupt once per frame period. When an interrupt occurs, the MPEG interrupt routine shown in FIG. 12A is executed, and here, the reading operation of the elementary stream ES held in the FIFO memory 123 is performed.
[0009]
Reading from the FIFO memory 123 reads from the FIFO memory 123 the number of data constituting one picture (I picture, P picture, or B picture) every time an interrupt occurs. The amount of data constituting one picture varies from frame to frame. Therefore, the MPEG1 encoder LSI 122 sets the number of data written in the FIFO memory 123 to the internal register (hereinafter referred to as “FIFO read register”) at the beginning of the frame period shown in FIG. . . It has a writing mechanism like
[0010]
(4) Program operation until Ethernet packet generation
A program operation from reading the elementary stream ES held in the FIFO memory 123 to generating an Ethernet packet will be described with reference to the timing chart of FIG. 11 and the flowchart of FIG.
[0011]
In response to a hardware interrupt (MPEG interrupt) request MIRQ generated in the frame period of the input video signal, the MPEG interrupt routine (phase A1, see FIG. 11) shown in FIG.
In step S101, the content (X1 byte in FIG. 11) of the FIFO read register, which is an internal register of the MPEG1 encoder LSI 122, is read to obtain the number of bytes of data to be read within the current frame period.
[0012]
In step S102, data is read from the FIFO memory 123 by the number of bytes and written to the MPEG area secured on the DRAM 113.
In step S103, the network process (FIG. 12B) is called and the MPEG interrupt routine is terminated.
[0013]
Step S103 starts phase B1 of the network process. FIG. 13 shows a procedure for generating a packet from the elementary stream ES, and is referred to with FIG.
[0014]
In step S111 of FIG. 12B, as shown in FIG. 13, 1460 bytes of data (the last read data is 1460 bytes or less) is read from the MPEG area of the DRAM 113, and an 8-byte UDP header is obtained. And a 20-byte IP header.
[0015]
Next, this data is written into the memory of the Ethernet circuit 114, and a transmission start procedure is performed (step S112). Thereafter, hardware processing by the Ethernet circuit 114 is performed. Further, a 14-byte Ethernet header is added to this data (FIG. 13 (d)), resulting in a 1502-byte packet. This packet is sent out to the Ethernet 102.
[0016]
In step S113 of FIG. 12B, it is checked whether there is data written in the MPEG area of the DRAM 113. If data remains, the process returns to step S111, and the processes of steps S111 to S113 are repeated. As described above, the Ethernet circuit 114 divides continuous data into packets (= 1502 bytes) and sequentially sends them to the Ethernet 102.
[0017]
If there is no more data to be read from the MPEG area of the DRAM 113 in step S113, the network process is terminated.
When the network process is completed, the Ethernet circuit 114 holds a plurality of packets in the internal memory. When all the packets are transmitted, the Ethernet circuit 114 sends a hardware interrupt request (hereinafter referred to as “Ethernet interrupt request”) to the CPU 112. ) And go to software processing again. At this time, the Ethernet interrupt routine shown in FIG. 12C is called, and the following processing is performed.
[0018]
In step S121, it is determined whether or not it is a transmission end interrupt. If it is not a transmission end interrupt, the process is immediately ended. If it is a transmission end interrupt, a transmission end procedure is performed for the Ethernet circuit 114 (step S122), the memory of the Ethernet circuit 114 used at the time of packet transmission is cleared (step S123), and the Ethernet interrupt routine is ended. To do.
[0019]
The above is the processing performed within one frame period. When an interrupt for the next frame occurs, phase A2 of the MPEG interrupt routine starts, and processing is similarly performed from step S101.
Through such software processing, the elementary stream ES output from the MPEG1 encoder LSI 122 as needed is packetized and sent to the Ethernet 102.
[0020]
[Problems to be solved by the invention]
In the server 101 described above, 1) When the network is congested, packet collisions frequently occur, so packet retransmission is repeated. 2) When broadcast packets are frequently received, the network executed by the CPU 112 The load on the CPU 112 temporarily increases due to the busy reception process of the network, the network process and the Ethernet interrupt routine shown in FIG. 12 are delayed, and the execution time becomes longer than usual. Processing performance (such as real-time performance) is impaired.
[0021]
For example, FIG. 14 shows a case where the execution time of the network process B1 and the Ethernet interrupt process C1 is long. In such a case, since B1 and C1 are executed at the second frame in the figure, the MPEG interrupt routine A2 should be executed at this timing, but until the third frame, that is, the phase A3 should be executed originally. It will be out of timing. At this time, since the value of the FIFO register of the MPEG1 encoder LSI 122 has already been updated to X3, the MPEG interrupt routine A2 cannot read the value of X2.
[0022]
That is, since the MPEG interrupt routine is not executed once in one frame period, the number of data to be originally read becomes unknown. If such a state continues, data that could not be read is accumulated in the FIFO memory 123, and the capacity of the FIFO memory 123 is eventually exceeded. For this reason, continuous stream data cannot be read out, and MPEG data is not packetized normally, and broken data is transmitted. As a result, the client receives and expands the broken data, and thus a problem arises in that the reproduced image to be displayed is disturbed and cannot be recovered.
[0023]
The present invention has been made to prevent such a problem, and detects a delay in software processing by the CPU so that a situation in which a reproduced image is disturbed on the image data receiving side and cannot be restored can be avoided. An object of the present invention is to provide an image data transmission apparatus and a control method thereof.
[0024]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 performs an information compression process of input moving image data, and stores the data after the process in a data memory, and is stored in the data memory. In an image data transmission apparatus comprising: an information sending unit that reads out image data, packetizes it, and sends it to a transmission line; and a control unit that controls the information compression unit and the information sending unit. Hardware count means for obtaining a first count value by counting the number of times the generated signal is generated, and the control unit counts the number of times one frame of data transmission processing has been completed in the information transmission unit. Software counting means for obtaining a second count value, wherein the first count value is different from the second count value; It may suspend the transmission of the transmission path of the image data At the same time, the first count value counted by the hardware count means and the second count value counted by the software count means are returned to their initial values, and the image data stored in the data memory is erased. Is processing It is characterized by resetting.
[0025]
The invention according to claim 2 performs an information compression process of input moving image data, reads an image compression unit that stores the processed data in a data memory, and image data stored in the data memory, In a control method of an image data transmission apparatus comprising an information transmission unit that packetizes and transmits to an transmission line, a step of obtaining a first count value by counting the number of times of generation of a signal generated in a frame period of the image data And secondly obtaining a count value by counting the number of times one frame of data transmission processing has been completed in the information transmission unit is different from the first count value and the second count value. When the transmission of the image data to the transmission line is interrupted And a process of returning the first count value and the second count value to their initial values and erasing the image data stored in the data memory. And a step of resetting.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a configuration of an image data transmission apparatus according to the first embodiment of the present invention. This device is obtained by adding a MIRQ count circuit 16 to the conventional transmission device shown in FIG. That is, the transmission apparatus 1 shown in FIG. 1 includes the MPEG encoder 111, the CPU 112, the DRAM 113, the Ethernet circuit 114, and the data bus 115 shown in FIG. 10, and the MPEG encoder 11, the CPU 12, the DRAM 13, the Ethernet circuit 14, and the data having the same functions. A MIRQ count circuit 16 is added to the bus 15. The MPEG encoder 11 includes an A / D converter 21, an MPEG1 encoder LSI 22, a FIFO memory 23, and an MPEG interface circuit 24.
[0027]
The MIRQ count circuit 16 counts the number of occurrences of the hardware interrupt request MIRQ requested by the MPEG interface circuit 24 to the CPU 12 and stores it in an internal register (hereinafter referred to as “hard count register”). In the following description, the MIRQ count circuit 16 is also referred to as a “hardware counter”.
[0028]
For example, when counting is performed using an 8-bit counter, the count value HC is updated by one for each rising edge of the hardware interrupt request MIRQ, as shown in FIGS. Since the operation is performed by independent hardware that does not depend on the instruction (software) of the CPU 12, the count value does not go wrong even if the processing of the CPU 12 becomes busy.
However, the CPU 12 is configured to be able to access the MIRQ count circuit 16 via the data bus 15 so that the MIRQ count circuit 16 can be reset and the hard count register can be read.
[0029]
(1) Software counter implementation and comparison method
Next, another counter is prepared separately from the MIRQ count circuit 16. It is a counter that counts the number of occurrences of hardware interrupt request MIRQ by software.
[0030]
Since the MPEG interrupt routine, which is an interrupt routine, is executed in response to the generation of the hardware interrupt request MIRQ, the number of interrupts that have occurred can be counted by performing a counting operation in the interrupt routine. The count value SC of this software counter is updated as shown in FIG.
[0031]
As can be seen from FIGS. 2A to 2H, if the processing of the CPU 12 is performed as usual, the value HC of the hardware counter coincides with the value SC of the software counter.
However, when an excessive load is temporarily applied to the CPU 12, the MPEG interrupt routine cannot be executed once per frame as shown in FIG. 2 (i), so the software counter as shown in FIG. The value SC is not updated every frame. That is, it deviates from the hardware counter value HC as many times as it is not executed.
Therefore, the value of the hardware counter is read during the execution of the MPEG interrupt routine and compared with the value of the software counter. If the values are different, the processing delay of the CPU 12 can be detected.
[0032]
(2) How to return to normal state
As described above, once the processing of the CPU 12 is delayed, the format of the elementary stream ES held in the FIFO memory 23 is broken, so that discontinuous data continues to be transmitted. In such a situation, in this embodiment, the transmission of data is interrupted, and the contents of the FIFO memory 23, the value HC of the hardware counter, and the value SC of the software counter are reset to return to the initial state. .
[0033]
By this operation, it becomes possible to write and read from the head address without reading discontinuous data remaining in the FIFO memory 23. Therefore, it is no longer necessary to continue transmitting broken data as in the prior art, and image disturbance on the receiving device side can be restored.
[0034]
(3) Program operation
The actual software operation will be described with reference to the flowcharts of FIGS.
(A) MPEG process operation
FIG. 3A is a flowchart of the MPEG process. The MPEG process is a program that mainly controls start / stop of the MPEG1 encoder LSI 22 and is started when the power is turned on.
[0035]
First, in step S11, the MPEG1 encoder LSI 22 is initialized. Here, hardware reset of the LSI itself, initial setting of the internal register group, and the like are performed. Further, the write reset of the FIFO memory 23 is performed, and the write address of the FIFO memory 23 is returned to the head address.
[0036]
In step S12, a microcode (a program for performing an encoding operation) is loaded into a memory area managed by the MPEG1 encoder LSI 22.
In step S13, both the hardware count register value HC in the MIRQ count circuit 16 that stores the hardware counter value HC and the software counter value SC (stored in the area SCA of the DRAM 13) are set to zero.
[0037]
In step S14, read reset of the FIFO memory 23 is performed via the MPEG interface circuit 24, and the read address is returned to the head address.
In step S15, the value of the encode start flag ESF indicating the encode start or stop state is set to zero. The flag ESF is stored in an area secured on the DRAM 13, and is set to 0 when in the stop state and 1 when in the start state. In the subsequent step S16, in order to start the encoding operation, the MPEG hardware interrupt is permitted and a start request command is issued to the MPEG1 encoder LSI 16. That is, the encode start flag ESF is set to 1.
As a result, the encoding operation starts and the MPEG interrupt routine is executed for each frame. The operation of the MPEG process during the encoding operation will be described later, and the MPEG interrupt routine will be described first.
[0038]
(B) Operation of MPEG interrupt routine
FIG. 3B is a flowchart of the MPEG interrupt routine. When encoding is started by the MPEG process, a hardware interrupt request MIRQ is generated at the frame period of the input video signal, the MPEG interrupt routine is executed, and phase A1 (see FIG. 2 (e)) is started.
[0039]
In step S21, the software counter value SC is incremented by one. Even when the hardware interrupt request MIRQ is generated, when the CPU 12 is executing the network process or the Ethernet interrupt routine, the MPEG interrupt process is not started, and the software counter value SC is not incremented. Therefore, the value SC of the software counter corresponds to the number of end times of image data for one frame.
[0040]
In step S22, the content of the FIFO read register (X1 byte in FIG. 2B), which is an internal register of the MPEG1 encoder LSI 22, is read to obtain the number of bytes of data to be read within the current frame period TFM.
In step S23, data is read from the FIFO memory 23 by the number of bytes and written in the MPEG area, which is an area secured on the DRAM 13.
[0041]
In step S24, the hardware counter value HC is read from the hard count register of the MIRQ count circuit 16.
In step S25, it is determined whether or not the hardware counter value HC and the software counter value SC are equal. As a result, if both match, it can be seen that the processing of the CPU 12 is in time, so the soft count error flag SCEF stored in the DRAM 13 is set to 0 (step S26), and then normal data is packetized. Then, the network process (FIG. 4A) is called to end the interrupt routine.
[0042]
On the other hand, if the hardware counter value HC and the software counter value SC do not coincide with each other in step S25, it means that the processing of the CPU 12 is delayed, so the soft count error flag SCEF is set to 1. In this case, in order to prevent transmission of broken data, the subsequent processing is interrupted without calling the network process.
[0043]
(C) Network process operation
When the processing of the CPU 12 is in time, the network process shown in FIG. 4A is executed. In response to phase A1 of the MPEG interrupt routine, phase B1 of the network process (see FIGS. 2E and 2G) starts.
[0044]
In step S31 of FIG. 4A, as shown in FIG. 13, 1460 bytes of data (the last read data may be 1460 bytes or less) is read from the MPEG area of the DRAM 13, and an 8-byte UDP header is obtained. And a 20-byte IP header.
[0045]
In step S32, this data is written in the memory of the Ethernet circuit 14, and a transmission start procedure is performed. Thereafter, hardware processing by the Ethernet circuit 14 is performed. In the hardware processing, a 14-byte Ethernet header is further added to this data to form a 1502-byte packet. This packet is sent to the Ethernet.
[0046]
In step S33, it is checked whether there is data written in the MPEG area of the DRAM 13. If data remains, the process returns to step S31, and the processes in steps S31 to S33 are repeated. In this way, continuous data is divided into packets (= 1502 bytes) and sequentially transmitted to the Ethernet 2. When there is no more data to be read from the MPEG area of the DRAM 13, the network process is terminated.
[0047]
When step S32 of the network process is completed, the Ethernet circuit 14 holds a large number of packets in the internal memory. When all the packets are transmitted, the Ethernet circuit 14 issues a hardware interrupt request EIRQ to the CPU 12, and again. Move on to software processing. At this time, the Ethernet interrupt routine is called, phase C1 (see FIG. 2 (h)) is started, and the following processing is performed.
[0048]
(D) Ethernet interrupt routine operation
In step S41, it is determined whether or not it is a transmission end interrupt. If no transmission end interrupt is issued, this routine is immediately ended. If it is a transmission end interrupt, a transmission end procedure is performed for the Ethernet circuit 14 (step S42). Next, the memory of the Ethernet circuit 14 used at the time of packet transmission is cleared (step S43), and the Ethernet interrupt routine is terminated.
[0049]
The above is the processing performed within one frame period. When an interrupt for the next frame occurs, phase A2 of the MPEG interrupt routine starts, and the processing is again performed from step S11 of the MPEG interrupt routine.
Through such software processing, the elementary stream ES output from the MPEG1 encoder LSI 22 as needed is packetized and sent to the Ethernet 2.
[0050]
(E) Operation during encoding of MPEG process
During the encoding operation, the MPEG process performs the following processing.
In step S17 of FIG. 3A, it is determined whether or not the soft count error flag SCEF stored in the DRAM 13 is 1. If the flag SCEF is 0, the software counter is normally updated, that is, the processing of the CPU 12 In this case, step S17 is repeated without doing anything. If it is normal, it loops here.
[0051]
On the other hand, when the flag SCEF is 1, as shown in FIGS. 2 (i) to (l) (when the processing of the CPU is delayed), the hardware counter value HC ((d) in the figure) This means that the software counter value SC ((j) in the figure) has shifted, and it can be seen that the processing of the CPU 12 is delayed. In this state, data that cannot be read from the FIFO memory 23 is accumulated, and if the memory capacity is exceeded, continuous data cannot be read. For this reason, the broken data continues to be sent to the Ethernet 2. As a result, the image displayed on the client (receiving device) does not return while being distorted.
[0052]
In order to avoid this, in step S18 of FIG. 3A, the data stored in the FIFO memory 23 is once cleared. In actual operation, the MPEG interface circuit 24 is accessed, the FIFO memory 23 is read reset, the FIFO memory 23 is write reset via the MPEG1 encoder LSI 22, and the FIFO read register which is an internal register of the MPEG1 encoder 22. The process of writing 0 in With this process, it is possible to write / read data continuously from the beginning of the memory without reading the non-continuous data stored in the FIFO memory 23.
[0053]
In the subsequent step S19, since the error processing is completed, the soft count error flag SCEF is set to 0, and the process returns to step S17.
As described above, in the present embodiment, the CPU 12 detects a processing delay by comparing the two counters, that is, the hardware counter value HC and the software counter value SC, and the transmission of broken data is triggered by this. Since the interruption is made temporarily, image disturbance on the receiving device side (client) can be minimized.
[0054]
In addition, since the write reset and read reset of the FIFO memory 23 are performed and the write / read operation is forcibly performed from the top address, the discontinuous data remaining in the FIFO memory 23 is wiped out, and the continuous data is read again. It becomes possible to transmit. As a result, it is possible for the client to quickly return to normal the image that has been interrupted in a disturbed manner.
[0055]
(Second Embodiment)
In the first embodiment described above, the processing delay of the CPU 12 is detected by counting the hardware interrupt request MIRQ output from the MPEG interface circuit 24 to the CPU 12, but in this embodiment, instead of the hardware interrupt request MIRQ. The hardware interrupt request EIRQ output from the Ethernet circuit 14 to the CPU 12 is counted.
[0056]
FIG. 5 shows a circuit configuration of a transmission apparatus (server) in the present embodiment. In this configuration, the MIRQ count circuit 16 is deleted from the configuration shown in FIG. 1, and the EIRQ count circuit 17 is added. In this embodiment, the hardware interrupt request EIRQ is output once per frame in synchronization with the frame pulse FP at the timing shown in FIG. 6E (immediately before the end of the frame period). The EIRQ count circuit 17 counts the number of occurrences of the hardware interrupt request EIRQ requested by the Ethernet circuit 14 to the CPU 12, and stores it in an internal register (hard count register). For example, when counting is performed using an 8-bit counter, as shown in FIG. 6F, it is updated by one for each rising edge of the hardware interrupt request EIRQ. Since the operation is performed by independent hardware that does not depend on the instruction (software) of the CPU 12, the count value does not go wrong even if the processing of the CPU 12 becomes busy.
However, the CPU 12 is configured to be able to access the EIRQ count circuit 17 via the data bus 15 so that the EIRQ count circuit 17 can be reset and the hard count register can be read.
[0057]
(1) Software counter implementation and comparison method
In this embodiment, the counting operation by software is performed by the Ethernet interrupt routine shown in FIG. Since the Ethernet interrupt routine is executed by the hardware interrupt request EIRQ, the number of occurrences of the generated Ethernet interrupt request EIRQ can be counted by performing a counting operation in the interrupt routine. The operation timing of this software counter is as shown in FIG.
[0058]
Therefore, if the processing of the CPU 12 is performed as usual, the hardware counter value HC and the software counter value SC match.
However, when an excessive load is temporarily applied to the CPU 12, the value SC of the software counter deviates from the value HC of the hardware counter as shown in FIG.
Therefore, the value HC of the hardware counter is read during the execution of the Ethernet interrupt routine, and when the value is different from the value SC of the software counter, a processing delay of the CPU 12 is detected.
[0059]
(2) How to return to normal state
As a countermeasure against this situation, as in the first embodiment, the contents of the FIFO memory 23, the hardware counter value HC, and the software counter value SC are reset and returned to the initial state. Do.
[0060]
By this operation, it becomes possible to write / read from the head address without reading discontinuous data remaining in the FIFO memory 23. Therefore, it is no longer possible to continue transmitting broken data as in the conventional case, and it is possible to restore the disturbance of the image of the client.
[0061]
(3) Program operation
The actual software operation will be described along the flowcharts of FIGS.
(A) MPEG process operation
The MPEG process (FIG. 7A) of this embodiment is the same as that of the first embodiment (FIG. 3A).
[0062]
(B) Operation of MPEG interrupt routine
When encoding is started by the MPEG process, a hardware interrupt is generated in the frame period of the input video signal, the MPEG interrupt routine is executed, and phase A1 (see FIG. 6C) is started. The MPEG interrupt routine of this embodiment consists only of steps S22, S23 and S27 as shown in FIG.
[0063]
That is, in step S22, the contents of the FIFO register (X1 byte in FIG. 6B) which is an internal register of the MPEG1 encoder LSI 22 are read to obtain the number of bytes of data to be read within the current frame period TFM. Next, data is read from the FIFO memory 23 by the number of bytes and written to the MPEG area, which is an area secured on the DRAM 13 (step S23). Then, the network process is called (step S27), and the MPEG interrupt routine is terminated.
[0064]
(C) Network process operation
The network process (FIG. 7C) of this embodiment is the same as the network process of the first embodiment shown in FIG. Therefore, when step S32 of the network process ends, the Ethernet circuit 14 holds a plurality of packets in the internal memory, and these packets are sequentially transmitted.
[0065]
However, in this embodiment, the Ethernet circuit 14 outputs a hardware interrupt request EIRQ to the CPU 12 at a timing immediately before the end of the frame period TFM, as shown in FIG. At this time, the Ethernet interrupt routine is called, phase C1 (see FIG. 6G) is started, and the following processing is performed.
[0066]
(D) Ethernet interrupt routine operation
In step S51, it is determined whether it is a transmission end interrupt. If it is not a transmission end interrupt, the processing is immediately terminated, and if it is a transmission end interrupt, the value SC of the software counter is incremented by 1 (step S52). Even when the hardware interrupt request EIRQ is generated, when the CPU 12 is executing the network process or the Ethernet interrupt routine, the Ethernet interrupt routine is not started, and therefore the value SC of the software counter is not incremented. Therefore, the value SC of the software counter corresponds to the number of end times of image data for one frame.
[0067]
In the subsequent step S53, the value HC of the hardware counter is read from the hard count register of the EIRQ count circuit 17.
In step S54, it is determined whether the value SC of the software counter is equal to the value HC of the hardware counter. If they match, it indicates that the processing of the CPU 12 is in time, so the soft count error flag SCEF is set to 0 (step S55). On the other hand, if the value SC of the software counter does not match the value HC of the hardware counter, it indicates that there is a delay in the processing of the CPU 12, so the soft count error flag SCEF is set to 1 (step S56).
[0068]
In step S57, a procedure for ending transmission is performed for the Ethernet circuit 14. Next, the memory of the Ethernet circuit 14 used for packet transmission is cleared (step S58), and the Ethernet interrupt routine is ended.
The above is the processing performed within one frame period TFM. When an interrupt for the next frame occurs, phase A2 of the MPEG interrupt routine is started, and processing is performed again from step S11 of the MPEG interrupt routine.
Through such software processing, the elementary stream output from the MPEG1 encoder LSI 22 as needed is packetized and sent to the Ethernet.
[0069]
(E) Operation during encoding of MPEG process
Processing during the encoding operation when the soft count error flag SCEF is set to 1 (FIG. 7A, steps S18 and S19) is the same as that in the first embodiment.
[0070]
As described above, in the present embodiment, the EIRQ count circuit 17 that counts the number of occurrences of the Ethernet interrupt request EIRQ output in synchronization with the frame pulse FP is provided, and the hardware counter value HC obtained thereby and the CPU 12 When there is no delay in the process, it is possible to detect the process delay of the CPU 12 by comparing with the value SC of the software counter that operates in the Ethernet interrupt process executed in response to the Ethernet interrupt request EIRQ. Therefore, the same effect as the first embodiment can be obtained.
[0071]
【The invention's effect】
As described in detail above, according to the first or second aspect of the present invention, the first count value obtained by counting the number of occurrences of the signal generated in the frame period of the input image data, and the image The first count value is compared with the second count value obtained by counting the number of times one frame of data transmission processing has been completed in the information transmission unit that transmits data. When they are different from each other, the transmission of the image data to the transmission path is interrupted, so that it is possible to detect a delay in the information transmission process and prevent the transmission of broken data from being continued. As a result, image disturbance on the receiving device side can be minimized. Furthermore, when a delay in information transmission processing is detected, The first count value and the second count value are returned to their initial values, and the image data stored in the data memory is deleted. Since the reset process is executed, normal data transmission can be resumed. As a result, on the receiving device side, the problem that the reproduced image cannot be recovered from the disordered state can be solved, and a normal image can be displayed quickly.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an image data transmission apparatus according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the apparatus of FIG. 1;
FIG. 3 is a flowchart of processing executed by the CPU of FIG. 1;
4 is a flowchart of processing executed by the CPU of FIG.
FIG. 5 is a block diagram showing a configuration of an image data transmission apparatus according to a second embodiment of the present invention.
6 is a timing chart for explaining the operation of the apparatus shown in FIG. 5;
7 is a flowchart of processing executed by the CPU of FIG.
FIG. 8 is a flowchart of processing executed by the CPU of FIG.
FIG. 9 is a block diagram illustrating a configuration of a conventional image transmission system.
10 is a block diagram illustrating a configuration of the transmission apparatus illustrated in FIG. 9;
11 is a timing chart for explaining the operation of the apparatus shown in FIG. 10;
12 is a flowchart of processing executed by the CPU of FIG.
FIG. 13 is a diagram for explaining a method for generating a packet for transmitting image data.
FIG. 14 is a timing chart for explaining problems of a conventional apparatus.
[Explanation of symbols]
1 Image data transmission device
11 MPEG encoder
12 CPU (control unit, software counting means)
13 DRAM
14 Ethernet circuit (information sending part)
15 Data bus
16 MIRQ count circuit (hardware count means)
17 EIRQ count circuit (hardware counting means)
22 MPEG1 encoder LSI (information compression unit)

Claims (2)

Information compression processing for input moving image data, information compression unit for storing the processed data in a data memory, and information for reading out the image data stored in the data memory, packetizing it, and sending it to the transmission line In an image data transmission apparatus comprising a sending unit and a control unit for controlling the information compression unit and the information sending unit,
Hardware counting means for obtaining a first count value by counting the number of occurrences of a signal generated in a frame period of the image data;
The control unit includes software count means for obtaining a second count value by counting the number of times one frame of data transmission processing has been completed in the information transmission unit, and the first count value and the first count value When the count value is different from 2, the transmission of the image data to the transmission path is interrupted , the first count value counted by the hardware count means, and the second count value counted by the software count means The image data transmission apparatus is characterized in that resetting is performed, which is a process of erasing image data stored in the data memory . Information compression processing for input moving image data, information compression unit for storing the processed data in a data memory, and information for reading out the image data stored in the data memory, packetizing it, and sending it to the transmission line In a control method of an image data transmission device comprising a sending unit,
Obtaining a first count value by counting the number of occurrences of a signal generated in a frame period of the image data;
Secondly obtaining a count value by counting the number of times one frame of data transmission processing has been completed in the information transmission unit;
When the first count value and the second count value are different, the transmission of the image data to the transmission path is interrupted , and the first count value and the second count value are set respectively. A control method for an image data transmission apparatus, comprising: resetting to an initial value and resetting which is a process of erasing image data stored in the data memory .

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