JP3750324B2 - Device having thin film multilayer electrode and method for manufacturing the same - Google Patents

Device having thin film multilayer electrode and method for manufacturing the same Download PDF

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JP3750324B2
JP3750324B2 JP33188597A JP33188597A JP3750324B2 JP 3750324 B2 JP3750324 B2 JP 3750324B2 JP 33188597 A JP33188597 A JP 33188597A JP 33188597 A JP33188597 A JP 33188597A JP 3750324 B2 JP3750324 B2 JP 3750324B2
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thin film
film
multilayer electrode
film multilayer
thin
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JPH11168306A (en
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充 中野
真人 小林
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Description

【0001】
【発明の属する技術分野】
本発明は、主として高周波領域において使用される薄膜多層電極を有する素子およびその製造方法に関する。
【0002】
【従来の技術】
近年、電子部品の小型化が進む中、マイクロ波、準ミリ波またはミリ波などの高周波帯においても、高誘電率材料を用いることによってデバイスの小型化が図られている。しかし、高誘電率材料を用いることによって形状を縮小すると、体積の立方根に反比例してエネルギー損失が増大するという問題点があった。この高周波デバイスのエネルギー損失は、表皮効果による導体損失と、誘電体材料による誘電体損失とに大きく分類することができるが、近年では、高誘電率のものでも低損失な特性を有する誘電体材料が実用化されており、従って、誘電体損失よりも導体損失の方がエネルギー損失において支配的な割合を占めるようになっている。
【0003】
以上のような状況の下、本出願人は国際出願公開第WO95/06336号公報において、高周波帯での導体損失を低減しうる電極として、誘電体基板上に薄膜導体層と薄膜誘電体層とを接着層を介して交互に積層して構成した薄膜多層電極を提案した。なお、ここで提案されている薄膜多層電極は、平坦な表面を有する誘電体基板(鏡面研磨の施されたアルミナの単結晶からなるサファイア基板が例示されている)上に形成されることを前提として薄膜導体層と薄膜誘電体層の各膜厚が設定されている。
【0004】
【発明が解決しようとする課題】
しかしながら、例えば誘電体基板としてセラミック基板を用いるような場合、通常その基板表面はポア等の存在により凹凸を有している。この凹凸は、表面研磨処理等によってある程度平坦化することが可能である。しかし、ポアは基板表面のみならず基板内部にも多数存在するため、研磨処理によって新たなポアが表面に顕在化することになり、基板表面を充分には平坦化することができない。ここで、ポアを有する誘電体基板上に薄膜多層電極を形成した場合の膜構造を示す断面図を、図3に示す。図3に示すように、誘電体基板32上に薄膜導体層35および薄膜誘電体層36がそれぞれ積層されて薄膜多層電極34が形成されているが、薄膜導体層35および薄膜誘電体層36は基板32のポア37に対応して凹凸を有するものとなる。このように各層が凹凸を持って形成されると、当初の設計通りの低損失動作を実現できなくなる。また、ポアを有する基板上に薄膜を積層する場合、成膜プロセス上、隣接する薄膜導体層同士が短絡する恐れが非常に高くなる。これらの事態は、いずれも薄膜多層電極の有する表皮効果の抑制効果を大幅に劣化させてしまう。
【0005】
このような問題に対処して本願出願人は、特願平8−140056および特願平9−288748において、誘電体基板と薄膜多層電極との間に基板の凹凸を平坦化するための平坦化膜を介在させる方法を提案し、これらの問題点の解決を図った。
【0006】
しかしながらこれらの方法によった場合であっても、新たに以下のような問題点が発生していた。すなわち平坦化膜を成膜するにあたっては、図4(a)〜(d)に示すように、誘電体基板32上に例えばスパッタリング等の手法で平坦化膜33の表面が平坦になるまで成膜を続け、その後に薄膜多層電極34を形成していた。このため、平坦化膜33の成膜完了までに多くの時間がかかり量産には不向きであった。また平坦化膜33の膜厚が厚くなるため、その上に形成される薄膜多層電極34の電気的特性に与える影響が大きくなる等の問題があった。
【0007】
従って本発明の目的は、上述の技術的問題点を解決するためになされたものであって、基板の凹凸の影響を受けにくい構造を有する薄膜多層電極を有する素子、及びその製造方法を提供することにある。
【0008】
【課題を解決するための手段】
上記目的を達成するために、本発明の薄膜多層電極を有する素子においては、誘電体基板と、誘電体基板上に薄膜導体層と薄膜誘電体層とを接着層を介して交互に積層した薄膜多層電極と、誘電体基板と薄膜多層電極との間に介在された平坦化膜とを備えてなる薄膜多層電極を有する素子であって、前記平坦化膜の薄膜多層電極と接する面に、その表面を平坦化するための研磨処理が施されている。
【0009】
このように、平坦化膜に研磨処理を施して基板の平坦化に寄与していない部分の平坦化膜は積極的に除去することにより、誘電体基板と薄膜多層電極との間に介在する平坦化膜の膜厚を薄くすることができる。これにより平坦化膜が薄膜多層電極に及ぼす影響を低く抑えることができる。また従来と異なり、研磨処理によって平坦化するので、平坦化されるまで成膜し続ける必要がなくなり、成膜時間の短縮を図ることができる。
【0010】
なお、平坦化膜にはTi、Ta、W、Cr、Zr、Nb、Hf、V、Mo、Ti−N、Ta−N、あるいはこれらを2種以上混合して得られる材料、あるいはこれらに添加物を加えた材料などを使用する
これらの材料は、誘電体基板や薄膜多層電極を構成する薄膜導体層と結合しやすく、その接着作用により誘電体基板と薄膜多層電極との密着度を高めることができるからである。
またこれらの材料は、薄膜多層電極を構成する薄膜導体層と薄膜誘電体層との接着のためにも用いられており、使用する材料を共通化でき成膜の効率化を図ることができる。
【0011】
また、本発明の薄膜多層電極を有する素子の製造方法は、誘電体基板上に薄膜導体層と薄膜誘電体層とを接着層を介して交互に積層した薄膜多層電極を形成してなる薄膜多層電極を有する素子の製造方法において、誘電体基板を準備する工程と、誘電体基板表面に、基板表面の凹凸を平坦化する平坦化膜を、Ti、Ta、W、Cr、Zr、Nb、Hf、V、Mo、Ti−N、Ta−N、あるいはこれらを2種以上混合して得られる材料、あるいはこれらに添加物を加えた材料を用いて形成する工程と、平坦化膜の表面が平坦になるように不要部分を除去する除去工程と、除去工程後の平坦化膜上に薄膜多層電極を形成する工程とを有する。
【0012】
なお除去工程は、薄膜多層電極を安定して低損失動作させるために、平坦化膜の表面粗さRaが0.05μm以下となるように研磨処理を施す工程を含むことが望ましい。
【0013】
また、特に平面研削やバフ研磨などの研磨方法によった場合、研磨処理中に平坦化膜の表面が酸化して加工変質層となり導電性の悪化を招く場合がある。従って、ウェットエッチング等により、この加工変質層を除去することが望ましい。
【0014】
【発明の実施の形態】
以下、本発明の実施の形態を図を参照して詳細に説明する。
【0015】
[第1実施例、図1〜図2]
第1実施例の薄膜多層電極を有する素子1を、図1に示す。図1は素子1の断面図であり、誘電体基板2上に平坦化膜3および薄膜多層電極4が形成されて構成されている。誘電体基板2にはポア7が存在しているが、平坦化膜3によって、誘電体基板2の表面は平坦化されている。平坦化膜3上には薄膜導体層5と薄膜誘電体層6とを交互に積層して構成された薄膜多層電極4が形成されている。薄膜多層電極4を構成する各層は、ポア7の影響を受けることなくそれぞれ平坦に形成されている。
【0016】
次に、本実施例の素子1の製造方法について図2(a)〜(d)を用いて説明する。
【0017】
まず誘電体基板2を準備し、該基板上にスパッタリング法によってTiからなる平坦化膜3を形成する。平坦化膜3はポア7の窪んだ部分が十分に埋まる程度以上に厚く成膜する(図2(a)、(b))。つぎに、必要以上に厚く成膜された平坦化膜3の不要部分(すなわち平坦化膜のうち、誘電体基板の平坦化に寄与していない部分)を研磨処理によって除去する(図2(c))。そして、研磨処理の施された平坦化膜3上に薄膜多層電極4を所定の膜厚設計値に基づいて形成する(図2(d))。以上のようにして素子1を製造する。
【0018】
ところで、本実施例において平坦化膜3の材料としてTiを使用したのは、TiがSiO2などからなる誘電体基板2およびCuなどからなる薄膜導体層5の双方に対して高い密着度を有するからである。このように密着性の高い材料を使用することにより、経時劣化や熱膨張係数の差によって生じる膜剥がれを効果的に抑制することができる。誘電体基板2および薄膜導体層5の双方に対して高い密着度を有する材料としては、Tiの他にTa、W、Cr、Zr、Nb、Hf、V、Mo、Ti−N、Ta−N、あるいはこれらを2種以上混合して得られる材料、あるいはこれらに添加物を加えた材料を考慮しうる。なお、これらの材料は薄膜多層電極4を構成する薄膜導体層5と薄膜誘電体層6との間にも接着層として介在させる場合が多いが、この接着層と平坦化膜の材料は成膜効率を向上させるために共通化することが好ましい。
【0019】
以上で平坦化膜に好適な材料について説明したが、これに限定するものではなく、成膜の用に供することのできる材料であれば既知の種々の材料を使用することができる。例えば、薄膜導体層として使用するCu、Ag、Au、Alや、Y−Ba−Cu−Oに代表される超伝導体、また薄膜誘電体層として使用するSiO2、Al23、Si34、Ta25等の使用が可能である。
【0020】
なお本実施例において、平坦化膜3の成膜にスパッタリング法を用いたのは、ポアを平坦化するために要する膜厚が比較的薄く済むからである。これにより、成膜時間の短縮化が図れ同時に研磨処理に要する時間も短縮することができる。また、平坦化膜3上に形成する薄膜多層電極4は通常スパッタリング法によって形成されるので、成膜手法の共通化をはかれる。もっとも成膜方法はこれに限定するものではなく、蒸着法、MO−CVD法等の真空成膜法、印刷焼成法、電解メッキ法および無電解メッキ法などの種々の成膜法を使用することができる。
【0021】
また本実施例の平坦化膜3の研磨処理の具体的方法としては、平面研削、バフ研磨、斜め方向からのミリング、ウェットエッチング等の種々の研磨方法を用いることができる。なお、平坦化膜の表面粗さRaが0.05μm以下となるように研磨処理を施すと、薄膜多層電極4を構成する薄膜導体層5や薄膜誘電体層6を、薄膜多層電極4が当初の設計値通りに安定して低損失動作をする程度に平坦に形成することができることが確認されている。
【0022】
[第2実施例]
本発明の第2実施例の薄膜多層電極を有する素子は、平坦化膜の不要部分を研磨処理によって除去した後に、さらに以下で説明する加工変質層をウェットエッチングによって除去することを特徴とする。
【0023】
すなわち、平面研削やバフ研磨などの物理的な研削方法で研磨処理を施す場合には、一般に、摩擦により研磨表面が比較的高温となったり、研磨工程中に研磨する表面を水洗する。このような状況下においては研磨表面が非常に酸化しやすくなるが、研磨表面が酸化されると平坦化膜3の導電性の悪化を引き起こし、その上に形成される薄膜多層電極の特性に悪影響を及ぼす。また、研磨表面が酸化すると平坦化膜3の有する密着性が悪化するので、平坦化膜3の有する膜剥がれの抑制効果を十分に実現できなくなる。
【0024】
そこで加工変質層、すなわち平坦化膜の表面に形成された酸化物の層を、平坦化膜3表面の表面粗さを所望の値に保ちつつ酸化物層を除去しうるウェットエッチングによって改めて除去したものである。
【0025】
なお、その他の点においては素子の構造、製造方法のいづれにおいても第1実施例の素子1と変わるところはないので、その説明を省略する。
【0026】
【発明の効果】
以上の説明からも明らかなように、本発明の薄膜多層電極を有する素子やその製造方法によった場合、以下の優れた効果が得られる。
【0027】
すなわち、平坦化膜に研磨処理を施して基板の平坦化に寄与していない部分の平坦化膜は積極的に除去することにより、誘電体基板と薄膜多層電極との間に介在する平坦化膜の膜厚を薄くすることができる。これにより平坦化膜が薄膜多層電極の特性に及ぼす影響を低く抑えることができる。また従来と異なり、研磨処理によって平坦化するので、ポア部分が埋まる程度まで成膜すれば足り、平坦化膜表面が完全に平坦化されるまで成膜し続ける必要がなくなるので、成膜時間の短縮を図ることができる。
【0028】
また、平坦化膜にTi、Ta、W、Cr、Zr、Nb、Hf、V、Mo、Ti−N、Ta−N、あるいはこれらを2種以上混合して得られる材料、あるいはこれらに添加物を加えた材料を使用することにより、その接着作用により誘電体基板と薄膜多層電極との密着度を高めることができ、経時劣化や熱膨張係数の差によって生じる膜剥がれを効果的に抑制することができる。またこれらの材料は、薄膜多層電極を構成する薄膜導体層と薄膜誘電体層との接着のためにも用いられており、使用する材料を共通化でき成膜の効率化を図ることができる。
【0029】
さらに、除去工程において平坦化膜の表層に生じた加工変質層をウェットエッチングにより除去することにより、平坦化膜の導電性および密着性を良好に保つことができる。
【図面の簡単な説明】
【図1】 本発明の第1実施例の薄膜多層電極を有する素子の断面図である
【図2】(a)〜(d) 素子の製造方法を示す図である。
【図3】 従来例の薄膜多層電極を有する素子の断面図である。
【図4】(a)〜(d) 異なる従来例の薄膜多層電極の製造方法を示す図である。
【符号の説明】
1、31 ・・・ 薄膜多層電極を有する素子
2、32 ・・・ 誘電体基板
3、33 ・・・ 平坦化膜
4、34 ・・・ 薄膜多層電極
5、35 ・・・ 薄膜導体層
6、36 ・・・ 薄膜誘電体層
7、37 ・・・ ポア
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an element having a thin film multilayer electrode mainly used in a high frequency region and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, as electronic components have been miniaturized, devices have been miniaturized by using high dielectric constant materials even in high frequency bands such as microwaves, quasi-millimeter waves, and millimeter waves. However, when the shape is reduced by using a high dielectric constant material, there is a problem in that energy loss increases in inverse proportion to the cubic root of the volume. The energy loss of this high-frequency device can be broadly classified into conductor loss due to the skin effect and dielectric loss due to the dielectric material. In recent years, dielectric materials having low loss characteristics even with high dielectric constants. Therefore, the conductor loss dominates the energy loss rather than the dielectric loss.
[0003]
Under the circumstances as described above, the present applicant disclosed in International Application Publication No. WO95 / 06336 that a thin film conductor layer, a thin film dielectric layer, and a thin film dielectric layer are formed on a dielectric substrate as electrodes capable of reducing conductor loss in a high frequency band. A thin film multi-layer electrode was proposed, which was constructed by alternately laminating layers through adhesive layers. The thin film multilayer electrode proposed here is assumed to be formed on a dielectric substrate having a flat surface (a sapphire substrate made of a single crystal of alumina subjected to mirror polishing is exemplified). Each film thickness of the thin film conductor layer and the thin film dielectric layer is set as follows.
[0004]
[Problems to be solved by the invention]
However, for example, when a ceramic substrate is used as the dielectric substrate, the substrate surface usually has irregularities due to the presence of pores or the like. The unevenness can be flattened to some extent by surface polishing or the like. However, since there are a large number of pores not only on the substrate surface but also on the inside of the substrate, a new pore becomes apparent on the surface by the polishing process, and the substrate surface cannot be sufficiently flattened. Here, FIG. 3 shows a cross-sectional view showing a film structure when a thin film multilayer electrode is formed on a dielectric substrate having a pore. As shown in FIG. 3, the thin film conductor layer 35 and the thin film dielectric layer 36 are laminated on the dielectric substrate 32 to form the thin film multilayer electrode 34. The thin film conductor layer 35 and the thin film dielectric layer 36 are Corrugations corresponding to the pores 37 of the substrate 32 are provided. If each layer is formed with irregularities in this way, the low-loss operation as originally designed cannot be realized. Further, when a thin film is laminated on a substrate having a pore, there is a very high possibility that adjacent thin film conductor layers are short-circuited in the film formation process. Any of these situations greatly deteriorates the skin effect suppression effect of the thin-film multilayer electrode.
[0005]
In response to such a problem, the applicant of the present application disclosed in Japanese Patent Application No. 8-140056 and Japanese Patent Application No. 9-288748 is a flattening for flattening the irregularities of the substrate between the dielectric substrate and the thin film multilayer electrode. A method of interposing a film was proposed to solve these problems.
[0006]
However, even if these methods are used, the following new problems have occurred. That is, in forming the planarizing film, as shown in FIGS. 4A to 4D, the planarizing film 33 is formed on the dielectric substrate 32 until the surface of the planarizing film 33 becomes flat by a technique such as sputtering. The thin film multilayer electrode 34 was formed after that. For this reason, it takes a long time to complete the formation of the planarizing film 33 and is not suitable for mass production. Further, since the planarizing film 33 is thick, there is a problem that the influence on the electrical characteristics of the thin film multilayer electrode 34 formed thereon is increased.
[0007]
Accordingly, an object of the present invention is to solve the above technical problems, and to provide an element having a thin film multilayer electrode having a structure that is not easily affected by unevenness of a substrate, and a method for manufacturing the same. There is.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, in an element having a thin film multilayer electrode of the present invention, a thin film in which a dielectric substrate and thin film conductor layers and thin film dielectric layers are alternately laminated on the dielectric substrate via an adhesive layer An element having a thin film multilayer electrode comprising a multilayer electrode and a planarization film interposed between the dielectric substrate and the thin film multilayer electrode, the surface of the planarization film in contact with the thin film multilayer electrode, A polishing process is performed to flatten the surface.
[0009]
In this way, the planarization film interposed between the dielectric substrate and the thin film multilayer electrode is removed by actively removing the portion of the planarization film that does not contribute to the planarization of the substrate by polishing the planarization film. The thickness of the chemical film can be reduced. As a result, the influence of the planarizing film on the thin film multilayer electrode can be kept low. Further, since the surface is flattened by polishing processing unlike the conventional case, it is not necessary to continue film formation until the surface is flattened, and the film formation time can be shortened.
[0010]
The planarizing film is made of Ti, Ta, W, Cr, Zr, Nb, Hf, V, Mo, Ti—N, Ta—N, or a material obtained by mixing two or more of these, or added to these. Use materials with added ingredients .
This is because these materials are easily bonded to the dielectric substrate and the thin film conductor layer constituting the thin film multilayer electrode, and the adhesion between the dielectric substrate and the thin film multilayer electrode can be increased by the adhesive action.
These materials are also used for adhesion between the thin-film conductor layer and the thin-film dielectric layer constituting the thin-film multilayer electrode, so that the materials used can be shared and the efficiency of film formation can be improved.
[0011]
The method for manufacturing an element having a thin film multilayer electrode according to the present invention comprises a thin film multilayer electrode comprising a thin film multilayer electrode in which thin film conductor layers and thin film dielectric layers are alternately laminated on a dielectric substrate via an adhesive layer. In a method for manufacturing an element having an electrode, a step of preparing a dielectric substrate, and a planarizing film for planarizing unevenness of the substrate surface on the surface of the dielectric substrate are made of Ti, Ta, W, Cr, Zr, Nb, Hf. , V, Mo, Ti—N, Ta—N, a process obtained by using a material obtained by mixing two or more of these, or a material obtained by adding an additive to these, and the surface of the planarizing film is flat The removal process which removes an unnecessary part so that it may become, and the process of forming a thin film multilayer electrode on the planarization film | membrane after a removal process.
[0012]
The removing step preferably includes a step of performing a polishing process so that the surface roughness Ra of the planarizing film is 0.05 μm or less in order to stably operate the thin-film multilayer electrode with low loss.
[0013]
In particular, when a polishing method such as surface grinding or buffing is used, the surface of the planarizing film may be oxidized during the polishing process to become a work-affected layer, resulting in deterioration of conductivity. Therefore, it is desirable to remove the work-affected layer by wet etching or the like.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0015]
[First embodiment, FIGS. 1 to 2]
An element 1 having a thin film multilayer electrode of the first embodiment is shown in FIG. FIG. 1 is a cross-sectional view of the element 1, in which a planarizing film 3 and a thin film multilayer electrode 4 are formed on a dielectric substrate 2. The dielectric substrate 2 has pores 7, but the surface of the dielectric substrate 2 is planarized by the planarization film 3. A thin film multilayer electrode 4 is formed on the planarizing film 3 by alternately laminating thin film conductor layers 5 and thin film dielectric layers 6. Each layer constituting the thin film multilayer electrode 4 is formed flat without being affected by the pore 7.
[0016]
Next, a method for manufacturing the element 1 of this example will be described with reference to FIGS.
[0017]
First, a dielectric substrate 2 is prepared, and a planarizing film 3 made of Ti is formed on the substrate by sputtering. The flattening film 3 is formed thicker than the portion where the recessed portion of the pore 7 is sufficiently filled (FIGS. 2A and 2B). Next, an unnecessary portion of the planarizing film 3 formed thicker than necessary (that is, a portion of the planarizing film that does not contribute to planarization of the dielectric substrate) is removed by polishing (FIG. 2C). )). Then, the thin-film multilayer electrode 4 is formed on the planarized film 3 subjected to the polishing process based on a predetermined thickness design value (FIG. 2D). The element 1 is manufactured as described above.
[0018]
By the way, the reason why Ti is used as the material of the planarizing film 3 in this embodiment is that Ti has high adhesion to both the dielectric substrate 2 made of SiO2 and the like and the thin film conductor layer 5 made of Cu and the like. It is. By using such a highly adhesive material, it is possible to effectively suppress film peeling caused by deterioration with time and difference in thermal expansion coefficient. Materials having high adhesion to both the dielectric substrate 2 and the thin film conductor layer 5 include Ta, W, Cr, Zr, Nb, Hf, V, Mo, Ti—N, and Ta—N in addition to Ti. Alternatively, a material obtained by mixing two or more of these, or a material obtained by adding an additive to these may be considered. In many cases, these materials are interposed as an adhesive layer between the thin-film conductor layer 5 and the thin-film dielectric layer 6 constituting the thin-film multilayer electrode 4, but the material of the adhesive layer and the flattening film is formed. It is preferable to make it common in order to improve efficiency.
[0019]
Although the material suitable for the planarization film has been described above, the present invention is not limited to this, and various known materials can be used as long as the material can be used for film formation. For example, Cu to be used as a thin film conductor layer, Ag, Au, and Al, SiO 2, Al 2 O 3 used superconductors as represented by Y-Ba-Cu-O, also as a thin film dielectric layer, Si 3 N 4 , Ta 2 O 5 or the like can be used.
[0020]
In the present embodiment, the sputtering method is used to form the planarizing film 3 because the film thickness required for planarizing the pores can be relatively thin. Thereby, the film formation time can be shortened and the time required for the polishing process can be shortened at the same time. Further, since the thin film multilayer electrode 4 formed on the planarizing film 3 is usually formed by sputtering, the film forming method can be shared. However, the film forming method is not limited to this, and various film forming methods such as vacuum film forming methods such as vapor deposition and MO-CVD, printing and baking methods, electrolytic plating methods and electroless plating methods should be used. Can do.
[0021]
Further, as a specific method for polishing the planarizing film 3 of this embodiment, various polishing methods such as surface grinding, buff polishing, milling from an oblique direction, and wet etching can be used. Note that when the polishing process is performed so that the surface roughness Ra of the planarizing film is 0.05 μm or less, the thin film multilayer electrode 4 initially forms the thin film conductor layer 5 and the thin film dielectric layer 6 constituting the thin film multilayer electrode 4. It has been confirmed that it can be formed flat enough to stably operate with low loss as designed.
[0022]
[Second Embodiment]
The element having the thin film multilayer electrode according to the second embodiment of the present invention is characterized in that after the unnecessary portion of the flattening film is removed by the polishing process, the work-affected layer described below is further removed by wet etching.
[0023]
That is, when a polishing process is performed by a physical grinding method such as surface grinding or buffing, generally, the polishing surface becomes relatively high due to friction, or the surface to be polished is washed with water during the polishing process. Under such circumstances, the polishing surface is very easily oxidized, but if the polishing surface is oxidized, the conductivity of the planarizing film 3 is deteriorated, and the characteristics of the thin film multilayer electrode formed thereon are adversely affected. Effect. Further, when the polished surface is oxidized, the adhesiveness of the planarizing film 3 is deteriorated, so that the effect of suppressing the film peeling of the planarizing film 3 cannot be realized sufficiently.
[0024]
Therefore, the work-affected layer, that is, the oxide layer formed on the surface of the flattening film, was removed again by wet etching that can remove the oxide layer while maintaining the surface roughness of the surface of the flattening film 3 at a desired value. Is.
[0025]
In other respects, the structure and manufacturing method of the element are the same as those of the element 1 of the first embodiment, and the description thereof is omitted.
[0026]
【The invention's effect】
As is clear from the above description, the following excellent effects can be obtained by the element having the thin film multilayer electrode of the present invention and the method for manufacturing the same.
[0027]
That is, the planarization film interposed between the dielectric substrate and the thin-film multilayer electrode is removed by applying a polishing process to the planarization film and actively removing the portion of the planarization film that does not contribute to the planarization of the substrate. The film thickness can be reduced. As a result, the influence of the planarizing film on the characteristics of the thin-film multilayer electrode can be kept low. Also, unlike the conventional case, since the surface is flattened by the polishing process, it is sufficient to form the film until the pores are filled, and it is not necessary to continue the film formation until the flattened film surface is completely flattened. Shortening can be achieved.
[0028]
Further, Ti, Ta, W, Cr, Zr, Nb, Hf, V, Mo, Ti-N, Ta-N, or a material obtained by mixing two or more of these, or additives to the planarizing film By using this material, the adhesion between the dielectric substrate and the thin film multilayer electrode can be increased by the adhesive action, and the film peeling caused by the deterioration with time and the difference in thermal expansion coefficient can be effectively suppressed. Can do. These materials are also used for adhesion between the thin-film conductor layer and the thin-film dielectric layer constituting the thin-film multilayer electrode, so that the materials used can be shared and the efficiency of film formation can be improved.
[0029]
Furthermore, by removing the work-affected layer generated on the surface layer of the planarizing film in the removing step by wet etching, the conductivity and adhesion of the planarizing film can be kept good.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an element having a thin film multilayer electrode according to a first embodiment of the present invention. FIGS. 2 (a) to (d) are diagrams showing a method for manufacturing the element.
FIG. 3 is a cross-sectional view of a device having a thin film multilayer electrode of a conventional example.
FIGS. 4A to 4D are diagrams showing a method for manufacturing a thin film multilayer electrode of a different conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 31 ... Element 2 which has a thin film multilayer electrode, 32 ... Dielectric substrate 3, 33 ... Planarization film 4, 34 ... Thin film multilayer electrode 5, 35 ... Thin film conductor layer 6, 36: Thin film dielectric layers 7, 37: Pore

Claims (4)

誘電体基板と、誘電体基板上に薄膜導体層と薄膜誘電体層とを接着層を介して交互に積層した薄膜多層電極と、誘電体基板と薄膜多層電極との間に介在された平坦化膜とを備えてなる薄膜多層電極を有する素子であって、
前記平坦化膜の薄膜多層電極と接する面に、その表面を平坦化するための研磨処理が施されており、かつ前記平坦化膜は、Ti、Ta、W、Cr、Zr、Nb、Hf、V、Mo、Ti−N、Ta−N、あるいはこれらを2種以上混合して得られる材料、あるいはこれらに添加物を加えた材料からなることを特徴とする薄膜多層電極を有する素子。
A dielectric substrate, a thin film multilayer electrode in which thin film conductor layers and thin film dielectric layers are alternately laminated on the dielectric substrate via an adhesive layer, and planarization interposed between the dielectric substrate and the thin film multilayer electrode An element having a thin film multilayer electrode comprising a film,
A surface of the flattening film in contact with the thin film multilayer electrode is subjected to a polishing process for flattening the surface , and the flattening film includes Ti, Ta, W, Cr, Zr, Nb, Hf, An element having a thin-film multilayer electrode, characterized by comprising V, Mo, Ti—N, Ta—N, a material obtained by mixing two or more of these, or a material obtained by adding an additive thereto .
誘電体基板上に薄膜導体層と薄膜誘電体層とを交互に積層した薄膜多層電極を形成してなる薄膜多層電極を有する素子の製造方法において、
誘電体基板を準備する工程と、
誘電体基板表面に、基板表面の凹凸を平坦化する平坦化膜を、Ti、Ta、W、Cr、Zr、Nb、Hf、V、Mo、Ti−N、Ta−N、あるいはこれらを2種以上混合して得られる材料、あるいはこれらに添加物を加えた材料を用いて形成する工程と、
平坦化膜の表面が平坦になるように不要部分を除去する除去工程と、
除去工程後の平坦化膜上に薄膜多層電極を形成する工程と、を有することを特徴とする薄膜多層電極を有する素子の製造方法。
In a method for manufacturing an element having a thin film multilayer electrode formed by forming a thin film multilayer electrode in which thin film conductor layers and thin film dielectric layers are alternately laminated on a dielectric substrate,
Preparing a dielectric substrate; and
A flattening film for flattening the unevenness of the substrate surface on the surface of the dielectric substrate is Ti, Ta, W, Cr, Zr, Nb, Hf, V, Mo, Ti-N, Ta-N, or two of these. A step of using a material obtained by mixing the above, or a material obtained by adding an additive to these, and
A removal step of removing unnecessary portions so that the surface of the planarization film becomes flat;
And a step of forming a thin film multilayer electrode on the planarized film after the removing step. A method of manufacturing an element having a thin film multilayer electrode.
前記除去工程は、平坦化膜の表層に生じた加工変質層をウェットエッチングにより除去する工程を含むことを特徴とする請求項に記載の薄膜多層電極を有する素子の製造方法。3. The method of manufacturing an element having a thin film multilayer electrode according to claim 2 , wherein the removing step includes a step of removing the work-affected layer generated on the surface layer of the planarizing film by wet etching. 前記除去工程は、平坦化膜の表面粗さRaが0.05μm以下となるように研磨処理を施す工程を含むことを特徴とする請求項または請求項に記載の薄膜多層電極を有する素子の製造方法。Said removing step includes elements having a thin-film multilayer electrode according to claim 2 or claim 3 surface roughness Ra of the flattening film is characterized in that it comprises a step of performing polishing processing so as to 0.05μm or less Manufacturing method.
JP33188597A 1997-12-02 1997-12-02 Device having thin film multilayer electrode and method for manufacturing the same Expired - Fee Related JP3750324B2 (en)

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