JP2003017366A - Thin film capacitor element and its manufacturing method - Google Patents

Thin film capacitor element and its manufacturing method

Info

Publication number
JP2003017366A
JP2003017366A JP2001201036A JP2001201036A JP2003017366A JP 2003017366 A JP2003017366 A JP 2003017366A JP 2001201036 A JP2001201036 A JP 2001201036A JP 2001201036 A JP2001201036 A JP 2001201036A JP 2003017366 A JP2003017366 A JP 2003017366A
Authority
JP
Japan
Prior art keywords
electrode
thin film
layer
substrate
capacitor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001201036A
Other languages
Japanese (ja)
Other versions
JP3934366B2 (en
Inventor
Kiyoshi Sato
清 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP2001201036A priority Critical patent/JP3934366B2/en
Publication of JP2003017366A publication Critical patent/JP2003017366A/en
Application granted granted Critical
Publication of JP3934366B2 publication Critical patent/JP3934366B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a thin film capacitor element in which a high Q can be realized while preventing short circuit of electrodes surely and limitation on the available substrate is not severe. SOLUTION: A resist pattern 10 is formed on an underlying material 9 formed on the surface of a substrate 1 and after the surface of the underlying material 9 is subjected to electrolytic plating of a conductive material 11, the resist pattern 10 is stripped and unnecessary underlying material 9 is removed thus forming a laminate of the underlying material 9 and the conductive material 11 having a desired shape on the substrate 1. Subsequently, an insulating material 12 is deposited on the substrate 1 to cover the laminate and the conductive material 11 is polished together with the insulating material 12 thus forming first and second electrode parts 2 and 3 and an insulator layer 4 having flattened upper surface on the substrate 1. Thereafter, a dielectric layer 5 is patterned on the upper surface of the first electrode part 2 and the insulator layer 4 and a first upper electrode part 6 being connected with the upper surface of the first electrode part 2 and a second upper electrode part 7 being connected with the upper surface of the second electrode part 3 through the surface of the dielectric layer 5 are formed thus obtaining a thin film capacitor element where the first electrode part 2 faces the second upper electrode 7 through the dielectric layer 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、各種の小型電子回
路に用いられる薄膜キャパシタ素子およびその製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film capacitor element used in various small electronic circuits and a method for manufacturing the same.

【0002】[0002]

【従来の技術】図5は従来より知られている薄膜キャパ
シタ素子の断面図であり、この薄膜キャパシタ素子は基
板100上に順次形成された下部電極101と誘電体層
102および上部電極103の積層構造となっている。
2. Description of the Related Art FIG. 5 is a cross-sectional view of a conventionally known thin film capacitor element. This thin film capacitor element is formed by laminating a lower electrode 101, a dielectric layer 102 and an upper electrode 103 which are sequentially formed on a substrate 100. It has a structure.

【0003】基板100はアルミナ100aの表面全体
にガラス膜100bをコーティングしたグレーズドアル
ミナ基板で、その表面はガラス膜100bによって平滑
化されている。下部電極101は基板100上にスパッ
タ法やめっき法を用いて形成したCu等を所望のパター
ン形状にエッチングしたものであり、この下部電極10
1の端部にはテーパが形成されている。誘電体層102
は基板100と下部電極101上にスパッタ法やCVD
法を用いて形成したSiOを所望のパターン形状にエ
ッチングしたものであり、パターニング後の誘電体層1
02は下部電極101の表面と端部のテーパ面を通って
基板100上まで延びている。上部電極103は基板1
00と誘電体層102上にスパッタ法やめっき法を用い
て形成したCu等を所望のパターン形状にエッチングし
たものであり、パターニング後の上部電極103は誘電
体層102の表面と端部のテーパ面を通って基板100
上まで延びている。
The substrate 100 is a glazed alumina substrate in which the entire surface of the alumina 100a is coated with a glass film 100b, and the surface thereof is smoothed by the glass film 100b. The lower electrode 101 is formed by etching Cu or the like formed on the substrate 100 by a sputtering method or a plating method into a desired pattern shape.
A taper is formed at the end portion of 1. Dielectric layer 102
On the substrate 100 and the lower electrode 101 by sputtering or CVD
SiO 2 formed by using the etching method is etched into a desired pattern shape, and the dielectric layer 1 after patterning
Reference numeral 02 extends to the substrate 100 through the surface of the lower electrode 101 and the tapered surface of the end portion. The upper electrode 103 is the substrate 1
00 and Cu formed on the dielectric layer 102 by a sputtering method or a plating method are etched into a desired pattern shape, and the upper electrode 103 after patterning has a taper on the surface and the end portion of the dielectric layer 102. Substrate 100 through the surface
It extends to the top.

【0004】このように構成された薄膜キャパシタ素子
にあっては、下部電極101の端部がテーパ面となって
いるため、誘電体層102を下部電極101の表面から
基板100上にかけて均一膜厚に形成することができ、
下部電極101と上部電極103の短絡を防止すること
ができる。
In the thin film capacitor element having such a structure, since the end portion of the lower electrode 101 has a tapered surface, the dielectric layer 102 has a uniform film thickness from the surface of the lower electrode 101 to the substrate 100. Can be formed into
It is possible to prevent a short circuit between the lower electrode 101 and the upper electrode 103.

【0005】[0005]

【発明が解決しようとする課題】前述の如く構成された
従来の薄膜キャパシタ素子では、下部電極101の端部
がテーパ面となっているため、誘電体層102を下部電
極101の表面から基板100上にかけて均一膜厚に形
成することができ、下部電極101と上部電極103の
短絡を防止することができる。しかしながら、誘電体層
102の膜厚を均一化するためには、下部電極101の
テーパ角度をできるだけ緩やかにする必要があり、かか
るテーパ処理は製造工程の困難性を伴うという問題があ
った。また、このように傾斜角度の緩やかなテーパを形
成するためには、下部電極101の膜厚を薄く設定しな
ければならず、その結果、キャパシタのQ値が低下する
という問題があった。さらに、下部電極101の膜厚を
薄くしなければならないため、基板100として表面が
平滑化されたグレーズドアルミナ基板を使用する必要が
あり、安価なアルミナ基板を使用できないという制約も
あった。
In the conventional thin film capacitor element configured as described above, since the end portion of the lower electrode 101 has a tapered surface, the dielectric layer 102 is formed from the surface of the lower electrode 101 to the substrate 100. It is possible to form a uniform film thickness on the upper side, and it is possible to prevent a short circuit between the lower electrode 101 and the upper electrode 103. However, in order to make the film thickness of the dielectric layer 102 uniform, it is necessary to make the taper angle of the lower electrode 101 as gentle as possible, and there is a problem that such a taper process involves difficulty in the manufacturing process. Further, in order to form such a taper having a gentle inclination angle, it is necessary to set the film thickness of the lower electrode 101 thin, and as a result, there is a problem that the Q value of the capacitor is lowered. Furthermore, since the film thickness of the lower electrode 101 must be reduced, it is necessary to use a glaze alumina substrate having a smooth surface as the substrate 100, and there is a restriction that an inexpensive alumina substrate cannot be used.

【0006】本発明は、このような従来技術の実情に鑑
みてなされたもので、その目的は、電極の短絡を確実に
防止できると共に高Q値化を実現でき、かつ、使用可能
な基板の制限が少ない薄膜キャパシタ素子を提供するこ
とにある。
The present invention has been made in view of the circumstances of the prior art as described above, and an object of the present invention is to reliably prevent a short circuit of an electrode and realize a high Q value, and to provide a usable substrate. An object is to provide a thin film capacitor element with few restrictions.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明による薄膜キャパシタ素子では、基板上に絶
縁体層によって分離された第1および第2の下部電極を
形成すると共に、これら絶縁体層と第1および第2の下
部電極の上面を平坦面となし、前記第1の下部電極上に
形成した誘電体層の端部を少なくとも前記絶縁体層まで
延出し、この誘電体層上に形成した上部電極を前記第2
の下部電極の上面に積層したことを特徴としている。
In order to achieve the above object, in a thin film capacitor element according to the present invention, first and second lower electrodes separated by an insulating layer are formed on a substrate, and at the same time, these insulating layers are formed. The upper surface of the body layer and the first and second lower electrodes are flat surfaces, and the end portion of the dielectric layer formed on the first lower electrode is extended to at least the insulator layer. The upper electrode formed on the second
It is characterized by being laminated on the upper surface of the lower electrode of.

【0008】このように構成された薄膜キャパシタ素子
にあっては、絶縁体層と第1および第2の下部電極の上
面が同一平面に平坦化処理されており、この平坦面に誘
電体層と上部電極が順次積層されているため、下部電極
の厚膜化を実現できると共に電極間の短絡を確実に防止
することができ、安価なアルミナ基板の使用も可能とな
る。
In the thin film capacitor element thus constructed, the upper surfaces of the insulating layer and the first and second lower electrodes are flattened to the same plane, and the flat surface is covered with the dielectric layer. Since the upper electrode is sequentially laminated, the lower electrode can be made thicker and a short circuit between the electrodes can be surely prevented, and an inexpensive alumina substrate can be used.

【0009】上記の構成において、薄膜キャパシタ素子
の容量値は誘電体層を介して対向する第1の下部電極と
上部電極の重なる範囲によって決定されが、この上部電
極とは別に第1の下部電極にも上部電極を接続すること
が好ましい。
In the above structure, the capacitance value of the thin film capacitor element is determined by the overlapping range of the first lower electrode and the upper electrode that face each other with the dielectric layer in between. Also, it is preferable to connect the upper electrode.

【0010】また、上記目的を達成するために、本発明
による薄膜キャパシタ素子の製造方法では、基板上にギ
ャップによって分離された一対の下部電極をめっき形成
する下部電極形成工程と、前記ギャップの内部に絶縁体
層を成膜する絶縁体層形成工程と、前記両下部電極およ
び前記絶縁体層の上面を同一平面にする平坦化処理工程
と、前記一方の下部電極の上面から少なくとも前記絶縁
体層の上面にかけて誘電体層を形成する誘電体層形成工
程と、前記誘電体層の上面から前記他方の下部電極の上
面にかけて上部電極をめっき形成する上部電極形成工程
とを具備することを特徴としている。
In order to achieve the above object, in the method of manufacturing a thin film capacitor element according to the present invention, a lower electrode forming step of forming a pair of lower electrodes separated by a gap on a substrate by plating, and the inside of the gap. An insulating layer forming step of forming an insulating layer on the insulating layer, a flattening step of making the upper surfaces of the lower electrodes and the insulating layer flush with each other, and at least the insulating layer from the upper surface of the one lower electrode. And a dielectric layer forming step of forming a dielectric layer on the upper surface of the dielectric layer, and an upper electrode forming step of forming an upper electrode by plating from the upper surface of the dielectric layer to the upper surface of the other lower electrode. .

【0011】このような構成によれば、めっきを用いて
厚膜の下部電極を形成することにより、電極の低抵抗化
や高Q値化を実現することができ、しかも、一対の下部
電極と絶縁体層の上面が同一平面に平坦化処理され、こ
の平坦面に誘電体層と上部電極が順次積層されると共
に、この上部電極に接続する下部電極と誘電体層の真下
に位置する下部電極とが絶縁体層を介して絶縁されてい
るため、電極間の短絡を確実に防止することができる。
According to such a structure, by forming the thick film lower electrode by plating, it is possible to realize a lower resistance and a higher Q value of the electrode, and moreover, to form a pair of lower electrodes. The upper surface of the insulator layer is flattened on the same plane, the dielectric layer and the upper electrode are sequentially laminated on the flat surface, and the lower electrode connected to the upper electrode and the lower electrode located directly below the dielectric layer Since and are insulated via the insulator layer, it is possible to reliably prevent a short circuit between the electrodes.

【0012】上記の構成において、上部電極形成工程と
して、誘電体層上に積層される上部電極とは別に誘電体
層の真下の下部電極上にも別の上部電極を同時にめっき
形成することが好ましい。
In the above structure, it is preferable that, in the upper electrode forming step, another upper electrode is simultaneously formed on the lower electrode directly below the dielectric layer by plating, in addition to the upper electrode laminated on the dielectric layer. .

【0013】また、上記の構成において、下部電極形成
工程として、基板上に下地層を形成した後、この下地層
の表面にレジストパターンを形成して金属材料をめっき
し、しかる後、レジストパターンを剥離して露出した下
地層を除去する工程を採用すると、所望形状の下部電極
と絶縁体層を簡単に形成することができるので好まし
い。
Further, in the above structure, in the lower electrode forming step, after forming an underlayer on the substrate, a resist pattern is formed on the surface of the underlayer and a metal material is plated, and then the resist pattern is formed. It is preferable to employ a step of removing the underlying layer exposed by peeling because the lower electrode and the insulating layer having a desired shape can be easily formed.

【0014】[0014]

【発明の実施の形態】以下、発明の実施の形態について
図面を参照して説明すると、図1は本発明の実施形態例
に係る薄膜キャパシタ素子の断面図、図2と図3は該薄
膜キャパシタ素子の製造工程を示す説明図である。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a thin film capacitor element according to an embodiment of the present invention, and FIGS. 2 and 3 are the thin film capacitor. It is explanatory drawing which shows the manufacturing process of an element.

【0015】図1に示すように、本実施形態例に係る薄
膜キャパシタ素子は、基板1上に形成された第1の電極
部2と第2の電極部3および絶縁体層4と、これらの平
坦な上面に形成された誘電体層5と第1の上部電極6お
よび第2の上部電極7とで構成されており、第1および
第2の電極部2,3は下地層8を介して基板1上に形成
されている。第1の電極部2と第2の電極部3とは絶縁
体層4によって分離されており、第1の上部電極6は第
1の電極部2からその左隣の絶縁体層4の上面にかけて
形成されている。誘電体層5は第1の電極部2からその
右隣の絶縁体層4の上面にかけて形成されており、第2
の上部電極7は誘電体層5から第2の電極部3の上面に
かけて形成されている。第1の電極部2と第1の上部電
極6は薄膜キャパシタ素子の下部電極として機能し、第
2の電極部3と第2の上部電極7は薄膜キャパシタ素子
の上部電極として機能するものであり、この薄膜キャパ
シタ素子の容量値は誘電体層5を介して対向する第1の
電極部2と第2の上部電極7の重なり部分で規定され
る。
As shown in FIG. 1, the thin film capacitor element according to the present embodiment example includes a first electrode portion 2, a second electrode portion 3 and an insulating layer 4 formed on a substrate 1, and these. It is composed of a dielectric layer 5 formed on a flat upper surface, a first upper electrode 6 and a second upper electrode 7, and the first and second electrode portions 2 and 3 are provided with an underlying layer 8 in between. It is formed on the substrate 1. The first electrode portion 2 and the second electrode portion 3 are separated by the insulator layer 4, and the first upper electrode 6 extends from the first electrode portion 2 to the upper surface of the insulator layer 4 adjacent on the left side thereof. Has been formed. The dielectric layer 5 is formed from the first electrode portion 2 to the upper surface of the insulator layer 4 on the right side of the first electrode portion 2.
The upper electrode 7 is formed from the dielectric layer 5 to the upper surface of the second electrode portion 3. The first electrode portion 2 and the first upper electrode 6 function as the lower electrode of the thin film capacitor element, and the second electrode portion 3 and the second upper electrode 7 function as the upper electrode of the thin film capacitor element. The capacitance value of this thin film capacitor element is defined by the overlapping portion of the first electrode portion 2 and the second upper electrode 7 that face each other with the dielectric layer 5 in between.

【0016】基板1にはグレーズドアルミナ基板やグレ
ーズの無いアルミナ基板が用いられ、本実施形態例では
純度99.5%のアルミナ基板を使用しているため、基
板1の表面の面粗度(Ra)は30〜100nm程度の
凹凸面となっている。下地層8としてはCr/Cu、T
i/Cu、Cr/Au、Ti/Au等が用いられ、これ
らの材料を基板1の表面にスパッタ法や蒸着法あるいは
イオンビームスパッタ等を用いて成膜することによって
形成される。この場合、基板1への密着層となる下層の
CrやTiの厚みは5〜50nm、上層のCuやAuの
厚みは50〜200nm程度が好ましい。
A glaze alumina substrate or a glaze-free alumina substrate is used as the substrate 1. Since the alumina substrate having a purity of 99.5% is used in this embodiment, the surface roughness (Ra) of the surface of the substrate 1 is ) Is an uneven surface of about 30 to 100 nm. Cr / Cu, T as the underlayer 8
i / Cu, Cr / Au, Ti / Au, or the like is used, and these materials are formed on the surface of the substrate 1 by sputtering, vapor deposition, ion beam sputtering, or the like. In this case, it is preferable that the thickness of Cr or Ti in the lower layer, which is the adhesion layer to the substrate 1, be 5 to 50 nm, and the thickness of Cu or Au in the upper layer be about 50 to 200 nm.

【0017】第1および第2の電極部2,3にはCu、
Au、Cu/Ni、Cu/Ni−P等の導体材料が用い
られ、これらの導体材料を下地層8の表面に電解めっき
することによって形成される。下地層8と第1および第
2の電極部2,3は同一形状に形成されており、この場
合、基板1上に成膜した下地層8の表面に所望形状のレ
ジストパターンを形成した後、上記した導体材料を下地
層8の表面に電解めっきし、その後にレジストを剥離す
れば所望形状の第1および第2の電極部2,3が形成さ
れる。そして、かかるレジスト剥離後、レジストパター
ンによって覆われていた下地層8をイオンミリング法を
用いて除去すれば、第1および第2の電極部2,3と同
一形状の下地層8が形成される。絶縁体層4にはAl
等の絶縁材料が用いられ、この絶縁材料をスパッタ
法やCVD法により第1および第2の電極部2,3を覆
うように基板1上に成膜した後、第1および第2の電極
部2,3と絶縁材料の表面をCMP(Chemical Mechani
cal Polish)法を用いて平坦化することによって形成さ
れる。
Cu is used for the first and second electrode portions 2 and 3,
Conductive materials such as Au, Cu / Ni, and Cu / Ni-P are used, and they are formed by electrolytically plating these conductive materials on the surface of the underlayer 8. The base layer 8 and the first and second electrode portions 2 and 3 are formed in the same shape. In this case, after forming a resist pattern of a desired shape on the surface of the base layer 8 formed on the substrate 1, By electroplating the surface of the underlayer 8 with the above-described conductor material, and then removing the resist, the first and second electrode portions 2 and 3 having a desired shape are formed. After the resist is peeled off, the underlying layer 8 covered with the resist pattern is removed by ion milling to form the underlying layer 8 having the same shape as the first and second electrode portions 2 and 3. . Al 2 is used as the insulator layer 4.
An insulating material such as O 3 is used. The insulating material is formed on the substrate 1 by sputtering or CVD so as to cover the first and second electrode portions 2 and 3, and then the first and second insulating materials are formed. The surfaces of the electrodes 2 and 3 and the insulating material are CMP (Chemical Mechanical)
It is formed by flattening using the cal polish) method.

【0018】誘電体層5にはSiO、Ta、A
lSiO等の絶縁材料が用いられ、これらの絶縁材料
をスパッタ法やCVD法により成膜した後、これを所望
形状にパターニングすることによって形成される。より
具体的には、まず、第1および第2の電極部2,3と絶
縁体層4の表面にSiO、Ta、AlSiO
等の絶縁材料を成膜した後、この絶縁材料上にレジスト
を塗布し、このレジストを露光/現像することにより所
望形状のレジストパターンを形成する。しかる後、この
レジストパターンをマスクとして、RIE法においては
CFガスまたはCあるいはそれらにOを添加
したガスを用いて絶縁材料をエッチングし、RIE法以
外ではArガスを用いたイオンミリング法にて絶縁材料
をエッチングし、その後にレジストパターンを剥離すれ
ば所望形状の誘電体層5が形成される。
SiO is used for the dielectric layer 5.Two, TaTwoO5, A
lSiOTwoInsulating materials such as
After forming a film by sputtering or CVD method, this is desired
It is formed by patterning into a shape. Than
Specifically, first, disconnect the first and second electrode portions 2 and 3.
SiO on the surface of the edge layer 4Two, TaTwoO5, AlSiO Two
After depositing an insulating material such as
By coating and exposing / developing this resist.
A resist pattern having a desired shape is formed. After this, this
In the RIE method using the resist pattern as a mask
CFFourGas or CThreeF8Or O to themTwoAdd
The insulating material is etched by using the selected gas, and the
Insulating material outside by ion milling method using Ar gas
The resist pattern and then remove the resist pattern.
For example, the dielectric layer 5 having a desired shape is formed.

【0019】第1および第2の上部電極6,7は第1お
よび第2の電極部2,3と同様の手法によって形成され
る。すなわち、誘電体層5を含む第1および第2の電極
部2,3と絶縁体層4の表面に下地層を形成し、この下
地層の表面に両上部電極6,7に対応した形状のレジス
トパターンを形成した後、Cu、Au、Cu/Ni、C
u/Ni−P等の導体材料を下地層の表面に電解めっき
し、その後にレジストを剥離して不要な下地層をイオン
ミリング法にて除去すれば、所望形状の第1および第2
の上部電極6,7が形成される。
The first and second upper electrodes 6 and 7 are formed in the same manner as the first and second electrode portions 2 and 3. That is, a base layer is formed on the surfaces of the first and second electrode portions 2 and 3 including the dielectric layer 5 and the insulator layer 4, and the surface of the base layer has a shape corresponding to both upper electrodes 6 and 7. After forming the resist pattern, Cu, Au, Cu / Ni, C
If a conductive material such as u / Ni-P is electroplated on the surface of the underlayer and then the resist is peeled off and the unnecessary underlayer is removed by the ion milling method, the first and second desired shapes can be obtained.
Upper electrodes 6 and 7 are formed.

【0020】次に、このように構成された薄膜キャパシ
タ素子の製造工程について主として図2と図3を用いて
説明する。
Next, the manufacturing process of the thin film capacitor element thus constructed will be described mainly with reference to FIGS.

【0021】まず、下部電極形成工程として、図2
(a)に示すように、基板(アルミナ基板またはグレー
ズドアルミナ基板)1の表面にCr/Cu、Ti/C
u、Cr/Au、Ti/Au等の下地材料9をスパッタ
法や蒸着法あるいはイオンビームスパッタ等により成膜
した後、図2(b)に示すように、この下地材料9上に
塗布したフォトレジストを所望のパターン形状に露光・
現像してレジストパターン10を形成する。次に、図2
(c)に示すように、レジストパターン10が形成され
た下地材料9の表面にCu、Au、Cu/Ni、Cu/
Ni−P等の導体材料11を電解めっきする。この導体
材料11は第1および第2の電極部2,3を形成するも
ので、その膜厚は回路設計によって決定されるが、1.
5〜5.0μm程度の膜厚が好ましい。次に、図2
(d)に示すように、レジストパターン10を剥離した
後、図2(e)に示すように、イオンミリング法にてA
rイオンを0〜30度の角度で入射し、レジストパター
ン10の剥離によって露出した下地材料9を除去する
と、第1および第2の電極部2,3と同一形状の下地層
8が形成される。
First, as a lower electrode forming step, FIG.
As shown in (a), Cr / Cu, Ti / C are formed on the surface of the substrate (alumina substrate or glazed alumina substrate) 1.
After forming a base material 9 such as u, Cr / Au, or Ti / Au by a sputtering method, a vapor deposition method, an ion beam sputtering, or the like, as shown in FIG. Exposing the resist to the desired pattern shape
The resist pattern 10 is formed by developing. Next, FIG.
As shown in (c), Cu, Au, Cu / Ni, Cu / is formed on the surface of the base material 9 on which the resist pattern 10 is formed.
A conductor material 11 such as Ni-P is electrolytically plated. The conductor material 11 forms the first and second electrode portions 2 and 3, and the film thickness thereof is determined by the circuit design.
A film thickness of about 5 to 5.0 μm is preferable. Next, FIG.
After removing the resist pattern 10 as shown in FIG. 2D, as shown in FIG.
When the r ion is incident at an angle of 0 to 30 degrees and the base material 9 exposed by peeling the resist pattern 10 is removed, a base layer 8 having the same shape as the first and second electrode portions 2 and 3 is formed. .

【0022】次に、絶縁体層形成工程として、図3
(a)に示すように、Al等の絶縁材料12をス
パッタ法やCVD法により基板1上に成膜し、この絶縁
材料12によって導体材料11を完全に覆った後、平坦
化処理工程として、導体材料11と絶縁材料12をCM
P法により同図の破線位置まで研磨する。その結果、導
体材料11と絶縁材料12の上面が同一平面に平坦化さ
れ、図3(b)に示すように、基板1上に上面が平坦化
された第1および第2の電極部2,3と絶縁体層4が形
成される。
Next, as an insulating layer forming step, FIG.
As shown in (a), an insulating material 12 such as Al 2 O 3 is formed on the substrate 1 by a sputtering method or a CVD method, the conductor material 11 is completely covered with the insulating material 12, and then a flattening treatment is performed. In the process, the conductor material 11 and the insulating material 12 are commercialized.
The P method is used to polish to the position indicated by the broken line in FIG. As a result, the upper surfaces of the conductor material 11 and the insulating material 12 are flattened on the same plane, and as shown in FIG. 3B, the first and second electrode portions 2 having the flattened upper surfaces on the substrate 1 are formed. 3 and the insulator layer 4 are formed.

【0023】次に、誘電体層形成工程として、平坦化さ
れた第1および第2の電極部2,3と絶縁体層4の表面
にSiO、Ta、AlSiO等の絶縁材料を
スパッタ法等により成膜した後、これをフォトリソ技術
を用いて所望形状にパターニングすることにより、図3
(c)に示すように、第1の電極部2と絶縁体層4の上
面に誘電体層5を形成する。なお、この誘電体層5は少
なくとも第1の電極部2の上面から絶縁体層4の上面に
かけて形成する必要があるが、絶縁体層4を越えて第2
の電極部3の上面まで延ばしても良い。
Next, as a dielectric layer forming step, an insulating material such as SiO 2 , Ta 2 O 5 or AlSiO 2 is formed on the surfaces of the flattened first and second electrode portions 2 and 3 and the insulating layer 4. 3 is formed by sputtering and then patterned into a desired shape by using a photolithography technique.
As shown in (c), the dielectric layer 5 is formed on the upper surfaces of the first electrode portion 2 and the insulating layer 4. Although the dielectric layer 5 needs to be formed at least from the upper surface of the first electrode portion 2 to the upper surface of the insulator layer 4, the dielectric layer 5 extends beyond the insulator layer 4 to the second surface.
It may be extended to the upper surface of the electrode part 3.

【0024】次に、上部電極形成工程として、図3
(d)に示すように、第1の電極部2の上面に接続する
第1の上部電極6と、誘電体層5の表面を通って第2の
電極部3の上面に接続する第2の上部電極7とを形成す
る。かかる上部電極形成工程は、前述した下部電極形成
工程と同じプロセスであるため、ここでは詳細な説明を
省略する。
Next, as an upper electrode forming step, FIG.
As shown in (d), the first upper electrode 6 connected to the upper surface of the first electrode portion 2 and the second upper electrode 6 connected to the upper surface of the second electrode portion 3 through the surface of the dielectric layer 5. The upper electrode 7 is formed. Since the upper electrode forming process is the same as the lower electrode forming process described above, detailed description thereof is omitted here.

【0025】このように本実施形態例に係る薄膜キャパ
シタ素子では、めっきを用いて厚膜の第1の電極部2と
第2の電極部3を形成すると共に、薄膜キャパシタ素子
の下部電極が第1の電極部2と第1の上部電極6の2層
構造で、薄膜キャパシタ素子の上部電極も第2の電極部
3と第2の上部電極7の2層構造であるため、電極の低
抵抗化や高Q値化を実現することができる。また、第1
および第2の電極部2,3と絶縁体層4の上面が同一平
面に平坦化処理され、この平坦面に誘電体層5と第2の
上部電極7が順次積層されると共に、誘電体層5の真下
に位置する第1の電極部2と第2の上部電極7に接続す
る第2の電極部3とが絶縁体層4を介して絶縁されてい
るため、薄膜キャパシタ素子の上部電極と下部電極間の
短絡を確実に防止することができる。
As described above, in the thin film capacitor element according to the present embodiment, the first electrode portion 2 and the second electrode portion 3 which are thick films are formed by plating, and the lower electrode of the thin film capacitor element is formed into the first electrode portion. 1 has a two-layer structure of the electrode portion 2 and the first upper electrode 6, and the upper electrode of the thin film capacitor element also has a two-layer structure of the second electrode portion 3 and the second upper electrode 7. And high Q value can be realized. Also, the first
The upper surfaces of the second electrode portions 2 and 3 and the insulating layer 4 are flattened on the same plane, and the dielectric layer 5 and the second upper electrode 7 are sequentially laminated on the flat surface and the dielectric layer is formed. Since the first electrode portion 2 located immediately below 5 and the second electrode portion 3 connected to the second upper electrode 7 are insulated via the insulator layer 4, It is possible to surely prevent a short circuit between the lower electrodes.

【0026】なお、上記実施形態例では、第1の上部電
極6が第1の電極部2の引き出し部分に部分的にオーバ
ーラップするように形成されているが、第2の電極部3
と第2の上部電極7の接続構造と同様に、第1の上部電
極6を第1の電極部2に完全にオーバーラップするよう
に形成しても良く、このように構成すると、電極の低抵
抗化や高Q値化をさらに推進することができる。
In the embodiment described above, the first upper electrode 6 is formed so as to partially overlap the lead-out portion of the first electrode portion 2, but the second electrode portion 3 is formed.
Similarly to the connection structure between the first upper electrode 6 and the second upper electrode 7, the first upper electrode 6 may be formed so as to completely overlap with the first electrode portion 2. Resistance and high Q value can be further promoted.

【0027】図4は電子回路基板への適用例を示す断面
図であり、この電子回路基板は各種の高周波デバイスと
して使用されるものである。同図に示すように、この電
子回路基板の基板1上には、薄膜キャパシタ素子20と
薄膜抵抗素子30および薄膜インダクタ素子40等の薄
膜回路素子が形成されており、これらの薄膜回路素子2
0,30,40は必要とされる回路構成に応じて基板1
上の有効エリア内に多数形成されている。なお、薄膜キ
ャパシタ素子20は前述した実施形態例と同様に構成さ
れているため、ここでは重複する説明を省略することと
する。
FIG. 4 is a cross-sectional view showing an application example to an electronic circuit board, and this electronic circuit board is used as various high frequency devices. As shown in the figure, thin film circuit elements such as a thin film capacitor element 20, a thin film resistance element 30, and a thin film inductor element 40 are formed on a substrate 1 of this electronic circuit board.
0, 30, 40 are the substrate 1 depending on the required circuit configuration.
Many are formed in the upper effective area. Since the thin film capacitor element 20 has the same configuration as that of the above-described embodiment, duplicate description will be omitted here.

【0028】薄膜抵抗素子30は、基板1上に形成され
たヒートシンク部31と一対の電極部32および絶縁体
層33、これらの平坦な上面に順次積層された絶縁膜3
4と抵抗膜35および保護膜36とで構成されており、
ヒートシンク部31と一対の電極部32は絶縁体層33
によって分離されている。ヒートシンク部31と一対の
電極部32は薄膜キャパシタ素子20の第1および第2
の電極部2,3と同一材料からなり、これらは同一工程
で形成される。また、絶縁体層33は薄膜キャパシタ素
子20の絶縁体層4と同一材料からなり、これらも同一
工程で形成される。絶縁膜34はヒートシンク部31の
上面を覆ってその両側の絶縁体層33まで延びており、
この絶縁膜34はAlSiO,AlSiN,AlSiO
N,AlN,Al,SiO等の絶縁材料をスパ
ッタ法やCVD法等により成膜した後、これを所望形状
にパターニングすることによって形成される。抵抗膜3
5は絶縁膜34を覆って一対の電極部32の上面まで延
びており、この抵抗膜35はTaNやTaSiO等の抵
抗材料をスパッタ法等により成膜した後、これを所望形
状にパターニングすることによって形成される。保護膜
36は抵抗膜35を覆っており、この保護膜36はポリ
イミドやレジスト等の有機系絶縁材料またはSiO
Al等の無機系絶縁材料をスパッタ法等により成
膜した後、これを所望形状にパターニングすることによ
って形成される。
The thin film resistance element 30 includes a heat sink portion 31 formed on the substrate 1, a pair of electrode portions 32, an insulating layer 33, and an insulating film 3 sequentially laminated on the flat upper surfaces thereof.
4 and the resistance film 35 and the protection film 36,
The heat sink portion 31 and the pair of electrode portions 32 are made of an insulating layer 33.
Are separated by. The heat sink portion 31 and the pair of electrode portions 32 serve as the first and second electrodes of the thin film capacitor element 20.
The electrode parts 2 and 3 are made of the same material and are formed in the same step. The insulator layer 33 is made of the same material as the insulator layer 4 of the thin film capacitor element 20, and these are also formed in the same process. The insulating film 34 covers the upper surface of the heat sink portion 31 and extends to the insulating layers 33 on both sides thereof,
The insulating film 34 is made of AlSiO, AlSiN, AlSiO.
It is formed by forming a film of an insulating material such as N, AlN, Al 2 O 3 , or SiO 2 by a sputtering method, a CVD method, or the like, and then patterning this into a desired shape. Resistive film 3
Reference numeral 5 covers the insulating film 34 and extends to the upper surfaces of the pair of electrode portions 32. This resistance film 35 is formed by forming a resistance material such as TaN or TaSiO by a sputtering method or the like and then patterning it into a desired shape. Formed by. The protective film 36 covers the resistance film 35. The protective film 36 is formed of an organic insulating material such as polyimide or resist, or SiO 2 ,
It is formed by forming a film of an inorganic insulating material such as Al 2 O 3 by a sputtering method or the like and then patterning this into a desired shape.

【0029】薄膜インダクタ素子40は、基板1上に形
成された導体層41および絶縁体層42と、これらの導
体層41と絶縁体層42の平坦な上面に形成された絶縁
層43と、導体層41の内端部上面から絶縁層43上を
通って外側へ導出する内側電極44、および導体層41
の外端部上面から絶縁層43上を通って引き回された外
側電極45とで構成されており、導体層41は平面視渦
巻き状に形成されている。導体層41は薄膜キャパシタ
素子20の両電極部2,3や薄膜抵抗素子30のヒート
シンク部31および両電極部32と同一材料からなり、
これらは同一工程で形成される。絶縁体層42は薄膜キ
ャパシタ素子20の絶縁体層4や薄膜抵抗素子30の絶
縁体層33と同一材料からなり、これらも同一工程で形
成される。絶縁層43は、AlSiO、SiO、T
等の無機系絶縁材料を導体層41と絶縁体層4
2上にスパッタ法等により成膜した後、これを所望形状
にパターニングしたもの、またはレジスト等の有機系絶
縁材料をフォトリソ技術により形成して高温で硬化させ
たもので、パターニング後の絶縁層43は導体層41の
内端部上面と外端部上面を露出する形状となっている。
内側電極44と外側電極45はCu、Cu/Ni、Cu
/Ni−P、Cu/Ni/Au、Cu/Ni−P/A
u、Au等の導体材料からなり、これらの導体材料を導
体層41と同一プロセスで絶縁層43の表面に電解めっ
きすることによって形成される。
The thin film inductor element 40 includes a conductor layer 41 and an insulator layer 42 formed on the substrate 1, an insulating layer 43 formed on the flat upper surfaces of the conductor layer 41 and the insulator layer 42, and a conductor. The inner electrode 44 extending from the upper surface of the inner end portion of the layer 41 to the outside through the insulating layer 43, and the conductor layer 41.
And an outer electrode 45 that is routed from the upper surface of the outer end of the conductive layer 41 over the insulating layer 43, and the conductor layer 41 is formed in a spiral shape in plan view. The conductor layer 41 is made of the same material as the electrode portions 2 and 3 of the thin film capacitor element 20, the heat sink portion 31 and the electrode portions 32 of the thin film resistance element 30,
These are formed in the same process. The insulator layer 42 is made of the same material as the insulator layer 4 of the thin film capacitor element 20 and the insulator layer 33 of the thin film resistance element 30, and these are also formed in the same process. The insulating layer 43 is made of AlSiO 2 , SiO 2 , T
Inorganic insulating material such as a 2 O 5 is used for the conductor layer 41 and the insulator layer 4.
The insulating layer 43 after patterning is formed by depositing a film on the substrate 2 by a sputtering method or the like and then patterning it into a desired shape, or by forming an organic insulating material such as a resist by a photolithography technique and curing it at a high temperature. Has a shape exposing the upper surface of the inner end portion and the upper surface of the outer end portion of the conductor layer 41.
The inner electrode 44 and the outer electrode 45 are made of Cu, Cu / Ni, Cu
/ Ni-P, Cu / Ni / Au, Cu / Ni-P / A
It is made of a conductor material such as u or Au, and is formed by electrolytically plating these conductor materials on the surface of the insulating layer 43 in the same process as the conductor layer 41.

【0030】このように構成された電子回路基板におい
ては、薄膜キャパシタ素子20の第1および第2の電極
部2,3と、薄膜抵抗素子30のヒートシンク部31と
両電極部32および絶縁体層33と、薄膜インダクタ素
子40の導体層41および絶縁体層42とを、前述した
図2(a)〜図2(e)に示す下部電極形成工程と図3
(a)に示す絶縁体層形成工程および図3(b)に示す
平坦化処理工程によって同一プロセスで形成できるた
め、電子回路基板の製造工程を簡略化することができ
る。また、薄膜抵抗素子30の抵抗膜35がヒートシン
ク部31と両電極部32および絶縁体層33の平坦面に
絶縁膜34を介して形成されているため、めっきを用い
て厚膜のヒートシンク部31と両電極部32を形成する
ことにより電極の低抵抗化を実現することができると共
に、抵抗膜形成面の凹凸に起因する抵抗値のばらつきを
低減でき、しかも、抵抗膜35からの発熱をその真下の
ヒートシンク部31によって効率良く放熱できる。さら
に、薄膜インダクタ素子40の絶縁層43と内側電極4
4は、平坦化処理された導体層41と絶縁体層42の上
面に積層形成されているため、めっきを用いて厚膜の導
体層41を形成することにより高Q値化を実現すること
ができると共に、絶縁層43と内側電極44および外側
電極45の製造工程を簡略化することができる。
In the electronic circuit board thus constructed, the first and second electrode portions 2 and 3 of the thin film capacitor element 20, the heat sink portion 31 of the thin film resistance element 30, both electrode portions 32 and the insulator layer. 33, the conductor layer 41 and the insulator layer 42 of the thin film inductor element 40, and the lower electrode forming step shown in FIG. 2A to FIG.
Since the insulating layer forming step shown in (a) and the flattening step shown in FIG. 3 (b) can be formed in the same process, the manufacturing process of the electronic circuit board can be simplified. Further, since the resistance film 35 of the thin film resistance element 30 is formed on the flat surfaces of the heat sink portion 31, both electrode portions 32 and the insulator layer 33 with the insulating film 34 interposed therebetween, the thick film heat sink portion 31 is formed by plating. By forming both the electrode portions 32 and, it is possible to reduce the resistance of the electrodes, reduce the variation in the resistance value due to the unevenness of the resistance film forming surface, and heat generated from the resistance film 35 can be reduced. The heat sink 31 directly below can efficiently dissipate heat. Furthermore, the insulating layer 43 of the thin film inductor element 40 and the inner electrode 4
Since No. 4 is laminated on the upper surfaces of the conductor layer 41 and the insulator layer 42 that have been flattened, it is possible to realize a high Q value by forming the thick conductor layer 41 by plating. In addition, the manufacturing process of the insulating layer 43, the inner electrode 44, and the outer electrode 45 can be simplified.

【0031】[0031]

【発明の効果】本発明は、以上説明したような形態で実
施され、以下に記載されるような効果を奏する。
The present invention is carried out in the form as described above, and has the following effects.

【0032】基板上にめっきを用いて厚膜の下部電極を
形成することにより、電極の低抵抗化や高Q値化を実現
することができ、しかも、一対の下部電極と絶縁体層の
上面が同一平面に平坦化処理され、これらの平坦面に誘
電体層と上部電極が順次積層されているため、電極間の
短絡を確実に防止することができるばかりでなく、安価
なアルミナ基板の使用も可能となる。
By forming a thick film lower electrode on the substrate by plating, lower resistance and higher Q value of the electrode can be realized, and moreover, a pair of lower electrode and the upper surface of the insulating layer are formed. Is planarized on the same plane, and the dielectric layer and the upper electrode are sequentially laminated on these flat surfaces, so that it is possible to reliably prevent a short circuit between the electrodes and use an inexpensive alumina substrate. Will also be possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施形態例に係る薄膜キャパシタ素子
の断面図である。
FIG. 1 is a cross-sectional view of a thin film capacitor element according to an exemplary embodiment of the present invention.

【図2】該薄膜キャパシタ素子の製造工程を示す説明図
である。
FIG. 2 is an explanatory view showing a manufacturing process of the thin film capacitor element.

【図3】該薄膜キャパシタ素子の製造工程を示す説明図
である。
FIG. 3 is an explanatory view showing a manufacturing process of the thin film capacitor element.

【図4】本発明を適用した電子回路基板の断面図であ
る。
FIG. 4 is a cross-sectional view of an electronic circuit board to which the present invention has been applied.

【図5】従来例に係る薄膜キャパシタ素子の断面図であ
る。
FIG. 5 is a cross-sectional view of a thin film capacitor element according to a conventional example.

【符号の説明】[Explanation of symbols]

1 基板 2 第1の電極部 3 第2の電極部3 4 絶縁体層 5 誘電体層 6 第1の上部電極 7 第2の上部電極 8 下地層 9 下地材料 10 レジストパターン 11 導体材料 12 絶縁材料 20 薄膜キャパシタ素子 30 薄膜抵抗素子 40 薄膜インダクタ素子 1 substrate 2 First electrode part 3 Second electrode part 3 4 Insulator layer 5 Dielectric layer 6 First upper electrode 7 Second upper electrode 8 Underlayer 9 Base material 10 Resist pattern 11 Conductor material 12 Insulation material 20 Thin film capacitor element 30 Thin film resistance element 40 Thin film inductor element

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 基板上に絶縁体層によって分離された第
1および第2の下部電極を形成すると共に、これら絶縁
体層と第1および第2の下部電極の上面を平坦面とな
し、前記第1の下部電極上に形成した誘電体層の端部を
少なくとも前記絶縁体層まで延出し、この誘電体層上に
形成した上部電極を前記第2の下部電極の上面に積層し
たことを特徴とする薄膜キャパシタ素子。
1. A first lower electrode and a second lower electrode which are separated by an insulating layer are formed on a substrate, and the upper surfaces of the insulating layer and the first lower electrode are made flat. The end portion of the dielectric layer formed on the first lower electrode extends to at least the insulator layer, and the upper electrode formed on the dielectric layer is laminated on the upper surface of the second lower electrode. Thin film capacitor element.
【請求項2】 請求項1の記載において、前記第1の下
部電極の上面に別の上部電極を積層したことを特徴とす
る薄膜キャパシタ素子。
2. The thin film capacitor element according to claim 1, wherein another upper electrode is laminated on the upper surface of the first lower electrode.
【請求項3】 基板上にギャップによって分離された一
対の下部電極をめっき形成する下部電極形成工程と、前
記ギャップの内部に絶縁体層を成膜する絶縁体層形成工
程と、前記両下部電極および前記絶縁体層の上面を同一
平面にする平坦化処理工程と、前記一方の下部電極の上
面から少なくとも前記絶縁体層の上面にかけて誘電体層
を形成する誘電体層形成工程と、前記誘電体層の上面か
ら前記他方の下部電極の上面にかけて上部電極をめっき
形成する上部電極形成工程とを具備することを特徴とす
る薄膜キャパシタ素子の製造方法。
3. A lower electrode forming step of forming a pair of lower electrodes separated by a gap on a substrate by plating, an insulating layer forming step of forming an insulating layer inside the gap, and both lower electrodes. And a flattening treatment step for making the upper surface of the insulator layer flush with each other; a dielectric layer forming step for forming a dielectric layer from the upper surface of the one lower electrode to at least the upper surface of the insulator layer; An upper electrode forming step of forming an upper electrode by plating from the upper surface of the layer to the upper surface of the other lower electrode.
【請求項4】 請求項3の記載において、前記上部電極
形成工程が、前記上部電極と前記一方の下部電極の上面
に積層された別の上部電極とを同時にめっき形成する工
程を含むことを特徴とする薄膜キャパシタ素子の製造方
法。
4. The method according to claim 3, wherein the upper electrode forming step includes a step of simultaneously forming the upper electrode and another upper electrode stacked on the upper surface of the one lower electrode by plating. And a method for manufacturing a thin film capacitor element.
【請求項5】 請求項3または4の記載において、前記
下部電極形成工程が、前記基板上に下地層を形成した
後、この下地層の表面にレジストパターンを形成して金
属材料をめっきし、しかる後、前記レジストパターンを
剥離して露出した前記下地層を除去する工程を含むこと
を特徴とする薄膜キャパシタ素子の製造方法。
5. The method according to claim 3 or 4, wherein in the lower electrode forming step, after forming an underlayer on the substrate, a resist pattern is formed on a surface of the underlayer and a metal material is plated, Then, the method of manufacturing a thin film capacitor element, which comprises a step of removing the exposed underlayer by peeling the resist pattern.
JP2001201036A 2001-07-02 2001-07-02 Method for manufacturing thin film capacitor element Expired - Fee Related JP3934366B2 (en)

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