JP3743809B2 - Power circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power supply circuit, and more particularly to a power supply circuit including a charge pump circuit that generates and outputs a predetermined voltage level by controlling charging / discharging of a capacitive element according to an input voltage.
[0002]
[Prior art]
In general, in an electronic circuit that requires a plurality of different voltage levels as a driving voltage, such as a liquid crystal display device, an input voltage is generated by using a power supply circuit that generates an output voltage having a new voltage level based on the input voltage. The number of power sources and the number of power sources are reduced. As such a power supply circuit, a so-called charge pump type that controls charging / discharging operation to a capacitive element based on an input voltage and outputs a voltage level corresponding to the amount of charge accumulated in the capacitive element as an output voltage. The power supply circuit is known.
[0003]
Hereinafter, an example of a conventional charge pump type power supply circuit will be described with reference to the drawings.
As shown in FIG. 3, a conventional charge pump type power supply circuit is roughly divided into an input terminal Nin to which a charge pump driving clock signal (hereinafter referred to as clock pulse) CP is applied, and an input terminal Nin. The inverter element groups INV1 to INV3 are connected in series between the high-potential-side voltage level VDD supplied from the external power supply and the output terminal Nout, and are turned on based on the output voltage from the inverter element groups INV1 to INV3. Transistor group Tr11-Tr15 to be controlled / OFF, a capacitor C11 connected between a contact N11 (terminal NA) of the transistors Tr11 and Tr12 and a contact N14 (terminal NB) of the transistors Tr14 and Tr15, and an input terminal Nin A transistor connected between the contact N12 (terminal NC) of the transistors Tr12 and Tr13. A capacitor C12, and is configured with a.
[0004]
The transistor Tr11 is composed of a PMOS transistor, and the transistors Tr12 to Tr15 are composed of NMOS transistors. The output potential of the inverter element INV3 is applied to the gates of the transistors Tr11, Tr12, Tr15, and the output potential of the inverter element INV2 is applied to the gates of the transistors Tr13, Tr14. Here, the inverter element INV1 performs an inverter operation based on the power supply voltage VDD-VSS, and the inverter elements INV2 and INV3 are configured to perform an inverter operation based on the power supply voltage VDD-VEE, and are applied to the input terminal Nin. With the clock pulse CP, the voltage level is sequentially shifted from VCC-VSS to VDD-VEE so that the subsequent transistor groups Tr11 to Tr15 are driven as analog switches.
[0005]
Further, the voltage level VSS on the low potential side is directly applied to the contact N13 of the transistors Tr13 and Tr14. Further, the output terminal Nout is connected to a capacitor C13 whose other end is connected to the voltage level VSS on the low potential side, and to a predetermined load (not shown). Therefore, the capacitor C13 may be a capacitance parasitic to the load connected to the output terminal Nout.
In such a configuration, the input terminal Nin has a clock whose low-potential side voltage level is VSS (here, ground potential GND) and whose high-potential side voltage level is VCC (that is, voltage amplitude VCC−VSS). By applying the pulse CP, an output voltage having a voltage level VEE = − (VDD + VCC) is output from the output terminal Nout.
[0006]
Specifically, when the clock pulse CP is at a high level (voltage level VCC), the output of the inverter element INV2 shown in FIG. 3 is at a high level (VDD), the output of INV3 is at a low level (VEE), and the transistor Tr11 Tr13 and Tr14 are turned on, and therefore, as shown in the equivalent circuit of the connection state in FIG. 4A (the relationship between the connection state of the transistor group and the capacitor and the voltage level), the voltage level VDD is applied across the capacitor C11. And the voltage level VSS is applied, and the voltage level VCC and the voltage level VSS are applied to both ends of the capacitor C12. The capacitor C13 to which the voltage level VSS is applied to one end is connected to the output terminal Nout (voltage level VEE) independently of (disconnected from) the other capacitors C11 and C12.
Thus, when the clock pulse CP is at a high level, the capacitor C1 is charged with the voltage levels VDD and VSS, and the capacitor C2 is charged with the voltage levels VCC and VSS.
[0007]
On the other hand, when the clock pulse CP is at the low level (voltage level VSS), the output of the inverter element INV2 shown in FIG. 3 is at the low level (VEE), the output of INV3 is at the high level (VDD), and the transistors Tr12 and Tr15 are turned on. Since the ON state is established, capacitors C11 and C12 are connected in series as shown in the equivalent circuit of the connection state in FIG. 4B (the relationship between the connection state of the transistor group and the capacitor and the voltage level), and is connected to one end side. The voltage level VSS is applied, and the other end is connected to the output terminal Nout (voltage level VEE). The capacitor C13 to which the voltage level VSS is applied to one end side is connected in parallel with the other capacitors C11 and C12 via the output terminal Nout (voltage level VEE).
[0008]
Thus, when the clock pulse CP is at the low level, the voltage levels charged in the capacitors C1 and C2 are added (VDD + VCC), and the polarity is inverted with respect to the output terminal Nout. (VDD + VCC) is generated, and this voltage level is charged in the capacitor C13 and supplied as the output voltage VEE.
Therefore, in the conventional charge pump type power supply circuit, the charge (charged voltage level) accumulated in the capacitor is added by periodically repeating the high level and the low level with a clock pulse having a predetermined voltage amplitude. These are combined and output as an output voltage VEE.
[0009]
[Problems to be solved by the invention]
As described above, the conventional power supply circuit described above has a configuration in which the output voltage VEE is generated by serially connecting capacitors C1 and C2 that are individually charged. However, the combined capacitance (sum of reciprocals) of the capacitors C1 and C2 was smaller than the capacitance of the capacitor C1 or C2 alone. For this reason, when the load connected to the output terminal Nout fluctuates intermittently or when a large load is temporarily applied, the potential fluctuation of the output potential VEE increases (resistance to load fluctuation decreases), which is favorable. There was a problem that it was impossible to supply the voltage level.
[0010]
Therefore, the present invention solves the above-described problem, and even when the load connected to the output terminal fluctuates, the power supply circuit can suppress the potential fluctuation and supply a stable output voltage. The purpose is to provide.
[0011]
[Means for Solving the Problems]
The power supply circuit according to claim 1, charge storage means including first and second capacitive elements;
Based on a power supply means including predetermined first and second constant voltage power supplies, and an input signal having a predetermined voltage amplitude, the first and second capacitive elements, and the first and second capacitors comprising a connection state setting means for setting switching a connection state between the between the element first and second power supply, wherein the connection state setting means, at the first timing of said input signal, said first capacitor a first charge amount than the first constant voltage power supply as well as storage, sets the connection state to output a potential based on the amount of charge accumulated in the second capacitor as the output voltage, the in the second timing of the input signals, supplies the second charge amount to said second of said second capacitive element from the constant voltage power source, the first capacitive element at a first timing of the input signal stored the 1 of the charge amount, the in order to move to the second capacitor, the first capacitive element to set the connection state so as to connect in series with said second capacitor, said second A charge amount that is a sum of the first charge amount and the second charge amount accumulated in the first capacitor element at a first timing of the input signal is accumulated in the capacitor element, and the first timing and The connection state at the second timing is repeated at a predetermined cycle.
[0012]
The power supply circuit according to claim 2 is the power supply circuit according to claim 1, wherein the output voltage is obtained by combining the first charge amount and the second charge amount stored in the second capacitor element. The voltage is based on the amount of charge.
A power supply circuit according to a third aspect of the present invention is the power supply circuit according to the first or second aspect, wherein the connection state setting means includes the first and second capacitive elements, and the first and second capacitance elements. A plurality of switching elements for switching the connection state between the capacitor element and the first and second constant voltage power supplies, and a drive voltage generating means for generating a drive voltage for individually controlling the operations of the plurality of switching elements; The drive voltage generation means generates the drive voltage at the first timing and the second timing based on the voltage amplitude of the input signal and applies the generated drive voltage to the plurality of switching elements. It is a feature.
[0013]
Power circuit according to claim 4, wherein, in the power supply circuit of claim 3, wherein the plurality of switching elements, and said drive voltage generating means is characterized by being constituted by the transistors of the electric field effect.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a power supply circuit according to the present invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram showing an embodiment of a power supply circuit according to the present invention. Here, the same components as those in the prior art will be described with the same reference numerals.
As shown in FIG. 1, the power supply circuit according to the present embodiment is roughly divided into an input terminal Nin to which a clock pulse (input signal) CP for driving the power supply circuit is applied, and three stages connected to the input terminal Nin. The inverter element groups INV1 to INV3 are connected in series between the high-potential-side voltage level VDD supplied from the external power supply and the output terminal Nout. Based on the output voltage from the inverter element groups INV1 to INV3, ON / A transistor group Tr1 to Tr3 to be controlled OFF, a capacitor (first capacitive element) C1 connected between the output (terminal Na) of the inverter element INV1 and the contact N1 (terminal Nb) of the transistors Tr1 and Tr2, A capacitor (second capacitor) C2 connected between the input terminal Nin and the contact N2 (terminal Nc) of the transistors Tr2 and Tr3. It is configured Te.
[0015]
Each of the transistor groups Tr1 to Tr3 is composed of an N-type field effect transistor (NMOS transistor). The output potential of the inverter element INV3 is applied to the gates of the transistors Tr1 and Tr3, and the gate of the transistor Tr2 is The output potential of the inverter element INV2 is applied. Here, the inverter element INV1 is driven by the power supply voltage VDD-VSS, and the inverter elements INV2 and INV3 are driven by the power supply voltage VDD-VEE, and the clock pulse CP applied to the input terminal Nin causes the latter stage. The voltage level is sequentially shifted from VCC-VSS to VDD-VSS and VDD-VEE so that the transistor groups Tr1 to Tr3 are driven as analog switches.
[0016]
The output terminal Nout is connected to a capacitor C3 whose other end is connected to the low potential side voltage level VSS and to a predetermined load (not shown). Accordingly, the capacitor C3 may be a capacitance parasitic to the load connected to the output terminal Nout.
Here, the capacitors C1 and C2 are capacitive elements and constitute charge storage means. Further, the transistors Tr1 to Tr3 are switching elements, and the inverter element groups INV1 to INV3 are drive voltage generation means, which constitute connection state setting means.
[0017]
Next, the operation of the power supply circuit having the above-described configuration will be described with reference to the drawings.
FIG. 2 is an equivalent circuit diagram showing the relationship between the voltage level and the connection state of the transistor group and the capacitor in the power supply circuit according to the present embodiment.
In the configuration as described above, the voltage level VEE = − (VDD + VCC) is output from the output terminal Nout by applying the clock pulse CP having the voltage amplitude VCC−VSS to the input terminal Nin as in the configuration of the prior art. The output voltage having is output.
[0018]
Specifically, when the clock pulse CP is at a low level (voltage level VSS) (first timing), the output of the inverter element INV1 shown in FIG. 1 is high level (VDD), and the output of INV2 is low level ( VEE) and INV3 output are at a high level (VDD), and the transistors Tr1 and Tr3 are turned on. Therefore, as shown in the equivalent circuit of the connection state in FIG. The level VDD and the voltage level VSS are applied. The voltage level VSS is applied to one end Nin of the capacitor C2, and the other end Nc is connected to the output terminal Nout (voltage level VEE). Further, the capacitor C3 to which the voltage level VSS is applied to one end side is connected to the output terminal Nout (voltage level VEE).
Thus, when the clock pulse CP is at a low level, the capacitor C1 is charged based on the potential difference between the voltage levels VDD and VSS, and the capacitor C3 is charged by the capacitor C2 connected to the output terminal Nout. As described below, after the clock pulse CP passes the high level (voltage level VCC), the charge of VDD + VCC is accumulated in the capacitor C2, so that the output voltage VEE is output to the capacitor C3. In the initial state, the voltage charged in the capacitor is unknown.
[0019]
On the other hand, when the clock pulse CP is at a high level (voltage level VCC) (second timing), the output of the inverter element INV1 is low level (VSS), the output of INV2 is high level (VDD), and the output of INV3 is low. Since the level becomes VEE and only the transistor Tr2 is turned on, the capacitors C1 and C2 are connected in series as shown in the equivalent circuit of the connection state in FIG. 2B, and the voltage levels VDD and VSS are connected in the capacitor C1. In accordance with the voltage charged based on the potential difference, the accumulated charge is transferred to the capacitor C2. That is, a potential of −VDD is applied to one end side (low potential side; Nc) of the capacitor C2. In addition, at this time, the high voltage level VCC is applied to the other end side (high potential side; Nin) of the capacitor C2 by the clock pulse CP. Note that the capacitor C3 to which the voltage level VSS is applied to one end is disconnected from the other capacitors C1 and C2 and connected to the output terminal Nout (voltage level VEE).
[0020]
As a result, when the clock pulse CP is at a high level, the potential difference VDD + VCC is applied to the capacitor C2, and charges are stored according to the potential difference.
When the clock pulse CP becomes low level again, as described above, the low potential side (terminal Nc) of the capacitor C2 is connected to the output terminal Nout. By applying the voltage level of the level and the low level, the capacitor C3 is charged with the charge supplied from the capacitor C2, and the output voltage VEE having a voltage level of − (VDD + VCC) is stably output.
[0021]
Therefore, according to the power supply circuit according to the present embodiment, unlike the operation of the charge pump type power supply circuit (FIGS. 3 and 4) in the prior art described above, the output is based on the charge accumulated in the single capacitor C2. Since the voltage is generated and output, the capacitance value can be increased, and when charging is performed in a sufficiently long time so as not to be affected by the time constant, more charge is supplied from the capacitors C2 to C3. Can do. Therefore, even when the load connected to the output terminal Nout fluctuates intermittently or when a large load is temporarily applied, fluctuations in the output potential can be suppressed and stable power can be supplied. .
[0022]
Further, in the power supply circuit according to the present embodiment, a power supply having high resistance to load fluctuation can be configured with a configuration in which three NMOS transistors are connected in series as a switching element for switching the connection state of the capacitors C1 to C3. Therefore, compared with the prior art, the circuit configuration can be further simplified and reduced in size, and the manufacturing process can be simplified. Furthermore, by adopting a CMOS configuration as the configuration of the inverter element groups INV1 to INV3 that supply drive voltages to the transistor elements Tr1 to Tr3, it can be manufactured in the same process as the MOS transistors that constitute the transistor elements Tr1 to Tr3. Further simplification of the manufacturing process and miniaturization of the power supply circuit can be achieved.
[0023]
In the present embodiment, the case where the externally supplied voltages (VDD, VCC) are added and the polarity is inverted to generate the negative output voltage VEE (= − (VDD + VCC)) has been described. The invention is not limited to this, and it goes without saying that an output voltage having a desired polarity can be generated by any combination of voltages.
In the present embodiment, the capacitors C1 and C2 are each a single capacitor, but each may be composed of a plurality of capacitors.
Further, in the present embodiment, the configuration including the inverter element group and the transistor is not particularly described. However, these connection state switching means are configured as an integrated circuit (IC) on a single substrate. May be.
[0024]
【The invention's effect】
According to the first aspect of the present invention, the first and second capacitor elements, the predetermined first and second constant voltage power supplies, and the connection state for switching and setting the connection state between the first and second capacitor elements A charge pump type power supply circuit including a setting unit, wherein the first charge amount is accumulated in the first capacitor element from the first power source at the first timing of the input signal, and the second capacitor element is stored in the second capacitor element. A potential based on the accumulated charge amount is output as an output voltage, and the second charge amount is supplied from the second power source to the second capacitor element at the second timing of the input signal, and the first capacitor Charges accumulated in the element are transferred to the second capacitor element, and the charge to the series of capacitor elements that accumulates the charge amount of the first charge amount and the second charge amount in the second capacitor element is accumulated. It is configured to repeat the accumulation and release operations at a predetermined cycle. Since it is, can result in the output potential at the second capacitive element alone is generated, as compared to the combined capacitance of the conventional series connection to increase the capacitance value. Therefore, even when a change in the load driven by the output voltage occurs or when a large load is temporarily applied, a stable power supply can be supplied while suppressing the change in the output potential.
[0025]
According to the second aspect of the present invention, the output voltage generated and output by the above configuration is based on the total amount of charges accumulated in the second capacitor element, which is the sum of the first charge amount and the second charge amount. Since the voltage is different from the voltage supplied by the first and second constant voltage power supplies, a desired voltage can be generated based on only the supplied voltage, and the power supply type and the number of power supplies can be set. It is possible to reduce the product scale and the product cost.
According to a third aspect of the present invention, the connection state setting means includes the first and second capacitive elements, and the connection between the first and second capacitive elements and the first and second constant voltage power supplies. A plurality of switching elements for switching states, and drive voltage generating means for generating a drive voltage for individually controlling the operations of the plurality of switching elements, and driving the switching elements satisfactorily based on the voltage amplitude of the input signal Therefore, the degree of freedom in setting the voltage amplitude applied to the input signal can be increased.
According to the fourth aspect of the present invention, the switching element and the driving voltage generating unit, which is configured by the transistors of the electric field effect, simplify the manufacturing process of the power supply circuit, and, by integration of the circuit scale The power supply circuit can be reduced in size.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing an embodiment of a power supply circuit according to the present invention.
FIG. 2 is an equivalent circuit diagram showing a relationship between a connection state of a transistor group and a capacitor and a voltage level in the power supply circuit according to the present embodiment.
FIG. 3 is a schematic configuration diagram showing a configuration example of a power supply circuit in a conventional technique.
FIG. 4 is an equivalent circuit diagram showing a relationship between a connection state of a transistor group and a capacitor of a power supply circuit and a voltage level in a conventional technique.
[Explanation of symbols]
Tr1-Tr3 Transistors INV1-INV3 Inverter elements C1, C2, C3 Capacitor CP Clock pulse VEE Output voltage Nin Input terminal Nout Output terminal

Claims (4)

Charge storage means comprising first and second capacitive elements;
Power supply means comprising predetermined first and second constant voltage power supplies;
Based on an input signal having a predetermined voltage amplitude, the first and second capacitive elements and the connection state between the first and second capacitive elements and the first and second power sources are switched and set. And a connection state setting means for
The connection state setting means includes
At the first timing of the input signal, as well as accumulating a first charge amount than the first constant-voltage power supply to the first capacitor, based on the amount of charge accumulated in the second capacitor potential Set the connection state to output as an output voltage,
In the second timing of the input signal, the supplies the second charge amount to a second of said second capacitive element from the constant voltage power source, said at the first timing of the input signal first capacitor The connection state is set so that the first capacitor element is connected in series to the second capacitor element in order to move the first charge amount stored in the first capacitor element to the second capacitor element. A charge amount obtained by combining the first charge amount and the second charge amount accumulated in the first capacitor element at the first timing of the input signal is accumulated in the second capacitor element ;
A power supply circuit, wherein the connection state at the first timing and the second timing is repeated at a predetermined cycle.   2. The power supply according to claim 1, wherein the output voltage is a voltage based on a charge amount accumulated in the second capacitor element, which is a sum of the first charge amount and the second charge amount. circuit. The connection state setting means includes a plurality of switching elements for switching the connection state between the first and second capacitive elements and between the first and second capacitive elements and the first and second constant voltage power supplies. And drive voltage generating means for generating a drive voltage for individually controlling the operations of the plurality of switching elements,
The drive voltage generation unit generates the drive voltage at the first timing and the second timing based on the voltage amplitude of the input signal, and applies the generated drive voltage to the plurality of switching elements. The power supply circuit according to claim 1. Wherein the plurality of switching elements, and said drive voltage generating means, the power supply circuit according to claim 3, characterized in that it is constituted by the electric field effect type transistor.

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