JP3742260B2 - Liquid crystal driver device and liquid crystal display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal driver device and a liquid crystal display device for gradation display of an image, and in particular, the number of gradation voltage signal lines and transistors in a row direction of a decoder section can be reduced, and the vertical size can be reduced. The present invention relates to a liquid crystal driver device and a liquid crystal display device.
[0002]
[Prior art]
In general, in various electronic devices such as a personal computer, a liquid crystal television, and an electronic notebook, liquid crystal display devices excellent in portability such as thin and light weight and display properties such as high definition and multi-gradation are widely used.
[0003]
FIG. 5 is a schematic diagram showing a schematic configuration of this type of general liquid crystal display device. The liquid crystal display device 10 is disposed on the outer frame side of the liquid crystal panel unit 13 and a display controller 11 that performs gradation control and synchronization control for each color of R (red), G (green), and B (blue). The LCD driver (liquid crystal driver device) 12 is controlled by the display controller 11 and outputs a gradation voltage signal to the liquid crystal panel unit 13 and is driven by the LCD drivers 12 and 14, for example, multilevel such as 64 gradations or 256 gradations. The liquid crystal panel unit 13 is capable of displaying image information, character information, and the like having the following gradations.
[0004]
Normally, the term “LCD driver” has two meanings: a gate driver 14 that outputs a scanning signal to each row electrode of the liquid crystal panel section 13 and a source driver 12 that outputs a gradation voltage signal to each column electrode. However, in this specification, the (source) driver 12 related to the gradation voltage signal is targeted.
[0005]
The LCD driver 12 includes an n-bit input decoder unit for selectively outputting a 2 ⁿ level gradation voltage signal. That is, the decoder section, on the basis of the gradation select bits n bits input from the display controller 11, among the 2 ⁿ levels of the gray scale voltage signal consisting of 2 ⁿ divided voltage, the voltage indicated by the gradation select bits One level voltage signal is selected and output. Note that the 2 ⁿ level grayscale voltage signal is always supplied from a grayscale voltage generator (not shown) to the decoder unit.
[0006]
For example, when n = 3, as shown in FIG. 6, the decoder unit 15 is supplied with eight grayscale voltage signals V1 to V8 corresponding to eight divided voltages in parallel, while each grayscale voltage signal V1. In the direction orthogonal to .about.V8, 3-bit gradation select bits A to C are inputted together with their inverted bits / A to / C.
[0007]
Here, at the intersections of the gradation voltage signals V1 to V8 and the input bits A to C, / A to / C, the input bits A to C in the truth table shown in FIG. Thus, short-circuiting MOS transistors TrA to TrC (short transistors: indicated by bold black circles in the figure) are arranged so that the input bits A to C are applied to the gates.
[0008]
When the input bits A to C in the truth table are “0”, the MOS transistors Tr / A are applied so that the inverted bits / A to / C are applied to the gates at the positions of the inverted bits / A to / C. ~ Tr / C are arranged. That is, in the truth table including both the input bits A to C and their inverted bits / A to / C, each of the MOS transistors TrA to TrC is placed at a position where each bit A to C, / A to / C is “1”. , Tr / A to Tr / C are arranged. Here, the subscripts A to C and / A to / C of the transistors TrA to TrC and Tr / A to Tr / C are made to coincide with the input bits A to C and / A to / C applied to the transistors. It is attached.
[0009]
Each of such MOS transistors TrA to TrC and Tr / A to Tr / C is for turning on / off the gradation voltage signal line based on the gate input of the hierarchical select bit. Since it is arranged corresponding to the value table, it has the function of realizing the operation of the truth table as a result.
[0010]
Accordingly, the decoder unit 15 operates according to the truth table shown in FIG. 6 and outputs the corresponding gradation voltage signal Vi (1 ≦ i ≦ 8) based on the combination of the gradation select bits A to C. Output. Regardless of which gradation voltage signal Vi is selected, the gradation voltage signal Vi is output to the same pixel column of the liquid crystal panel unit 13 via the same output pin.
[0011]
The decoder unit 15 as described above is arranged in the horizontal direction corresponding to each pixel column of the liquid crystal panel unit 13 at the subsequent stage. For this reason, the LCD driver 12 has a rectangular shape elongated in the horizontal direction, and has a shape in which 240 to 480 output pins are arranged in parallel. Here, the decoder unit 15 is designed in a layout pattern in which gradation voltage signal lines are arranged so as to increase the width (vertical width) in the row direction from the viewpoint of narrowing the width (horizontal width) in the column direction per output pin. Is done.
[0012]
Such decoder unit 15, the case of 2 ⁿ gradations, for selecting one of the gradation voltage signal lines each gradation of n bits input, 2 ⁿ row-direction gradation voltage signal line and , N × 2 ⁿ MOS transistors are required. This means that, for example, in the case of 8-bit input and 256 gradation output, 256 gradation voltage signal lines and 8 × 256 MOS transistors are arranged in the decoder unit 15. Therefore, these gradation voltage signal lines and MOS transistors use a space of 2 ⁿ rows, and thus occupy a large proportion of the size of the LCD driver 12 in the vertical direction.
[0013]
[Problems to be solved by the invention]
However, in the LCD driver and the liquid crystal display device as described above, from the viewpoint of display property that increases the area of the liquid crystal panel unit 13 occupying the area of the liquid crystal display device 10, or from the viewpoint of portability that reduces the area of the liquid crystal display device 10 itself. Therefore, it is desired to reduce the vertical size of the LCD driver 12.
[0014]
Here, in order to reduce the vertical size of the LCD driver 12, for example, the decoder unit 15 shown in FIG. 6 is modified, and the gradation voltage signal lines of the first half gradation voltage signals V1 to V4 are changed to the second half gradation. This can be dealt with by creating a layout pattern by moving the voltage signals V5 to V8 to the right or left side of the gradation voltage signal lines. However, in this case, although the size in the vertical direction can be reduced to ½ times, there is a problem that the area of the LCD driver 12 cannot be reduced in the end because the size in the horizontal direction is increased twice.
[0015]
The present invention has been made in consideration of the above circumstances, and can reduce the number of grayscale voltage signal lines and transistors arranged in the vertical direction in proportion to the number of grayscales in the decoder unit, thereby reducing the vertical size. An object is to provide a liquid crystal driver device and a liquid crystal display device.
[0016]
[Means for Solving the Problems]
The essence of the present invention is that adjacent to each other in the decoding area of the upper bits A and B excluding the least significant bit C of the decoder unit corresponding to the truth table, as illustrated in FIG. 3 and FIG. The configuration in which redundant MOS transistors and grayscale voltage signal lines are shared between grayscale voltage signal lines is to reduce the vertical size of the region occupied by the grayscale voltage signal lines.
[0017]
For example, the i-th gradation voltage signal line is compared with the i ± 1-th gradation voltage signal lines before and after the i-th gradation voltage signal line. The preceding and succeeding gradation voltage signal lines always have different values in the least significant bit C with respect to the i-th gradation voltage signal line. Bits A and B have the same value.
[0018]
Therefore, two adjacent grayscale voltage signal lines to which the upper bits A and B having the same value are input are connected to the input area of the least significant bit C (including the / C input area branched from C) and the others. The upper bits A and B are divided into input areas (including / A and / B input areas branched from A and B), and the MOS transistors and grayscale voltage signal lines in the upper bits A and B input areas are divided. Make common.
[0019]
Subsequently, the common gradation voltage signal line and the two MOS transistors in the input region of the least significant bit C are arranged in the same row. As described above, the gradation voltage signal lines in the input areas for the upper bits A and B are shared, and the MOS transistors in the input area for the least significant bit C are arranged in the same row, so that the gradation of the decoder section as a whole. The number of voltage signal lines can be reduced by half, and the vertical size can be reduced.
Now, based on the gist of the present invention as described above, the following means are specifically taken.
[0020]
According to the first aspect of the present invention, when a multilevel grayscale voltage signal is supplied, the multilevel grayscale voltage signal is generated based on the content of the grayscale select bit introduced in the column direction relatively. A liquid crystal driver device provided with a decoder unit that passes one of them in the row direction for output, wherein the decoder unit includes a plurality of levels based on the least significant bit of the gradation select bits. A plurality of least significant bit decoding units having a plurality of first transistors arranged in the same row so that any one of the regulated voltage signals passes through the same row, and the least significant bit decoding unit of each row. , A plurality of gray-scale selection bits arranged in the same row that pass the gray-scale voltage signal that has passed through the corresponding first transistor, based on the upper bits excluding the least significant bit of the gray-scale selection bits. A liquid crystal driver device including an upper bit decode unit of the plurality of rows having a second transistor.
[0021]
According to a second aspect of the present invention, in the liquid crystal driver device according to the first aspect, the number of rows of the upper bit decoding unit is half of the number of levels of the gradation voltage signal.
[0022]
Furthermore, the invention corresponding to claim 3 is the liquid crystal display device using the liquid crystal driver device corresponding to claim 1 or claim 2, and the image is obtained based on the gradation voltage signal output from the liquid crystal driver device. It is a liquid crystal display device provided with a liquid crystal panel portion for gradation display.
[0023]
(Function)
Therefore, according to the invention corresponding to claim 1, by taking the above-described means, the decoder unit of the liquid crystal driver device can generate a plurality of gradation voltage signals based on the least significant bit of the gradation select bits. A plurality of least significant bit decoding units having a plurality of first transistors arranged in the same row so as to pass any one through the same row, and a gradation select bit provided for each least significant bit decoding unit of each row A plurality of upper bit decoding units having a plurality of second transistors arranged in the same row that allow the gradation voltage signal that has passed through the corresponding first transistor to pass based on the upper bits excluding the least significant bit It is the composition provided with.
[0024]
As described above, since the gradation voltage signal lines are shared and any one of the plurality of gradation voltage signals is passed through the same row, a large number are arranged in the vertical direction in proportion to the number of gradations in the decoder unit. The grayscale voltage signal lines and transistors can be reduced, and the vertical size can be reduced.
[0025]
In the invention corresponding to claim 2, since the number of rows of the upper bit decoding section is half of the number of levels of the gradation voltage signal, the operation corresponding to claim 1 can be easily and reliably performed.
[0026]
Furthermore, in the invention corresponding to claim 3, the liquid crystal panel unit of the liquid crystal display device displays an image in gradation based on the gradation voltage signal output from the liquid crystal driver device. A liquid crystal display device having an action corresponding to the above can be realized.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram showing a configuration of a decoder unit for one pixel column applied to an LCD driver according to an embodiment of the present invention. Is omitted.
[0028]
That is, this embodiment has a configuration in which redundant grayscale voltage signal lines and transistors are shared in the decoder unit in the LCD driver from the viewpoint of reducing the size in the vertical direction.
[0029]
Specifically, the decoder unit 20 branches and extracts the gradation select bits A to C input from the display controller 11 (not shown) and inputs the inverted bits / A to / C, and a floor (not shown). The plurality of grayscale voltage signals V1 to V8 supplied from the voltage regulator and the least significant bits C and / C of the above-described bits A to C and / A to / C are input to the lowest row of the plurality of rows. Any one of the lower-level bit decoding unit 22 and each gradation voltage signal that has passed through the lowest-order bit decoding unit 22 in each row is converted into the higher-order bits A to B and / A to / B other than the least significant bits C and / C described above. And a plurality of rows of upper bit decoding units 23 for outputting to the pixel columns of the liquid crystal panel unit 13.
[0030]
Here, the least significant bit decoding unit 22 of each row is based on the least significant bit C of the gradation select bits A to C from the display controller 11 and its inverted bit / C. Are provided with a plurality of first transistors TrC and Tr / C arranged in the same row so as to constitute a circuit for passing any one of the grayscale voltage signals in the same row and inputting the same to the upper bit decoding unit 23. ing.
[0031]
Specifically, for example, the first transistors TrC and Tr / C are individually provided for all the gradation voltage signals V1 to V8, and are arranged side by side in the same row so that the drains are on the outside and the sources are on the inside. The gradation voltage signals V1 to V8 are individually applied to the drains outside the transistors TrC and Tr / C, and the connection point between the sources inside the transistors TrC and Tr / C is electrically connected to the upper bit decoding unit. 23. Needless to say, the gate of the first transistor TrC is connected to the input wiring of the least significant bit C, and the gate of the first transistor Tr / C is connected to the input wiring of the lowest inverted bit / C.
[0032]
On the other hand, the upper bit decoding unit 23 of each of the plurality of rows is based on the upper bits A and B excluding the least significant bit C of the gradation select bits A to C from the display controller 11 and its inverted bits / A and / B. In this manner, circuits that pass the gradation voltage signal Vi input from the first transistor TrC (or Tr / C) selected by the least significant bit C and output the same to the liquid crystal panel unit 13 are configured to mutually. A plurality of second transistors TrA, Tr / A, TrB, Tr / B are arranged in the same row.
[0033]
The second transistors TrA, Tr / A, TrB, Tr / B are individually provided for each of the two gradation voltage signals V1 to V2, V3 to V4, V5 to V6, and V7 to V8. In the truth table of the present invention in which the overlapping portions of the upper bits A, / A, B, / B are made common as shown in FIG. 1, each bit A, / A, B, / B is placed at the position of “1”. Has been placed. Note that the total number of all the second transistors TrA, Tr / A, TrB, Tr / B is the same as the number of levels of the grayscale voltage signal due to the common use. The second transistors TrA, Tr / A, TrB, Tr / B are connected to the input wirings of the upper bits A, / A, B, / B corresponding to the respective gates, and the drains / sources are arranged in the same manner as described above. Needless to say, it is connected to the regulated voltage signal line.
[0034]
In addition, the liquid crystal display device 10 includes a liquid crystal panel unit 13 that performs gradation display of an image on the basis of a gradation voltage signal output from the LCD driver 12 having the decoder unit 20 having a reduced size in the vertical direction. It becomes the composition.
[0035]
With the above configuration, when multi-level grayscale voltage signals V1 to V8 are supplied, multilevel grayscale voltage signals are based on grayscale select bits A to C that are relatively input in the column direction. When passing one of V1 to V8 in the row direction for output, two adjacent gradation voltage signal lines and their selection transistors can be shared, so the vertical size of the decoder portion in the LCD driver can be reduced. It can be reduced to nearly half.
[0036]
Specifically, in the case of ²ⁿ gradations, the conventional configuration requires ²ⁿ gradation voltage signal lines, whereas in the present invention, there are ^2n-1 gradation voltage signal lines. For example, in the case of 8 gradations, as shown in FIG. 2A, conventionally, 8 gradation voltage signal lines are required. However, as shown in FIG. The number is halved to 4. In the case of 64 gradations, 64 gradation voltage signal lines are conventionally required, but in the present invention, the number of gradation voltage signal lines is halved to 32. Further, in the case of 256 gradations, the number of gradation voltage signal lines is conventionally 256, but in the present invention, the number of gradation voltage signal lines is halved to 128.
[0037]
According to a specific prototype, the vertical size of the decoder unit of 256 gradations was 1.1 mm in the past, but it was 0.64 mm in the present invention, which could be reduced by 0.46 mm. With this reduction, the area occupied by the LCD driver could be reduced by about 40% compared to the conventional case. Note that the size of the 256-level LCD driver at this time was 2.2 mm in length and 17.4 mm in width, and the number of output pins was 384.
[0038]
Note that even if the number of gradation voltage signal lines on the output side is reduced by half using the present invention, the overall vertical size is not reduced to half. This is because the number of signal lines is necessary, and the number of input lines cannot be reduced. For the same reason, there is a limit to the reduction in the vertical size even if a modification in which the upper digits of the upper bits are further shared is provided. In other words, the above-described operational effect relating to the reduction in the vertical size can be realized most efficiently, easily and reliably when the number of rows of the upper bit decoder section is half the number of levels of the gradation voltage signal. However, in the modified example in which the upper digit side of the upper bits is further shared, there is a limit in reducing the vertical size, but compared with the conventional configuration, the vertical size is reduced by the same method. Of course, it is included in the scope of the present invention.
[0039]
In addition, since the present invention is easy to understand and implement, it can be applied without increasing the labor cost of the designer, and the area occupied by the decoder can be actually reduced, greatly increasing the cost of the LCD driver (LSI). Can be lowered.
[0040]
Further, with such a reduction in the vertical size of the decoder unit, the liquid crystal display device 10 can increase the display area by increasing the area of the liquid crystal panel unit 13 occupying the area of the liquid crystal display device 10, or the liquid crystal display The area of the device 20 itself can be reduced, and the portability can be improved.
[0041]
(Other embodiments)
1 and 2 are equivalent circuit diagrams schematically showing gaps for easy explanation of the present invention, and do not show actual mounting patterns. That is, the actual mounting pattern is equivalent in circuit to the circuit shown in FIG. 1, but without creating a gap as shown by the intersection (+) in FIG. 1 and the white circle (◯) in FIG. It can be formed by various integration.
[0042]
For example, if the equivalent circuit is the same, the present invention also includes a modified configuration in which MOS transistors TrA to TrC and Tr / A to Tr / C are further closely arranged between the common gradation voltage signal lines. Needless to say, it is included.
[0043]
Further, the present invention has been described by taking the case of n = 3 (3-bit input, 8-gradation output) as an example in the case of n-bit input, ^2n- gradation output, but not limited to n = 3, A configuration applied to an arbitrary n is also included and can be implemented in the same manner to obtain the same effect.
[0044]
In addition, the present invention can be implemented with various modifications without departing from the gist thereof.
[0045]
【The invention's effect】
As described above, according to the present invention, the liquid crystal driver device capable of reducing the size in the vertical direction by reducing the number of grayscale voltage signal lines and transistors arranged in the vertical direction in proportion to the number of gray levels in the decoder unit, and A liquid crystal display device can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating a configuration of a decoder unit for one pixel column applied to an LCD driver according to an embodiment of the present invention. FIG. 2 is a schematic diagram for explaining an effect of the embodiment. FIG. 4 is a schematic diagram for explaining the essence of the present invention from a logical point of view. FIG. 4 is a schematic diagram for explaining the essence of the present invention from the viewpoint of mounting layout. FIG. Schematic diagram showing FIG. 6 Schematic diagram showing the configuration of one pixel column of a conventional decoder unit.
DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device 11 ... Display controller 12, 14 ... LCD driver 13 ... Liquid crystal panel part 20 ... Decoder part 21 ... Inverter part 22 ... Least significant bit decoding part 23 ... High order bit decoding part V1-V8 ... Gradation voltage signal A ~ C ... Input bit
/ A to C /... Inverted bits TrA to TrC, Tr / A to TrC /.

Claims (3)

When a multilevel grayscale voltage signal is supplied, one of the multilevel grayscale voltage signals is relatively moved in the row direction based on the content of the grayscale select bit introduced in the column direction. A liquid crystal driver device including a decoder unit for passing and outputting,
The decoder unit
Based on the least significant bit of the grayscale select bits, the plurality of rows having the plurality of first transistors arranged in the same row so that any one of the plurality of grayscale voltage signals passes through the same row. A lower bit decoding unit;
Provided for each least significant bit decoding unit of each row, and based on the upper bits excluding the least significant bit of the gradation select bits, the same row mutually passing the gradation voltage signal that has passed through the corresponding first transistor A liquid crystal driver device comprising: a plurality of rows of upper bit decoding units each having a plurality of second transistors arranged on the liquid crystal driver device. The liquid crystal driver device according to claim 1,
The liquid crystal driver device according to claim 1, wherein the number of rows of the upper bit decoding unit is half of the number of levels of the gradation voltage signal. In the liquid crystal display device using the liquid crystal driver device according to claim 1 or 2,
A liquid crystal display device, comprising: a liquid crystal panel unit that displays an image in gradation based on a gradation voltage signal output from the liquid crystal driver device.

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