JP3736455B2 - Solid-state image pickup device and image pickup apparatus including the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device in which photoelectric conversion elements are two-dimensionally arranged, and more particularly, to a solid-state imaging device capable of capturing still images and moving images and having high pixels, and an imaging apparatus including the same. .
[0002]
[Prior art]
In recent years, in an imaging apparatus such as a digital still camera or a video camera using a solid-state imaging device in which photoelectric conversion elements such as photodiodes are two-dimensionally arranged, those capable of shooting a moving image and a still image are widely used. The solid-state imaging device used in such an imaging apparatus includes a CCD (Charge Coupled Device) sensor that transfers charges obtained by imaging with a photoelectric conversion element pixel by pixel using a potential barrier, and imaging with a photoelectric conversion element. There is a C-MOS sensor that outputs the electric charge obtained by using a MOS transistor for each pixel.
[0003]
As described above, in an imaging apparatus capable of capturing a moving image and a still image, when capturing a still image, it is required to capture a high-quality image. It becomes. On the other hand, when shooting a moving image, a solid-state image sensor is required because shooting in accordance with analog TV signal standards such as NTSC (National Television System Committee) and PAL (Phase Alternation Line) is required. A method has been proposed in which the frequency for reading from the image is increased, the output from the plurality of pixels is added and read out, or the output from the plurality of pixels is thinned out and read out.
[0004]
As a solid-state imaging device using a CCD sensor, an imaging device disclosed in Japanese Patent Laid-Open No. 2000-308075, an imaging device disclosed in Japanese Patent Laid-Open No. 2001-197371, and the like have been proposed. In Japanese Patent Application Laid-Open No. 2000-308075, a vertical stripe color filter is used, and outputs from a plurality of pixels adjacent in the vertical direction are mixed, or one pixel among a plurality of pixels adjacent in the vertical direction By reading out only the output from the pixel and thinning out the outputs of a plurality of pixels, a high-resolution solid-state imaging device can be used to capture a moving image. Further, in Japanese Patent Laid-Open No. 2001-19731, output from pixels that are not required when taking a moving image is performed in a vertical blanking period, and outputs from a plurality of pixels vertically adjacent to the horizontal blanking period are mixed. By moving to the next line as an output for one line, a moving image can be shot with a high-resolution solid-state image sensor.
[0005]
In contrast to such a solid-state imaging device using a CCD sensor, a solid-state imaging device using a C-MOS sensor can be configured on the same semiconductor chip as other electronic circuit components, and is thus inexpensive. be able to. As an apparatus using a C-MOS sensor as the solid-state image pickup device, an image pickup apparatus disclosed in Japanese Patent Laid-Open No. 2001-36920 has been proposed. In Japanese Patent Laid-Open No. 2001-36920, the output from a plurality of adjacent pixels is added and read, so that moving image shooting can be performed with a high-resolution solid-state imaging device.
[0006]
[Problems to be solved by the invention]
As described above, a high-resolution still image can be captured and a high-quality moving image can be captured. However, the imaging device disclosed in Japanese Patent Application Laid-Open No. 2000-308075 and Japanese Patent Application Laid-Open No. 2001-197371. In the image pickup apparatus disclosed in Japanese Laid-Open Patent Publication No. HEI, it is necessary to operate the CCD sensor at high speed in order to transfer charges in the vertical direction. Therefore, the power consumption increases. In particular, in Japanese Patent Application Laid-Open No. 2001-197371, since the output of the pixels in the extra area at the time of moving image shooting is performed, it is necessary to output from all the pixels provided in the solid-state image pickup device. High speed driving of the sensor is required.
[0007]
On the other hand, in the imaging apparatus disclosed in Japanese Patent Application Laid-Open No. 2001-36920, since it is not necessary to set the frequency of a signal supplied for reading the output from the pixel to a high frequency, the power consumption can be suppressed. However, in order to add and read outputs from a plurality of adjacent pixels, it is necessary to perform an addition processing operation for outputs from the plurality of pixels, and it is necessary to provide time for the addition processing operation.
[0008]
In addition, a CCD sensor using a honeycomb arrangement is provided as a solid-state imaging device capable of capturing a high-resolution still image with a small number of pixels. In this honeycomb arrangement, a plurality of pixels are arranged in a zigzag manner so that pixels arranged in the horizontal direction in even rows adjacent in the vertical direction are arranged between pixels arranged in the horizontal direction in odd rows. . That is, pixels arranged in the vertical direction in the even columns adjacent in the horizontal direction are arranged between the pixels arranged in the vertical direction in the odd columns. At the time of moving image capturing, RGB pixels are arranged on the horizontal CCD for readout, so that signal processing in a processing circuit connected to the subsequent stage of the solid-state imaging device is facilitated. However, even in such a CCD sensor using a honeycomb arrangement, since it is a CCD sensor, when a higher resolution is required, it is necessary to perform high-speed readout when shooting a moving image, resulting in an increase in power consumption. End up.
[0009]
In view of such a problem, the present invention can capture a high-resolution still image, improve image quality and reduce power consumption during moving image shooting, and can output a random video signal. An object of the present invention is to provide a Y-scanning solid-state imaging device and an imaging apparatus provided with the same.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention Imaging device Has multiple pixels with m kinds of color filters that output electrical signals according to the amount of incident light as video signals, and outputs m kinds of color signals And N adjacent (n is m Greater than A block is formed for each pixel (natural number) And By outputting in parallel from the n pixels in each block, n video signals including m kinds of color signals are parallelly output. XY scanning solid-state imaging device for output and a control unit for performing exposure control or automatic focus adjustment, when shooting a movie In From the solid-state image sensor Of the n video signals output for each block, any one of two or more same-type color signals is A control signal given to the control unit for use in exposure control or automatic focus adjustment It is used as.
[0011]
In such a solid-state imaging device, when three types of color filters are provided and one block is configured for every four or six pixels, four or six video signals composed of three types of color signals are output for each block. In addition, at the time of moving image shooting, only three video signals that are three kinds of color signals may be output as image signals.
[0013]
In such a solid-state imaging device, when three types of color filters are provided and one block is configured for every four pixels, four video signals composed of three types of color signals are output for each block. Only three video signals that are three kinds of color signals may be output as image signals, and the remaining one video signal may be output as a control signal for use in exposure control or automatic focus adjustment. Absent. If one block is provided for every six pixels with three types of color filters, six video signals composed of three types of color signals are output for each block, and three types of color signals and Only the three video signals may be output as image signals, and at least one of the remaining three video signals may be output as a control signal for use in exposure control or automatic focus adjustment. Absent.
[0014]
like this Of imaging device For solid-state image sensor Leave The pixels may be constituted by a honeycomb arrangement in which the pixels are arranged in a zigzag manner in the horizontal direction and the vertical direction. At this time, one block may be constituted by 4 pixels in 2 rows and 4 columns, or 1 block may be constituted by 6 pixels in 2 rows and 6 columns. The pixels may be configured by a Bayer array in which the pixels are arranged in a matrix. At this time, one block may be constituted by four pixels in two rows and two columns.
[0015]
or, Of the present invention The imaging device Any of the above A solid-state imaging device and an image processing unit that performs arithmetic processing on a video signal from the solid-state imaging device, and at the time of still image shooting, the image processing unit includes n blocks for each block of the solid-state imaging device. Interpolation is performed using the video signal output to the video signal, and m types of color signals are obtained and output, and at the time of moving image shooting, m video signals output from the solid-state imaging device are interpolated for each block. It is characterized by being output as m kinds of color signals without being processed.
[0016]
or, The solid-state imaging device includes three types of color filters for the three primary colors of RGB, and the m types of color signals are three types of color signals for RGB, respectively. , Each of the three video signals output from the solid-state image sensor for each block may be output as a plane signal for the RGB3 plane. In this way, the RGB three types of color signals at the time of moving image capturing can be simulated as surface signals for the RGB3 surface of the RGB3 plate type image pickup device, and when such a video signal is reproduced, You can get a picture.
[0017]
In such an image pickup apparatus, at the time of moving image shooting, the blocks arranged in the even-numbered rows and the blocks arranged in the odd-numbered rows may be alternately picked up for each field. Absent. Furthermore, at this time, the imaging operation may be performed by skipping predetermined blocks in both the vertical direction and the horizontal direction. In this way, in the solid-state imaging device, when each pixel is arranged in a honeycomb arrangement, the color signal from each block is not changed over at the time of moving image shooting, and serially time-sequentially for each color signal. Can be output.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
<First Embodiment>
A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the internal configuration of the solid-state imaging device in the present embodiment.
[0019]
As shown in FIG. 1, the solid-state imaging device includes a horizontal scanning circuit 1 that provides a signal for each column, a vertical scanning circuit 2 that provides a signal for each row, a sensor unit 3 including a plurality of pixels, and a sensor. A / D converters 4a to 4d for converting the video signal output from the unit 3 into a digital signal.
[0020]
In this solid-state imaging device, each pixel in the sensor unit 3 is arranged as shown in FIG. That is, the pixels arranged in the even rows between the pixels arranged in the odd rows, or the pixels arranged in the odd rows between the pixels arranged in the even rows, respectively, The pixel array is a honeycomb array. Therefore, the pixels arranged in the even columns between the pixels arranged in the odd columns, or the pixels arranged in the odd columns between the pixels arranged in the even columns are respectively positioned. Pixels will be arranged.
[0021]
At this time, four pixels existing in 2 rows and 4 columns are set as one block, and each column is assigned a column number as 1a to 1d, 2a to 2d, 3a to 3d, ..., ma to md every four columns. In addition, each row is assigned a row number as 1x, 1y, 2x, 2y, 3x, 3y, ..., nx, ny every two rows. Each block pixel is provided with three types of color filters, R (Red), G (Green), and B (Blue), and each block is provided with one R, B color filter. 2 pixels each having a G color filter are provided. In FIG. 2, B11 to Blmn represent blocks.
[0022]
Further, as shown in FIG. 2, the color filters of the respective pixels arranged in the sensor unit 3 are arranged in the order of R, B, R, B,... From the upper side in the ia column (1 ≦ i ≦ m). Are arranged in the order of B, R, B, R,... From the upper side, and only G is arranged in the ib column and id column. Therefore, in the jx row (j is an odd number of 1 ≦ j ≦ n), in the order of R, B, R, B,... From the left side, in the kx row (k is an even number of 1 ≦ k ≦ n), from the left side. Are arranged in the order of B, R, B, R,..., And only G is arranged in the jy row and the ky row. Further, the block Bil (1 ≦ l ≦ n) is composed of four pixels, Ril provided with an R color filter, Bil provided with a B color filter, and Gail and Gbil provided with a G color filter. The
[0023]
The wiring relationship for each pixel arranged as shown in FIG. 2 is represented by four blocks Blij, Bli (j + 1), B1 (i + 1) j, B1 (i + 1) (j + 1). I will explain. As shown in FIG. 3, the signals φVj and φV (j + 1) are supplied from the vertical scanning circuit 2 to the vertical selection lines 31j and 31 (j + 1), respectively, and the vertical reset lines 32j and 32 (j + 1) Signals φRj and φR (j + 1) are given to each. From the horizontal scanning circuit 1, a signal φHi is applied to the gates of the MOS transistors Tia to Tid, and a signal φH (i + 1) is applied to the gates of the MOS transistors T (i + 1) a to T (i + 1) d. Given. The MOS transistors Tia to Tid and T (i + 1) a to T (i + 1) d are N-channel MOS transistors, respectively.
[0024]
The pixels Rij, Gaij, Bij, Gbij, R (i + 1) j, Ga (i + 1) j, B (i + 1) j, Gb (i + 1) are added to the vertical selection line 31j and the vertical reset line 32j. ) j is added to the vertical selection line 31 (j + 1) and the vertical reset line 32 (j + 1) by the pixels Bi (j + 1), Gai (j + 1), Ri (j + 1), Gbi (j + 1), B (i + 1) (j + 1), Ga (i + 1) (j + 1), R (i + 1) (j + 1), Gb (i + 1) (j + 1) Are connected to each other.
[0025]
The pixels Rij and Bi (j + 1) are connected to the horizontal signal line 33ia connected to the drain of the MOS transistor Tia, and the pixels Gaij and Gai (j + 1) are connected to the horizontal signal line 33ib connected to the drain of the MOS transistor Tib. However, the pixels Bij, Ri (j + 1) are connected to the horizontal signal line 33ic connected to the drain of the MOS transistor Tic, and the pixels Gbij, Gbi (j + 1) are connected to the horizontal signal line 33id connected to the drain of the MOS transistor Tid. Are connected to each other.
[0026]
Also, pixels R (i + 1) j and B (i + 1) (j + 1) are connected to the horizontal signal line 33 (i + 1) a connected to the drain of the MOS transistor T (i + 1) a. The pixels Ga (i + 1) j and Ga (i + 1) (j + 1) are connected to the horizontal signal line 33 (i + 1) b connected to the drain of the MOS transistor T (i + 1) b. Pixels B (i + 1) j and R (i + 1) (j + 1) are connected to the MOS transistor T (i) on the horizontal signal line 33 (i + 1) c connected to the drain of T (i + 1) c. Pixels Gb (i + 1) j and Gb (i + 1) (j + 1) are connected to the horizontal signal line 33 (i + 1) d connected to the drain of i + 1) d.
[0027]
Further, the sources of the MOS transistors Tia, T (i + 1) a are on the output signal line 34a, the sources of the MOS transistors Tib, T (i + 1) b are on the output signal line 34b, and the MOS transistors Tic, T (i +). 1) The source of c is connected to the output signal line 34c, and the sources of the MOS transistors Tid, T (i + 1) d are connected to the output signal line 34d. The output signal lines 34a to 34d are connected to the A / D converters 4a to 4d, respectively.
[0028]
Each pixel configured in the sensor unit 3 includes, for example, a MOS transistor and a photodiode as shown in FIG. 4 includes a photodiode PD having an anode grounded, a MOS transistor T1 having a gate connected to the cathode of the photodiode PD, a MOS transistor T2 having a drain connected to the source of the MOS transistor T1, and a photodiode. A MOS transistor T3 having a source connected to a connection node between the cathode of the PD and the gate of the MOS transistor T1 is provided. The MOS transistors T1 to T3 are N-channel MOS transistors.
[0029]
The DC voltage VDD is applied to the drain of the MOS transistor T1. Further, the source of the MOS transistor T2 is connected to a horizontal signal line 33 (corresponding to 33ia to 33id, 33 (i + 1) a to 33 (i + 1) d in FIG. 3) and perpendicular to the gate of the MOS transistor T2. A selection line 31 (corresponding to 31j and 31 (j + 1) in FIG. 3) is connected. A DC voltage VDD is applied to the drain of the MOS transistor T3, and a vertical reset line 32 (corresponding to 32j and 32 (j + 1) in FIG. 3) is connected to the gate of the MOS transistor T3. Furthermore, the drain of a MOS transistor T (corresponding to Tia to Tid, T (i + 1) a to T (i + 1) d in FIG. 3) is connected to the horizontal signal line 33, and an output signal is connected to the source thereof. A line 34 (corresponding to 34a to 34d in FIG. 3) is connected.
[0030]
Therefore, the signal φV (corresponding to φVj, φ (j + 1) in FIG. 3) is applied to the gate of the MOS transistor T2, and the signal φR (corresponding to φRj, φR (j + 1) in FIG. 3) is applied to the gate of the MOS transistor T3. Are provided from the vertical scanning circuit 2 respectively. Further, a signal φH (corresponding to φHi and φH (i + 1) in FIG. 3) is applied from the horizontal scanning circuit 1 to the gate of the MOS transistor T.
[0031]
When each pixel is configured in this way, first, the signal φR is supplied to the vertical reset line 32 to turn on the MOS transistor T3, thereby resetting the connection node between the gate of the MOS transistor T1 and the cathode of the photodiode PD. To do. Thereafter, when the MOS transistor T3 is turned off, photocharge corresponding to the amount of light incident on the photodiode PD is accumulated at the gate of the MOS transistor T1.
[0032]
Then, the signal φV is applied to the vertical selection line 31 to turn on the MOS transistor T2, and the signal φH is applied to the gate of the MOS transistor T to turn on the MOS transistor T, so that the signal is accumulated at the gate of the MOS transistor T1. An output current obtained by amplifying the amount of the photocharge is output as a video signal to the output signal line 34 via the MOS transistor T2 and the horizontal signal line 33.
[0033]
An example of the operation of the solid-state imaging device configured as described above during moving image shooting and still image shooting will be described below. It should be noted that an operation corresponding to the interlace scanning is performed at the time of moving image shooting.
[0034]
1. First operation example during movie shooting
A first operation example during moving image shooting will be described with reference to the drawings. FIG. 5 shows the timing of the signals φV1 to φVn, φR1 to φRn (n is an even number). FIG. 6 shows the timing of the signals φH1 to φHm when the signal φVl is given as a representative.
[0035]
First, in order to perform the imaging operation of the first field, the signal φR1 is given, and the pixels R11 to Rm1, Ga11 to Gm1, B11 to Bm1, and Gb11 to Gbm1 of the blocks B11 to Blm1 are reset. Next, the signal φR3 is applied, and the pixels R13 to Rm3, Ga13 to Gm3, B13 to Bm3, and Gb13 to Gbm3 of the blocks B13 to Blm3 are reset. Similarly, signals .phi.R5, .phi.R7,..., .Phi.R (n-1) are sequentially applied to the respective pixels of the blocks Bl15 to Blm5, Bl17 to Blm7,..., Bl1 (n-1) to Blm (n-1). Are reset in sequence every two rows.
[0036]
In this way, when each pixel of the blocks B11 to Blm1, B13 to Blm3,..., B11 (n-1) to Blm (n-1) is reset, the signal φV1 is given. That is, when the signal φR1 is given and a predetermined exposure period t has passed, the signal φV1 is given to the pixels R11 to Rm1, Ga11 to Gm1, B11 to Bm1, and Gb11 to Gbm1 of the blocks B11 to Blm1. At this time, as shown in FIG. 6, first, the signal φH1 is given, and the video signals of the pixels R11, Ga11, B11, Gb11 of the block Bl11 are respectively output via the output signal lines 34a, 34b, 34c, 34d. The data is output to the A / D converters 4a, 4b, 4c, 4d.
[0037]
Thereafter, as shown in FIG. 6, signals .phi.H2, .phi.H3,..., .Phi.Hm are sequentially given, and the video signals of the pixels of the blocks Bl21, Bl31,. That is, the video signals of the pixels R21, R31,..., Rm1 are sequentially output to the A / D converter 4a via the output signal line 34a, and the video signals of the pixels Ga21, Ga31,. , Bm1 are sequentially output to the A / D converter 4c via the output signal line 34c, and the pixels Gb21, Gb31,..., Gbm1 are output to the A / D converter 4b. Are sequentially output to the A / D converter 4d via the output signal line 34d.
[0038]
As described above, when the video signals from the pixels of the blocks Bl11 to Blm1 arranged in the 1x and 1y rows are output, next, the signal φV3 and the signals φH1, φH2,. Thus, the video signals of the pixels of the blocks Bl13, Bl23,..., Blm3 are sequentially output. That is, as described above, when the signal φR3 is given and a predetermined exposure period t elapses, the pixels R13 to Rm3, Ga13 to Gm3, B13 to Bm3 of the blocks Bl13 to Blm3 arranged in the 3x and 3y rows, A signal φV3 is applied to Gb13 to Gbm3.
[0039]
Therefore, the video signals of the pixels R13, R23,..., Rm3 are sequentially output to the A / D converter 4a via the output signal line 34a, and the video signals of the pixels Ga13, Ga23,. , Bm3 are sequentially output to the A / D converter 4c via the output signal line 34c, and the pixels Gb13, Gb23,..., Gbm3 are output to the A / D converter 4b. Are sequentially output to the A / D converter 4d via the output signal line 34d.
[0040]
Thereafter, similarly, signals φV5, φV7,..., ΦV (n−1) are sequentially applied, and signals φH1 to φHm are sequentially applied while signals φV5 to φV (n−1) are being applied. .., (N−1) x, (n−1) y, blocks Bl15 to Blm5, Bl17 to Blm7,..., Bl1 ( Video signals are output from the pixels n-1) to Blm (n-1).
[0041]
Therefore, the video signals of the pixels R15 to Rm5, R17 to Rm7,..., R1 (n-1) to Rm (n-1) are sequentially output to the A / D conversion unit 4a via the output signal line 34a, and the pixel Ga15 To Gam5, Ga17 to Gam7,..., Ga1 (n-1) to Gam (n-1) are sequentially output to the A / D converter 4b via the output signal line 34b, and the pixels B15 to Bm5, B17 are output. To Bm7,..., B1 (n-1) to Bm (n-1) are sequentially output to the A / D converter 4c via the output signal line 34c, and the pixels Gb15 to Gbm5, Gb17 to Gbm7,. , Gb1 (n-1) to Gbm (n-1) are sequentially output to the A / D converter 4d via the output signal line 34d.
[0042]
Thus, when the imaging operation of the first field is performed, the imaging operation of the second field is performed as follows. When a signal φV1 is given and a video signal is outputted from each pixel of the blocks B11 to Blm1, a signal φR2 is given and each pixel B12 to Bm2, Ga12 to Gam2, R12 to Rm2, Gb12 to G11 of the blocks B12 to Blm2. Gbm2 is reset. Thereafter, signals .phi.R4, .phi.R6,..., .Phi.Rn are sequentially applied, and the pixels of the blocks Bl14 to Blm4, Bl16 to Blm6,..., Bl1n to Blmn are sequentially reset every two rows. That is, the signals φR4, φR6,..., ΦRn are applied after the signals φV3, φV5,.
[0043]
In this way, when the pixels of the blocks B12 to Blm2, B14 to Blm4,..., B11n to Blmn are reset, the signal φV2 is given. That is, when the signal φR2 is given and a predetermined exposure period t has elapsed, the signal φV2 is given to each pixel of the blocks B12 to Blm2. Then, as shown in FIG. 6, signals .phi.H1, .phi.H2,..., .Phi.Hm are sequentially given, and the video signals of the pixels of the blocks Bl12, Bl22,. .
[0044]
Therefore, the video signals of the pixels B12, B22,..., Bm2 are sequentially output to the A / D converter 4a via the output signal line 34a, and the video signals of the pixels Ga12, Ga22,. , Rm2 are sequentially output to the A / D converter 4c via the output signal line 34c, and the pixels Gb12, Gb22,..., Gbm2 are output to the A / D converter 4b. Are sequentially output to the A / D converter 4d via the output signal line 34d.
[0045]
Thereafter, similarly, the signals φV4, φV6,..., ΦVn are sequentially given, and while the signals φV4 to φVn are given, the signals φH1 to φHm are given in order, so that the 4x, 4th row, 6x , 6x,..., Nx, ny, video signals are output from the respective pixels of the blocks Bl14 to Blm4, Bl16 to Blm6,..., Bl1n to Blmn.
[0046]
Therefore, the video signals of the pixels B14 to Bm4, B16 to Bm6,..., B1n to Bmn are sequentially output to the A / D converter 4a via the output signal line 34a, and the pixels Ga14 to Gam4, Ga16 to Gam6,. To Gamn video signals are sequentially output to the A / D converter 4b via the output signal line 34b, and video signals of the pixels R14 to Rm4, R16 to Rm6,..., R1n to Rmn are sequentially output via the output signal line 34c. The video signals of the pixels Gb14 to Gbm4, Gb16 to Gbm6,..., Gb1n to Gbmn are sequentially output to the A / D conversion unit 4d via the output signal line 34d.
[0047]
As described above, when the imaging operation of the second field is performed, the signals φR1, φR3,..., ΦR (n−1) are given after the signals φV2, φV4,. Then, as described above, when each signal is repeatedly given, the imaging operations of the first and second fields are repeated, and moving image shooting is performed.
[0048]
Therefore, when the video signal of the first field is output, in the blocks Bl11 to Blm1, Bl13 to Blm3,..., Bl1 (n-1) to Blm (n-1), pixels from the R filter are provided. The output from the A / D converter 4a, the output from the pixel provided with the G filter (Ga) to the A / D converter 4b, and the output from the pixel provided with the B filter to the A / D converter 4c The outputs from the pixels provided with the G filter (Gb) are output in parallel to the A / D converter 4d.
[0049]
When the video signal of the second field is output, the output from the pixel provided with the B filter in the blocks Bl12 to Blm2, Bl14 to Blm4,..., Bl1n to Blmn is sent to the A / D converter 4a. The output from the pixel provided with the G filter (Ga) is provided to the A / D converter 4b, the output from the pixel provided with the R filter is provided to the A / D converter 4c, and the G filter (Gb) is provided. Outputs from the pixels are respectively output in parallel to the A / D converter 4d.
[0050]
2. Second operation example during movie shooting
A second operation example during moving image shooting will be described with reference to the drawings. FIG. 7 shows the timing of the signals φV1 to φVn, φR1 to φRn (n is an even number). Similarly to the first operation example, the timings of the signals φH1 to φHm are as shown in FIG.
[0051]
First, as in the first operation example, since the imaging operation of the first field is performed, the signals φR1, φR3,..., ΦR (n−1) are sequentially given, and the blocks Bl11 to Blm1, Bl13 to Blm3. ,..., Bl1 (n-1) to Blm (n-1) are sequentially reset. Then, signals φR1, φR3,..., ΦR (n-1) are given, and when a predetermined exposure period t elapses, signals φV1, φV3,.
[0052]
.., .Phi.V (n-1) is applied to each of the signals .phi.H1, .phi.H2,..., .Phi.Hm in turn, and the blocks Bl11 to Blm1, Bl13 to Blm3,. -1) to Blm (n-1), video signals are output in order. Therefore, the video signals of the pixels R11 to Rm1, R13 to Rm3,..., R1 (n-1) to Rm (n-1) are sequentially output to the A / D converter 4a, and the pixels Ga11 to Gam1, Ga13 to Gam3, ..., Ga1 (n-1) to Gam (n-1) video signals are sequentially output to the A / D converter 4b, and pixels B11 to Bm1, B13 to Bm3, ..., B1 (n-1) to Bm ( n-1) are sequentially output to the A / D converter 4c, and the video signals of the pixels Gb11 to Gbm1, Gb13 to Gbm3,..., Gb1 (n-1) to Gbm (n-1) are sequentially converted to A / D. It is output to the D converter 4d.
[0053]
As described above, when the imaging operation of the first field is performed, when the signals φR1, φR3,..., ΦR (n−1) are respectively given and a predetermined period ta (ta <t) elapses, the signals φR2, φR4,..., φRn are given in order. Then, signals φR2, φR4,..., ΦRn are provided, and when a predetermined exposure period t elapses, signals φV2, φV4,. In this way, each time the signals φV2, φV4,..., ΦVn are given, the signals φH1, φH2,... ΦHm are given in order, and the pixels from the blocks Bl12 to Blm2, Bl14 to Blm4,. A video signal is output.
[0054]
Therefore, the video signals of the pixels B12 to Bm2, B14 to Bm4,..., B1n to Bmn are sequentially output to the A / D converter 4a, and the video signals of the pixels Ga12 to Gam2, Ga14 to Gam4,. The video signals of the pixels R12 to Rm2, R14 to Rm4,..., R1n to Rmn are output in order to the A / D converter 4c, and the pixels Gb12 to Gbm2, Gb14 to Gbm4,. Video signals Gb1n to Gbmn are sequentially output to the A / D converter 4d.
[0055]
Therefore, as shown in FIG. 7, after signals φR1, φR3,..., ΦR (n−1) are sequentially applied, signals φR2, φR4,. Further, after signals φV1, φV3,..., ΦV (n−1) are sequentially applied, signals φV2, φV4,. In this example, when the imaging operations of the first and second fields are performed, the signal φV2 is given immediately after the signal φV (n−1) is given, and the signal φVn is given immediately after the signal φVn is given. φV1 is given.
[0056]
By providing a signal at the timing as in this operation example, unlike the first operation example, the exposure time t from when each pixel is reset to when the video signal is read can be changed. Therefore, the exposure time can be changed according to the luminance of the subject, and a video signal with sufficient output can be obtained even at low luminance.
[0057]
3. Third operation example during movie shooting
A third operation example during moving image shooting will be described with reference to the drawings. FIG. 8 shows the timing of the signals φV1 to φVn, φR1 to φRn. FIG. 9 shows the timing of the signals φH1 to φHm when the signal φVj is given as a representative. Furthermore, in this operation example, unlike the first and second operation examples, only one of the four blocks is operated during moving image shooting. That is, a video signal is output from each pixel in the block Blij out of the four blocks Blij, Bli (j + 1), Bl (i + 1) j, Bl (i + 1) (j + 1). . Note that n is a multiple of 4 and m is an even number.
[0058]
First, in order to perform the imaging operation of the first field, the signal φR1 is given and each pixel of the blocks Bl11 to Blm1 is reset. Next, a signal φR5 is applied, and each pixel of the blocks Bl15 to Blm5 is reset. Similarly, signals .phi.R9, .phi.R13,..., .Phi.R (n-3) are sequentially applied to the respective pixels of the blocks Bl19-Blm9, Bl113-Blm13, ..., Bl1 (n-3) -Blm (n-3). Are reset in sequence every two rows.
[0059]
In this way, when the pixels of the blocks Bl19 to Blm9, Bl113 to Blm13,..., Bl1 (n-3) to Blm (n-3) are reset, the signal φV1 is given. At this time, similarly to the first operation example, the signal φR1 is given, and the signal φV1 is given when a predetermined exposure period t has passed. At this time, as shown in FIG. 9, first, the signal φH1 is given, and the video signals of the pixels R11, Ga11, B11, Gb11 of the block Bl11 are respectively sent to the A / D converters 4a, 4b, 4c, 4d. Is output.
[0060]
Thereafter, as shown in FIG. 9, signals φH3, φH5,... ΦH (m−1) are sequentially given, and the video signals of the pixels of the blocks Bl31, Bl51,. The That is, the video signals of the pixels R31, R51,..., R (m-1) 1 are sequentially output to the A / D converter 4a, and the video signals of the pixels Ga31, Ga51,. The video signals of the pixels B31, B51,..., B (m-1) 1 are output to the A / D conversion unit 4c in order, and the pixels Gb31, Gb51,. 1) The video signal 1 is sequentially output to the A / D converter 4d.
[0061]
In this way, when the video signal from each pixel of the blocks Bl11, Bl31,..., Bl (m−1) 1 arranged in the 1x and 1y rows is output, next, the signal φV5 is given, Signals φH1, φH3,... ΦH (m−1) are sequentially applied, and the video signals of the pixels of the blocks Bl15, Bl35,. That is, as described above, when the signal φR5 is given and a predetermined exposure period t elapses, each pixel of the blocks Bl15, Bl35,..., Bl (m−1) 5 arranged in the 5x, 5y rows is Signal φV5 is applied.
[0062]
Therefore, the video signals of the pixels R15, R25,..., R (m-1) 5 are sequentially output to the A / D converter 4a, and the video signals of the pixels Ga15, Ga25,. The video signals of the pixels B15, B25,..., B (m-1) 5 are output to the A / D converter 4c in order, and the pixels Gb15, Gb25,. 1) Video signals 5 are sequentially output to the A / D converter 4d via the output signal line 34d.
[0063]
Thereafter, similarly, the signals φV9, φV13,..., ΦV (n-3) are sequentially applied, and the signals φH1, φH3,. m-1) are given in order, so that the blocks Bl19, Bl39, 9th, 9y, 13x, 13y,..., (n-3) x, (n-3) y, ..., Bl (m-1) 9, Bl113, Bl313, ..., Bl (m-1) 13, ..., Bl1 (n-3), Bl3 (n-3), ..., Bl (m-1) (n A video signal is output from each pixel of -3).
[0064]
Therefore, the video signals of the pixels R19 to R (m-1) 9, R113 to R (m-1) 13,..., R1 (n-3) to R (m-1) (n-3) Are output to the D converter 4a, and the pixels Ga19 to Ga (m-1) 9, Ga113 to Ga (m-1) 13, ..., Ga1 (n-3) to Ga (m-1) (n-3) Video signals are sequentially output to the A / D converter 4b, and pixels B19 to B (m-1) 9, B113 to B (m-1) 13,..., B1 (n-3) to B (m-1) (n-3) video signals are sequentially output to the A / D converter 4c, and the pixels Gb19 to Gb (m-1) 9, Gb113 to Gb (m-1) 13,..., Gb1 (n-3) to Gb (m−1) (n−3) video signals are sequentially output to the A / D converter 4d.
[0065]
Thus, when the imaging operation of the first field is performed, the imaging operation of the second field is performed as follows. When the video signal is output from each pixel of the blocks Bl11 to Bl (m-1) 1 given the signal φV1, the signal φR3 is given and each pixel of the blocks Bl13 to Bl (m-1) 3 is reset. Is done. Thereafter, signals .phi.R7, .phi.R11,..., .Phi.R (n-1) are sequentially applied, and each pixel of the blocks Bl17-Blm7, Bl111-Blm11, ..., Bl1 (n-1) -Blm (n-1) is 2 in number. Reset line by line. That is, the signals φR7, φR11,..., ΦR (n−1) are given after the signals φV5, φV9,.
[0066]
In this way, when the pixels of the blocks B13 to Blm3, B17 to Blm7,..., B11 (n-1) to Blm (n-1) are reset, the signal [phi] V3 is given. That is, when the signal φR3 is given and the predetermined exposure period t has passed, the signal φV3 is given. Then, as shown in FIG. 9, signals .phi.H1, .phi.H3,..., .Phi.H (m-1) are given in order, and blocks Bl13, Bl33,..., Bl (m-1) 3 arranged in the 3x and 3y rows. The video signal of each pixel is sequentially output.
[0067]
Therefore, the video signals of the pixels R13, R33,..., R (m-1) 3 are sequentially output to the A / D converter 4a, and the video signals of the pixels Ga13, Ga33,. The video signals of the pixels B13, B33,..., B (m−1) 3 are output to the A / D converter 4c in order, and the pixels Gb13, Gb33,. 1) The video signal 3 is sequentially output to the A / D converter 4d.
[0068]
Thereafter, similarly, the signals φV7, φV11,..., ΦV (n−1) are sequentially applied, and the signals φH1, φH3,. m-1) is given in order. In this way, the blocks Bl17, Bl37,..., Bl () arranged in the 7x, 7y row, 11x, 11y row,..., (N-1) x, (n-1) y row. m-1) 7, Bl111, Bl311, ..., Bl (m-1) 11, ..., Bl1 (n-1), Bl3 (n-1), ..., Bl (m-1) (n-1) A video signal is output from each pixel.
[0069]
Accordingly, the video signals of the pixels R17 to R (m-1) 7, R111 to R (m-1) 11,..., R1 (n-1) to R (m-1) (n-1) Are output to the D conversion unit 4a, and pixels Ga17 to Ga (m-1) 7, Ga111 to Ga (m-1) 11, ..., Ga1 (n-1) to Ga (m-1) (n-1) Video signals are sequentially output to the A / D converter 4b, and pixels B17 to B (m-1) 7, B111 to B (m-1) 11,..., B1 (n-1) to B (m-1) (n-1) video signals are sequentially output to the A / D converter 4c, and pixels Gb17 to Gb (m-1) 7, Gb111 to Gb (m-1) 11,..., Gb1 (n-1) to Video signals of Gb (m−1) (n−1) are sequentially output to the A / D conversion unit 4d.
[0070]
In this way, when the imaging operation of the second field is performed, the signals φR1, φR5,..., ΦR (n-3) are given after the signals φV3, φV7,. It is done. Then, as described above, when each signal is repeatedly given, the imaging operations of the first and second fields are repeated, and moving image shooting is performed.
[0071]
Therefore, when the video signal of the first field is output, the blocks Bl11 to Bl (m-1) 1, Bl15 to Bl (m-1) 5, ..., Bl1 (n-3) to Bl (m-1). In (n-3), the output from the pixel provided with the R filter is supplied to the A / D converter 4a, the output from the pixel provided with the G filter (Ga) is supplied to the A / D converter 4b, and the B filter. Are output in parallel to the A / D converter 4c, and outputs from the pixels provided with the G filter (Gb) are output in parallel to the A / D converter 4d.
[0072]
Similarly, when the video signal of the second field is output, the blocks Bl13 to Bl (m-1) 3, Bl17 to Bl (m-1) 7, ..., Bl1 (n-1) to Bl (m -1) In (n-1), the output from the pixel provided with the R filter is supplied to the A / D converter 4a, and the output from the pixel provided with the G filter (Ga) is supplied to the A / D converter 4b. The output from the pixel provided with the B filter is output in parallel to the A / D converter 4c, and the output from the pixel provided with the G filter (Gb) is output to the A / D converter 4d in parallel.
[0073]
In this operation example, each signal is given at the same timing as in the first operation example, but each signal may be given at the same timing as in the second operation example. At this time, after the signals φR1, φR5,..., ΦR (n-3) are sequentially given, when the predetermined time ta has elapsed, the signals φR3, φR7,. Further, after the signals φV1, φV5,..., ΦV (n-3) are sequentially given, when the predetermined time ta elapses, the signals φV3, φV7,.
[0074]
4). Operation example when shooting still images
An operation example during still image shooting will be described with reference to the drawings. FIG. 10 shows the timing of the signals φV1 to φVn, φR1 to φRn (n is an even number). The timing of the signals φH1 to φHm is as shown in FIG.
[0075]
First, the signal φR1 is given, and each pixel of the blocks B11 to Blm1 is reset. Next, a signal φR2 is applied, and each pixel of the blocks B12 to Blm2 is reset. Similarly, signals .phi.R3, .phi.R4,..., .Phi.Rn are sequentially applied, and the pixels of the blocks Bl13 to Blm3, Bl14 to Blm4,..., Bl1n to Blmn are sequentially reset every two rows.
[0076]
In this way, when each pixel of the blocks Bl11 to Blmn is reset, the signal φV1 is given. That is, when the signal φR1 is given and a predetermined exposure period t has elapsed, the signal φV1 is given to each pixel of the blocks B11 to Blm1. At this time, as shown in FIG. 6, first, the signal φH1 is given, and the video signals of the pixels R11, Ga11, B11, Gb11 of the block Bl11 are respectively sent to the A / D converters 4a, 4b, 4c, 4d. Is output.
[0077]
Thereafter, as shown in FIG. 6, signals .phi.H2, .phi.H3,..., .Phi.Hm are sequentially given, and the video signals of the pixels of the blocks Bl21, Bl31,. That is, the video signals of the pixels R21, R31,..., Rm1 are sequentially output to the A / D converter 4a, and the video signals of the pixels Ga21, Ga31, ..., Gam1 are sequentially output to the A / D converter 4b, and the pixel B21. , B31,..., Bm1 are sequentially output to the A / D converter 4c, and video signals of the pixels Gb21, Gb31,..., Gbm1 are sequentially output to the A / D converter 4d.
[0078]
As described above, when the video signal from each pixel of the blocks Bl11 to Blm1 arranged in the 1x and 1y rows is output, next, the signal φV2 and the signals φH1, φH2,. Thus, the video signals of the respective pixels of the blocks Bl12, Bl22,..., Blm2 are output in order. That is, as described above, when the signal φR2 is given and the predetermined exposure period t has passed, the signal φV2 is given.
[0079]
Therefore, the video signals of the pixels B12, B22,..., Bm2 are sequentially output to the A / D converter 4a, and the video signals of the pixels Ga12, Ga22,. , R22,..., Rm2 are sequentially output to the A / D converter 4c, and video signals of the pixels Gb12, Gb22,..., Gbm2 are sequentially output to the A / D converter 4d.
[0080]
Thereafter, similarly, the signals φV3, φV4,..., ΦVn are sequentially given, and the signals φH1 to φHm are given in order while the signals φV3 to φVn are being given, so that the 3x, 3y rows, 4x Video signals are output from the pixels of the blocks Bl13 to Blm3, Bl14 to Blm4,..., Bl1n to Blmn arranged in the 4y row,.
[0081]
Therefore, the video signals of the pixels R13 to Rm3, B14 to Bm4, R15 to Rm5,..., B1n to Bmn are sequentially output to the A / D converter 4a, and the pixels Ga13 to Gam3, Ga14 to Gam4, Ga15 to Gam5,. The video signals Ga1n to Gamn are sequentially output to the A / D converter 4b, and the video signals of the pixels B13 to Bm3, R14 to Rm4, B15 to Bm5,..., R1n to Rmn are sequentially output to the A / D converter 4c. , Pixels Gb13 to Gbm3, Gb14 to Gbm4, Gb15 to Gbm5,..., Gb1n to Gbmn are sequentially output to the A / D converter 4d.
[0082]
In such a solid-state imaging device, when performing moving image shooting, video signals output from the A / D conversion units 4a to 4c are used as the color signals. That is, in the first or second operation example, the video signals from the A / D converters 4a to 4c are respectively RGB signals in the first field, and the A / D converter 4a in the second field. The video signals from ˜4c are BGR signals. Furthermore, the video signal output from the A / D conversion unit 4d is used as a signal for measuring the brightness of the subject or performing focus detection for performing exposure control or the like. Thus, when performing moving image shooting in the first or second operation example, three of the four pixels are used as the video signal.
[0083]
Therefore, for example, when moving image shooting is performed according to the VGA (Video Graphics Array) standard, in order to obtain an image equivalent to a three-plate type imaging device, about 330,000 pixels are required for each color. As described above, when RGB signals are extracted and used as surface signals for the RGB3 plane without interpolation, the signal may be about 1.3 million pixels, which is about four times that. Furthermore, by setting the solid-state imaging device in the present embodiment to about 1.3 million pixels, when performing still image shooting, after performing interpolation processing for pixels that do not output the color signal, each pixel has 4 pixels. A still image equivalent to about 2.6 million pixels can be obtained by performing a honeycomb process that performs an interpolation process on the enclosed positions.
[0084]
In the third operation example, the video signals from the A / D converters 4a to 4c are always RGB signals. Further, the video signal output from the A / D conversion unit 4d is used as a signal for performing luminance measurement or focus detection of the subject. Thus, when performing moving image shooting in the third operation example, three of the 16 pixels are used as the video signal.
[0085]
Therefore, for example, when moving image shooting is performed according to the VGA standard, in order to obtain an image equivalent to that of a three-plate type imaging device, about 5.3 million pixels, which is about four times that of the first or second operation example. And it is sufficient. Furthermore, by setting the solid-state imaging device in the present embodiment to about 5.3 million pixels, a still image equivalent to about 10 million pixels can be obtained by performing honeycomb processing during still image shooting.
[0086]
<Second Embodiment>
A second embodiment of the present invention will be described with reference to the drawings. In the present embodiment, as in the first embodiment, the internal configuration is as shown in FIG. Further, in the present embodiment, in the solid-state imaging device having the configuration as shown in FIG. 1, the sensor unit has a configuration as shown in FIG.
[0087]
In this embodiment, each pixel in the sensor unit 3 is arranged in a matrix as shown in FIG. That is, the array of each pixel is a Bayer array. At this time, four pixels existing in 2 rows and 2 columns are set as one block, and each column is assigned a column number as 1a, 1b, 2a, 2b, 3a, 3b, ..., ma, mb every two columns. In addition, each row is assigned a row number as 1x, 1y, 2x, 2y, 3x, 3y, ..., nx, ny every two rows. Each block is provided with one pixel each provided with R and B color filters and two pixels provided with G color filters. In FIG. 11, Bx11 to Bxmn represent blocks.
[0088]
As shown in FIG. 11, the color filters of the pixels arranged in the sensor unit 3 are ib columns in the order of G, B, G, B,... From the upper side in the ia column (1 ≦ i ≦ m). Are arranged in the order of R, G, R, G,. Therefore, in the lx row, they are arranged in the order of G, R, G, R,... From the left side, and in the ly row, they are arranged in the order of B, G, B, G,. Further, the block Bxil (1 ≦ l ≦ n) is composed of four pixels of Ril provided with an R color filter, Bil provided with a B color filter, and Gail and Gbil provided with a G color filter. The
[0089]
The wiring relationship for each pixel arranged as shown in FIG. 11 is representative of four blocks Bxil, Bxi (l + 1), Bx (i + 1) l, Bx (i + 1) (l + 1). I will explain. As shown in FIG. 12, the signals φVl and φV (l + 1) are supplied from the vertical scanning circuit 2 to the vertical selection lines 31l and 31 (l + 1), respectively, and the vertical reset lines 32l and 32 (l + 1) are supplied. Signals φRl and φR (l + 1) are respectively provided. The MOS transistors Tia to Tid and T (i + 1) a to T (i + 1) d are the same as those in the first embodiment, and thus description thereof is omitted.
[0090]
The vertical selection line 31l and the vertical reset line 32l are connected to the pixels Gail, Ril, Bil, Gbil, Ga (i + 1) l, R (i + 1) l, B (i + 1) l, Gb (i + 1). ) l is applied to the vertical selection line 31 (l + 1) and the vertical reset line 32 (l + 1) by the pixels Gai (l + 1), Ri (l + 1), Bi (l + 1), Gbi (l +). 1), Ga (i + 1) (l + 1), R (i + 1) (l + 1), B (i + 1) (l + 1), Gb (i + 1) (l + 1) Are connected to each other.
[0091]
Further, the pixels Gail, Gai (l + 1) are connected to the horizontal signal line 33ia connected to the drain of the MOS transistor Tia, and the pixels Bil, Bi (l + 1) are connected to the horizontal signal line 33ib connected to the drain of the MOS transistor Tib. However, the pixels Ril, Ri (l + 1) are connected to the horizontal signal line 33ic connected to the drain of the MOS transistor Tic, and the pixels Gbil, Gbi (l + 1) are connected to the horizontal signal line 33id connected to the drain of the MOS transistor Tid. Are connected to each other.
[0092]
Further, the pixels Ga (i + 1) l, Ga (i + 1) (l + 1) are connected to the horizontal signal line 33 (i + 1) a connected to the drain of the MOS transistor T (i + 1) a. The pixels B (i + 1) l and B (i + 1) (l + 1) are connected to the horizontal signal line 33 (i + 1) b connected to the drain of the MOS transistor T (i + 1) b. Pixels R (i + 1) l and R (i + 1) (l + 1) are connected to the MOS transistor T (i) on the horizontal signal line 33 (i + 1) c connected to the drain of T (i + 1) c. Pixels Gb (i + 1) l and Gb (i + 1) (l + 1) are connected to the horizontal signal line 33 (i + 1) d connected to the drain of i + 1) d, respectively.
[0093]
As described above, in the sensor unit 3, when each pixel is arranged, each signal is given at the same timing as in the first embodiment, thereby performing various imaging operations similar to those in the first embodiment.
[0094]
That is, at the time of moving image shooting, the blocks Bx11 to Bxm1, Bx13 to Bxm3,..., Bx1 (n-1) to Bx11 to Bxm1, Bx13 to Bxm3 are operated according to the timing charts of FIGS. The video signal of each pixel of Bxm (n-1) is output as the video signal of the first field, and the video signal of each pixel of the blocks Bx12 to Bxm2, Bx14 to Bxm4, ..., Bx1n to Bxmn is the second field. Output as a video signal.
[0095]
In addition, during moving image shooting, by operating according to the timing charts of FIGS. 8 and 9, each pixel image of blocks Bx11 to Bxm1, Bx15 to Bxm5,..., Bx1 (n-3) to Bxm (n-3). The signal is output as the video signal of the first field, and the video signal of each pixel of the blocks Bx13 to Bxm3, Bx17 to Bxm7, ..., Bx1 (n-1) to Bxm (n-1) is the video of the second field. Output as a signal.
[0096]
Further, at the time of still image shooting, by operating according to the timing charts of FIGS. 10 and 6, the video signals of the pixels of the blocks Bx11 to Bxm1, Bx12 to Bxm2,..., Bx1n to Bxmn are output as video signals of still images. Is done.
[0097]
Regardless of the timing at which the signal is applied, in this embodiment, the output from the pixel provided with the G filter (Ga) is always output from the pixel provided with the B filter to the A / D converter 4a. Output from the pixel provided with the R filter to the A / D converter 4c, and output from the pixel provided with the G filter (Gb) to the A / D converter 4d. Are output in parallel.
[0098]
In such a solid-state imaging device, when moving image shooting is performed, the video signals from the A / D conversion units 4a to 4c are respectively RGB signals. Further, the video signal output from the A / D conversion unit 4d is used as a signal for performing luminance measurement or focus detection of the subject. At this time, in the first or second operation example, three pixels out of the four pixels are used as the video signal when moving image shooting is performed.
[0099]
Therefore, for example, when moving image shooting is performed in accordance with the VGA standard, in order to obtain an image equivalent to that of a three-plate type imaging device, it may be about 1.3 million pixels as in the first embodiment. In the present embodiment, since only interpolation processing is performed for each color signal for pixels that do not output the color signal, a still image equivalent to about 1.3 million pixels can be obtained.
[0100]
In the third operation example, 3 out of 16 pixels are used as a video signal. Therefore, for example, when moving image shooting is performed in accordance with the VGA standard, in order to obtain an image equivalent to that of a three-plate type imaging device, it may be about 5.3 million pixels as in the first embodiment. Further, in the present embodiment, since only interpolation processing is performed for each color signal with respect to pixels for which no color signal is output, a still image equivalent to about 5.3 million pixels can be obtained.
[0101]
<Third Embodiment>
A third embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram showing an internal configuration of the solid-state imaging device in the present embodiment. In addition, about the part used for the same objective as FIG. 1, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted.
[0102]
13 includes a horizontal scanning circuit 1, a vertical scanning circuit 2, a sensor unit 3, and A / D conversion units 4a to 4f that convert video signals output from the sensor unit 3 into digital signals. . In such a solid-state imaging device, each pixel in the sensor unit 3 is arranged as shown in FIG. That is, as in the case of FIG. 2, the arrangement of the pixels is a honeycomb arrangement.
[0103]
At this time, 6 pixels existing in 2 rows and 6 columns are set as one block, and each column is assigned a column number as 1a to 1f, 2a to 2f, 3a to 3f, ..., ma to mf every four columns. In addition, each row is assigned a row number as 1x, 1y, 2x, 2y, 3x, 3y, ..., nx, ny every two rows. Each block is composed of two pixels provided with an R color filter, one pixel provided with a B color filter, and three pixels provided with a G color filter, and an R color. Some of them are composed of one pixel provided with a filter, two pixels provided with a B color filter, and three pixels provided with a G color filter. In FIG. 14, By11 to Bymn represent blocks.
[0104]
Since the positional relationship of the color filters provided in each pixel is the same as that in FIG. 2, the pa column and the pe column (p is an odd number of 1 ≦ p ≦ m) and the qc column (q is 1 ≦ q ≦ m (even number)) in the order of R, B, R, B,... From the upper side, and in the pc column, qa column, and qe column, in the order of B, R, B, R,. In the ib column, id column, and if column, only G is arranged. Further, the block Byil is composed of six pixels of Rail, Rbil, Bil provided with the R color filter, Bil provided with the B color filter, and Gil, Gbil, Gcil provided with the G color filter. , Ril with an R color filter, Bail, Bbil with a B color filter, and Gail, Gbil, Gcil with a G color filter.
[0105]
When each pixel is arranged as shown in FIG. 14, although not shown, signals φV1 to φVn and φR1 to φRn are given every two rows from the vertical scanning circuit 2 as in the first embodiment. In the present embodiment, since 6 pixels existing in 2 rows and 6 columns are used as one block, the horizontal scanning circuit 1 makes blocks By11 to Bym1, By13 to Bym3 arranged in odd rows from the horizontal scanning circuit 1. ..., By1 (n-1) to Bym (n-1) (where n is a multiple of 4 and m is an even number), signals φHx1 to φHxm are provided every 6 columns. .., By1n to Bymn, signals .phi.Hy1 to .phi.Hym are applied every 6 columns to the blocks By12 to Bym2, By14 to Bym4,. An example of operation during moving image shooting and still image shooting when each signal is supplied to the sensor unit 3 will be described below.
[0106]
1. Operation example during movie shooting
An operation example during moving image shooting will be described with reference to the drawings. FIG. 15 shows the timing of the signals φV1 to φVn, φR1 to φRn. In FIG. 16, the timing of signals φHx1 to φHxm and φHy1 to φHym when signal φVl is applied is shown as a representative.
[0107]
First, in order to perform the imaging operation of the first field, the signals φR1 and φR2 are simultaneously applied, and the pixels of the blocks By11 to Bym1 and By12 to Bym2 are reset. Next, the signals φR5 and φR6 are simultaneously applied to reset the pixels of the blocks By15 to Bym5 and By16 to Bym6. Similarly, signals φR9, φR10, φR13, φR14,..., ΦR (n−3), φR (n−2) are simultaneously applied to two signals, whereby blocks By19 to Bym9, By110 to Bym10, By113 to Bym13. , By114 to Bym14,..., By1 (n-3) to Bym (n-3), By1 (n-2) to Bym (n-2) are sequentially reset every four rows.
[0108]
When each pixel is reset in this way, signals φV1 and φV2 are given. That is, when the signals φR1 and φR2 are given and a predetermined exposure period t elapses, the signal φV1 is given to each pixel of the blocks By11 to Bym1, and the signal φV2 is given to each pixel of the blocks By12 to Bym2. At this time, as shown in FIG. 16, first, a signal φHx1 is given, and the video signals of the pixels Ra11, Ga11, B11, Gb11, Rb11, Gc11 of the block By11 are respectively converted into A / D conversion units 4a, 4b, 4c, 4d, 4e, and 4f are output.
[0109]
Thereafter, the signal φHy2 is given, and the video signals of the pixels Ra22, Ga22, B22, Gb22, Rb22, Gc22 of the block By22 are output to the A / D converters 4a, 4b, 4c, 4d, 4e, 4f, respectively. The .Phi.Hx3, .phi.Hy4,..., .Phi.Hx (m-1), Hym are given in order, and the video signals of the pixels of the blocks By31, By42,..., By (m-1) 1, Bym2 are output in order.
[0110]
That is, the video signals of the pixels Ra31, Ra42,..., Ra (m-1) 1, Ram2 are sequentially output to the A / D conversion unit 4a, and the pixels Ga31, Ga42, ..., Ga (m-1) 1, Gam2 are output. The video signals are sequentially output to the A / D converter 4b, and the video signals of the pixels B31, B42,..., B (m-1) 1, Bm2 are sequentially output to the A / D converter 4c, and the pixels Gb31, Gb42, .., Gb (m-1) 1, Gbm2 are sequentially output to the A / D converter 4d, and the video signals of the pixels Rb31, Rb42, ..., Rb (m-1) 1, Rbm2 are sequentially A / D. The video signals of the pixels Gc31, Gc42,..., Gc (m-1) 1, Gcm2 are sequentially output to the A / D converter 4f.
[0111]
Thereafter, similarly, the signals φV5, φV6, φV9, φV10,..., ΦV (n−3), φV (n−2) are sequentially applied every two signals, and each time two signals are applied, the signals φHx1, ..., .phi.Hx (m-1), .phi.Hym are given in order, whereby each block By15, By26,..., By (m-1) 5, Bym6, By19, By210,. , Bym10,..., By1 (n-3), By2 (n-2),..., By (m-1) (n-3), Bym (n-2), video signals are output.
[0112]
Thus, when the imaging operation of the first field is performed, the imaging operation of the second field is performed as follows. When the signals φV1 and φV2 are given, the signals φR3 and φR4 are given and the pixels of the blocks By13 to Bym3 and By14 to Bym4 are reset. Similarly, signals φR7, φR8, φR11, φR12,..., ΦR (n-1), φRn are simultaneously applied to two signals, whereby blocks By17 to Bym7, By18 to Bym8, By111 to Bym11, By112 to Bym12, ..., By1 (n-1) to Bym (n-1), By1n to Bymn are reset in order every four rows. That is, the signals φR7, φR8, φR11, φR12,..., ΦR (n-1), φRn are given by the signals φV5, φV6, φV9, φV10, ..., φV (n-3), φV (n-2), respectively. Given after being given.
[0113]
When each pixel is reset in this way, signals φV3 and φV4 are given. That is, when the signals φR3 and φR4 are given and a predetermined exposure period t elapses, the signal φV3 is given to each pixel of the blocks By13 to Bym3, and the signal φV4 is given to each pixel of the blocks By14 to Bym4. At this time, as shown in FIG. 16, first, a signal φHx1 is given, and the video signals of the pixels Ra13, Ga13, B13, Gb13, Rb13, Gc13 of the block By13 are respectively converted into A / D conversion units 4a, 4b, 4c, 4d, 4e, and 4f are output.
[0114]
Thereafter, a signal φHy2 is given, and the video signals of the pixels Ra24, Ga24, B24, Gb24, Rb24, Gc24 of the block By24 are output to the A / D converters 4a, 4b, 4c, 4d, 4e, 4f, respectively. The .Phi.Hx3, .phi.Hy4,..., .Phi.Hx (m-1), Hym are given in order, and the video signals of the pixels of the blocks By33, By44,..., By (m-1) 3, Bym4 are output in order.
[0115]
That is, the video signals of the pixels Ra33, Ra44,..., Ra (m-1) 3, Ram4 are sequentially output to the A / D converter 4a, and the pixels Ga33, Ga44, ..., Ga (m-1) 3, Gam4 are output. The video signals are sequentially output to the A / D converter 4b, and the video signals of the pixels B33, B44,..., B (m-1) 3, Bm4 are sequentially output to the A / D converter 4c, and the pixels Gb33, Gb44, .., Gb (m-1) 3, Gbm4 are sequentially output to the A / D converter 4d, and the video signals of the pixels Rb33, Rb44, ..., Rb (m-1) 3, Rbm4 are sequentially A / D. The video signals of the pixels Gc33, Gc44,..., Gc (m-1) 3, Gcm4 are sequentially output to the A / D converter 4f.
[0116]
Thereafter, similarly, the signals φV7, φV8, φV11, φV12,..., ΦV (n−1), φVn are sequentially applied every two signals, and every time two signals are applied, the signals φHx1, φHy2,. (m-1), φHym are given in order, so that each block By17, By28, ..., By (m-1) 7, Bym8, By111, By212, ..., By (m-1) 11, Bym12, ..., Video signals are output from the pixels By1 (n-1), By2n, ..., By (m-1) (n-1), Bymn.
[0117]
Thus, when the second field imaging operation is performed, the signals φR1, φR2, φR5, φR6,..., ΦR (n-3), φR (n-2) are the signals φV3, φV4, φV7, φV8, respectively. ,..., .Phi.V (n-1), .phi.Vn are given. Then, as described above, when each signal is repeatedly given, the imaging operations of the first and second fields are repeated, and moving image shooting is performed.
[0118]
Therefore, when the video signal of the first field is output, the blocks By11, By22,..., By (m-1) 1, Bym2, By15, By26,..., By (m-1) 5, Bym6,. In By1 (n-3), By2 (n-2),..., By (m-1) (n-3), Bym (n-2), an output from a pixel provided with an R filter (Ra) is obtained. The output from the pixel provided with the G filter (Ga) in the A / D converter 4a is output to the A / D converter 4b, and the output from the pixel provided with the B filter is supplied to the A / D converter 4c. The output from the pixel provided with the filter (Gb) is provided in the A / D converter 4d, the output from the pixel provided with the R filter (Rb) is provided in the A / D converter 4e, and the G filter (Gc) is provided. Outputs from the obtained pixels are output in parallel to the A / D converter 4f.
[0119]
When the video signal of the second field is output, the blocks By13, By24, ..., By (m-1) 3, Bym4, By17, By28, ..., By (m-1) 7, Bym8, ..., In By1 (n-1), By2n, ..., By (m-1) (n-1), Bymn, the output from the pixel provided with the R filter (Ra) is sent to the A / D conversion unit 4a and the G filter. The output from the pixel provided with (Ga) is supplied to the A / D converter 4b, the output from the pixel provided with the B filter is supplied from the pixel provided with the G filter (Gb) to the A / D converter 4c. Output from the pixel provided with the R filter (Rb) is output to the A / D converter 4e, and output from the pixel provided with the G filter (Gc) is A / D. The signals are output to the conversion unit 4f in parallel.
[0120]
In this operation example, each signal is given at the same timing as in the first operation example of the first embodiment. However, each signal is given at the same timing as in the second operation example. It doesn't matter.
[0121]
2. Operation example when shooting still images
An operation example during still image shooting will be described with reference to the drawings. As in the first embodiment, the timing of the signals φV1 to φVn, φR1 to φRn is as shown in FIG. The timings of the signals φHx1 to φHxm and φHy1 to φHym are as shown in FIG.
[0122]
First, as in the first embodiment, signals φR1, φR2,..., ΦRn are sequentially applied, and the pixels of the blocks By11 to Bym1, By12 to Bym2,..., By1n to Bymn are reset in sequence every two rows. . In this way, when each pixel of the blocks By11 to Bymn is reset, the signal φV1 is given. That is, when the signal φR1 is given and a predetermined exposure period t has passed, the signal φV1 is given to each pixel of the blocks By11 to Bym1. At this time, as shown in FIG. 17, first, a signal φHx1 is given, and the video signals of the pixels Ra11, Ga11, B11, Gb11, Rb11, Gc11 of the block By11 are respectively converted into A / D conversion units 4a, 4b, 4c, 4d, 4e, and 4f are output.
[0123]
Thereafter, as shown in FIG. 17, the signals φHx2, φHx3,... ΦHxm are sequentially given, and the video signals of the pixels of the blocks By21, By31,. That is, the video signals of the pixels Ba21, Ra31,..., Bam1 are sequentially output to the A / D converter 4a, and the video signals of the pixels Ga21, Ga31,. , B31,..., Rm1 are sequentially output to the A / D converter 4c, and video signals of the pixels Gb21, Gb31,..., Gbm1 are sequentially output to the A / D converter 4d, and the pixels Bb21, Rb31,. , Bbm1 are sequentially output to the A / D converter 4e, and the video signals of the pixels Gc21, Gc31,..., Gcm1 are sequentially output to the A / D converter 4f.
[0124]
Then, the signal φV2 is given, and the signals φHy1, φHy2,... ΦHym are given in order, and the video signals of the pixels of the blocks By12, By22,. That is, as described above, when the signal φR2 is given and the predetermined exposure period t has passed, the signal φV2 is given.
[0125]
Therefore, the video signals of the pixels Ba12, Ra22,..., Ram2 are sequentially output to the A / D converter 4a, and the video signals of the pixels Ga12, Ga22,..., Gam2 are sequentially output to the A / D converter 4b, and the pixel R12. , B22,..., Bm2 are sequentially output to the A / D converter 4c, and video signals of the pixels Gb12, Gb22,..., Gbm2 are sequentially output to the A / D converter 4d, and the pixels Bb12, Rb22,. , Rbm2 are sequentially output to the A / D converter 4e, and video signals of the pixels Gc12, Gc22,..., Gcm2 are sequentially output to the A / D converter 4f.
[0126]
Thereafter, similarly, signals φV3, φV4,..., ΦVn are sequentially applied, and signals φHx1 to φHxm are sequentially applied while signals φV3, φV5,. Each block arranged in the 3x, 3y row, 4x, 4y row,..., Nx, ny by sequentially applying the signals φHy1 to φHym while the signals φV4, φV6,. Video signals are output from the pixels By13 to Bym3, By14 to Bym4,..., By1n to Bymn.
[0127]
Therefore, video signals of the pixels Ra13, Ba23,..., Bam3, Ba14, Ra24,..., Ram4, ..., Ba1n, Ra2n, ..., Ramn are sequentially output to the A / D converter 4a, and the pixels Ga13 to Gam3, Ga14 to .., Ga1n to Gamn video signals are sequentially output to the A / D converter 4b, and pixels B13, R23,..., Rm3, R14, B24,..., Bm4, ..., R1n, B2n,. The signals are sequentially output to the A / D converter 4c, and the video signals of the pixels Gb13 to Gbm3, Gb14 to Gbm4,..., Gb1n to Gbmn are sequentially output to the A / D converter 4d, and the pixels Rb13, Bb23,. , Bb14, Rb24, ..., Rbm4, ..., Bb1n, Rb2n, ..., Rbmn are sequentially output to the A / D converter 4e, and the video signals of the pixels Gc13 to Gcm3, Gc14 to Gcm4, ..., Gc1n to Gcmn are output. Are sequentially output to the A / D converter 4f.
[0128]
In such a solid-state imaging device, when moving image shooting is performed, the video signals from the A / D conversion units 4a to 4c are respectively RGB signals. Further, the video signal output from the A / D conversion unit 4d is used as a signal for performing luminance measurement or focus detection of the subject. In this way, when performing moving image shooting, 3 pixels out of 12 pixels are used as the video signal.
[0129]
Therefore, for example, when moving image shooting is performed in accordance with the VGA standard, in order to obtain an image equivalent to that of a three-plate type imaging device, it is about three times as much as in the first operation example in the first embodiment. What is necessary is just about 4 million pixels. Furthermore, by setting the solid-state imaging device in the present embodiment to about 4 million pixels, a still image equivalent to about 8 million pixels can be obtained by performing honeycomb processing during still image shooting.
[0130]
<Configuration example of imaging device>
An imaging apparatus provided with the solid-state imaging device according to the first to third embodiments will be described with reference to the drawings. FIG. 18 is a block diagram showing an internal configuration of the imaging apparatus in this example.
[0131]
The image pickup apparatus in FIG. 18 outputs an image that is compression-coded by performing arithmetic processing on the image signal from the image pickup unit 100 and an image pickup unit 100 including an optical system and a solid-state image pickup device that outputs the image signal. An image processing unit 101, an AE (Automatic Exposure) / AF (Automatic Focusing) processing unit 102 that performs exposure control processing and automatic focus adjustment processing from a video signal supplied from the image processing unit 101, and a control unit that controls each block 103, a still image recording medium 104 that records a still image compression signal provided by the image processing unit 101, a moving image recording medium 105 that records a moving image compression signal provided by the image processing unit 101, and an image And a liquid crystal display screen 106 that reproduces an image based on a signal supplied from the processing unit 101.
[0132]
In the image processing unit 101, a signal switching unit 111 that switches between a case where a video signal supplied from the solid-state imaging device 100 is used for a still image and a case where it is used for a moving image, and a signal switching unit 111 that is used for a still image. An interpolation processing unit 112 that performs an interpolation process from the video signal selected as: a gamma conversion unit 113 that performs gamma correction, and a color space conversion unit 114 that obtains a luminance signal and a color difference signal from the video signal from the gamma conversion unit 113. A JPEG compression unit 115 that compresses and encodes the luminance signal and color difference signal from the color space conversion unit 114 according to the JPEG (Joint Photographic Experts Group) method; and the MPEG (Moving) from the luminance signal and color difference signal from the color space conversion unit 114. An MPEG compression unit 116 that performs compression encoding according to a (Picture Experts Group) system is provided.
[0133]
In such an imaging apparatus, the solid-state imaging device of the first embodiment is used. First, when a still image is shot, the video signal from the imaging unit 100 is given to the interpolation processing unit 112 by the signal switching unit 111. At this time, when a video signal is output from each pixel in the row of jx, yy (j is an odd number of 1 ≦ j ≦ n), the A / D conversion unit 4a outputs the R signal and the A / D conversion unit 4c. To B signal, and A / D converters 4b and 4d output G signal. Further, when a video signal is output from each pixel in the kx, ky (k is an even number of 1 ≦ k ≦ n) row, the B signal from the A / D conversion unit 4a and the A / D conversion unit 4c The R signal and the G signal are output from the A / D converters 4b and 4d.
[0134]
Further, in the signal switching unit 111, by switching the signals from the A / D conversion units 4a and 4c between the case of being output from the pixels in the jx and xy rows and the case of being output from the pixels in the kx and ky rows. , R signal, B signal, and G signal are given to the interpolation processing unit 112 as serial signals. The interpolation processing unit 112 performs an interpolation process for each of the R signal, the B signal, and the G signal.
[0135]
This interpolation processing will be described on behalf of R signal interpolation processing. First, as shown in FIG. 19A, an R signal is provided for every four pixels. Using this R signal, interpolation processing of the R signal is performed on the remaining portions of the three pixels as shown in FIG. 19B. Further, as shown in FIG. 19C, the interpolation process is further performed on the region surrounded by the four pixels. By performing such interpolation processing by honeycomb processing, it is possible to obtain an R signal for the number of pixels approximately twice the number of pixels actually arranged.
[0136]
Similarly, with respect to the B signal, the B signal corresponding to approximately twice the number of pixels actually arranged can be obtained by performing the honeycomb processing which is the above-described interpolation processing. Since the initial value of the G signal is in the state shown in FIG. 19B, the interpolation processing from FIG. 19B to FIG. 19C is performed. After the RGB signal thus interpolated is supplied to the gamma conversion unit 113 and subjected to gamma correction processing, the color space conversion unit 114 generates a luminance signal and a color difference signal. The luminance signal and the color difference signal generated by the color space conversion unit 114 are supplied to the JPEG compression unit 115, compressed and converted according to the JPEG method, and then recorded on the still image recording medium 104.
[0137]
Next, when a moving image is shot according to the first or second operation example of the first embodiment, the signal switching unit 111 converts the video signal from the imaging unit 100 into the gamma conversion unit 113 and the AE / AF processing unit. 102. At this time, when the first field is imaged, the RGB signals from the A / D conversion units 4a to 4c are sent to the gamma conversion unit 113, and the G signal from the A / D conversion unit 4d is sent to the AE / AF. It is sent to the processing unit 102. When the second field is imaged, the BGR signal from the A / D converters 4a to 4c is sent to the gamma converter 113, and the G signal from the A / D converter 4d is processed by the AE / AF process. Sent to the unit 102.
[0138]
Further, the signal switching unit 111 switches the signals from the A / D conversion units 4a and 4c between when the first field is imaged and when the second field is imaged. The G signal can be given to the gamma conversion unit 113 as a serial signal. Therefore, the same color signal as that of the three-plate imaging device is given to the gamma conversion unit 113.
[0139]
Then, after the RGB signal is subjected to gamma correction processing in the gamma conversion unit 113, a luminance signal and a color difference signal are generated in the color space conversion unit 114. The luminance signal and the color difference signal generated by the color space conversion unit 114 are supplied to the MPEG compression unit 116 and compressed and converted according to the MPEG system. The compression-converted signal is given to the moving image recording medium 105 and recorded. Further, the luminance signal and the color difference signal generated by the color space conversion unit 114 are given to the liquid crystal display screen 106, and an image is reproduced.
[0140]
In such an imaging apparatus, the solid-state imaging device according to the second embodiment or the third embodiment may be used as the solid-state imaging device. Further, at the time of moving image shooting, the solid-state imaging device is operated according to the first or second operation example, but may be operated according to the third operation example. Further, the compression methods used when recording still images and moving images are not limited to JPEG and MPEG, respectively.
[0141]
In addition, at the time of moving image shooting, the solid-state image sensor is operated in each operation example in each embodiment, so that it is not necessary to speed up the drive clock of the solid-state image sensor, and the solid-state image sensor mounted on a general video camera can be used. It can be about 13.5 MHz equivalent to the drive clock. Therefore, power consumption can be reduced. Furthermore, as in the first or third embodiment, by using the solid-state imaging device having the honeycomb arrangement, the pixel arrangement for outputting the RGB signals is close to the delta arrangement at the time of moving image shooting. An image equivalent to that of the imaging device can be obtained.
[0142]
Further, since interpolation processing is not required, processing can be performed at high speed, and a time lag generated in liquid crystal display or the like can be reduced. Further, when moving image recording is not performed, the power consumption can be further reduced by reading only one field (1/30 second). In the above-described imaging apparatus, a mechanical shutter that can reset all the pixels of the solid-state imaging element may be provided. By providing this mechanical shutter, it is possible to prevent blurring of a photographed subject that occurs in the case of an electronic focal plane shutter when photographing a moving subject.
[0143]
In this embodiment, the color filters provided in the solid-state imaging device are R, G, and B. However, Mg (Magenta), Cy (Cyan), Ye (Yellow), G (Green) color filters, and the like are used. Other filters may be used. In the present embodiment, each pixel of the sensor unit has a circuit configuration as shown in FIG. 4, but the present invention is not limited to this. For example, a MOS transistor that operates in the subthreshold region is provided. Other configurations such as a pixel configured to output a video signal logarithmically converted with respect to the amount of incident light may be used. Furthermore, in moving image shooting, an example is given in which the image pickup operation is performed by skipping one block at a time in both the vertical direction and the horizontal direction. However, the present invention is not limited to one block, and the image is shot by skipping predetermined blocks. You may make it perform operation | movement.
[0144]
【The invention's effect】
According to the present invention, it is possible to output video signals in parallel as various color signals without interpolation processing during moving image shooting. Therefore, the time required for the interpolation process can be shortened. Further, if the output video signal is a color signal of the three primary colors of RGB, it can be handled as a surface signal of the RGB3 surface without performing interpolation processing. Therefore, when the video is reproduced from this video signal, the image quality is high. Video can be played back.
[0145]
In addition, by arranging each pixel in a honeycomb arrangement, it is possible to shoot still images with even higher pixels, and when the color filters are set to the three primary colors, the arrangement relationship is close to a delta arrangement. A video signal equivalent to a video signal obtained in a three-plate type imaging apparatus can be obtained. In addition, during moving image shooting, each block is skipped and driven in the vertical and horizontal directions at the time of moving image shooting, so an image sensor with a higher pixel can be used, so that a higher-definition still image can be taken. .
[Brief description of the drawings]
FIG. 1 is a block diagram showing an internal configuration of a solid-state imaging device according to first and second embodiments.
FIG. 2 is a diagram for illustrating an example of an arrangement of each pixel in the solid-state image sensor of FIG. 1;
FIG. 3 is a block circuit diagram for illustrating a wiring relationship of pixels in the arrangement relationship of FIG. 2;
4 is a circuit diagram for illustrating a configuration of each pixel in the solid-state imaging device of FIG. 2;
FIG. 5 is a timing chart illustrating a first operation example during moving image shooting.
FIG. 6 is a timing chart showing the horizontal operation during moving image shooting and still shooting.
FIG. 7 is a timing chart showing a second operation example during moving image shooting.
FIG. 8 is a timing chart showing a third operation example during moving image shooting.
FIG. 9 is a timing chart showing a third operation example during moving image shooting.
FIG. 10 is a timing chart showing an operation example during still image shooting.
11 is a diagram for illustrating an example of an arrangement of each pixel in the solid-state imaging device in FIG. 1;
12 is a block circuit diagram for illustrating a wiring relationship of pixels in the arrangement relationship of FIG.
FIG. 13 is a block diagram showing an internal configuration of a solid-state imaging device according to a third embodiment.
14 is a diagram for illustrating an example of an arrangement of each pixel in the solid-state imaging device in FIG. 13;
FIG. 15 is a timing chart showing an operation example during moving image shooting.
FIG. 16 is a timing chart showing an operation example during moving image shooting.
FIG. 17 is a timing chart showing an operation example during still image shooting.
FIG. 18 is a block diagram showing an internal configuration of the imaging apparatus according to the present invention.
FIG. 19 is a diagram for explaining honeycomb processing.
[Explanation of symbols]
1 Horizontal scanning circuit
2 Vertical scanning circuit
3 Sensor part
4a to 4f A / D converter
100 Imaging unit
101 Image processing unit
102 AE / AF processing unit
103 Control unit
104 Recording medium for still images
105 Recording media for video
106 Liquid crystal display screen

Claims (3)

An electrical signal with a plurality of pixels each provided with a m kinds of color filter for outputting a video signal corresponding to the amount of incident light, and outputs the m kinds of color signals, said n number of adjacent (n is greater than m natural number) An XY scanning type in which a block is configured for each pixel and n video signals including m kinds of color signals are output in parallel by outputting in parallel from the n pixels in each block. A solid-state image sensor,
A control unit for performing exposure control or automatic focus adjustment;
Have
At the time of moving image shooting , any one of two or more color signals of the same type out of n video signals output for each block from the solid-state imaging device is given to the control unit to control exposure. Alternatively , the imaging apparatus is used as a control signal for use in automatic focus adjustment . In the solid-state imaging device, an imaging apparatus according to claim 1, wherein the pixel is characterized in that it is constituted by a honeycomb arrangement disposed in a zigzag in the horizontal and vertical directions. The m kinds of color filters are three kinds of color filters for the three primary colors of red, green, and blue ,
The imaging apparatus according to claim 1 or 2, wherein the two or more same-type color signals are green color signals .

Images