JP3735629B2 - Display device - Google Patents

Description

  The present invention relates to a display device such as a liquid crystal display device in which a plurality of display pixels are arranged in a matrix and a driving method thereof.

  Liquid crystal display devices are used in various fields such as televisions, computer displays, and electronic notebooks. In particular, liquid crystal display devices are attracting attention because of their light weight, thin shape, and low power consumption.

  For example, a liquid crystal projector splits white light from a light source into three primary colors of red, green, and blue using a dichroic mirror and the like, and makes each of these color component light incident on three independent liquid crystal display devices. , Green, and blue images are displayed, and these display images are optically synthesized again and projected onto a transmissive or reflective screen for color display.

  A liquid crystal display device for a liquid crystal projector is required to be downsized in order not to increase the size of the incident optical system and the projection optical system. In addition, since the display image of the liquid crystal display device is enlarged and projected onto the screen, it is necessary to reduce not only the size of the display device but also the pitch of the display pixels.

  In such a liquid crystal display device, a display panel composed of a plurality of display pixels and a drive circuit unit for driving these display pixels are integrally formed on a substrate, and the connection between the display panel and the drive circuit unit is troublesome. Attempts have been made to eliminate this problem.

  By the way, the drive circuit portion of the above-described display device is generally configured mainly by a shift register row in which a plurality of shift registers are connected in a row. This is disclosed in Non-Patent Document 1, for example.

  However, since the shift register train is configured to transfer signals sequentially through these shift registers, if a defect such as disconnection or short circuit exists in a part of the shift register train, all the downstream shift registers will malfunction. .

  In order to solve this problem, for example, Japanese Patent Application Laid-Open No. H10-228707 replaces a drive circuit unit mainly composed of a shift register, and outputs a pair of pulses sequentially based on a binary count value obtained by counting clock pulses and its inverted output. It is disclosed that a driving circuit including a decoder is used as a driving circuit unit of a display device.

In this way, if the drive circuit unit is composed mainly of the decoder, even if a defect such as a disconnection or a short circuit exists in the middle of the wiring, only the output corresponding to the defective part cannot be obtained. It is possible to ensure sufficient reliability by providing the drive circuit portion redundantly.
Japanese Patent Laid-Open No. Sho 62-27169 SID 93 DIGEST p.383-p.386 "A 1.9-in.1.5-MPixel Driver Fully-Integrated Poly-Si TFT-LCD for HDTV Projection"

  However, in the configuration disclosed in Patent Document 1, each decoder has a plurality of logic circuit portions provided corresponding to one scanning line or one signal line. In addition to the number of wiring lines for transmitting signals, the number of logic circuit sections increases remarkably, and conversely the manufacturing yield decreases. Furthermore, if each logic circuit unit is arranged corresponding to one scanning line or one signal line, it is difficult to sufficiently cope with high-speed operation associated with higher definition of the display device.

  For example, when the number of effective scanning lines of the video signal is smaller than the number of horizontal pixel lines of the display panel, the remaining horizontal pixel lines of the display panel that do not correspond to the effective scanning lines of the video signal are scanned in the vertical blanking period. A method of displaying a black blank is known. However, in the above-described configuration, it is difficult to scan all of these excess horizontal pixel lines in an extremely short time, and reliable black display cannot be expected.

  The present invention has been made in response to the above-described technical problems, and an object of the present invention is to provide a display device in which malfunctions are remarkably reduced.

  Another object of the present invention is that the number of horizontal pixel lines of the display panel and the number of effective scanning lines of the video signal, or the number of display pixels constituting one horizontal pixel line and the number of video data of the video signal are different. Even in such a case, it is an object of the present invention to provide a display device that can obtain a good display image and a driving method thereof.

  The display device of the present invention includes a plurality of signal lines and a plurality of scanning lines arranged in a matrix, a plurality of switching elements electrically connected to the signal lines and the scanning lines, and each of the switching elements. A display panel including a pixel electrode connected to the scanning line; a scanning circuit unit that supplies a scanning signal to the scanning line; and an input numerical signal of n (n is a positive integer greater than or equal to 2) bits to the scanning circuit unit; A scanning control circuit unit for supplying an inverted input numerical signal of the input numerical signal, wherein the scanning circuit unit receives the input numerical signal and the inverted input numerical signal for each bit. An input wiring group composed of a plurality of input wirings, a plurality of logic circuit units less than the number of scanning lines to which the input numerical signal and the inverted input numerical signal are selectively input, and one output from the logic circuit unit is reduced. Both are characterized by including a power distribution unit to correspond to two of the scanning lines.

  Further, the display device of the present invention includes a plurality of signal lines and a plurality of scanning lines arranged in a matrix, a switch element electrically connected to the signal line and the scanning line, and a connection to the switch element A display panel including a pixel electrode, a selection control circuit unit for generating an input numerical signal of n (n is a positive integer of 2 or more) bits and an inverted input numerical signal of the input numerical signal, and the selection control A display device comprising: a video signal supply circuit unit that selects a video signal input based on the input numeric signal and the inverted input numeric signal from the circuit unit at a predetermined timing and supplies the selected signal to the signal line as video data. The video signal supply circuit unit includes an input wiring group including a plurality of input wirings to which the input numerical signal and the inverted input numerical signal are input for each bit, the input numerical signal and A plurality of logic circuit units less than the number of the signal lines that selectively receive the inverted input numerical signal, and an output distribution unit that associates an output from the logic circuit unit with at least two signal lines. It is characterized by that.

  Further, the display device driving method of the present invention is a display device driving method for forming a display image based on video data of a video signal on a display panel in which a plurality of horizontal pixel lines composed of a plurality of display pixels are arranged. When the number of effective scanning lines in one vertical scanning period of the video signal is smaller than the number of corresponding horizontal pixel lines, non-display data is vertically transferred to at least one horizontal pixel line not corresponding to the effective scanning line of the video signal. The display is performed in the first period to which the scanning period belongs, and non-display data is transferred to the other horizontal pixel line not corresponding to the effective scanning line of the video signal to which the other vertical scanning period belongs to another vertical scanning period different from the vertical layer scanning period. It is characterized by displaying in two periods. Furthermore, the display device driving method of the present invention is a display device driving method for forming a display image based on video data of a video signal on a display panel in which a plurality of horizontal pixel lines including a plurality of display pixels are arranged. When the number of video data in one horizontal scanning period of the video signal is smaller than the number of display pixels of one horizontal pixel line, non-display data is displayed in the first period on at least one display pixel that does not correspond to the video data. The non-display data is displayed in a second period different from the first period on the other display pixels not corresponding to the video data.

  According to the display device of the present invention, the scanning circuit unit or the video signal supply circuit unit is configured by the logic circuit unit that is smaller than the number of scanning lines or the number of signal lines that are selectively output based on the input numerical signal from the selection control circuit unit. Therefore, even when the display device has a higher definition, it is possible to suppress the increase in the number of wirings for transmitting numerical signals and the number of logic circuit units, and to manufacture with high manufacturing yield. In addition, since the number of logic circuit sections is small, the operating frequency of the numerical signal can be kept low, and a margin can be given to the element design.

  According to the driving method of the display device of the present invention, the number of horizontal pixel lines of the display panel and the number of effective scanning lines of the video signal, or the number of display pixels constituting one horizontal pixel line and the number of video data of the video signal are obtained. Even if they are different, for example, non-display data is displayed in the first period on at least one horizontal pixel line that does not correspond to the effective scanning line of the video signal, and other horizontal lines that do not correspond to the effective scanning line of the video signal. Non-display data is displayed on the pixel line in a second period different from the first period, or non-display data is displayed in the first period on at least one display pixel that does not correspond to video data, and another display that does not correspond to video data By displaying non-display data on the pixels in a second period different from the first period, non-display data can be displayed in the non-display area.

  By configuring the scanning circuit unit or video signal supply circuit unit of the display device with a logic circuit unit that selectively outputs based on the input numerical signal from the selection control circuit unit, the above driving method can be achieved with a simple configuration. It can be easily realized.

  A liquid crystal projector according to an embodiment of the present invention will be described below with reference to the drawings.

  FIG. 1 schematically shows the configuration of the liquid crystal projector 1. The liquid crystal projector 1 includes a light source 2, a reflecting mirror 3 that reflects light source light emitted on the back surface of the light source 2, a first aperture mask 4 that restricts light source light from the light source 2, and light source light that has passed through the aperture mask 4. The first dichroic mirror 7 that reflects only the red component R contained in the light source light that has passed through the light source optical lens 5 and transmits the green and blue components G and B. A red component R reflected by one dichroic mirror 7 is guided to the liquid crystal display device 101 for red display, and only green component G is reflected from the transmitted light that has passed through the first dichroic mirror 7 and green. The second dichroic mirror 9 and the liquid crystal display device 10 which are guided to the liquid crystal display device 501 for display and transmit the blue component B to the liquid crystal display device 601 for blue display. The third dichroic mirror 13 for combining the image transmitted through the liquid crystal display device 501 with the image transmitted through the liquid crystal display device 501 and the second image for combining the image transmitted through the liquid crystal display device 601 with the image transmitted through the liquid crystal display device 101. A reflection mirror 15 and a fourth dichroic mirror 17 are provided. The synthesized image is condensed by the condenser lens 19, passes through the opening of the second aperture mask 21, and then projected onto the screen 41 by the projection lens 31.

  FIG. 2 schematically shows the configuration of the liquid crystal display device 101 shown in FIG. Since the other liquid crystal display devices 501 and 601 have substantially the same structure as the liquid crystal display device 101, their description is omitted.

  The liquid crystal display device 101 includes a pair of electrode substrates 111 and 191 and a polymer-dispersed nematic liquid crystal layer 103 held therebetween. The liquid crystal layer 103 is composed of a polymer resin material and a nematic liquid crystal having positive dielectric anisotropy dispersed in the polymer resin material.

  One electrode substrate 111 is disposed on the quartz transparent insulating substrate on the left and right sides of the liquid crystal layer 103 and a pair of redundant scanning line drive circuits 201 a and 201 b and on the upper and lower sides of the liquid crystal layer 103. .. Of the redundant video signal line drive circuits 301a and 301b and 1035 scan lines 161 (Yj: j = 1, 2,...) Connected to the respective scan line drive circuits 201a and 201b. , 1035) 1840 video signal lines 163 (Xi: i = 1, 2,..., 1840) connected to one set of video signal line drive circuits 301a and 301b. A thin film transistor (hereinafter abbreviated as TFT) 165 made of polycrystalline silicon, whose gate is electrically connected to the scanning line 161 and whose drain is electrically connected to the video signal line 163, is electrically connected to the source of the TFT 165. A pixel electrode 167 made of ITO (Indium-Tin-Oxide), and an auxiliary capacitance line 169 arranged substantially in parallel with the scanning line 161 to form an auxiliary capacitance CS electrically connected to the pixel electrode 167 in parallel. They are arranged in one piece.

  The other electrode substrate 191 is configured by disposing a common electrode 195 made of ITO on a transparent insulating substrate.

  Each of the liquid crystal display devices 101, 501, and 601 has 1840 display pixels arranged in the direction of the scanning line 161, which is composed of the polymer dispersed nematic liquid crystal layer 103 held between the pixel electrode 167 and the common electrode 195. 1035 horizontal pixel lines configured as described above are provided, and the same applies to the display image that is transmitted through the liquid crystal display devices 101, 501, and 601 and projected.

  Next, one scanning line driving circuit 201a will be described with reference to FIG. In this embodiment, the pair of scanning line driving circuits 201a and 201b has substantially the same structure, and therefore the description of the other scanning line driving circuit 201b is omitted.

  The scanning line driving circuit 201a is connected to a numerical signal conversion circuit unit 211a, a scanning selection circuit unit 221a connected to the numerical signal conversion circuit unit 211a, a buffer amplifier 231a connected to the scanning selection circuit unit 221a, and a buffer amplifier 231a. Output control circuit unit 241a.

  The numerical signal conversion circuit unit 211a includes 10 non-inverted signal lines for supplying 10-bit digital numerical signals SA1-SA10 and 10 digital numerical signals SA11-SA20 obtained by inverting these digital numerical signals SA1-SA10. Twenty numerical signal lines 212a composed of inverted signal lines, a plurality of stages of logic circuit sections 215a each including a set of three-input NOR gates NO1-NO4, and a non-inverted signal line and an inverted signal for each common bit A plurality of matrix wiring parts 213a are connected to one of the lines selected from the three-input NOR gates NO1-NO4 of the corresponding logic circuit part 215a.

The non-inverted signal lines and the inverted signal lines for 10 bits are selected in different combinations for each matrix wiring portion 213a. For example, in the first-stage matrix wiring part 213a, the 10th bit (2 ⁹ ) non-inverted signal line, the 9th bit (2 ⁸ ) non-inverted signal line, and the 8th bit (2 ⁷ ) non-inverted signal line 7th bit (2 ⁶ ) non-inverted signal line, 6th bit (2 ⁵ ) non-inverted signal line, 5th bit (2 ⁴ ) non-inverted signal line, 4th bit (2 ³ ) non-inverted signal The non-inverted signal line of the third bit (2 ² ), the non-inverted signal line of the second bit (2 ¹ ), and the inverted signal line of the first bit (2 ⁰ ) are selected. In the second-stage matrix wiring section 213a, the 10th bit (2 ⁹ ) non-inverted signal line, the 9th bit (2 ⁸ ) non-inverted signal line, the 8th bit (2 ⁷ ) non-inverted signal line, 7th bit (2 ⁶ ) non-inverted signal line, 6th bit (2 ⁵ ) non-inverted signal line, 5th bit (2 ⁴ ) non-inverted signal line, 4th bit (2 ³ ) non-inverted signal line The third bit (2 ² ) non-inverted signal line, the second bit (2 ¹ ) inverted signal line, and the first bit (2 ⁰ ) non-inverted signal line are selected.

  The number of stages of the logic circuit unit 215a is configured to be 518, which is smaller than 1035 which is the number of scanning lines 161 (Yj: j = 1, 2,..., 1035), for example. Each stage of the logic circuit is composed of four 3-input NOR gates NO1-NO4, two 2-input NAND gates NA1 and NA2, and one 2-input NOR gate NO5. The output terminals of the NOR gates NO1 and NO2 are connected to the first and second input terminals of the NAND gate NA1, respectively. The output terminals of the NOR gates NO3 and NO4 are connected to the first and second input terminals of the NAND gate NA2, respectively. The output terminals of NAND gates NA1 and NA2 are connected to the first and second input terminals of NOR gate NO5, respectively.

  The output signal of the NOR gate NO5 of each logic circuit portion 215a is led to the scan selection circuit portion 221a. In the scan selection circuit unit 221a, the output signal of the NOR gate NO5 of each logic circuit unit 215a is divided into three parts, which are respectively supplied to the first input terminals of the first, second and third two-input NAND gates NA3-NA5. Supplied. The second input terminals of these NAND gates NA3-NA5 are connected to three scanning selection lines A, B, and C, respectively. The output terminal of the first NAND gate NA3 is connected to the second input terminal of a 2-input NOR gate NO6 provided in common with the NAND gate NA5 for the logic circuit portion 215a in the previous stage. The output terminal of the second NAND gate NA4 is connected to the first input terminal of the two-input NOR gate NO7. The second input terminal of the NOR gate NO7 is connected to a power supply terminal set to the ON level. The output terminal of the third NAND gate NA5 is connected to the first input terminal of another two-input NOR gate NO6 provided in common with the NAND gate NA3 for the logic circuit portion 215a in the subsequent stage.

  The output signals of the NOR gates NO6 and NO7 are respectively led to the output control circuit unit 241a through the buffer amplifier 231a. These output control circuit units 241a are controlled by output control signals VG0 and VG1 supplied via output control signal lines G0 and G1, respectively. The output control signal VG1 is a signal obtained by inverting the output control signal VG0, and the output control circuit unit 241a determines whether or not to connect the buffer amplifier 231a to the scanning line 161 based on the output control signals VG0 and VG1.

  That is, when an operation failure occurs in one scanning line driving circuit 201a, the electrical connection between the scanning line driving circuit 201a and the scanning line 161 is cut off, and the other scanning is performed without undesired influence of the scanning line driving circuit 201a. It can be operated by the line driver circuit 201b.

  This scanning line driving circuit 201a makes two scanning lines suitable for display of a video signal VS such as television broadcasting as one set, and selectively scans so that combinations of scanning lines selected simultaneously in the odd field period and the even field period are different. A case where two lines are simultaneously driven will be described with reference to FIG.

As shown in FIG. 4A, the numeric signal line 212a is a 10-bit digital numeric signal SA1 that is sequentially added from the counter circuit to {0000000001}, {0000000010}, {0000000011}, etc. every two horizontal scanning periods. -SA10 ^{2 9} signal line of the numerical signal line 212a for each bit, ^{2 8} signal line, ^{2 7} signal line, ^{2 6} signal line, ^{2 5} signal line, ^{2 4} signal line, ^{2 3} signal line, 2 ² signal line, ^{2 1} signal line line is output to the ^{2 0} signal line, through the inverting output circuit from the not shown counter circuit {1111111110}, {1111111101}, 10 are sequentially subtracted {1111111100} and ^{2 9} inverted signal line of the inverted digital numbers signal SA11-SA20 bit numerical signal lines 212a, ^{2 8} inverted signal line, 2 ⁷ inverted signal line, 2 ⁶ inverted signal line, 2 ⁵ inverted signal line, 2 ⁴ inverted signal line, 2 ³ inverted signal line, 2 ² inverted signal line, 2 ¹ inverted signal line, 2 ⁰ inverted signal line . For example, when the digital numbers signal SA1-SA10 which is output from the counter circuit as shown in FIG. 4 (a) is a {0000000001}, the ^{2 9} signal line, ^{2 8} signal line, ^{2 7} signal line, ^{2 6} signal line, 2 ⁵ signal line, ^{2 4} signal line, ^{2 3} signal line, ^{2 2} signal line, to each of ^{2 1} signal line and ^{2 0} inverted signal line is {0} and ^{2 9} inverted signal line, ^{2 8} inverted signal Line, 2 ⁷ inverted signal line, 2 ⁶ inverted signal line, 2 ⁵ inverted signal line, 2 ⁴ inverted signal line, 2 ³ inverted signal line, 2 ² inverted signal line, 2 ¹ inverted signal line and 2 ⁰ signal line {1} is respectively applied to.

Therefore, for the input of {0000000001} as the digital numerical signal SA1-SA10, only the output S1 from the first stage of the numerical signal conversion circuit unit 211a is obtained as shown in FIG. 4B. Similarly, when the digital numbers signal SA1-SA10 from the counter circuit is {0000000010}, the ^{2 9} signal line of the numerical signal lines 212a, ^{2 8} signal line, ^{2 7} signal line, ^{2 6} signal line, 2 {0} is applied to each of the ⁵ signal lines, 2 ⁴ signal lines, 2 ³ signal lines, 2 ² signal lines, 2 ⁰ signal lines and 2 ¹ inverted signal lines, 2 ⁹ inverted signal lines, 2 ⁸ inverted signal lines 2 ⁷ inverted signal line, 2 ⁶ inverted signal line, 2 ⁵ inverted signal line, 2 ⁴ inverted signal line, 2 ³ inverted signal line, 2 ² inverted signal line, 2 ⁰ inverted signal line and 2 ¹ signal line {1} is applied. Therefore, only the output S2 from the second stage of the numerical signal conversion circuit unit 211a is obtained for the input of this digital numerical signal {0000000010}.

  Further, as shown in FIG. 4C, the first scanning selection line A has a selection signal VA that is ON level in the first field period and OFF level in the second field, and the second scanning selection line B has A selection signal VB having a constant ON level is applied, and a selection signal VC having a phase opposite to that of the selection signal VA is applied to the third scanning selection line C.

  Therefore, the output S from the numerical signal conversion circuit section 211a and the selection signals VA, VB, and VC of the scanning selection lines A, B, and C are shown in FIG. The scanning signal VYj is output to the two scanning lines 161 adjacent to each horizontal scanning period. In the first field period and the second field period, the combination of the two scanning lines 161 selected at the same time is different.

  Next, the scanning line driving circuit 201a uses the scanning line driving circuit 201a to selectively scan odd scanning lines in the odd field period and every other even scanning line in the even field period so as to be suitable for display of a video signal VS such as television broadcasting. The case will be described with reference to FIG.

  As described above, when the 10-bit digital numerical signal SA1-SA10 and the 10-bit inverted digital numerical signal SA11-SA20 are input to the numerical signal line 212a as shown in FIG. 5A, the numerical signal conversion circuit The output S shown in FIG. 5B is obtained from each stage of the unit 211a.

  Further, as shown in FIG. 5C, a selection signal VA that takes ON level in the first field period and takes OFF level in the second field period is applied to the second scanning selection line B on the first scanning selection line A. A selection signal VB having a phase opposite to that of the selection signal VA is applied, and a selection signal VC having a constant OFF level is applied to the third scanning selection line C.

  Therefore, each horizontal scan is performed from the scanning line 161 by the output from the numerical signal conversion circuit unit 211a and the selection signals VA, VB, and VC of the scanning selection lines A, B, and C as shown in FIG. A scanning signal VYj is output every other scanning line in the period. The selected scanning line 161 is made different between the first field period and the second field period.

  Further, a case of sequential scanning driving in which all scanning lines are sequentially selected and scanned in each vertical scanning period by the scanning line driving circuit 211a so as to be suitable for display of a video signal VS such as a computer signal will be described with reference to FIG.

  Similarly to the above, when the 10-bit digital numerical signal SA1-SA10 and the 10-bit inverted digital numerical signal SA11-SA20 are input to the numerical signal line 212a as shown in FIG. As shown in FIG. 6B, the output S shown in FIG. 6B is obtained from each stage of the numerical signal conversion circuit unit 211a.

  Further, as shown in FIG. 5C, the selection signal VA for setting one cycle to ½ horizontal scanning period is applied to the first scanning selection line A, and the selection signal VA is opposite in phase to the second scanning selection line B. The selection signal VB is applied to the third scanning selection line C, and a selection signal VC having a constant OFF level is applied to the third scanning selection line C.

  Accordingly, one horizontal scanning is performed from the scanning line 161 by the output from the numerical signal conversion circuit section 211a and the selection signals VA, VB, and VC of the scanning selection lines A, B, and C as shown in FIG. A scanning signal VYj for sequentially selecting and scanning two scanning lines in a period is output.

  As described above, two-line simultaneous driving and interlace driving corresponding to the input digital numerical signals SA1 to SA10 and the selection signals VA, VB, and VC input to the scanning selection lines A, B, and C. In addition, each of the progressive scanning can be selected.

  Next, the video signal line drive circuit 301a of the liquid crystal display device 101 will be described with reference to FIG. In this embodiment, the pair of video signal line drive circuits 301a and 301b has substantially the same structure, and therefore the description of the video signal line drive circuit 301b is omitted.

  The video signal line drive circuit 301a includes a numerical signal conversion circuit unit 311a including a matrix wiring unit 313a and a logic circuit unit 315a, a buffer amplifier 321a connected to the numerical signal conversion circuit unit 311a, and an output connected to the buffer amplifier 321a. The control circuit unit 331a includes a video signal selection circuit unit 341a connected to the output control circuit unit 331a, and a storage capacitor unit 351a connected to the output of the video signal selection circuit unit 341a.

  The numerical signal conversion circuit unit 311a includes nine non-inverted signal lines that supply 9-bit digital numerical signals DA1-DA9 and nine that supply inverted digital numerical signals DA10-DA18 obtained by inverting these digital numerical signals DA1-DA9. 18 numerical signal lines 312a composed of a plurality of inverted signal lines, a plurality of stages of logic circuit portions 315a each including a set of three-input NAND gates NA1-NA3, and a non-inverted signal line and an inverted signal for each common bit A plurality of matrix wiring portions 313a are connected to one selected from the signal lines and connected to the three-input NAND gates NA1-NA3 of the corresponding logic circuit portion 315a.

The non-inverted signal lines and the inverted signal lines for 9 bits are selected in different combinations for each matrix wiring portion 313a. For example, in the first-stage matrix wiring section 313a, the ninth bit (2 ⁸ ) inverted signal line, the eighth bit (2 ⁷ ) inverted signal line, the seventh bit (2 ⁶ ) inverted signal line, Inverted signal line of bit (2 ⁵ ), inverted signal line of fifth bit (2 ⁴ ), inverted signal line of fourth bit (2 ³ ), inverted signal line of third bit (2 ² ), second bit ( The inverted signal line of 2 ¹ ) and the non-inverted signal line of the first bit (2 ⁰ ) are selected. In the second-stage matrix wiring portion 313a, although not shown, the ninth bit (2 ⁸ ) non-inverted signal line, the eighth bit (2 ⁷ ) non-inverted signal line, and the seventh bit (2 ⁶ ) non-inverted Signal line, 6th bit (2 ⁵ ) non-inverted signal line, 5th bit (2 ⁴ ) non-inverted signal line, 4th bit (2 ³ ) non-inverted signal line, 3rd bit (2 ² ) A non-inverted signal line, an inverted signal line of the second bit (2 ¹ ), and a non-inverted signal line of the first bit (2 ⁰ ) are selected.

  Each logic circuit portion 315a includes three 3-input NAND gates NA1-NA3 and one 3-input NOR gate NO1. The output terminals of NAND gates NA1-NA3 are connected to the first, second, and third input terminals of one three-input NOR gate NO1, respectively. The output signal of the NOR gate NO1 of each logic circuit unit 315a is led to the output control circuit unit 331a via the buffer amplifier 321a. In this output control circuit not 331a, the output signal of the NOR gate NO1 of each logic circuit portion 315a is divided into eight and supplied to the first input terminals of the eight 2-input NOR gates NO2 via the buffer amplifier 333a. The The output control line G2 is connected to the second input terminal of these NOR gates NO2.

  The output signals of these NOR gates NO2 are led to the video signal selection circuit unit 341a as output signals of the output control circuit unit 331a, and the eight analog switches 343a provided for video data selection in the video signal selection circuit unit 341a. Input to the gate. The drains of these analog switches 343a are respectively connected to eight video signal input lines 345a, and the video signals VS1,..., VS8 are supplied from the source of the analog switch 343a during the ON period of each output S from the output control circuit unit 331a. It has a mechanism for sampling output. Each video data VD sampled by the video signal selection circuit unit 341a is supplied to the corresponding video signal line 163 via a storage capacitor unit 351a that holds the video data VD.

  The operation of the video signal line driving circuit 301a will be described with reference to FIG.

As shown in FIG. 8A, the 9-bit digital numerical signal DA1-DA9 is sequentially output by a counter circuit or the like (not shown) at the timing of selectively outputting the video data VD to the video signal line 163 corresponding to each display pixel. Is added. In each timing, ^{2 8} signal line of the digital numbers signal DA1-DA9 numerical signal lines 312a, ^{2 7} signal line, ^{2 6} signal line, ^{2 5} signal line, ^{2 4} signal line, ^{2 3} signal line, ^{2 2} signal line, ^{2 1} signal line, ^{2 0} when output to the signal line by a counter circuit or the like (not shown), a digital numeric signal DA1-DA9 inverted signal DA10-DA18 are not shown inverted output numbers from the circuit the signal line 312a ^{2 9} inverted signal line of the ^{two 8} inverted signal line, ^{2 7} inverted signal line, ^{2 6} inverted signal line, ^{2 5} inverted signal line, ^{2 4} inverted signal line, ^{2 3} inverted signal line, ^{2 2} inverted signal line 2 ¹ inverted signal line, 2 ⁰ inverted signal line.

For example, when the digital numerical signal DA1-DA9 from the counter circuit is {000000001}, 2 ⁸ signal lines, 2 ⁷ signal lines, 2 ⁶ signal lines, 2 ⁵ signal lines, 2 ⁴ signal lines, 2 ³ signal lines, 2 ² signal line, ^{2 1} signal line and the ^{2 0} inverted signal line is {0} and ^{2 9} inverted signal line, ^{2 8} inverted signal line, ^{2 7} inverted signal line, ^{2 6} inverted signal line, ^{2 5} inverted signal line, ^{2 4} inverted signal line, ^{2 3} inverted signal line, ^{2 2} inverted signal line, ^{2 1} inverted signal line, and the ^{2 0} signal line is {1} are respectively applied. Therefore, when the digital numerical signal DA1-DA9 is {0000000001}, the output S1 is obtained from the first stage of the output control circuit section 331a as shown in FIG.

  Further, the video signals VS1,..., VS8 as shown in FIG.

  Therefore, while the output S1 from the first stage of the output control circuit section 331a is ON, the first to eighth video data selection analog switches 343a are simultaneously selected, and the first to eighth video signal lines are selected. Each video data VD1,..., VD8 is output to 163.

  In addition, while the output S2 from the second stage of the output control circuit section 331a is ON, the ninth to sixteenth video data selection analog switches 343a are simultaneously selected, and the ninth to sixteenth video signal lines are selected. Each video data VD9,..., VD16 is output to 163.

  In this way, video data VD1,..., VD1840 are output to 1840 video signal lines 163 for each horizontal scanning period.

  As described above, during the period when the scanning line 161 is selected, the video data VD output to the video signal line 163 is written to the pixel electrode 167 via the TFT 165, and between the pixel electrode 167 and the common electrode 195. The potential difference is held for a period until the next scanning line 161 is selected and displayed.

  Next, the number of effective scanning lines of the video signal VS and the number of video data VD are smaller than the number of horizontal pixel lines or the number of display pixels constituting one horizontal pixel line of the liquid crystal display device 101. For example, as shown in FIG. A case will be described in which a display in which the number of effective video data VD of the signal VS is 1024 per effective scanning line and the number of effective scanning lines is 768 is realized.

  Here, for example, as shown in FIG. 9, non-display areas 901 and 903 each including 140 and 127 horizontal pixel lines are provided at the top and bottom of the display screen, and non-display areas each including 408 display pixels are provided on the left and right. A case will be described in which the areas 905 and 907 are provided and the display area 700 is provided and displayed in the approximate center of the display screen by, for example, sequential driving shown in FIG.

  The scanning line driving circuit 201a shown in FIG. 2 is based on the 10-bit digital numerical signal SA1-SA10 from the ROM that sequentially increases from {0001000111} to {0111000110} in one vertical scanning period in the first field period. , The 141st to 908th horizontal pixel lines are sequentially selected, and 10 bits from the ROM are sequentially increased from {0000000001} to {000010110} in the first vertical blanking period in the first field period. The first to 28 horizontal pixel lines are sequentially scanned as the first block 701 based on the digital numerical signals SA1 to SA10, and from {0000111011} in the fifth vertical blanking period in the subsequent fifth field period. 10 bits from ROM increasing sequentially to {0001000110} The 113th to 140th horizontal pixel lines are sequentially scanned as the fifth block 705 based on the digital numerical signal SA1-SA10, and {0111000111} to {0111010100} in the sixth vertical blanking period in the sixth field period. On the basis of the 10-bit digital numerical signal SA1-SA10 from the ROM which sequentially increases until the sixth block 706, the 909th to 936th horizontal pixel lines are sequentially scanned, and the 10th vertical period during the subsequent 10th field period. During the blanking period, the 1021 to 1035 horizontal pixel lines are sequentially scanned as the tenth block 710 based on the 10-bit digital numerical signal SA1-SA10 from the ROM that sequentially increases from {0111111111} to {1000000110}.

  The video input line 345a of the video signal line driving circuit 301a includes the 1024 video data VD corresponding to the 409th to 1432st display pixels during the horizontal scanning period, and the horizontal blanking period during the horizontal blanking period. A video signal including non-display data VB corresponding to the 1st to 408th non-display pixels and non-display data VB corresponding to the 1433th to 1840th non-display pixels is input.

  Further, non-display data VB corresponding to 1840 display pixels is input to the video input line 345a in each vertical blanking period of each field period.

  Accordingly, the 136th to 903th horizontal pixel lines are sequentially selected in one vertical scanning period, and the non-display data VB is supplied to the first to 28 horizontal pixel lines as the first block 701 within the vertical blanking period. Is displayed. This is sequentially repeated, and the non-display data VB is displayed in all of the non-display areas 901 and 903 divided into 10 blocks.

  By the way, it is temporal to transfer the non-display data VB corresponding to the first to 408 non-display pixels and the non-display data VB corresponding to the 1433 to 1840 non-display pixels within each horizontal blanking period. It may be difficult. In such a case, the non-display data VB corresponding to the first to 408 non-display pixels and the non-display data VB corresponding to the 1433 to 1840 non-display pixels are all displayed in the same horizontal scanning period. Instead of displaying, a plurality of blocks may be displayed.

  For example, in one vertical scanning period in the first field period, the non-display data VB corresponding to the first to 80th non-display pixels is transferred and displayed in each horizontal blanking period, and one vertical in the second field period. The non-display data VB corresponding to the 81st to 160th non-display pixels is transferred and displayed in each horizontal blanking period in the scanning period, and thereafter, from the 1752th to 1840th in one vertical scanning period in the 11th field period. The non-display areas 901 and 903 may be formed by transferring and displaying the non-display data VB corresponding to the non-display pixels within each horizontal blanking period.

  In addition, the non-display pixels corresponding to the non-display data in each field period and each horizontal pixel column need not be equal as described above, and may be different from each other. For example, during the first field period, for the 141st to 142nd horizontal pixel lines, the 1st to 80th non-display pixels display non-display data VB, and the 143rd to 144th horizontal pixel lines. The non-display data VB is displayed on the 81st to 146th non-display pixels, and the non-display data VB is displayed on the 161st to 240th non-display pixels for the 145th to 142nd horizontal pixel lines. As described above, the non-display area may be divided into a plurality of blocks, and the non-display pixels for displaying the non-display data may be different for each horizontal pixel line. In this way, for example, regarding the 143rd to 144th horizontal pixel lines, the non-display data VB corresponding to the 1st to 80th non-display pixels is the 141st to 142nd horizontal pixel lines. Is stored in the storage capacitor portion 351a during display, and therefore, the non-display data VB corresponding to the first to 80th non-display pixels need not be transferred, and the first to 80th non-display pixels are not transferred. Display data VB is displayed, and non-display data VB is displayed on the 81st to 160th non-display pixels.

  By configuring the liquid crystal display device 101 as described above, the display area 700 can be easily displayed on the display screen by controlling the digital numerical signals input to the scanning line driving circuits 201a and 201b and the video signal driving circuits 301a and 301b, respectively. It can arrange | position to the approximate center of.

  In addition, regarding the video signal drive circuits 301a and 301b, by using the memory function of the storage capacitor 351a, even if there are many non-display pixels in each horizontal pixel line, no special frame memory or the like is required. A display region can be formed.

  Further, the 136th to 903th horizontal pixel lines are selected in one vertical scanning period, and the first, 11, 21,... Horizontal pixel lines as the first block in the first vertical blanking period, the second .., 10th horizontal pixel line as the second block in the vertical blanking period, 3rd, 13th, 23rd,... Horizontal pixel lines as the third block in the third vertical blanking period,. The digital numerical signals SA1 to SA20 may be selected so that the tenth block, the tenth, twenty, thirty,... Horizontal pixel lines are sequentially selected during the vertical blanking period.

  By dividing and driving the non-display areas 901 and 903 in this way, the horizontal pixel lines constituting the non-display areas 901 and 903 selected in one vertical blanking period are displayed in the display screen as compared with the above-described method. Since it is uniformly distributed, even if the number of blocks dividing the non-display areas 901 and 903 is increased, a good display image free from flicker can be realized.

  In this embodiment, the non-display areas 901 and 903 in the vertical scanning direction are divided into 10 blocks, and non-display data (VB) is written to the horizontal pixel lines of the non-display areas 901 and 903 in 10 vertical blanking periods. Although configured as described above, it goes without saying that all the horizontal pixel lines constituting the non-display areas 901 and 903 may be selected at one time.

  The case where non-display data (VB) is written in one horizontal pixel line is the same as described above.

  As described above, when the number of effective scanning lines of the video signal VS and the number of video data VD are smaller than the number of horizontal pixel lines of the liquid crystal display device 101 or the number of display pixels constituting one horizontal pixel line, the liquid crystal projector shown in FIG. 1, a display area 700 and non-display areas 901, 903, 905, and 907 are displayed on the screen 41, for example, as shown in FIG. 9.

  In such a case, the enlargement ratio of the projection lens 31 of the liquid crystal projector 1 is automatically detected as the number of effective scanning lines of the video signal VS or the number of reductions in the number of effective video data VD. If the enlargement ratio of the projection lens 31 is increased, a display area 700 having a substantially constant size is always displayed on the screen 41 even if the number of effective scanning lines or the number of effective image data VD of the image signal VS varies. Composed.

  As described above, according to the liquid crystal display device 101 of this embodiment, each scanning line 161 and each analog switch 343a for selecting video data are selected corresponding to the input digital numerical signals SA1-SA20, DA1-DA18. Is done. Therefore, according to the liquid crystal display device 101 of this embodiment, not only the scanning line 161 and the video data selection analog switch 343a are sequentially selected as described above, but also the digital numerical values applied to the numerical signal lines 212a and 312a. An arbitrary scanning line 161 and an analog switch 343a for selecting video data can be selected by the signals SA1-SA20 and DA1-DA18.

  Thus, according to the liquid crystal projector 1 of this embodiment, even if the number of horizontal pixel lines and the number of effective scanning lines of the video signal VS are different, the number of display pixels constituting one horizontal pixel line and one effective Even when the number of video data VD constituting the scanning line is different, the display area and the non-display area can be configured at arbitrary positions in the display screen.

  Furthermore, according to the liquid crystal projector 1 of this embodiment, even when the number of horizontal pixel lines and the number of effective scanning lines of the video signal VS are greatly different, the number of display pixels constituting one horizontal pixel line and one effective Even when the number of video data VD constituting the scanning line is greatly different, the horizontal pixel line in the non-display area is divided into a plurality of vertical blanking periods for scanning, or a plurality of display pixels in the non-display area are scanned. By applying the non-display data VB by dividing it into the horizontal blanking period of the vertical scanning period, the display area and the non-display area can be configured at arbitrary positions in the display screen.

  Therefore, in this embodiment, as described above, the example in which the display area is arranged at the approximate center of the display screen is shown, but the present invention is not limited to this, and the digital numerical signals SA1-SA10, DA1-DA9. By controlling this, it is possible to arrange a display area at an arbitrary position, or to support a multi-screen or the like.

  Further, depending on how the digital numerical signals SA1-SA10, DA1-DA9 are increased or decreased, the scanning lines 161 and the analog switches 343a for selecting video data can be selected in an arbitrary order. For example, as described above, the liquid crystal projector 1 of this embodiment is configured by three liquid crystal display devices 101, 501, and 601 that are substantially the same, but as can be seen from FIG. Since the number of inversions is an odd number, the selection order of the analog switch 343a for selecting video data or the selection order of the scanning lines 161 is different from the other liquid crystal display devices 101 and 601. However, according to this embodiment, it is possible to use the three common liquid crystal display devices 101, 501, and 601 only by connecting to a counter circuit that outputs a digital numerical signal that is sequentially subtracted from only the digital numerical signal input to the liquid crystal display device 501. It becomes possible. In such a case, the display pixel shape of each of the liquid crystal display devices 101, 501, and 601 is preferably configured so that the shapes are substantially equal even when the transmitted light is inverted.

  In addition, according to this embodiment, since the display image can be mirror-inverted, the display image from the liquid crystal projector 1 is displayed on a transmissive screen and the reflective screen is displayed. The case can be easily switched by setting the digital numerical signals SA1-SA10 and DA1-DA9 from a counter or ROM.

  In this embodiment, the input numerical signals SA1-SA20 for operating the scanning line driving circuit 201a are configured with 10 bits, and the input numerical signals DA1-DA18 for operating the video signal line driving circuit 301a are configured with 9 bits. For example, in the scanning line driving circuit 201a, the maximum number of scanning lines 161 that can be controlled by the combination of connections in the matrix wiring portion 213a is 1024.

  However, in this embodiment, a scanning selection circuit unit 221a is provided between the matrix wiring unit 213a and each scanning line 161, thereby enabling various types of driving and unnecessary input numerical signal (SA1-SA20). 1035 scanning lines 161 can be controlled without increasing the number of bits.

  Of course, this may be dealt with by increasing the number of bits of the input numerical signal, and conversely, when the number of video signal lines 163 or scanning lines 161 is small, the number of bits of the input numerical signal can be reduced.

  In the above embodiment, as shown in FIG. 2, the troublesome connection is eliminated by integrally forming the scanning line driving circuits 201a and 201b and the video signal line driving circuits 301a and 301b on the substrate 113. However, an external circuit using an individual IC or the like may be used.

  In the liquid crystal display device 101 of this embodiment, either one of the scanning line driving circuits 201a and 201b and the video signal line driving circuits 301a and 301b, or one of the pair of driving circuits 201a, 201b, 301a, and 301b is conventionally used. As shown in FIG. 5, the shift register may be composed of a plurality of stages, or the connection form of the numerical signal lines 212a and the logic circuit part 215a in the matrix wiring part 213a may be different between the scanning line drive circuits 201a and 201b on both sides. good.

  In this embodiment, the case where a polymer dispersed liquid crystal capable of significantly increasing the light utilization efficiency is used because a polarizing plate is unnecessary is not limited thereto. Various conventionally known liquid crystal materials can be used.

  For example, as each of the liquid crystal display devices 101, 501, and 601, although not shown, nematic liquid crystal having positive dielectric anisotropy is interposed between the pixel electrode and the common electrode through an alignment film so that liquid crystal molecules are twisted by 90 ° between the electrodes. A polarizing plate may be arranged on the outer surface of the substrate so that the polarization axis coincides with the alignment axis.

  In this way, as shown in FIG. 10, the transmittance is maximized when the potential difference between the pixel electrode and the common electrode is 0 V, and the transmittance decreases as the potential difference increases. Liquid crystal display devices 101, 501, and 601 are configured.

  According to the liquid crystal projector 1 using the normally white mode liquid crystal display devices 101, 501, and 601 configured as described above, when the non-display data VB is written in the non-display areas 901 and 903, 905, and 907 shown in FIG. As shown in FIG. 5, the non-display areas 901 and 903, 905, 907 are obtained by selecting and using the driving voltage of the potential difference area 63 outside the potential difference area 61 between the pixel electrode and the common electrode that can be taken in the normal display state. Even when the display is divided into a plurality of blocks and the display is completed in a plurality of periods, good black display can be secured.

  Further, in this embodiment, the liquid crystal projector 1 composed of the three liquid crystal display devices 101, 501, and 601 is taken as an example, but it is needless to say that the liquid crystal display device may be composed of one liquid crystal display device. This method may be adopted, or a direct-view type liquid crystal display device may be used.

  Further, in this embodiment, the case where a liquid crystal pixel is used as the display element is shown. However, a display element whose light transmittance or light reflectance changes according to the driving voltage, or a display element whose light emission amount changes according to the driving voltage. If the display device uses an element capable of modulating light such as the present invention, the present invention works effectively.

  Furthermore, this embodiment may be modified so that a predetermined digital numerical signal, for example, all bits “0”, which are not output by each numerical signal conversion circuit, is inserted between the digital numerical signal sequences. Since the predetermined digital numerical signal can prevent the output pulses from overlapping, the display device can be operated stably.

  According to the display device of the present invention, the scanning circuit unit or the video signal supply circuit unit is configured by the logic circuit unit that is smaller than the number of scanning lines or the number of signal lines that are selectively output based on the input numerical signal from the selection control circuit unit. Therefore, even when the display device has a higher definition, it is possible to suppress the increase in the number of wirings for transmitting numerical signals and the number of logic circuit units, and to manufacture with high manufacturing yield.

  According to the driving method of the display device of the present invention, the number of horizontal pixel lines of the display panel and the number of effective scanning lines of the video signal, or the number of display pixels constituting one horizontal pixel line and the number of video data of the video signal are obtained. Even if they are different, for example, non-display data is displayed in at least one horizontal pixel line that does not correspond to the effective scanning line of the video signal in the first period, and other horizontal lines that do not correspond to the effective scanning line of the video signal. Non-display data is displayed in a pixel line in a second period different from the first period, or non-display data is displayed in at least one display pixel that does not correspond to video data in the first period, and other display that does not correspond to video data By displaying non-display data on the pixels in a second period different from the first period, non-display data can be displayed in the non-display area.

  In particular, by configuring the scanning circuit unit or the video signal supply circuit unit of the display device with a logic circuit unit that selectively outputs based on an input numerical signal from the selection control circuit unit, the above driving method can be easily performed with a simple circuit configuration. Can be realized.

1 is a diagram schematically showing a configuration of a liquid crystal projector according to an embodiment of the present invention. It is a figure which shows schematically the structure of the liquid crystal display device shown in FIG. FIG. 3 is a diagram schematically showing a configuration of a scanning line driving circuit shown in FIG. 2. FIG. 3 is a diagram showing one driving waveform of the scanning line driving circuit shown in FIG. 2. FIG. 3 is a diagram showing another driving waveform of the scanning line driving circuit shown in FIG. 2. FIG. 3 is a diagram showing another driving waveform of the scanning line driving circuit shown in FIG. 2. FIG. 3 is a diagram schematically showing a configuration of a video signal line driving circuit shown in FIG. 2. FIG. 3 is a diagram showing one driving waveform of the video signal line driving circuit shown in FIG. 2. It is a figure which shows an example of the image displayed by the liquid crystal projector shown in FIG. It is a figure which shows the voltage-light transmittance characteristic showing the relationship between the voltage between the pixel electrode of the liquid crystal display device shown in FIG. 1, and a common electrode, and the transmittance | permeability.

Explanation of symbols

  Reference numeral 161: scanning line, 163 ... signal line, 165 ... thin film transistor, 101 ... display panel, 201a ... scanning line driving circuit, 213a ... matrix wiring part, 215a ... logic circuit part, 221a ... scanning selection circuit part

Claims (8)

A plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, a plurality of pixels respectively disposed in the vicinity of intersection positions of the plurality of scanning lines and the plurality of signal lines, and each A display panel including a plurality of switch elements for supplying video data from the corresponding signal line to the corresponding pixel in response to a scanning signal from the corresponding scanning line; and a scanning circuit unit for supplying the scanning signal to the plurality of scanning lines. The scanning circuit section is provided for a numerical signal input wiring group for inputting a numerical signal that changes sequentially, and for a predetermined number of scanning lines each of two or more, and different numerical signals from the numerical signal input wiring group a plurality of logic circuit for outputting a response to the output signal, respectively, and an output distributing means for distributing the output signal to a corresponding scan line of said predetermined number as said scanning signal to each output signal from each logic circuit Seen, the output distribution means the constant number corresponding scanning lines sequentially selected by one by one and outputs the scanning signals sequentially selected one by two corresponding scan lines of the certain number in the second mode in the first mode The display device is configured to output the scanning signal .
The output distribution means specifies a plurality of selection lines for inputting a selection signal for the predetermined number of scanning lines and an output signal from one of the plurality of logic circuit units by a selection signal from the plurality of selection lines. The display device according to claim 1, further comprising: a plurality of selection circuits that output to the scanning lines. The video signal supply circuit unit further supplies video data to the plurality of signal lines, and the video signal supply circuit unit inputs video data for a predetermined number of signal lines of 2 or more as video signals. Signal input lines, a plurality of sets of analog switch means for extracting video data from the fixed number of video signal input lines and outputting the data to the fixed number of signal lines corresponding to the plurality of signal lines, and numerical values that change sequentially A second numerical signal input wiring group for inputting a signal, a plurality of second logic circuit units for outputting an output signal in response to different numerical signals from the second numerical signal input wiring group, and each second logic The display device according to claim 1, further comprising second output distribution means for distributing an output signal from the circuit unit as a drive signal to a corresponding set of analog switch means. The display device according to claim 1, wherein the switch element and the scanning circuit unit are integrally formed on one substrate of the display panel. 4. The display device according to claim 3, wherein the switch element, the scanning circuit unit, and the video signal supply circuit unit are integrally formed on one substrate of the display panel. The numerical signal is at least one that does not correspond to an effective scanning line of the video signal when the number of effective scanning lines in one vertical scanning period of the video signal is smaller than the number of horizontal pixel lines that match the number of rows of the plurality of pixels. Non-display data is displayed on the horizontal pixel line in the first period, and non-display data is displayed on the other horizontal pixel line not corresponding to the effective scanning line of the video signal in a second period different from the first period. The display device according to claim 1, wherein the display device is controlled. The display device according to claim 1, further comprising a projection optical system that projects a display image displayed on the display panel onto a screen. When the display image on the screen is smaller in the number of effective scanning lines in one vertical scanning period of the video signal than the number of horizontal pixel lines matching the number of rows of the plurality of pixels, the video signal in one vertical scanning period 8. The display device according to claim 7, further comprising adjustment means for adjusting the projection optical system so that the number of effective scanning lines is substantially equal to the number of horizontal pixel lines.

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