JP3733970B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention belongs to the technical field of an active matrix drive type electro-optical device and a method for manufacturing the same, and particularly to the technical field of an electro-optical device including a storage capacitor electrode for adding a storage capacitor.

  2. Description of the Related Art Conventionally, in an active matrix driving type electro-optical device using TFT driving, a large number of TFTs are provided on a TFT array substrate corresponding to a large number of scanning lines and data lines arranged in the vertical and horizontal directions and their intersections. Yes. In each TFT, the gate electrode is connected to the scanning line, the source region of the semiconductor layer is connected to the data line, and the drain region of the semiconductor layer is connected to the pixel electrode. Here, in particular, the pixel electrode is provided on various layers constituting the TFT and wiring and on the interlayer insulating film for insulating the pixel electrode from each other. Therefore, the pixel electrode is interposed through a contact hole opened in the interlayer insulating film. Connected to the drain region of the semiconductor layer constituting the TFT. When the scanning signal is supplied to the gate electrode of the TFT via the scanning line, the TFT is turned on, and the image signal supplied to the source region of the semiconductor layer via the data line is supplied to the source-drain of the TFT. It is supplied to the pixel electrode through the gap. Such an image signal is supplied for only a very short time for each pixel electrode through each TFT. For this reason, in order to hold the voltage of the image signal supplied through the TFT that is turned on for only a very short time for a much longer time than the time that is turned on, each pixel electrode has In general, a storage capacitor is formed in parallel with a liquid crystal capacitor. On the other hand, in this type of electro-optical device, a source region and a drain region of a pixel switching TFT and a channel region therebetween are formed from a semiconductor layer formed on the TFT array substrate. The pixel electrode needs to be connected to the drain region of the semiconductor layer through wirings such as a scanning line, a capacitor line, and a data line having a laminated structure and a plurality of interlayer insulating films for electrically insulating them from each other. There is.

  In this type of electro-optical device, there is a strong general demand for high-quality display images. If the resistance of the electrode forming the storage capacitor is high, the image quality cannot be improved.

  The present invention has been made in view of the above problems.

The electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines intersecting with the plurality of scanning lines, and a thin film transistor and a pixel electrode disposed corresponding to the intersection of the scanning lines and the data lines. And a storage capacitor, comprising a light-shielding lower conductive film overlying a channel region of the thin film transistor and the data line, below the semiconductor layer of the thin film transistor, and constituting the storage capacitor One storage capacitor electrode is formed in the same layer as the gate electrode of the thin film transistor, and is electrically connected to the lower light-shielding film in a region where the data line extends, and the other storage capacitor is formed. the storage capacitor electrode, said to overlap with one storage capacitor electrodes of, consisting drain region of the thin film transistor is formed in a region of extension of the data lines And wherein the door.

  As a result, the resistance of one of the storage capacitor electrodes constituting the storage capacitor can be lowered, and the image quality can be improved. Further, it can function as a redundant wiring.

  In the electro-optical device according to the aspect of the invention, the storage capacitor may be formed along the scanning line.

  In addition, according to one aspect of the electro-optical device of the present invention, the channel region of the thin film transistor may be provided in a region where the data line and the scanning line intersect.

  According to one aspect of the electro-optical device of the present invention, the thin film transistor may be a dual gate or a triple gate.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

(Basic form of electro-optical device)
A configuration of a liquid crystal device which is a basic form of an electro-optical device according to the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements and wirings in a plurality of pixels formed in a matrix that constitutes an image display area of the liquid crystal device, and FIG. 2 is a data line, a scanning line, a pixel electrode, a light shielding film, and the like. 3 is a plan view of a plurality of pixel groups adjacent to each other on the TFT array substrate on which is formed, and FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. In FIG. 3, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing.

  In FIG. 1, a plurality of pixels formed in a matrix form that constitutes an image display area of the liquid crystal device in the present embodiment has a plurality of TFTs 30 for controlling the pixel electrodes 9a formed in a matrix form, and an image signal is transmitted. The supplied data line 6 a is electrically connected to the source of the TFT 30. The pixel electrode 9a and the TFT 30 are arranged corresponding to the intersection of the scanning line 3a and the data line 6a. The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. good. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are held for a certain period with a counter electrode (described later) formed on a counter substrate (described later). . The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. In the normally white mode, incident light cannot pass through the liquid crystal part according to the applied voltage. In the normally black mode, incident light passes through the liquid crystal part according to the applied voltage. Through the liquid crystal device as a whole, light having a contrast according to the image signal is emitted. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the source voltage is applied. Thereby, the holding characteristics are further improved, and a liquid crystal device with a high contrast ratio can be realized.

  In FIG. 2, on the TFT array substrate of the liquid crystal device, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ′) are provided in a matrix, and the vertical and horizontal boundaries of the pixel electrodes 9a are provided. A data line 6a, a scanning line 3a, and a capacitor line 3b are provided along each line. The data line 6a is electrically connected to a source region, which will be described later, of the semiconductor layer 1a made of a polysilicon film or the like through the contact hole 5, and the pixel electrode 9a is a region indicated by an oblique line rising to the right in the drawing. And a drain region described later in the semiconductor layer 1a via the first contact hole 8a and the second contact hole 8b via a conductive layer 80 (hereinafter referred to as a barrier layer) formed as a buffer. Is electrically connected. In addition, the scanning line 3a is disposed so as to face the channel region 1a '(the hatched region in the lower right in the drawing) of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode. As described above, the TFT 30 in which the scanning line 3a is arranged to face the channel region 1a 'as the gate electrode is provided at each intersection of the scanning line 3a and the data line 6a.

  Capacitor line 3b has a main line portion extending substantially linearly along scanning line 3a, and a protruding portion protruding upward (in the drawing, upward) along data line 6a from a location intersecting data line 6a. .

  Further, the first light-shielding film 11a is provided so as to pass through the lower side of the scanning line 3a, the capacitor line 3b, and the TFT 30, respectively, in the region indicated by the thick line in the drawing. More specifically, in FIG. 2, each of the first light shielding films 11a is formed in a stripe shape along the scanning line 3a, and a portion intersecting with the data line 6a is formed wide in the lower part in the figure. These wide portions are provided at positions covering channel regions 1a ′ of the respective TFTs as viewed from the TFT array substrate side.

  Next, as shown in the cross-sectional view of FIG. 3, the liquid crystal device includes a TFT array substrate 10 that constitutes an example of one transparent substrate, and a counter substrate that constitutes an example of the other transparent substrate disposed opposite thereto. 20. The TFT array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive thin film such as an ITO film. The alignment film 16 is made of an organic thin film such as a polyimide thin film.

  On the other hand, a counter electrode 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is made of a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

  The TFT array substrate 10 is provided with a pixel switching TFT 30 that controls switching of each pixel electrode 9a at a position adjacent to each pixel electrode 9a.

  As shown in FIG. 3, the counter substrate 20 may be further provided with a second light-shielding film 23 in the non-opening region of each pixel. For this reason, incident light does not enter the channel region 1a ', the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the counter substrate 20 side. Furthermore, the second light-shielding film 23 has functions of improving contrast and preventing color mixture of color materials when a color filter is formed.

  Between the TFT array substrate 10 and the counter substrate 20, which are configured in this manner and arranged so that the pixel electrode 9 a and the counter electrode 21 face each other, an electro-optical substance is surrounded in a space surrounded by a seal material described later. A liquid crystal which is an example is sealed, and the liquid crystal layer 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the counter substrate 20 around them, and the distance between the two substrates is set to a predetermined value. Gap materials such as glass fibers or glass beads are mixed.

  Further, as shown in FIG. 3, a first light shielding film 11 a is provided between the TFT array substrate 10 and each pixel switching TFT 30 at a position facing each pixel switching TFT 30. The first light-shielding film 11a is preferably made of a single metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pb, which are preferably opaque high melting point metals. If comprised from such a material, the 1st light shielding film 11a will not be destroyed or melt | dissolved by the high temperature process in the formation process of the pixel switching TFT30 performed after the formation process of the 1st light shielding film 11a on the TFT array substrate 10 You can Since the first light shielding film 11a is formed, the channel region 1a ′ and the low concentration source region 1b of the pixel switching TFT 30 in which reflected light (return light) from the TFT array substrate 10 side is easily excited with respect to the light. The incident on the low-concentration drain region 1c can be prevented in advance, and the characteristics of the pixel switching TFT 30 are not changed or deteriorated due to the generation of the photocurrent resulting from this.

  Further, a base insulating film 12 is provided between the first light shielding film 11 a and the plurality of pixel switching TFTs 30. The base insulating film 12 is provided to electrically insulate the semiconductor layer 1a constituting the pixel switching TFT 30 from the first light shielding film 11a. Further, the base insulating film 12 has a function as a base film for the pixel switching TFT 30 by being formed on the entire surface of the TFT array substrate 10. That is, the TFT array substrate 10 has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughness during polishing of the surface of the TFT array substrate 10 and dirt remaining after cleaning. The base insulating film 12 is, for example, a highly insulating glass such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), or BPSG (boron phosphorus silicate glass), a silicon oxide film, or a nitride. It consists of a silicon film or the like. The base insulating film 12 can also prevent the first light shielding film 11a from contaminating the pixel switching TFT 30 and the like.

  In this basic mode, the semiconductor layer 1a extends from the high-concentration drain region 1e to serve as the first storage capacitor electrode 1f, a part of the capacitor line 3b facing the second storage capacitor electrode serves as the second storage capacitor electrode, and the insulating thin film 2 is scanned. A first storage capacitor 70a is configured by forming a first dielectric film extending from a position facing the line 3a and sandwiched between these electrodes. Further, a part of the barrier layer 80 facing the second storage capacitor electrode is used as a third storage capacitor electrode, and a first interlayer insulating film 81 is provided between these electrodes. The first interlayer insulating film 81 also functions as a second dielectric film, and a second storage capacitor 70b is formed. The first storage capacitor 70a and the second storage capacitor 70b are connected in parallel through the first contact hole 8a to form the storage capacitor 70.

  More specifically, the high-concentration drain region 1e of the semiconductor layer 1a extends below the data line 6a and the scanning line 3a to form a pixel switching TFT 30, and also extends along the data line 6a and the scanning line 3a. The first storage capacitor electrode 1f is disposed opposite to the capacitor line 3b via the first dielectric film 2. In particular, since the first dielectric film 2 is nothing but the insulating thin film 2 of the TFT 30 formed on the polysilicon film by high-temperature oxidation or the like, the first dielectric film 2 can be made a thin and high withstand voltage insulating film. It can be configured as a large storage capacity with a relatively small area. Further, since the second dielectric film 81 can also be formed as thin as the insulating thin film 2, the second storage capacitor 70b is utilized by utilizing the area between the adjacent data lines 6a as shown in FIG. Can be configured as a large storage capacity with a relatively small area. Accordingly, the storage capacitor 70 that is three-dimensionally composed of the first storage capacitor 70a and the second storage capacitor 70b has a region under the data line 6a and a region where liquid crystal disclination occurs along the scanning line 3a (that is, By effectively utilizing a space outside the pixel opening region (region where the capacitor line 3b is formed), a large-capacity storage capacitor can be formed with a small area.

  In FIG. 3, the pixel switching TFT 30 has an LDD structure, and includes a scanning line 3a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, the scanning line 3a and the semiconductor layer. Insulating thin film 2 that insulates 1a, data line 6a, low concentration source region 1b and low concentration drain region 1c of semiconductor layer 1a, high concentration source region 1d and high concentration drain region 1e of semiconductor layer 1a. A corresponding one of the plurality of pixel electrodes 9 a is connected to the high concentration drain region 1 e through the barrier layer 80. The low concentration source region 1b and the high concentration source region 1d and the low concentration drain region 1c and the high concentration drain region 1e are predetermined according to whether an n-type or p-type channel is formed in the semiconductor layer 1a, as will be described later. It is formed by doping a concentration of n-type or p-type impurities. An n-type channel TFT has an advantage of high operating speed, and is often used as a pixel switching TFT 30 which is a pixel switching element. In this basic mode, the data line 6a is particularly composed of a light-shielding and conductive thin film such as a low-resistance metal film such as Al or an alloy film such as metal silicide. A second contact hole 5 leading to the high-concentration source region 1d and a contact hole 8b leading to the barrier layer 80 are formed on the barrier layer 80 and the second dielectric film (first interlayer insulating film) 81, respectively. An interlayer insulating film 4 is formed. The data line 6a is electrically connected to the high concentration source region 1d through the contact hole 5 to the high concentration source region 1d. Further, on the data line 6 a and the second interlayer insulating film 4, a third interlayer insulating film 7 in which a contact hole 8 b to the barrier layer 80 is formed is formed. The pixel electrode 9a is electrically connected to the barrier layer 80 through the contact hole 8b, and further connected to the high-concentration drain region 1e through the contact hole 8a via the barrier layer 80. Yes. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured.

  The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurities are not implanted into the low concentration source region 1b and the low concentration drain region 1c, or a part of the scanning line 3a. A self-aligned TFT may be used in which impurities are implanted at a high concentration using the gate electrode as a mask to form high concentration source and drain regions in a self-aligning manner.

  In this basic mode, a single gate structure in which only one gate electrode which is a part of the scanning line 3a of the pixel switching TFT 30 is arranged between the high concentration source region 1d and the high concentration drain region 1e is used. Two or more gate electrodes may be disposed on the substrate. At this time, the same signal is applied to each gate electrode. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source-drain region can be prevented, and the off-time current can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-current can be further reduced and a stable switching element can be obtained.

  As shown in FIGS. 2 and 3, in the liquid crystal device of this basic form, the data lines 6 a and the scanning lines 3 b are three-dimensionally crossed via the second interlayer insulating film 4 on the TFT array substrate 10. Is provided. The barrier layer 80 is interposed between the semiconductor layer 1a and the pixel electrode 9a, and the high-concentration drain region 1e and the pixel electrode 9a are electrically connected via the first contact hole 8a and the second contact hole 8b. Connect.

  Therefore, the diameters of the first contact hole 8a and the second contact hole 8b can be reduced as compared with the case where one contact hole is opened from the pixel electrode 9a to the drain region of the semiconductor layer 1a. That is, in the case of opening one contact hole, the etching accuracy decreases as the contact hole is opened deeper if the selection ratio at the time of etching is low. For example, the penetration in a very thin semiconductor layer 1a of about 50 nm is prevented. In order to achieve this, it is necessary to assemble a process in which dry etching capable of reducing the diameter of the contact hole is stopped halfway and finally the semiconductor layer 1a is opened by wet etching. Alternatively, it becomes necessary to separately provide a polysilicon film for preventing penetration by dry etching.

  On the other hand, in this basic mode, the pixel electrode 9a and the high-concentration drain region 1e may be connected by the two first contact holes 8a and the second contact holes 8b in series. Each contact hole 8b can be opened by dry etching. Alternatively, it is possible to reduce the distance for opening at least by wet etching. However, in order to slightly taper the first contact hole 8a and the second contact hole 8b, respectively, a relatively short wet etching may be performed after the dry etching.

  As described above, according to this basic mode, the diameters of the first contact hole 8a and the second contact hole 8b can be reduced, and the depressions and irregularities formed on the surface of the barrier layer 80 in the first contact hole 8a are also small. As a result, flattening at the portion of the pixel electrode 9a located thereabove is promoted. Furthermore, since the depressions and irregularities formed on the surface of the pixel electrode 9a in the second contact hole 8b can be small, flattening of the pixel electrode 9a is promoted. As a result, the disclination in the liquid crystal layer 50 due to the depressions and irregularities on the surface of the pixel electrode 9a is reduced, and finally, the liquid crystal device can display a high-quality image. For example, if the total film thickness of the second interlayer insulating film 4 and the third interlayer insulating film 7 interposed between the barrier layer 80 and the pixel electrode 9a is suppressed to about several hundred nm, the surface of the pixel electrode 9a described above. The diameter of the second contact hole 8b that directly affects the depressions and irregularities in can be made very small.

  In this basic mode, since the barrier layer 80 is made of a refractory metal film or an alloy film thereof, the etching selectivity between the metal film and the interlayer insulating film is greatly different. There is little possibility of penetration of layer 80.

  In this basic mode, in particular, the first dielectric film 2 and the second dielectric film 81 in the storage capacitor 70 that is three-dimensionally configured with the barrier layer 80 at the center are both data lines that cross three-dimensionally. This is a dielectric film provided in a different layer from the second interlayer insulating film 4 interposed between 6a and the scanning line 3b. Therefore, in order to suppress the parasitic capacitance between the data line 6a and the scanning line 3a causing the voltage drop of the image signal that causes flicker or the like, the barrier layer 80 is provided via a layer different from the second interlayer insulating film 4. In order to add a storage capacitor, in the case of this basic form, it is possible to make the first dielectric film 2 and the second dielectric film 81 thin to the technical limit. As a result, particularly in the second storage capacitor 70b, the capacitance value inversely proportional to the thickness of the second dielectric film 81 can be increased extremely efficiently. In particular, if the insulating switching thin film 2 in the pixel switching TFT 30 is made too thin, a unique phenomenon such as a tunnel effect does not occur. Therefore, on the condition that defects such as film breakage do not occur, for example, about 200 nm or an insulating thin film By forming the very thin second dielectric film 81 having a thickness of 10 nm to 50 nm, which is thinner than 2, a very large capacity second storage capacitor 70a can be formed in a relatively small region. . Accordingly, not only the occurrence of flicker can be suppressed, but also the voltage holding capability can be increased, and thus a high-contrast electro-optical device can be provided.

  According to the experiments and researches of the inventors of the present application, in the above-described conventional technique in which the barrier layer is configured by the same conductive layer as the data line 6a, the barrier layer is used as one electrode of the storage capacitor, and data is stored. Assuming that the interlayer insulating film between the line 6a and the scanning line 3a is used as a dielectric film, in order to prevent the parasitic capacitance between the data line 6a and the scanning line 3a from becoming a problem, a dielectric film (this basic form) The film corresponding to the second interlayer insulating film) needs to have a thickness of about 800 nm. Therefore, in this basic form in the same area, the second storage capacitor 70b having a capacitance value of several times to several tens of times or more can be realized, which is extremely advantageous.

  In addition, another one or a plurality of barrier layers are further laminated between the barrier layer 80 and the pixel electrode 9a via an interlayer insulating film, thereby further utilizing a limited area on the TFT array substrate 10. It is also possible to increase the storage capacity three-dimensionally.

  As described above, the second dielectric film 81 constituting the second storage capacitor 70b may be a silicon oxide film, a silicon nitride film, or the like, or a multilayer film in which a plurality of these films are stacked. The second dielectric is formed by various known techniques (low pressure CVD method, atmospheric pressure CVD method, plasma CVD method, thermal oxidation method, sputtering method, ECR plasma method, remote plasma method, etc.) generally used for forming the insulating thin film 2. The body film 81 can be formed. However, instead of or in addition to the function of adding the storage capacitor by the barrier layer 80, the light shielding function of the barrier layer 80 made of a light shielding film, the layout of the first contact hole 8a and the second contact hole 8b, etc. are emphasized. When the barrier layer 80 and the second dielectric film 81 are formed up to the scanning line 3a, the second dielectric film 81 is thick enough that the parasitic capacitance between the barrier layer 80 and the scanning line 3a does not cause a problem. Preferably formed.

  On the other hand, the film thickness of the barrier layer 80 is preferably about 50 nm to 500 nm, for example. If the thickness is about 50 nm, the possibility of penetrating through the second contact hole 8b in the manufacturing process is low, and if the thickness is about 500 nm, the unevenness of the surface of the pixel electrode 9a is not a problem or relatively easy. This is because flattening is possible.

  Furthermore, in this basic form, the diameter of the first contact hole 8a can be further reduced by thinly forming the first interlayer insulating film (second dielectric film) 81 in this way. The depressions and irregularities of the barrier layer 80 can be further reduced, and the planarization of the pixel electrode 9a located above the depression is further promoted. Therefore, the discnation of the liquid crystal due to the depressions and irregularities in the pixel electrode 9a is reduced, and finally, the liquid crystal device can display a higher quality image.

  In the configuration of the liquid crystal device according to the present basic embodiment, the parasitic capacitance between the wirings of the second interlayer insulating film 4 interposed between the scanning lines 3b and the data lines 6a is not problematic as in the prior art. (For example, a thickness of about 800 nm) is required.

  Particularly in this basic configuration configured as described above, the first light shielding film 11a formed in a striped shape extends under the scanning line 3a and is electrically connected to a constant potential source or a large capacity portion. May be. With this configuration, the potential fluctuation of the first light shielding film 11a does not adversely affect the pixel switching TFT 30 disposed opposite to the first light shielding film 11a. In this case, the constant potential source includes a negative power source supplied to a peripheral circuit for driving the liquid crystal device (for example, a scanning line driving circuit, a data line driving circuit, etc.), a constant potential source such as a positive power source, and a ground power source. And a constant potential source supplied to the counter electrode 21.

  The capacitor line 3b and the scanning line 3a are made of the same polysilicon film, and the first dielectric film 2 of the first storage capacitor 70a and the insulating thin film 2 of the pixel switching TFT 30 are the same high-temperature oxide film or the like. The first storage capacitor electrode 1f and the channel region 1a ′, the low concentration source region 1b, the low concentration drain region 1c, the high concentration source region 1d, the high concentration drain region 1e, etc. of the pixel switching TFT 30 are the same semiconductor. It consists of layer 1a. For this reason, the laminated structure formed on the TFT array substrate 10 can be simplified. Further, in the electro-optical device manufacturing method described later, the capacitor line 3b and the scanning line 3a can be simultaneously formed in the same thin film forming process, and accumulated. The first dielectric film and the insulating thin film 2 of the capacitor 70a can be formed simultaneously.

  Particularly in this basic mode, the barrier layer 80 is made of a conductive light shielding film. Accordingly, each pixel opening region can be at least partially defined by the barrier layer 80. Further, by defining the pixel opening in combination with the barrier layer 80 or the light-shielding film formed on the TFT array substrate 10 of the light-shielding wiring such as the data line 6a, the pixel on the counter substrate 20 side is defined. It is also possible to omit the second light shielding film. The configuration in which the barrier layer 80 is provided as the built-in light shielding film on the TFT array substrate 10 instead of the second light shielding film 23 on the counter substrate 20 is that the pixel aperture ratio is reduced by the positional deviation between the TFT array substrate 10 and the counter substrate 20 in the manufacturing process. This is extremely advantageous in that it does not cause a decrease.

  The second light-shielding film 23 on the counter substrate 20 may be formed to be small (narrow) so as not to define the pixel opening region, mainly for the purpose of suppressing the temperature rise of the liquid crystal device due to incident light. Good. In this case, if the second light shielding film 23 is formed of a material having a high reflectance such as an Al film, the temperature rise can be suppressed more efficiently. If the second light-shielding film 23 is formed to be smaller than the light-shielding region in the TFT array substrate in this way, the pixel opening region does not have to be small due to a slight positional deviation between the two substrates in the manufacturing process.

  The barrier layer 80 made of a light shielding film is made of, for example, a simple metal, an alloy, a metal silicide, or the like containing at least one of opaque high melting point metals Ti, Cr, W, Ta, Mo, and Pb. . If comprised in this way, it can prevent that the barrier layer 80 is destroyed or melt | dissolved by the high temperature process performed after the barrier layer 80 formation process.

  Furthermore, even if these refractory metals come into contact with the ITO film constituting the pixel electrode 9a, the refractory metal is not melted due to the difference in ionization rate. Therefore, the barrier layer 80 is interposed via the second contact hole 8b. In addition, good electrical connection can be established between the pixel electrodes 9a.

  Further, in this basic mode, in particular, the barrier layer 80 made of a light shielding film has a planar shape on the TFT array substrate 10 extending between adjacent data lines 6a along the scanning lines 3a as shown in FIG. Each unit has an island shape. Thereby, the stress by the light shielding film can be relieved. It is also possible to define a part or all of the side along the scanning line 3a of the pixel opening region by the barrier layer 80. Here, when the parasitic capacitance between the scanning line 3a and the barrier layer 80 becomes a problem according to the specific circuit design, the capacitance is not provided on the scanning line 3a without providing the barrier layer 80 as in this basic mode. The side along the scanning line 3a of the pixel opening region on the side where the line 3b and the pixel electrode 9a are adjacent to each other is preferably defined by the barrier layer 80. Alternatively, if the parasitic capacitance between the scanning line 3a and the barrier layer 80 does not matter according to the specific circuit design, the barrier layer 80 is located at a position facing the scanning line 3a via the second dielectric film 81. May also be formed. With this configuration, the light-shielding barrier layer 80 that at least partially covers both the scanning line 3a and the capacitor line 3b defines a larger part of the side along the scanning line 3a in the pixel opening region. It becomes possible. In other words, in the case of such a configuration, it is preferable that the second dielectric film 81 is formed thick enough that the parasitic capacitance of the scanning line 3a and the barrier layer 80 does not become a problem. Alternatively, in order to keep the parasitic capacitance small, it is preferable that the barrier layer 80 covers the scanning line 3a only in an area necessary for defining the pixel opening area.

  The side along the scanning line 3a of the pixel opening region on the side where the scanning line 3a and the pixel electrode 9a are adjacent (lower side in FIG. 2) is defined by the first light shielding film 11a and the second light shielding film 23. That's fine. Further, the side of the pixel opening area along the data line 6 a may be defined by the data line 6 a made of Al or the like, or the first light shielding film 11 a or the second light shielding film 23.

  Further, as shown in FIG. 2, it is preferable that each end of the island-shaped barrier layer 80 in the scanning line 3a direction and the edge of the data line 6a are slightly overlapped when seen in a plan view. With this configuration, it is not necessary to create a gap through which incident light passes between the two, and display defects such as light leakage in this portion can be prevented. Here, the pixel opening can be defined by a light-shielding film such as the data line 6a and the barrier layer 80 and the first light-shielding film 11a or the data line 6a and the barrier layer 80. In such a case, since it is not necessary to form the second light shielding film 23 on the counter substrate 20, it is possible to reduce the step of forming the second light shielding film 23 on the counter substrate 20. Further, it is possible to prevent a decrease or variation in pixel aperture ratio due to misalignment between the counter substrate 20 and the TFT array substrate 10. When the second light-shielding film 23 is provided on the counter substrate 20, the second light-shielding film 23 is formed larger in consideration of misalignment with the TFT array substrate 10, but the TFT array substrate 10 such as the data line 6 a and the barrier layer 80 as described above. Since the pixel opening is defined by the light-shielding film formed on the side, the pixel opening can be precisely defined, compared with the case where the pixel opening is determined by the second light-shielding film 23 provided on the counter substrate 20. The aperture ratio can be improved.

  As described above, in this basic form, various advantages can be obtained because the barrier layer 80 is made of a conductive light-shielding film. However, the barrier layer 80 is not a refractory metal film but is doped with, for example, phosphorus. You may comprise from a conductive polysilicon film. With this configuration, the barrier layer 80 does not exhibit the function as a light shielding film, but can sufficiently exhibit the function of increasing the storage capacity 70 and the original relay function of the barrier layer. Furthermore, since stress due to heat or the like is less likely to occur between the second interlayer insulating film 4, it is useful for preventing cracks in the barrier layer 80 and its surroundings. On the other hand, light shielding for defining the pixel opening region may be performed separately by the first light shielding film 11a and the second light shielding film 23.

  In this basic mode, part or all of the pixel opening region may be defined by the first light-shielding film 11 a formed below the TFT 30. For example, if the first light shielding film 11a is arranged side by side or slightly overlapping the barrier layer 80 when viewed in plan in FIG. 2, the first light shielding film 11a and the barrier layer 80 scan the pixel opening region. A side along the line 3a can be defined.

  In this basic form, in particular, as shown in FIGS. 2 and 3, the first contact hole 8a and the second contact hole 8b are opened at different planar positions on the TFT array substrate 10. Accordingly, it is possible to avoid a situation where the unevenness generated at the planar position where the first contact hole 8a and the second contact hole 8b are opened overlaps and the unevenness is amplified. Therefore, good electrical connection in these contact holes can be expected.

  The planar shape of the contact holes 8a, 8b and 5 may be a circle, a rectangle or other polygonal shapes, but the circle is particularly useful for preventing cracks in the interlayer insulating film around the contact hole. In order to obtain a good electrical connection, it is preferable that wet etching is performed after dry etching to slightly taper these contact holes 8a, 8b and 5.

(Manufacturing process in basic form of electro-optical device)
Next, a manufacturing process of the liquid crystal device in the embodiment having the above-described configuration will be described with reference to FIGS. 4 to 7 are process diagrams showing each layer on the TFT array substrate side in each process corresponding to the AA ′ cross section of FIG.

First, as shown in step (1) in FIG. 4, a TFT array substrate 10 such as a quartz substrate, hard glass, or silicon substrate is prepared. Here, heat treatment is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pretreatment is performed so as to reduce distortion generated in the TFT array substrate 10 in a high-temperature process to be performed later. Keep it. That is, the TFT array substrate 10 is heat-treated in advance at the same temperature or higher in accordance with the temperature at which the high temperature treatment is performed at the maximum temperature in the manufacturing process. Then, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo, and Pb or a metal silicide is formed on the entire surface of the TFT array substrate 10 processed in this manner, and a film of about 100 to 500 nm is formed by sputtering or the like. A light shielding film 11 having a thickness, preferably about 200 nm, is formed. An antireflection film such as a polysilicon film may be formed on the light shielding film 11 in order to reduce surface reflection.

  Next, as shown in step (2), a resist mask corresponding to the pattern of the first light shielding film 11a (see FIG. 2) is formed on the formed light shielding film 11 by a photolithography process, and the resist mask is interposed therebetween. Then, the first light shielding film 11a is formed by etching the light shielding film 11.

  Next, as shown in step (3), TEOS (tetra-ethyl ortho-silicate) gas, TEB (tetra-ethyl boat rate) is formed on the first light-shielding film 11a by, for example, normal pressure or low pressure CVD. ) A base insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using a gas, TMOP (tetramethyloxy phosphite) gas, or the like. . The film thickness of the base insulating film 12 is, for example, about 500 to 2000 nm. If the return light from the back surface of the TFT array substrate 10 does not matter, the first light shielding film 11a need not be formed.

  Next, as shown in step (4), a monosilane gas, a disilane gas, or the like having a flow rate of about 400 to 600 cc / min is formed on the base insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. An amorphous silicon film is formed by low pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa). Thereafter, a heat treatment is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the polysilicon film 1 has a thickness of about 50 to 200 nm, preferably about Solid phase growth is performed until the thickness becomes 100 nm. As a method for solid phase growth, heat treatment using RTA (Rapid Thermal Anneal) may be used, or laser heat treatment using an excimer laser or the like may be used.

  At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30 shown in FIG. 3, Vb such as Sb (antimony), As (arsenic), P (phosphorus), etc. is formed in the channel region. Group element impurities may be slightly doped by ion implantation or the like. Further, when the pixel switching TFT 30 is a p-channel type, a group III element impurity such as B (boron), Ga (gallium), or In (indium) may be slightly doped by ion implantation or the like. Note that the polysilicon film 1 may be directly formed by a low pressure CVD method or the like without going through an amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low pressure CVD method or the like to make it amorphous and then recrystallizing it by heat treatment or the like.

  Next, as shown in step (5), a semiconductor layer 1a having a predetermined pattern as shown in FIG. 2 is formed by a photolithography process, an etching process, or the like.

  Next, as shown in step (6), the semiconductor layer 1a constituting the pixel switching TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C., so that it is relatively thin at about 30 nm. A thermally oxidized silicon film 2a having a thickness is formed, and as shown in step (7), an insulating film 2b made of a high temperature silicon oxide film (HTO film) or a silicon nitride film is formed by a relatively low pressure of about 50 nm by a low pressure CVD method. A first dielectric film 2 for forming a storage capacitor is formed simultaneously with the insulating thin film 2 of the pixel switching TFT 30 having a multilayer structure including a thermal silicon oxide film 2a and an insulating film 2b. As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating thin film (first dielectric film) 2 has a thickness of about 20 to 150 nm. The thickness is preferably about 30 to 100 nm. By shortening the high-temperature thermal oxidation time in this way, it is possible to prevent warpage due to heat, particularly when a large substrate of about 8 inches is used. However, the insulating thin film 2 having a single layer structure may be formed only by thermally oxidizing the polysilicon film 1.

Next, as shown in step (8), after a resist layer 500 is formed on the semiconductor layer 1a excluding a portion that becomes the first storage capacitor electrode 1f by a photolithography process, an etching process, etc., for example, a dose of P ions is reduced to about The first storage capacitor electrode 1f may be reduced in resistance by doping at 3 × 10 ¹² / cm ² .

  Next, as shown in step (9), after removing the resist layer 500, a polysilicon film 3 is deposited by a low pressure CVD method or the like, and P is thermally diffused to make the polysilicon film 3 conductive. Alternatively, a doped polysilicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. The polysilicon film 3 is deposited to a thickness of about 100 to 500 nm, preferably about 300 nm.

  Next, as shown in step (10) of FIG. 5, the capacitor line 3b is formed together with the scanning line 3a having a predetermined pattern as shown in FIG. 2 by a photolithography process, an etching process, etc. using a resist mask. The scanning line 3a and the capacitor line 3b may be formed of a metal alloy film such as a refractory metal or metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like.

Next, as shown in step (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel TFT having an LDD structure, the low concentration source region 1b and the low concentration drain region are first formed in the semiconductor layer 1a. In order to form 1c, a gate electrode which is a part of the scanning line 3a is used as a mask, and a V group element impurity such as P is doped at a low concentration (for example, P ions are dosed at 1 to 3 × 10 ¹³ / cm ² . Dope in amount). As a result, the semiconductor layer 1a under the scanning line 3a becomes a channel region 1a ′.

Next, as shown in step (12), in order to form the high concentration source region 1d and the high concentration drain region 1e constituting the pixel switching TFT 30, the resist layer 600 is scanned with a mask wider than the scanning line 3a. After the formation on the line 3a, the impurity of a V-group element such as P is doped at a high concentration (for example, P ions at a dose of 1 to 3 × 10 ¹⁵ / cm ² ). When the pixel switching TFT 30 is a p-channel type, B or the like is used to form the low concentration source region 1b and the low concentration drain region 1c, the high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a. Doping is performed using Group III element impurities. For example, an TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask. The resistance of the capacitor line 3b and the scanning line 3a is further reduced by doping the impurities.

  In parallel with the element forming process of these TFTs 30, peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of an n-channel TFT and a p-channel TFT are arranged on the TFT array substrate 10. You may form in the upper peripheral part. As described above, if the semiconductor layer 1a constituting the pixel switching TFT 30 is formed of a polysilicon film in this embodiment, a peripheral circuit can be formed in almost the same process when the pixel switching TFT 30 is formed. It is advantageous.

  Next, as shown in step (13), after removing the resist layer 600, the capacitor line 3b, the scanning line 3a, and the insulating thin film (first dielectric film) 2 are heated to a high temperature by a low pressure CVD method, a plasma CVD method or the like. A first interlayer insulating film 81 made of a silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively thin thickness of 10 nm to 200 nm. However, as described above, the first interlayer insulating film 81 may be formed of a multilayer film, and the first interlayer insulating film 81 is generally formed by various known techniques used for forming an insulating thin film of a TFT. It can be formed. In the case of the first interlayer insulating film 81, if it is made too thin as in the case of the second interlayer insulating film 4, the parasitic capacitance between the data line 6a and the scanning line 3a does not increase, and the insulating thin film in the TFT 30 If it is configured to be too thin as shown in 2, a unique phenomenon such as a tunnel effect does not occur. The first interlayer insulating film 81 functions as a second dielectric film between the second storage capacitor electrode that is part of the capacitor line and the barrier layer 80. The thinner the second dielectric film 81 is, the larger the second storage capacitor 70b is. Therefore, the second dielectric film 81 has a thickness of 50 nm or less, which is thinner than the insulating thin film 2, on the condition that no defects such as film breakage occur. If the second dielectric film 81 is formed so as to be an extremely thin insulating film, the effect of this basic mode can be increased.

  Next, as shown in step (14), a contact hole 8a for electrically connecting the barrier layer 80 and the high concentration drain region 1e is formed by dry etching such as reactive ion etching or reactive ion beam etching. To do. Since such dry etching has high directivity, a contact hole 8a having a small diameter can be opened. Alternatively, wet etching advantageous for preventing the contact hole 8a from penetrating the semiconductor layer 1a may be used in combination. This wet etching is also effective from the viewpoint of providing a taper for better electrical connection to the contact hole 8a.

  Next, as shown in step (15), a metal or metal such as Ti, Cr, W, Ta, Mo and Pb is formed on the entire surface of the high-concentration drain region 1e viewed through the first interlayer insulating film 81 and the contact hole 8a. A metal alloy film such as silicide is deposited by sputtering or the like to form a conductive film 80 ′ having a thickness of about 50 to 500 nm. If the thickness is about 50 nm, there is almost no possibility of penetrating through the second contact hole 8b later. Note that an antireflection film such as a polysilicon film may be formed on the conductive film 80 'in order to reduce surface reflection. The conductive film 80 'may be a doped polysilicon film or the like for stress relaxation. At this time, a laminated conductive film 80 ′ having two or more layers may be formed using a doped polysilicon film (conductive polysilicon film) as a lower layer and a metal film as an upper layer. Alternatively, a metal film may be sandwiched between two layers of polysilicon film to form three layers. As described above, when the conductive film 80 'and the high-concentration drain region 1e are electrically connected, if the same polysilicon film is formed, the contact resistance can be greatly reduced.

  Next, as shown in step (16) of FIG. 6, a resist mask corresponding to the pattern of the barrier layer 80 (see FIG. 2) is formed on the formed conductive film 80 ′ by photolithography, and the resist mask is formed. Then, the conductive layer 80 ′ is etched to form the barrier layer 80 including the third storage capacitor electrode.

  Next, as shown in step (17), NSG, PSG, BSG, BPSG, etc. are used to cover the first interlayer insulating film 81 and the barrier layer 80 by using, for example, atmospheric pressure or reduced pressure CVD, TEOS gas, or the like. A second interlayer insulating film 4 made of a silicate glass film, a silicon nitride film, a silicon oxide film or the like is formed. The film thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm. If the thickness of the second interlayer insulating film 4 is 500 nm or more, the parasitic capacitance between the data line 6a and the scanning line 3a is not excessive or hardly causes a problem.

  Next, in step (18), a heat treatment at about 1000 ° C. is performed for about 20 minutes in order to activate the high-concentration source region 1d and the high-concentration drain region 1e, and then a contact hole 5 for the data line 6a is opened. To do. Further, contact holes for connecting the scanning lines 3 a and the capacitor lines 3 b to wirings (not shown) in the peripheral region of the TFT array substrate 10 may be opened in the second interlayer insulating film 4 by the same process as the contact holes 5. it can.

  Next, as shown in step (19), a low resistance metal such as light-shielding Al or a metal silicide or the like is formed on the second interlayer insulating film 4 by sputtering or the like as a metal film 6 to have a thickness of about 100 to 500 nm. Deposit to a thickness, preferably about 300 nm.

  Next, as shown in the step (20), the data line 6a is formed by a photolithography process, an etching process, or the like.

  Next, as shown in step (21) of FIG. 7, a silicate glass such as NSG, PSG, BSG, or BPSG is used to cover the data line 6a using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas. A third interlayer insulating film 7 made of a film, a silicon nitride film, a silicon oxide film or the like is formed. The thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm.

  Next, as shown in step (22), a contact hole 8b for electrically connecting the pixel electrode 9a and the barrier layer 80 is formed by dry etching such as reactive ion etching or reactive ion beam etching. Further, wet etching may be used to form a taper.

  Next, as shown in step (23), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. As shown in 24), the pixel electrode 9a is formed by a photolithography process, an etching process, or the like. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

  Subsequently, after applying a polyimide alignment film coating solution on the pixel electrode 9a, the alignment film 16 (see FIG. 3) is subjected to a rubbing process so as to have a predetermined pretilt angle and in a predetermined direction. Is formed.

  On the other hand, for the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and after the second light shielding film 23 and a third light shielding film as a frame to be described later, for example, sputter metal chromium, a photolithography process, It is formed through an etching process. The second and third light shielding films may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist in addition to a metal material such as Cr, Ni, or Al. If the light shielding region is defined on the TFT array substrate 10 by the data line 6a, the barrier layer 80, the first light shielding film 11a, etc., the second light shielding film 23 and the third light shielding film on the counter substrate 20 can be omitted. it can.

  Then, the counter electrode 21 is formed by depositing a transparent conductive thin film such as ITO on the entire surface of the counter substrate 20 by sputtering or the like to a thickness of about 50 to 200 nm. Further, after applying a polyimide-based alignment film coating solution over the entire surface of the counter electrode 21, the alignment film 22 (see FIG. 3) is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle. It is formed.

  Finally, the TFT array substrate 10 on which the respective layers are formed as described above and the counter substrate 20 are bonded to each other with a sealant, which will be described later, so that the alignment films 16 and 22 face each other. For example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked into the space, and the liquid crystal layer 50 having a predetermined thickness is formed.

(First embodiment of electro-optical device)
The configuration of the liquid crystal device according to the first embodiment of the electro-optical device according to the invention will be described with reference to FIGS. 8 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed. FIG. 9 is a cross-sectional view taken along line BB ′ of FIG. It is. In the second embodiment shown in FIGS. 8 and 9, the same reference numerals are given to the same components as those in the basic embodiment shown in FIGS. 2 and 3, and the description thereof is omitted. Further, in FIG. 9, the scales are different for each layer and each member so that each layer and each member can be recognized in the drawing.

  8 and 9, unlike the basic mode in the first embodiment, the first light shielding film 11b covers the scanning line 3a, the capacitor line 3b, and the data line 6a when viewed from the TFT array substrate 10, that is, each It is provided over the entire area of the lattice-shaped non-opening region surrounding the pixel. Further, the base insulating film 12 is provided with a contact hole 15 for electrically connecting the capacitor line 3b and the first light shielding film 11b. The capacitor line 3b and the first light shielding film 11b are connected to the constant potential wiring in the peripheral region of the substrate. Other configurations are the same as those in the basic mode.

  Therefore, according to the first embodiment, the first light-shielding film 11b not only has a function of defining the pixel opening region and also functions as a constant potential wiring or a redundant wiring of the capacitor line 3b, but also reduces the resistance of the capacitor line itself. The image quality can be improved. If comprised in this way, it will become possible to prescribe | regulate a pixel opening area only with the 1st light shielding film 11b. Further, the potentials of the capacitor line 3b and the first light shielding film 11b can be set to the same constant potential, and adverse effects on the image signal and the TFT 30 due to potential fluctuations in the capacitor line 3b and the first light shielding film 11b can be reduced. Further, the base insulating film 12 interposed between the first light-shielding film 11b and the semiconductor layer 1a can be a dielectric film, and a storage capacitor can be added.

  If the first light-shielding film 11b is used as a capacitor line, the capacitor line 3b formed in the same process as the scanning line 3a may be provided in an island shape as a storage capacitor electrode for each pixel unit. With this configuration, the pixel aperture ratio can be improved.

  The first light shielding film 11b can be formed by changing the resist mask pattern in the step (2) during the manufacturing process according to the first embodiment. The contact hole 15 is opened by performing dry etching or wet etching such as reactive ion etching or reactive ion beam etching between the steps (8) and (9) during the manufacturing process in the basic form. do it.

(Second embodiment of electro-optical device)
A configuration of a liquid crystal device which is a second embodiment of the electro-optical device according to the invention will be described with reference to FIG. FIG. 10 is a cross-sectional view of the second embodiment corresponding to the BB ′ cross section of the plan view of FIG. 8 in the first embodiment. In the second embodiment shown in FIG. 10, the same components as those in the first embodiment shown in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 10, the scales are different for each layer and each member so that each layer and each member can be recognized on the drawing.

  In FIG. 10, the second embodiment differs from the first embodiment in that the third interlayer insulating film 7 'has a flat upper surface. As a result, the pixel electrode 9a and the alignment film 16 using the third interlayer insulating film 7 'as a base film are also planarized. Other configurations are the same as those in the second embodiment.

  Therefore, according to the second embodiment, the level difference between the region where the scanning line 3a, the TFT 30, the capacitor line 3b, etc. are formed so as to overlap the data line 6a is reduced. Since the pixel electrode 9a is flattened in this way, the occurrence of disclination in the liquid crystal layer 50 can be reduced according to the degree of flattening. As a result, according to the second embodiment, higher quality image display is possible, and the pixel opening area can be widened.

  The flattening of the third interlayer insulating film 7 ′ is performed by, for example, a CMP (Chemical Mechanical Polishing) process, a spin coat process, a reflow method, or the like in the step (21) in the manufacturing process of the basic form. Organic SOG (Spin On Glass), inorganic SOG, polyimide film or the like may be used. Thus, even when the thickness of the third interlayer insulating film 7 'is increased in order to flatten the film, the barrier layer 80 is formed of a film having a high selection ratio, so that it does not penetrate through the film during etching.

(Third embodiment of electro-optical device)
A configuration of a liquid crystal device which is a third embodiment of the electro-optical device according to the invention will be described with reference to FIG. FIG. 11 is a cross-sectional view of the third embodiment corresponding to the BB ′ cross section of the plan view of FIG. 8 in the first embodiment. In the third embodiment shown in FIG. 10, the same components as those in the first embodiment shown in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted. Further, in FIG. 11, the scales are different for each layer and each member so that each layer and each member can be recognized on the drawing.

  In FIG. 11, in the third embodiment, unlike the first embodiment, the TFT array substrate 10 ′ is formed such that the upper surface thereof is recessed in a portion facing the data line 6a, the scanning line 3a, and the capacitor line 3b. Has been. As a result, the pixel electrode 9a and the alignment film 16 formed on the TFT array substrate 10 'via these wirings and interlayer insulating films are also planarized. Other configurations are the same as those in the first embodiment.

  Therefore, according to the third embodiment, the level difference between the region where the scanning line 3a, the TFT 30, the capacitor line 3b and the like are formed and the region where the data line 6a is not formed is reduced. In this manner, the pixel electrode 9a is substantially flattened simply by filling at least a part of the non-opening region of the pixel, and the occurrence of disclination of the liquid crystal layer 50 can be reduced according to the degree of flattening. As a result, according to the third embodiment, higher-quality image display can be performed, and the pixel opening area can be widened.

  Note that such a TFT array substrate 10 ′ may be etched in a region where a concave depression is to be formed, for example, before step (1) in the manufacturing process of the first embodiment.

  As described above, in the second embodiment, the upper surface of the third interlayer insulating film is flattened, and in the third embodiment, the substrate and the element portion are formed after forming the groove in the concave shape, and finally the pixel electrode is formed. Although the planarization is performed, the same planarization effect can be obtained even when the second interlayer insulating film 4 or the base insulating film 12 is formed in a concave shape. In this case, as a method of forming each interlayer insulating film in a concave shape, each interlayer insulating film has a two-layer structure, a thin portion consisting of only one layer is used as a concave recess portion, and a thick portion in two layers is used as a concave bank portion. Thus, thin film formation and etching may be performed. Alternatively, each interlayer insulating film may have a single layer structure, and a concave recess may be opened by etching. In these cases, when dry etching such as reactive ion etching or reactive ion beam etching is used, there is an advantage that a concave portion can be formed as designed. On the other hand, at least when wet etching is used alone or in combination with dry etching, the side wall surface of the concave depression can be formed into a taper shape, so that the polysilicon film formed in the concave depression in a later step Further, since the residue around the sidewall of the resist or the like can be reduced, an advantage that the yield is not lowered can be obtained.

(Deformation of electro-optical device)
A configuration of a liquid crystal device which is a modification of the electro-optical device according to the present invention will be described with reference to FIG. 12 is a cross-sectional view of a modified embodiment corresponding to the cross-sectional view along AA ′ of FIG. 2 in the first embodiment. In the modification shown in FIG. 12, the same reference numerals are assigned to the same components as those in the basic form, and the description thereof is omitted, and only differences from the basic form will be described.

  In the modified embodiment, a second contact hole 8b for electrically connecting the barrier layer 80 and the pixel electrode 9a is formed on the capacitor line 3b. Thus, by forming the second contact hole 8b on the capacitor line 3b, the area under the region of the second contact hole 8b can also function as a capacitor, so that the capacitance can be increased accordingly.

(Overall configuration of electro-optical device)
The overall configuration of a liquid crystal device as an example of the electro-optical device according to each embodiment configured as described above will be described with reference to FIGS. FIG. 13 is a plan view of the TFT array substrate 10 as viewed from the counter substrate 20 side together with the components formed thereon, and FIG. 14 is a cross-sectional view taken along the line HH ′ of FIG.
In FIG. 13, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and an image display region made of, for example, the same or different material as the second light-shielding film 23 in parallel with the inner side. A third light-shielding film 53 is provided as a frame that defines the periphery of. In a region outside the sealing material 52, a data line driving circuit 101 and an external circuit connection terminal 102 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing along one side of the TFT array substrate 10. A scanning line driving circuit 104 that drives the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing is provided along two sides adjacent to the one side. Needless to say, if the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuit 101 may be arranged on both sides along the side of the image display area. For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit arranged along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. Alternatively, an image signal may be supplied from a data line driving circuit arranged in this manner. If the data lines 6a are driven in a comb-like shape in this way, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be configured. Further, on the remaining side of the TFT array substrate 10, a plurality of wirings 105 are provided for connecting between the scanning line driving circuits 104 provided on both sides of the image display area. In addition, at least one corner of the counter substrate 20 is provided with a conductive material 106 for electrical connection between the TFT array substrate 10 and the counter substrate 20. As shown in FIG. 14, the counter substrate 20 having substantially the same outline as the sealing material 52 shown in FIG. 13 is fixed to the TFT array substrate 10 by the sealing material 52. On the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104 and the like, a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, and a plurality of data lines A precharge circuit for supplying a precharge signal of a predetermined voltage level in advance to the image signal to 6a, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during manufacture or at the time of shipment may be formed. Good. According to the present embodiment, the second light shielding film 23 on the counter substrate 20 may be formed smaller than the light shielding region of the TFT array substrate 10. Further, the second light shielding film 23 can be easily removed depending on the use of the liquid crystal device.

  In each embodiment described above with reference to FIGS. 1 to 14, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, on a TAB (Tape Automated Bonding) substrate. The mounted LSI for driving may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. Further, for example, a TN (Twisted Nematic) mode, a VA (Vertically Aligned) mode, and a PDLC (Polymer Dispersed Liquid Crystal) are respectively provided on the side of the counter substrate 20 where the projection light is incident and the side of the TFT array substrate 10 where the emission light is emitted. ) Mode or the like, or a normally white mode / normally black mode, a polarizing film, a retardation film, a polarizing plate and the like are arranged in a predetermined direction.

  Since the electro-optical device in each of the embodiments described above is applied to a color display projector or the like, three electro-optical devices are respectively used as light valves for R (red) G (green) B (blue). The light of each color separated through the RGB color separation dichroic mirror is incident on each light valve as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 together with the protective film in a predetermined region facing the pixel electrode 9a where the second light shielding film 23 is not formed. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrodes 9 a facing RGB on the TFT array substrate 10. In this way, the electro-optical device according to each embodiment can be applied to a direct-view type or reflective type color liquid crystal television other than the projector. Furthermore, a microlens may be formed on the counter substrate 20 so as to correspond to one pixel. In this way, a bright electro-optical device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that produces RGB colors by using interference of light may be formed by depositing several layers of interference layers having different refractive indexes on the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color electro-optical device can be realized.

  In the electro-optical device according to each of the embodiments described above, incident light is incident from the counter substrate 20 side as in the conventional case. However, since the first light-shielding film 11a is provided, the light is incident from the TFT array substrate 10 side. Incident light may be incident and emitted from the counter substrate 20 side. That is, even if the electro-optical device is attached to the liquid crystal projector in this way, it is possible to prevent light from entering the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a, and the high image quality. Images can be displayed. Here, conventionally, in order to prevent reflection on the back side of the TFT array substrate 10, it is necessary to separately arrange an antireflection (AR) -coated polarizing plate or attach an AR film. However, in each embodiment, the first light shielding film 11a is formed between the surface of the TFT array substrate 10 and at least the channel region 1a ′ and the low concentration source region 1b and the low concentration drain region 1c of the semiconductor layer 1a. Therefore, there is no need to use such an AR-coated polarizing plate or AR film, or to use a substrate in which the TFT array substrate 10 itself is subjected to AR treatment. Therefore, according to each embodiment, the material cost can be reduced, and it is very advantageous that the yield is not lowered due to dust, scratches, or the like when the polarizing plate is attached. In addition, since the light resistance is excellent, even when a bright light source is used or polarization conversion is performed by a polarization beam splitter to improve light use efficiency, image quality degradation such as crosstalk due to light does not occur.

  In addition, the switching element provided in each pixel has been described as a normal stagger type or coplanar type polysilicon TFT, but other types of TFT such as an inverted stagger type TFT or an amorphous silicon TFT are also used. Each embodiment is effective.

(Electronics)
Next, an embodiment of an electronic apparatus including the electro-optical device 100 described in detail above will be described with reference to FIGS. 15 to 17.

  First, FIG. 15 shows a schematic configuration of an electronic apparatus including the electro-optical device 100 as described above.

  In FIG. 15, the electronic apparatus includes a display information output source 1000, a display information processing circuit 1002, a drive circuit 1004, an electro-optical device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like. Based on this, display information such as an image signal in a predetermined format is output to the display information processing circuit 1002. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a serial-parallel conversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and is input based on a clock signal. Digital signals are sequentially generated from the displayed information and output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the electro-optical device 100. The power supply circuit 1010 supplies predetermined power to the above-described circuits. The drive circuit 1004 may be mounted on the TFT array substrate constituting the electro-optical device 100, and in addition to this, the display information processing circuit 1002 may be mounted.

  Next, FIGS. 16 to 17 show specific examples of the electronic apparatus configured as described above.

  In FIG. 16, a projector 1100 as an example of an electronic device prepares three light valves including the electro-optical device 100 in which the driving circuit 1004 described above is mounted on a TFT array substrate, and each of the RGB light valves 100R and 100G. And as a projector used as 100B. In the projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light components R, G, and B corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. And are led to the light valves 100R, 100G and 100B corresponding to the respective colors. At this time, in particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.

  In FIG. 17, a laptop personal computer (PC) 1200 compatible with multimedia, which is another example of an electronic device, includes the above-described electro-optical device 100 in a top cover case, and further includes a CPU, a memory, and a modem. And a main body 1204 in which a keyboard 1202 is incorporated.

  In addition to the electronic devices described with reference to FIGS. 16 to 17, a liquid crystal television, a viewfinder type or a monitor direct view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, an engineering workstation ( EWS), a mobile phone, a video phone, a POS terminal, a device provided with a touch panel, and the like are examples of the electronic device shown in FIG.

  As described above, according to the present embodiment, it is possible to realize various electronic devices including an electro-optical device that can display images with high production efficiency and high quality.

2 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix pixels that form an image display region in a liquid crystal device that is a basic form of an electro-optical device. FIG. 4 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light shielding films, and the like are formed in a liquid crystal device of a basic form. It is A-A 'sectional drawing of FIG. It is process drawing (the 1) which shows the manufacturing process of the liquid crystal device of a basic form later on. It is process drawing (the 2) which shows the manufacturing process of the liquid crystal device of a basic form later on. It is process drawing (the 3) which shows the manufacturing process of the liquid crystal device of a basic form later on. It is process drawing (the 4) which shows the manufacturing process of the liquid crystal device of a basic form later on. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light shielding film, and the like are formed in the liquid crystal device that is the first embodiment of the electro-optical device. FIG. It is B-B 'sectional drawing of FIG. It is sectional drawing of the liquid crystal device which is 2nd Embodiment of an electro-optical apparatus. It is sectional drawing of the liquid crystal device which is 3rd Embodiment of an electro-optical apparatus. It is sectional drawing of the liquid crystal device which is a modification of an electro-optical device. It is the top view which looked at the TFT array board | substrate in the liquid crystal device of each embodiment from the side of the opposing board | substrate with each component formed on it. It is H-H 'sectional drawing of FIG. It is a block diagram which shows schematic structure of embodiment of the electronic device by this invention. It is sectional drawing which shows a projector as an example of an electronic device. It is a front view which shows the personal computer as another example of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer 1a '... Channel region 1b ... Low concentration source region 1c ... Low concentration drain region 1d ... High concentration source region 1e ... High concentration drain region 1f ... First storage capacitor electrode 2 ... Insulating thin film (first dielectric film) )
3a ... scanning line 3b ... capacitor line 4 ... second interlayer insulating film 5 ... contact hole 6a ... data line 7 ... third interlayer insulating film 8a ... first contact hole 8b ... second contact hole 9a ... pixel electrode 10 ... TFT array Substrate 11a, 11b ... 1st light shielding film 12 ... Base insulating film 15 ... Contact hole 16 ... Orientation film 20 ... Counter substrate 21 ... Counter electrode 22 ... Orientation film 23 ... 2nd light shielding film 30 ... TFT
50 ... Liquid crystal layer 52 ... Sealing material 53 ... Third light shielding film 70 ... Storage capacitor 70a ... First storage capacitor 70b ... Second storage capacitor 80 ... Barrier layer 81 ... First interlayer insulating film (second dielectric film)
101 ... Data line driving circuit 104 ... Scanning line driving circuit

Claims (5)

An electro-optical device having a plurality of scanning lines, a plurality of data lines intersecting with the plurality of scanning lines, a thin film transistor and a pixel electrode arranged corresponding to the intersection of the scanning lines and the data lines, and a storage capacitor Because
A light-shielding lower conductive film overlapping the channel region of the thin film transistor and the data line is provided below the semiconductor layer of the thin film transistor,
One storage capacitor electrode constituting the storage capacitor is formed in the same layer as the gate electrode of the thin film transistor, and is electrically connected to the lower light-shielding film in a region where the data line extends ,
The other storage capacitor electrode constituting the storage capacitor is formed such that a drain region of the thin film transistor is formed in a region where the data line extends so as to overlap the one storage capacitor electrode. apparatus. The electro-optical device according to claim 1 , wherein the storage capacitor is formed along the scanning line. 3. The electro-optical device according to claim 1, wherein a channel region of the thin film transistor is provided in a region where the data line and the scanning line intersect. The thin film transistor, an electro-optical device according to any one of claims 1 to 3, characterized in that a dual gate or triple gate. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 4.

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