JP3732128B2 - Memory control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory control device that performs writing and reading of a clock synchronous memory that operates in synchronization with a clock by controlling the phase of the clock.
[0002]
[Prior art]
In a clock synchronous memory (for example, synchronous D-RAM) that operates in synchronization with a clock, when data is read continuously every cycle of the reference clock, a read data signal is input from the clock synchronous memory to an input register. It is necessary that the maximum delay time until the signal is input to 1 cycle or less of the reference clock.
[0003]
However, when the clock synchronous memory is accessed at high speed, the maximum delay time until the read data signal is input from the clock synchronous memory to the input register may not be one cycle or less.
[0004]
Therefore, in Japanese Patent Laid-Open No. 2000-10849, as shown in FIG. 11, an output clock for outputting a memory access control signal input to the memory control signal register to the clock synchronous memory, and an input data register from the clock synchronous memory And an input clock for outputting the read data signal input to the clock, and each clock is generated by shifting the phase from the reference clock so that the access time is optimized by the clock phase controller.
[0005]
According to this, even when the maximum delay time until data is input from the clock synchronous memory to the input register does not become one cycle or less, the optimum access time can be automatically set.
[0006]
[Problems to be solved by the invention]
However, in the above-described prior art, the output clock 107 input to the output data register 14 is the reference clock 103 as shown in FIG. For this reason, as shown in FIG. 13, when the clock synchronous memory 13 is written and read (accessed), the control signal effective time dtRA from the rising edge of the output clock 107 (t time after the rising edge of the reference clock 103) The sum of the setup time tMST of the clock synchronous memory 13, the data signal valid time dtMA of the clock synchronous memory 13 and the setup time tR2ST of the input data register 16 becomes longer than one clock time tCLK, and the read data 102 is 2t. Instead of being taken in at the rising edge of the reference clock 103 for the time, it is taken in at the rising edge of the reference clock 103 for the next 3t time. As a result, there is a problem that the access time of the clock synchronous memory 13 becomes long.
[0007]
The present invention has been made in view of such circumstances, and in a clock synchronous memory operating in synchronization with a clock, when accessing the clock synchronous memory, the maximum delay time of data output from the clock synchronous memory It is an object of the present invention to provide a memory control device that does not increase the access time even when the cycle does not become one cycle or less.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, the memory control device according to the present invention employs the following means.
[0009]
The first aspect of the present invention is to output a memory clock for operating a clock synchronous memory and a memory access control signal input to the memory control signal register to the clock synchronous memory and write input to the output data register. A clock phase controller that generates an output clock that outputs a data signal to the clock synchronous memory and an input clock that outputs a read data signal input from the clock synchronous memory to the input data register;
This clock phase controller inputs a plurality of delay clocks generated by shifting the phase of each clock from a reference clock by a plurality of delay units to a switch corresponding to a memory clock, an output clock, and an input clock, It is generated by selecting one delay clock by a phase control signal corresponding to a memory clock, an output clock and an input clock,
The output clock delays the sum of the memory access control signal valid time from the rising edge of the reference clock and the setup time of the memory control signal register, and the memory clock is the time from the rising edge of the reference clock to the rising edge of the output clock. Delays the sum of the control signal valid time of the control signal register and the setup time of the clock synchronous memory, and the input clock is the time from the rise of the reference clock to the rise of the memory clock and the data signal valid time of the clock synchronous memory Further, the present invention relates to a clock control device that delays a time obtained by adding a setup time of an input data register.
[0010]
According to the first aspect of the present invention, the memory clock operates the clock synchronous memory, the output clock outputs the memory access control signal input to the memory control signal register to the clock synchronous memory, and the output data The write data signal input to the register is output to the clock synchronous memory, and the input clock outputs the read data signal input to the input data register from the clock synchronous memory.
As for each clock, a plurality of delayed clocks generated by shifting the phase from the reference clock by a plurality of delay units are input to a switch corresponding to the memory clock, output clock and input clock, and the memory clock, output clock and input It is generated by selecting one delay clock by a phase control signal corresponding to the clock.
The output clock is delayed by the sum of the memory access control signal valid time from the rise of the reference clock and the setup time of the memory control signal register, and the memory clock is the time from the rise of the reference clock to the rise of the output clock and the memory. Delay time is the sum of the control signal valid time of the control signal register and the setup time of the clock synchronous memory, and the input clock is the time from the rise of the reference clock to the rise of the memory clock and the data signal valid time of the clock synchronous memory And the input data register setup time are delayed.
[0011]
A second aspect of the present invention relates to the clock control device according to the first aspect, wherein the delay unit of the clock phase controller has different delay characteristics corresponding to the memory clock, the output clock, and the input clock.
[0012]
According to the second aspect of the present invention, the memory clock, the output clock, and the input clock are delayed by delay devices having different delay characteristics.
[0013]
According to a third aspect of the present invention, a clock phase controller is a switch that inputs a memory clock, an output clock, and a reference clock, selects one clock with a phase control signal corresponding to the output clock, and outputs the selected clock to a delay device. A switch that inputs an output clock, an input clock, and a reference clock, selects one clock by a phase control signal corresponding to the memory clock, and outputs the selected clock to a delay device; and inputs an output clock, a memory clock, and a reference clock 3. The clock control device according to claim 2, further comprising a switch for selecting one clock with a phase control signal corresponding to the input clock and outputting the selected clock to the delay unit.
[0014]
According to the third aspect of the present invention, the clock input to the first delay unit of the delay unit corresponding to the output clock is output from the switch to which the reference clock, the memory clock, and the input clock are input by the output clock phase control signal. The clock that is selected and input to the first delay unit of the delay unit corresponding to the memory clock is selected by the memory clock phase control signal from the switch to which the reference clock, the output clock, and the input clock are input, and corresponds to the input clock The clock input to the first delay unit of the delay unit is selected by the input clock phase control signal from the switch to which the reference clock, output clock and memory clock are input.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a memory control device according to the present invention will be described below with reference to the drawings.
[0016]
1 to 7 illustrate an embodiment (1) of a memory control device according to the present invention.
FIG. 1 is a block diagram showing a configuration of a memory control device 1 according to the present invention.
The memory control device 1 receives the reference clock 103, shifts the phase of the input reference clock 103 by the output clock phase control signal 104, the input clock phase signal 105, and the memory clock phase control signal 106, and outputs the output clock 107. The clock phase controller 2 that generates and outputs the input clock 108 and the memory clock 109, and the memory access control signal 100 is input and the control signal 110 is transferred to the clock synchronous memory 3 (hereinafter referred to as synchronous memory 3) by the output clock 107. ), The memory control signal register 4 that outputs the write data signal 101, the output data register 5 that outputs the data signal 111 by the output clock 107, and the data signal 111 that the synchronous memory 3 outputs. Read by 108 Is constructed from the input data register 6 for outputting the data signal 102.
[0017]
As shown in FIG. 2, the clock phase controller 2 receives a plurality of delay devices 21 to 2n connected in series for delaying the reference clock 103, and an output clock phase control signal 104 to input the delay devices 21 to 2n. A switch 251 for selecting the delay clocks 211 to 21n and the delay clock 210 (0 delay with respect to the reference clock) output from each of them and outputting the output clock 107 (1 delay clock), and the input clock phase control signal 105 , A switch 261 that selects the delay clocks 211 to 21n and the delay clock 210 output from the delay units 21 to 2n and outputs the input clock 108 (one delay clock), and a memory clock phase control signal 106, the delay clocks 211 to 21n output from the delay devices 21 to 24, respectively, Select an extended clock 210 and a switch 271 for outputting a memory clock 109 (first delay clock).
[0018]
Here, the number (n) of the delay devices 21 to 2n is n ≧ (1 / f) / D, where D is the delay time of each delay device of the delay devices 21 to 2n and f is the frequency of the reference clock 103. ing. When the delay devices 21 to 2n are semiconductor elements, the delay time increases or decreases due to a change in electrical characteristics due to an ambient temperature or the like, but in consideration of the change in the electrical properties, the delay devices 21 to 2n The number (n) is preferably n ≧ (1 / f) / Dmin, where Dmin is the minimum delay time.
[0019]
As shown in FIG. 3, the memory control signal register 4 includes a register 41 that receives a memory access control signal 100 and outputs a control signal 110 in synchronization with an input output clock 107.
[0020]
As shown in FIG. 4, the output data register 5 includes a register 51 that receives a write data signal 101 and outputs a data signal 111 in synchronization with an input output clock 107.
[0021]
As shown in FIG. 5, the input data register 6 includes a register 61 that receives the data signal 111 output from the synchronous memory 3 and outputs the read data signal 102 in synchronization with the input clock 108 input. Yes.
[0022]
Next, the operation of the memory control device according to the present invention will be described with reference to FIGS.
FIG. 6 is a diagram showing the timing of the reference clock 103 and the delayed clocks 210 to 21n in the clock phase controller 2. The delay clock 210 is 0 delay, and the delay clocks 211 to 21n are D delay to nD delay.
[0023]
FIG. 14 is a diagram showing timing when accessing a conventional synchronous memory. First, a memory access control signal 100 synchronized with time 0 of the reference clock 103 is input to a control unit (not shown), and a control signal 110 synchronized with time t of the reference clock 103 (one cycle time of the reference clock 103) is input to the synchronous memory. Is output. Next, the synchronous memory receives the control signal 110 at time 2t and outputs the data signal 111. Then, the control unit (not shown) receives the data signal 111 at time 3t and outputs the read data signal 102 to a higher-level device (not shown). Here, the frequency of the reference clock 103 is set such that the time obtained by adding the data signal valid time dtMA of the synchronous memory and the setup time tR2ST of the control unit (not shown) is one cycle or less.
[0024]
FIG. 7 is a diagram showing timings when accessing the synchronous memory 3 of the memory control device 1 according to the present invention. First, the memory access control signal 100 synchronized with the time 0 of the reference clock 103 is input to the memory control register 4. Next, the control signal 110 is output to the synchronous memory 3 in synchronization with the rising edge of the output clock 107. Here, the rise of the output clock 107 is delayed by a time dtOC or more obtained by adding the memory access control signal valid time dtMA from the time 0 of the reference clock 103 and the setup time dtMA of the memory control signal register 4. Next, the synchronous memory 3 receives the control signal 110 at the rising edge of the memory clock 109 and outputs a data signal 111. Here, the rise of the memory clock 109 is delayed by a time dtMC or more which is obtained by adding the time dtOC, the control signal valid time dtRA of the memory control signal register 4 and the setup time tMST of the synchronous memory 3. The input data register 4 receives the data signal 111 at the rising edge of the input clock 108. Here, the rising edge of the input clock 108 is delayed by a time dtIC or more obtained by adding the time dtMC, the data signal valid time dtMA of the synchronous memory 3 and the setup time tR2ST of the input data register.
[0025]
Since the memory control signal register 4 and the output data register 5 are registers synchronized with the output clock 107, the time dtMC is a time dtRA at which the control signal 110 becomes valid from the rise of the output clock 107 of the memory control signal register 4. And a time dtR1A when the data signal 111 is valid from the rising edge of the output clock 107 of the output data register 5 is compared and obtained using a large value.
[0026]
According to this, the read data signal 102 output from the input data register 6 can secure the setup time of the time tIMST with respect to the time 2t of the reference clock 107, shortening the access time and the data of the synchronous memory 3 The transfer timing margin can be improved.
[0027]
When the delay time of the output clock 107 is dtout, the delay time of the input clock 108 is dtin, and the delay time of the memory clock 109 is dtmen, the minimum delay time of the delay devices 21 to 2n is the greatest common commitment of dtout, dtin, and dtmem. Number.
[0028]
Therefore, for example, the delay time of the output clock 107 is 3A, the delay time of the input clock 108 is 5A, and the delay time of the memory clock 109 is 7A. If the time tCLK of one cycle of the reference clock 103 is 70A, 70 or more delay devices are required.
[0029]
More specifically, as shown in FIGS. 8 to 9, if the delay clocks 213 are composed of delay devices 21 to 2n having a minimum delay time A, the delay clock 213 corresponds to the output clock 107 and the reference clocks 103 to 3 The delay clock 215 is delayed by five delay devices from the reference clock 103 in correspondence with the input clock 108, and the delay clock 217 in correspondence with the memory clock 109 is seven reference clocks 103. Delayed by the delay unit.
[0030]
Next, an embodiment (2) of the memory control device according to the present invention will be described. FIG. 8 shows an embodiment (2) of the memory control device according to the present invention. In addition, the description similar to Embodiment (1) is abbreviate | omitted by attaching | subjecting the same code | symbol.
[0031]
As shown in FIG. 8, the memory control device 600 of this embodiment (2) is provided with the delay devices of the embodiment (1) corresponding to the output clock 107, the memory clock 109, and the input clock 108, respectively. It is the thing of the composition. Here, the delay devices 601 to 60n corresponding to the output clock 107, the delay devices 621 to 62n corresponding to the memory clock 109, and the delay devices 641 to 64n corresponding to the input clock 108 have different delay characteristics. .
[0032]
According to this embodiment (2), if the delay time of the output clock 107 is 3A, the delay time of the input clock 108 is 5A, the delay time of the memory clock 109 is 7A, and the cycle time of the reference clock 103 is 70A, the delay The total number of delay units 601 to 60n is 24, the number of delay units 621 to 62n is 14, the number of delay units 641 to 64n is 10 and a total of 48 delay units are required. The access time can be increased without increasing the number of delay units. Can be improved.
[0033]
Next, an embodiment (3) of the memory control device according to the present invention will be described. FIG. 9 shows an embodiment (3) of the memory control device according to the present invention. In addition, the description similar to Embodiment (1) is abbreviate | omitted by attaching | subjecting the same code | symbol.
[0034]
As shown in FIG. 9, the memory control device 900 of this embodiment (3) receives the memory clock 107, the output clock 107, and the reference clock 103 and outputs the output clock phase control signal 104 in the embodiment (1). The switch 952 that selects one clock and outputs it to the first delay unit 901 of the delay units 901 to 90n, the output clock 107, the input clock 108, and the reference clock 103 are input, and the memory clock phase control signal 106 sets 1 Switch 953 for selecting the first clock and outputting it to delay device 921 at the first stage of delay devices 921 to 92n, output clock 107, memory clock 109 and reference clock 103 are input, and input clock phase control signal 105 is set to one clock. Is selected and output to the first delay unit 941 of the delay units 941 to 94n. It is of the configuration in which attached the door.
[0035]
According to this embodiment (3), for example, in the case shown in FIG. 7, if the phase of the output clock 107 is shifted from the reference clock 103 and the phase of the memory clock 108 is shifted from the output clock 107, from the time dtMC. If the time memory clock 109 obtained by subtracting the time dtOC is delayed in advance and the phase of the input clock 108 is shifted from the memory clock 109, the time input clock 108 obtained by subtracting the time dtMC from the time dtIC is delayed in advance. Furthermore, the access time can be improved without increasing the number of delay devices.
[0036]
【The invention's effect】
As described above, according to the first aspect of the present invention, the memory clock operates the clock synchronous memory, and the output clock outputs the memory access control signal input to the memory control signal register to the clock synchronous memory. At the same time, the write data signal inputted to the output data register is outputted to the clock synchronous memory, and the read data signal inputted from the clock synchronous memory to the input data register is outputted from the input clock.
As for each clock, a plurality of delayed clocks generated by shifting the phase from the reference clock by a plurality of delay units are input to a switch corresponding to the memory clock, output clock and input clock, and the memory clock, output clock and input It is generated by selecting one delay clock by a phase control signal corresponding to the clock.
The output clock is delayed by the sum of the memory access control signal valid time from the rise of the reference clock and the setup time of the memory control signal register, and the memory clock is the time from the rise of the reference clock to the rise of the output clock and the memory. Delay time is the sum of the control signal valid time of the control signal register and the setup time of the clock synchronous memory, and the input clock is the time from the rise of the reference clock to the rise of the memory clock and the data signal valid time of the clock synchronous memory And the input data register setup time are delayed.
Thus, when accessing the clock synchronous memory, there is an effect that the access time is not increased even if the maximum delay time of data output from the clock synchronous memory does not become one cycle or less.
[0037]
According to the second aspect of the present invention, in the memory control device according to the first aspect, the memory clock, the output clock, and the input clock are delayed by delay elements having different delay characteristics. As a result, the access time can be improved without increasing the number of delay devices.
[0038]
According to the third aspect of the present invention, in the memory control device according to the second aspect, the clock input to the first-stage delay unit of the delay unit corresponding to the output clock is input with the reference clock, the memory clock, and the input clock. The clock that is selected by the output clock phase control signal from the switch and is input to the first delay unit of the delay unit corresponding to the memory clock is the memory clock phase control from the switch to which the reference clock, output clock, and input clock are input. The clock selected by the signal and input to the first delay unit of the delay unit corresponding to the input clock is selected by the input clock phase control signal from the switch to which the reference clock, the output clock and the memory clock are input. As a result, the access time can be improved without increasing the number of delay devices.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment (1) of a memory control device according to the present invention.
FIG. 2 is a block diagram illustrating the clock phase controller of FIG.
FIG. 3 is a block diagram showing a memory control register of FIG. 1;
4 is a block diagram showing the output data register of FIG. 1; FIG.
FIG. 5 is a block diagram showing an input data register of FIG. 1;
6 is a diagram illustrating the timing of the delayed clock in FIG. 2. FIG.
7 is a diagram showing signal timing of the memory control device of FIG. 1; FIG.
FIG. 8 is a block diagram showing the delay device of FIG. 1;
FIG. 9 is a diagram illustrating the timing of the delayed clock in FIG. 8;
FIG. 10 is a block diagram showing an embodiment (2) of the memory control device according to the present invention;
FIG. 11 is a block diagram showing an embodiment (3) of the memory control apparatus according to the present invention.
FIG. 12 is a block diagram showing a conventional memory control device.
FIG. 13 is a diagram illustrating signal timing of a conventional memory control device.
FIG. 14 is a diagram showing signal timing of a conventional memory control device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Memory device 2 Clock phase controller 3 Synchronous memory 4 Memory control signal register 5 Output data register 6 Input data register 21-2n Delay device 100 Memory access control signal 101 Write data signal 102 Read data signal 103 Reference clock 104 Output clock phase control Signal 105 input clock phase control signal 106 memory clock phase control signal 107 output clock 108 input clock 109 memory clock 110 control signal 111 data signal 210 to 21n delay clock 251 switch 261 switch 271 switch

Claims (3)

Outputs the memory clock that operates the clock synchronous memory and the memory access control signal input to the memory control signal register to the clock synchronous memory, and outputs the write data signal input to the output data register to the clock synchronous memory A clock phase controller that generates an output clock that generates an input clock that outputs a read data signal input to the input data register from the clock synchronous memory;
This clock phase controller inputs a plurality of delay clocks generated by shifting the phase of each clock from a reference clock by a plurality of delay units to a switch corresponding to a memory clock, an output clock, and an input clock, It is generated by selecting one delay clock by a phase control signal corresponding to a memory clock, an output clock and an input clock,
The output clock delays the sum of the memory access control signal valid time from the rise of the reference clock and the setup time of the memory control signal register, and the memory clock is the time from the rise of the reference clock to the rise of the output clock and the memory. Delays the sum of the control signal valid time of the control signal register and the setup time of the clock synchronous memory, and the input clock is the time from the rising edge of the reference clock to the rising edge of the memory clock and the data signal valid time of the clock synchronous memory And a clock control apparatus that delays a time obtained by adding the setup time of the input data register. 2. The clock control device according to claim 1, wherein the delay unit of the clock phase controller has different delay characteristics corresponding to the memory clock, the output clock, and the input clock. The clock phase controller receives a memory clock, an output clock, and a reference clock, selects a clock with a phase control signal corresponding to the output clock, and outputs the selected clock to a delay device; an output clock, an input clock, and a reference A switch that inputs a clock and selects one clock by a phase control signal corresponding to the memory clock and outputs it to the delay device; and a phase control signal that corresponds to the input clock by inputting the output clock, the memory clock, and the reference clock 3. A clock control apparatus according to claim 2, further comprising a switch for selecting one clock and outputting to the delay unit.

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