JP3731523B2 - Semiconductor element - Google Patents

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JP3731523B2
JP3731523B2 JP2001318796A JP2001318796A JP3731523B2 JP 3731523 B2 JP3731523 B2 JP 3731523B2 JP 2001318796 A JP2001318796 A JP 2001318796A JP 2001318796 A JP2001318796 A JP 2001318796A JP 3731523 B2 JP3731523 B2 JP 3731523B2
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JP2003124465A (en
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達司 永岡
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、第一導電型領域と第二導電型領域とを交互に配置した並列ｐｎ層を有する半導体素子について、高耐圧化を可能にする構造に関するものであり、ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）、バイポーラトランジスタ等に適用可能である。
【０００２】
【従来の技術】
一般に半導体素子は、片面に電極部をもつ横型素子と、両面に電極をもつ縦型素子とに大別される。縦型半導体素子は、オン時にドリフト電流が流れる方向と、オフ時の逆バイアス電圧による空乏層が延びる方向とが同じである。
例えば、通常の縦型ＭＯＳＦＥＴにおいて、ｎ型ドリフト領域の部分は、オン状態の時は縦方向にドリフト電流を流す電流経路として働き、オフ状態の時は空乏化して耐圧を高める。
【０００３】
そのｎ型ドリフト領域の電流経路を短くすることは、ｎ型ドリフト領域の抵抗分が低くなるので、実質的なオン電圧を下げる効果に繋がる。しかし耐圧を担うｐｎ接合から空乏層が広がる幅が狭く、シリコンの臨界電界強度に早く達するため、耐圧が低下してしまう。逆に耐圧の高い半導体装置では、ｎ型ドリフト領域が厚くなるため、必然的にオン電圧が大きくなり、損失が増すことになる。
【０００４】
すなわちオン電圧と耐圧との間にトレードオフ関係がある。このトレードオフ関係は、ＭＯＳＦＥＴ、ＩＧＢＴ、バイポーラトランジスタ、ｐｎダイオード等の半導体素子においても同様に成立することが知られている。また、この問題は、オン時にドリフト電流が流れる方向と、オフ時の逆バイアスによる空乏層の延びる方向が異なる横型半導体素子についても共通である。
【０００５】
このオン電圧と耐圧とのトレードオフ関係の問題に対する解決法として、ドリフト領域を、不純物濃度を高めたｎ型の領域とｐ型の領域を交互に配置した並列ｐｎ層で構成し、オフ状態の時は空乏化して耐圧を負担するようにした構造の半導体装置が、ＥＰ００５３８５４、ＵＳＰ５２１６２７５、ＵＳＰ５４３８２１５、特開平９−２６６３１１号および特開２０００−４０８２２号の公報に開示されている。
【０００６】
並列ｐｎ層の不純物濃度が高くても、オフ状態では並列ｐｎ層の縦方向に配向する各ｐｎ接合から空乏層がその横方向双方に拡張し、ドリフト領域全体を空乏化するため、高耐圧化を図ることができる。
なお本発明の発明者らは、オン状態では電流を流し、オフ状態では空乏化するドリフト層からなる並列ｐｎ層を備える半導体素子を超接合半導体素子と称することとする。
【０００７】
【発明が解決しようとする課題】
オン状態では電流を流すとともに、オフ状態では空乏化する並列ｐｎ層のｎ型の領域とｐ型の領域の形状は、最も単純な形状として通常薄板状とされることが多い。
並列ｐｎ層の二次元的な広がりは、その素子の大きさに合わせて必然的に制限される。したがって並列ｐｎ層の各ｎ型領域あるいはｐ型領域の、薄板状の主面に平行な方向の長さは有限であり、各領域の両側で途切れたところが端面となって現れる。また、ｎ型領域とｐ型領域とを繰り返した最も外側ではｎ型領域あるいはｐ型領域がむき出しとなる。
【０００８】
このような素子において並列ｐｎ層の外周での電界集中を緩和するためには、例えば高抵抗層を周辺構造部として用い、その高抵抗層の不純物濃度を調節する（特開２００１−１５７５２号公報）などの手段が採られる。
図１０はそのような超接合半導体素子の並列ｐｎ層部分の斜視断面図である。
縦形薄板状のｎ型ドリフト領域１ａと縦形薄板状のｐ型仕切領域１ｂとを交互に繰り返して接合した並列ｐｎ層１の周囲に電界集中を緩和するための高比抵抗領域２０が配置されており、更にその周囲にチャネルストッパ１４が配置されている。
【０００９】
縦型ＭＯＳＦＥＴであれば、並列ｐｎ層１の上方にベース領域、ソース領域、ゲート電極等が設けられる。
しかしながら、図１０の構造では、並列ｐｎ層１の各領域の端面と周辺構造部としての高比抵抗領域２０との境界（図１０のＡ−Ａ’線）、並列ｐｎ層１の最も外側に配置されたｎ型ドリフト領域１ａあるいはｐ型仕切領域１ｂと高比抵抗領域２０との境界（図１０のＢ−Ｂ’線）とで電界分布が異なるため、双方の境界について最適な接続をすることが困難であり、耐圧を確保しにくいという問題がある。例えば耐圧が６００V 級のＭＯＳＦＥＴを試作しても、境界の接合構造が適正でないと、耐圧が３００V しか得られないことがあった。
【００１０】
この発明の課題は、並列ｐｎ層と周辺構造部との境界のうち、並列ｐｎ層の各領域の端面と周辺構造部との境界を無くすことにより、並列ｐｎ層と周辺構造部とを接触して配置する際の電界集中を回避することを容易にし、高耐圧を確保することにある。
【００１１】
【課題を解決するための手段】
上記の課題を解決する手段として、並列ｐｎ層の各ｎ型領域あるいはｐ型領域の両側にある端面を互いに接続して環状の並列ｐｎ層を配置した構造を考案した。
すなわち、第一と第二の主面と、その第一と第二の主面間に、第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列ｐｎ層と低抵抗層とを有し、第一と第二の主面にそれぞれ設けられた第一、第二の二つの主電極を備える半導体素子において、並列ｐｎ層の各ｎ型領域あるいはｐ型領域が平面的に環状であるものとする。
【００１２】
このような構造では並列ｐｎ層全体に空乏層が広がって耐圧を維持するとともに、幾何学的に端面が無くなるため、周辺構造部との境界では並列ｐｎ層の最も外側に配置されたｎ型領域あるいはｐ型領域との接続のみとなるので、境界での電界集中を回避することが容易となり、安定的に高い耐圧を確保できるようになる。
【００１３】
前記環状の並列ｐｎ層が、高抵抗領域、真性半導体領域あるいは絶縁体層の一つ、又はそれらを複合した領域を中心にして配置されていても良い。例えば、絶縁体層を介した高抵抗領域を中心にして配置されていてもよい。
そのような構造でも、周囲の並列ｐｎ層は逆電圧印加時に空乏化する。
そして前記並列ｐｎ層の第一導電型領域と第二導電型領域の不純物濃度が外周に行くにしたがって低くなっているものとする。
【００１４】
並列ｐｎ層の各ｎ型領域あるいはｐ型領域の環の幅が同じであると、外周に向かうにしたがってその体積が大きくなって行くので、逆にそれぞれの不純物濃度を外周に向かって低くして行くことにより、不純物量を等しくして逆電圧印加時の空乏化を容易にすることができる。
または、素子の中心の第一導電型領域あるいは第二導電型領域の全幅と、それ以外の第一導電型領域あるいは第二導電型領域の環の幅とが外周に行くにしたがって小さくなっているものとする。
【００１５】
素子の中心に、高抵抗領域、真性半導体領域或いは絶縁体層の一つ、又はそれらを複合した層があるものでは、素子の中心に最も近い第１導電型領域と、素子の中心に最も近い第１導電型領域の外周に隣接し、素子の中心に最も近い第１導電型領域の環の幅の 2 倍の環の幅を有する第２導電型領域と、
並列ｐｎ層が素子の中心に最も近い第１導電型領域の環の幅の 2 倍の環の幅を有する第２導電型領域から外周に行くにしたがって環の幅が小さくなるものとする。先に記した不純物濃度を変える方法とは別の手段として、並列ｐｎ層の各ｎ型領域あるいはｐ型領域の幅を変化させることも可能である。この場合、外周に向かうにしたがって並列ｐｎ層の各ｎ型領域あるいはｐ型領域の環の周の長さが長くなるので、それに応じて幅を狭くして行くことで実現される。そのようにすれば、逆電圧印加時に周囲の並列ｐｎ層は効率良く空乏化する。
【００１６】
素子の中心または素子の中心に最も近い第一導電型領域あるいは第二導電型領域を除く他の隣接する第一導電型領域と第二導電型領域の環において、内側の環の幅方向における外側半分と、外側の環の幅方向における内側半分とに含まれる不純物量がほぼ等しいものとする。
逆電圧印加時に周囲の並列ｐｎ層を空乏化させ、効率的に耐圧を確保するためには各々のｐｎ接合における空乏層の広がり具合が素子全体にわたって均等になる必要がある。そのためには、並列ｐｎ層の隣接するｎ型領域、ｐ型領域の内側の環の外側半分の総不純物量と、外側の環の内側半分の総不純物量とが等しくなるようにするのが効果的である。
【００１７】
前記並列ｐｎ層は、同心円状に配置されていてもよい。
円は、環状の最も簡単な形状の一つである。
前記並列ｐｎ層の周囲が第一導電型チャネルストツパで囲まれているものとする。
素子チップの外周部に第一導電型チャネルストツパを設けることにより、外周表面での耐圧不安定を解消できる。
【００１８】
環状の並列ｐｎ層をもつ半導体素子を、並列に複数個備えた複合型の半導体素子とすることもできる。
その複合型の半導体素子の周囲が第一導電型チャネルストッパで囲まれていても良い。
前記並列ｐｎ層の周囲が第一導電型または第二導電型の高比抵抗領域で囲まれているものとすることもできる。
【００１９】
高比抵抗領域で囲むことにより、逆電圧印加時の空乏層の広がりを促進することができる。
更にその高比抵抗領域の周囲が高抵抗領域と同じ導電型のチャネルストッパで囲まれているものとする。
素子チップの外周部にチャネルストツパを設けることにより、外周表面での耐圧不安定を解消できる。
【００２０】
並列ｐｎ層の周囲が第一導電型または第二導電型の高比抵抗領域で囲まれている半導体素子を、並列に複数個備えた複合型の半導体素子とすることもできる。
更にその周囲が高比抵抗領域と同じ導電型のチャネルストッパで囲まれているものとする。
【００２１】
素子チップの外周部にチャネルストツパを設けることにより、外周表面での耐圧不安定を解消できる。
チャネルストッパに接触するチャネルストッパ電極が設けられていれば、チャネルストッパ領域の電位が確定される。
【００２２】
【発明の実施の形態】
［実施例１］
図２は、本発明第一の実施例の超接合縦形ＭＯＳＦＥＴの主要部の断面図である。図の左側がチップの中心、図の右側がチップの端である。
通常の縦型ＭＯＳＦＥＴのｎ型ドリフト層の代わりに、ｎ型ドリフト領域１ａとｐ型仕切り領域１ｂとからなる並列ｐｎ層１がある。ｐ型仕切り領域１ｂの上方に内部にｎ型ソース領域５を持つｐ型ベース領域３が形成されている。ｎ型ソース領域５とｎ型ドリフト領域１ａとに挟まれたｐ型ベース領域３の表面上にゲート酸化膜６を介してゲート電極７が設けられている。ｎ型ソース領域５とｐ型ベース領域３との表面に共通に接触してソース電極９が設けられている。ソース電極９はこのように層間絶縁膜８を介してゲート電極７上に延長しても良い。並列ｐｎ層１の下方にはｎ+ 型ドレイン層１２があり、その裏面にドレイン電極１３が設けられている。１１は並列ｐｎ層１と同様にｎ型領域１１ａとｐ型領域１１ｂとが交互に配置された周辺ｐｎ層である。１４は漏れ電流を低減させることを目的としたチャネルストッパであり、その表面にチャネルストッパ電極１５が設けられている。１０は周辺領域１１上の厚いフィールド酸化膜である。
【００２３】
図では分かりやすくするため、中心側から順にｎ型ドリフト領域１ａ、ｐ型仕切り領域１ｂ、周辺ｐｎ層１１のｎ型領域１１ａおよびｐ型領域１１ｂが、活性部と周辺構造部とを併せて５回繰り返されているが、この数は素子により任意に選ぶことができ、通常はもっと多い。
図１は図２のＣ−Ｃ’線位置での素子の断面図である。
【００２４】
並列ｐｎ層１の各ｎ型ドリフト領域１ａおよびｐ型仕切り領域１ｂが同心円状に配置され、また周辺ｐｎ層１１として活性部と同様の並列ｐｎ構造を用い、そのｎ型領域１１ａおよびｐ型領域１１ｂが同心円状に配置されている。さらにその周りにチャネルストッパ１４が見られる。
中心のｎ型ドリフト領域１ａの直径と、それ以外のｎ型ドリフト領域１ａ、ｐ型仕切り領域１ｂ、周辺構造部１１のｎ型領域１１ａおよびｐ型領域１１ｂの幅は全て同じである。
【００２５】
但し、終端に相当する最も外側の環がｐ型領域となっており、それがチャネルストッパ１４と接している。 なお、その繰り返しの始まりの層あるいは終わりの層はｎ型領域であってもｐ型領域であってもその構造の性質は同等である。これらの事項は以下の実施例のすべてにおいて当てはまることであり、それぞれの説明の中では省略するが、同様に適用される。
【００２６】
各領域の不純物濃度は、素子全体で均一に空乏層が広がるようにそれぞれの不純物濃度を図のようにＮn1、Ｎp1、Ｎn2、‥、Ｎn5、Ｎp5とするとき、Ｎn1＞Ｎp1＞Ｎn2＞‥＞Ｎn5＞Ｎp5であり、隣接する二つの環の幅の半分の部分の不純物の総量が互いに等しくなるようにする。
定量的には、次式が成り立つ、d は環の幅、i は整数である。
【００２７】
【数１】

Figure 0003731523
図１、２の超接合ＭＯＳＦＥＴは、ｎ型仕切り領域１ａ、ｐ型仕切り領域１ｂおよび周辺構造のｎ型領域１１ａ、ｐ型領域１１ｂが環状で端が無いため、終端部での電界集中が回避されて、高耐圧化できる。
【００２８】
この並列ｐｎ層のｎ型領域とｐ型領域は素子全体にわたって交互に繰り返されていれば良く、その繰り返しの数は目的とするデバイス特性に合わせて任意に決められる。
それぞれの環の形は本質的にはどのようなものであっても良いが、並列ｐｎ層における電界緩和や並列ｐｎ層と周辺構造部との接続最適化をより容易に行うためには、なるべく対称性の良い形状で同心状に配置することが望ましい。
【００２９】
またｐｎ接合における空乏層の広がり具合は、その接合面の曲率に依存する。そのため環状型の並列ｐｎ層では、すべてのｐｎ接合で均一に空乏層が広がるように各ｎ型領域とｐ型領域のピッチ幅あるいは不純物濃度が、その領域と隣り合う領域との間のｐｎ接合面の曲率に応じて決められる。
なお、本実施例は耐圧が６００V 級であり、各部の寸法及び不純物濃度等は次のような値をとる。並列ｐｎ層１の厚さ４０μm 、中央のｎ型ドリフト領域１ａの直径８μm、不純物濃度２．０×１０15cm-3、次のｐ型仕切り領域１ｂ以降の幅（ｄ）８μm、不純物濃度は上式による。ｎ+ ドレイン層４の厚さ３００μm、不純物濃度２．０×１０18cm-3である。
【００３０】
実際に試作して６００V の耐圧を確認した。
［実施例２］
図４は、本発明第二の実施例の超接合縦形ＭＯＳＦＥＴの主要部の断面図である。図の左側がチップの中心側、図の右側がチップの端である。
図２の実施例１のＭＯＳＦＥＴとの違いは、並列ｐｎ層１の中心が高比抵抗の真性半導体領域（以下ｉ領域と記す）１６である点、および中心ｉ領域１６に隣接するｎ型ドリフト領域１ａの幅が、他の部分の半分とされている点である。
【００３１】
これは、隣接するｎ型領域の半分とｐ型領域の半分とで互いに電子と正孔とが補償しあって空乏化するが、中心のｎ型領域はその内側にｐ型領域が無いため、同じ幅であると非空乏化領域が残ってしまい、耐圧が出なくなるので、それを防ぐためである。
実施例１では中心のｎ型領域の直径が、外側のｐ型領域およびｎ型領域の環の幅と等しくなっていた。但し、実施例１では中心のｎ型領域の直径を小さくし過ぎると、その上に形成されるソース電極またはゲート電極の作り込みが困難になる。これに対して実施例２のように中心をｉ領域とすると、その周りの環の設計の自由度を向上できる利点がある。
【００３２】
各領域の不純物濃度は、素子全体で均一に空乏層が広がるようにそれぞれの不純物濃度をＮn1、Ｎp1、Ｎn2、‥、Ｎn5、Ｎp5とするとき、Ｎn1＞Ｎp1＞Ｎn2＞‥＞Ｎn5＞Ｎp5である。定量的には、実施例１と同様にして隣接する二つの環の幅の半分の部分の不純物の総量が互いに等しくなるようにする。
図３は図４のＤ−Ｄ’線に沿った断面図である。
【００３３】
並列ｐｎ層１の各ｎ型ドリフト領域１ａおよびｐ型仕切り領域１ｂが同心円状に配置され、また周辺構造部１１として活性部と同様に並列ｐｎ層を用い、そのｎ型領域１１ａおよびｐ型領域１１ｂが同心円状に配置されている。さらにその周りにチャネルストッパ１４が見られる。
実施例２の超接合ＭＯＳＦＥＴも、ｎ型仕切り領域１ａ、ｐ型仕切り領域１ｂが環状で端が無いため、終端部での電界集中が回避されて、高耐圧化できる。
【００３４】
また、この例では周辺構造部として高比抵抗領域２０を用いている。このような場合でも、活性部と周辺構造部との境界では活性部の最外周に配置されたｐ型領域の環と高比抵抗領域２０の接続だけであるので、電界集中の回避が容易である。
実施例２で真性半導体領域とした中心部分は、高抵抗領域や絶縁体層、あるいはそれらを複合した層であっても良い。例えば絶縁体層を介して配置される高抵抗領域であっても良い。そのような場合も周囲の並列ｐｎ層は容易に空乏化される。
【００３５】
［実施例３］
図６は、本発明第三の実施例の超接合縦形ＭＯＳＦＥＴの主要部の断面図である。図の左側がチップの中心側、図の右側がチップの端である。
図２の実施例１のＭＯＳＦＥＴとの違いは、並列ｐｎ層１のｎ型ドリフト領域１ａ、ｐ型仕切り領域１ｂ、および周辺ｐｎ層１１のｎ型領域１１ａ、ｐ型領域１１ｂの不純物濃度を一定とし、その代わりにそれぞれの幅を次第に狭くしている点である。
【００３６】
図では分かりやすくするため、中心側から順にｎ型ドリフト領域１ａ、ｐ型仕切り領域１ｂ、周辺ｐｎ層１１のｎ型領域１１ａおよびｐ型領域１１ｂが、活性部と周辺構造部とを併せて６回繰り返されているが、この数は素子により任意に選ぶことができ、通常はもっと多い。
図５は図６のＥ−Ｅ’線に沿った水平断面図である。
【００３７】
並列ｐｎ層１の各ｎ型ドリフト領域１ａおよびｐ型仕切り領域１ｂが同心円状に配置され、また周辺ｐｎ層１１として活性部と同様に並列ｐｎ層を用い、そのｎ型領域１１ａおよびｐ型領域１１ｂが同心円状に配置されている。さらにその周りにチャネルストッパ１４が見られる。
並列ｐｎ層が環状であると、外周に向かうにしたがって各領域の円周が大きくなっていくので、外周に向かうにしたがって各領域の幅を狭くしていくことで、空乏層の広がりを均等にしいいる。
【００３８】
［実施例４］
図８は、本発明第四の実施例の超接合縦形ＭＯＳＦＥＴの主要部の断面図である。図の左側がチップの中心側、図の右側がチップの端である。
図６の実施例３のＭＯＳＦＥＴとの違いは、この例では並列ｐｎ層の中心に絶縁層１８を介して高抵抗領域１７を配置している点、および並列ｐｎ層１の外側に周辺構造部（エッジ部の影響を避けるために素子周辺部の耐圧を高め、耐圧特性が素子の内部側で決定されるようにするための構造）として高比抵抗領域２０を配置している点である。この高比抵抗領域２０は、逆電圧印加時に、即座に空乏化して耐圧を維持する。そして並列ｐｎ層１のｎ型ドリフト領域１ａ、ｐ型仕切り領域１ｂの不純物濃度を一定とし、その代わりにそれぞれの幅を次第に狭くしている点は実施例３と同じである。
【００３９】
中心の高抵抗領域１７の周囲には絶縁体層１８を介して不純物濃度が一定の同心円状の並列ｐｎ層１を配置しており、すなわち、中心のｎ型ドリフト領域１ａの直径をｄn1、その周囲の各領域の幅をｄp1、ｄn2、‥、ｄn3、ｄp3とするとき、ｄn1＞ｄp1＞ｄn2＞‥＞ｄn3＞ｄp3である。定量的には、隣接する二つの環の幅の半分の部分の不純物の総量が互いに等しくなるようにして、素子全体で均一に空乏層が広がるようにしている。ここでは中心の最も近くに配置されているｎ型領域の幅を２倍に換算している。
【００４０】
図７は図８のＦ−Ｆ’線に沿った水平断面図である。
並列ｐｎ層１の各ｎ型ドリフト領域１ａおよびｐ型仕切り領域１ｂが同心円状に配置され、また周辺ｐｎ層１１として活性部と同様に並列ｐｎ層を用い、そのｎ型領域１１ａおよびｐ型領域１１ｂが同心円状に配置されている。さらにその周りにチャネルストッパ１４が見られる。
【００４１】
実施例４の超接合ＭＯＳＦＥＴも、ｎ型仕切り領域１ａ、ｐ型仕切り領域１ｂおよび周辺のｎ型領域１１ａ、ｐ型領域１１ｂが環状で端が無いため、終端部での電界集中が回避されて、高耐圧化できる。
中心の高抵抗領域１７の代わりに、真性半導体領域や絶縁体層、あるいはそれらの複合した層であっても良い。
【００４２】
［実施例５］
図９は、本発明第五の実施例の超接合縦形ＭＯＳＦＥＴの下部の水平断面図である。
この例では実施例２に示した素子からチャネルストッパ１４を取り除いたものと同様な構造を持つ複数の素子を平面的に格子状に配置し、その周囲をチャネルストッパ１４で囲んでいる。
【００４３】
図では全く同じ構造を持つ素子４個を規則的に配置しているが、個々の素子は必ずしも同じ構造である必要はなく、またその個数や配置の仕方も目的とするデバイス特性に合わせて任意に決められる。
【００４４】
【発明の効果】
以上説明したように本発明によれば、第一と第二の主面と、その第一と第二の主面間に第一導電型領域と第二導電型領域とを交互に配置した並列ｐｎ層と低抵抗層とを有し、第一と第二の主面にそれぞれ設けられた第一、第二の二つの主電極を備える半導体素子において、並列ｐｎ層の第一導電型領域と第二導電型領域とを平面的に環状とすることによって、従来並列ｐｎ層と周辺構造部との境界で見られた電界集中を回避することが容易となり、高い耐圧を確保することができる。
【００４５】
環状の並列ｐｎ層の第一導電型領域と第二導電型領域の不純物濃度を外周に行くにしたがって低くし、或いは環の幅を外周に行くにしたがって小さくする。
縦型半導体素子の耐圧とオン電圧とのトレードオフ関係を大幅に改善できる超接合半導体素子において、並列ｐｎ層の周辺構造部との境界の問題を解決し、安定して高耐圧を実現できる本発明は、超接合半導体素子の普及、発展に画期的な寄与をなすものである。
【図面の簡単な説明】
【図１】本発明実施例１の超接合ＭＯＳＦＥＴの並列ｐｎ層部分（図２Ｃ−Ｃ’線）の水平断面図。
【図２】本発明実施例１の超接合ＭＯＳＦＥＴの部分断面図
【図３】本発明実施例２の超接合ＭＯＳＦＥＴの並列ｐｎ層部分（図４Ｄ−Ｄ’線）の水平断面図。
【図４】本発明実施例２の超接合ＭＯＳＦＥＴの部分断面図
【図５】本発明実施例３の超接合ＭＯＳＦＥＴの並列ｐｎ層部分（図６Ｅ−Ｅ’線）の水平断面図。
【図６】本発明実施例３の超接合ＭＯＳＦＥＴの部分断面図
【図７】本発明実施例４の超接合ＭＯＳＦＥＴの並列ｐｎ層部分（図８Ｆ−Ｆ’線）の水平断面図。
【図８】本発明実施例４の超接合ＭＯＳＦＥＴの部分断面図
【図９】本発明実施例５の超接合ＭＯＳＦＥＴの並列ｐｎ層部分の水平断面図。
【図１０】従来の超接合半導体素子の下部の斜視断面図
【符号の説明】
1：並列pn層
1a：n型ドリフト領域
1b：P型仕切り領域
3：P型べ−ス領域
4：表面n型ドリフト領域
5：n+ 型ソース領域
6：ゲート絶縁膜
7：ゲート電極
8：層間絶縁膜
9：ソース電極
10：フィールド酸化膜
11：周辺pn層
11a：周辺n型領域
11b：周辺P型領域
12：n+ 型ドレイン領域
13：ドレイン電極、
14：チャネルストッパ
15：チャネルストッパ電極
16：i領域
17：高抵抗領域
18: 絶縁体層
20：高比抵抗領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure capable of increasing the breakdown voltage of a semiconductor element having parallel pn layers in which first conductivity type regions and second conductivity type regions are alternately arranged. Transistor), IGBT (insulated gate bipolar transistor), bipolar transistor and the like.
[0002]
[Prior art]
In general, semiconductor elements are broadly classified into horizontal elements having electrode portions on one side and vertical elements having electrodes on both sides. In the vertical semiconductor element, the direction in which the drift current flows when turned on is the same as the direction in which the depletion layer extends due to the reverse bias voltage when turned off.
For example, in a normal vertical MOSFET, the n-type drift region portion functions as a current path through which a drift current flows in the vertical direction in the on state, and is depleted in the off state to increase the breakdown voltage.
[0003]
Shortening the current path in the n-type drift region reduces the resistance of the n-type drift region, leading to the effect of reducing the substantial on-voltage. However, the width of the depletion layer extending from the pn junction that bears the breakdown voltage is narrow and reaches the critical electric field strength of silicon quickly, so that the breakdown voltage decreases. On the other hand, in a semiconductor device with a high breakdown voltage, the n-type drift region is thick, so that the on-voltage is inevitably increased and the loss is increased.
[0004]
That is, there is a trade-off relationship between the ON voltage and the breakdown voltage. It is known that this trade-off relationship holds similarly in semiconductor elements such as MOSFETs, IGBTs, bipolar transistors, and pn diodes. This problem is also common to lateral semiconductor elements in which the direction in which the drift current flows when on and the direction in which the depletion layer extends due to the reverse bias when off is different.
[0005]
As a solution to the problem of the trade-off relationship between the on-voltage and the withstand voltage, the drift region is composed of parallel pn layers in which n-type regions and p-type regions having an increased impurity concentration are alternately arranged, and the off-state A semiconductor device having a structure that is depleted and bears a withstand voltage is disclosed in EP0053854, USP5216275, USP5438215, JP-A-9-266611, and JP-A-2000-40822.
[0006]
Even if the impurity concentration of the parallel pn layer is high, the depletion layer extends in both the lateral direction from each pn junction oriented in the vertical direction of the parallel pn layer in the off state, and the entire drift region is depleted, so that the withstand voltage is increased. Can be achieved.
The inventors of the present invention refer to a semiconductor element including a parallel pn layer formed of a drift layer that flows a current in an on state and is depleted in an off state as a super junction semiconductor element.
[0007]
[Problems to be solved by the invention]
The shape of the n-type region and the p-type region of the parallel pn layer that flows current in the on state and is depleted in the off state is usually a thin plate as the simplest shape in many cases.
The two-dimensional expansion of the parallel pn layer is necessarily limited according to the size of the element. Therefore, the length of each n-type region or p-type region of the parallel pn layer in the direction parallel to the thin plate-like main surface is finite, and the portions where the regions are interrupted on both sides appear as end surfaces. Further, the n-type region or the p-type region is exposed on the outermost side where the n-type region and the p-type region are repeated.
[0008]
In such an element, in order to alleviate the electric field concentration on the outer periphery of the parallel pn layer, for example, a high resistance layer is used as a peripheral structure, and the impurity concentration of the high resistance layer is adjusted (Japanese Patent Laid-Open No. 2001-157552). ) Etc. are taken.
FIG. 10 is a perspective sectional view of a parallel pn layer portion of such a superjunction semiconductor element.
A high specific resistance region 20 for relaxing electric field concentration is disposed around a parallel pn layer 1 in which a vertical thin plate-like n-type drift region 1a and a vertical thin plate-like p-type partition region 1b are joined alternately. Further, a channel stopper 14 is disposed around the periphery.
[0009]
In the case of a vertical MOSFET, a base region, a source region, a gate electrode, and the like are provided above the parallel pn layer 1.
However, in the structure of FIG. 10, the boundary (AA ′ line in FIG. 10) between the end face of each region of the parallel pn layer 1 and the high resistivity region 20 as the peripheral structure portion, on the outermost side of the parallel pn layer 1. Since the electric field distribution is different at the boundary between the n-type drift region 1a or p-type partition region 1b and the high specific resistance region 20 (BB 'line in FIG. 10), optimal connection is made at both boundaries. There is a problem that it is difficult to secure a withstand voltage. For example, even if a MOSFET with a withstand voltage of 600V class is prototyped, the withstand voltage of only 300V may be obtained if the boundary junction structure is not appropriate.
[0010]
An object of the present invention is to contact the parallel pn layer and the peripheral structure portion by eliminating the boundary between the end face of each region of the parallel pn layer and the peripheral structure portion among the boundaries between the parallel pn layer and the peripheral structure portion. It is easy to avoid electric field concentration when arranging and to secure a high breakdown voltage.
[0011]
[Means for Solving the Problems]
As means for solving the above problems, a structure has been devised in which each n-type region of the parallel pn layer or end faces on both sides of the p-type region are connected to each other and an annular parallel pn layer is arranged.
That is, the first and second main surfaces, and the parallel pn layer and the low resistance layer in which the first conductivity type drift regions and the second conductivity type partition regions are alternately arranged between the first and second main surfaces. And each of the n-type region or the p-type region of the parallel pn layer is planar in a semiconductor device including first and second main electrodes provided on the first and second main surfaces, respectively. It shall be circular.
[0012]
In such a structure, the depletion layer spreads over the entire parallel pn layer to maintain the withstand voltage, and the end face is geometrically eliminated. Therefore, the n-type region disposed on the outermost side of the parallel pn layer at the boundary with the peripheral structure portion Alternatively, since only the connection with the p-type region is provided, it is easy to avoid electric field concentration at the boundary, and a high breakdown voltage can be secured stably.
[0013]
The annular parallel pn layer may be arranged centering on one of a high resistance region, an intrinsic semiconductor region, an insulator layer, or a composite region thereof. For example, you may arrange | position centering on the high resistance area | region through an insulator layer.
Even in such a structure, the surrounding parallel pn layer is depleted when a reverse voltage is applied.
It is assumed that the impurity concentration of the first conductivity type region and the second conductivity type region of the parallel pn layer decreases as it goes to the outer periphery.
[0014]
If the width of each n-type region or p-type region ring in the parallel pn layer is the same, the volume increases toward the outer periphery. Conversely, the respective impurity concentrations are decreased toward the outer periphery. By going, it is possible to equalize the amount of impurities and facilitate depletion when a reverse voltage is applied.
Alternatively, the full width of the first conductivity type region or the second conductivity type region at the center of the element and the width of the ring of the other first conductivity type region or the second conductivity type region become smaller toward the outer periphery. Shall.
[0015]
In the case where there is one of a high resistance region, an intrinsic semiconductor region or an insulator layer, or a composite layer thereof in the center of the element, the first conductivity type region closest to the center of the element and the closest to the center of the element adjacent the outer periphery of the first conductivity type region, a second conductivity type region having a width of twice the ring nearest the width of the rings of the first conductivity type region in the center of the element,
Parallel pn layer is assumed that the width of the ring toward the outer periphery of the second conductivity type region having twice the width of the ring nearest the width of the rings of the first conductivity type region in the center of the element is reduced. As a means different from the method for changing the impurity concentration described above, it is also possible to change the width of each n-type region or p-type region of the parallel pn layer. In this case, the length of the circumference of each n-type region or p-type region ring of the parallel pn layer becomes longer toward the outer periphery, so that the width is reduced accordingly. By doing so, the surrounding parallel pn layer is efficiently depleted when a reverse voltage is applied.
[0016]
In the ring of the inner ring in the width direction of the inner ring in the ring of the first conductive type region or the second conductive type region other than the first conductive type region or the second conductive type region closest to the center of the element. It is assumed that the amount of impurities contained in the half and the inner half in the width direction of the outer ring are substantially equal.
In order to deplete surrounding parallel pn layers when a reverse voltage is applied and to ensure a breakdown voltage efficiently, it is necessary that the degree of spread of the depletion layers in each pn junction is uniform over the entire device. For this purpose, it is effective to make the total impurity amount in the outer half of the inner ring of the adjacent n-type region and p-type region of the parallel pn layer equal to the total impurity amount in the inner half of the outer ring. Is.
[0017]
The parallel pn layers may be arranged concentrically.
The circle is one of the simplest circular shapes.
It is assumed that the parallel pn layer is surrounded by a first conductivity type channel stopper.
By providing the first conductivity type channel stopper on the outer peripheral portion of the element chip, it is possible to eliminate the breakdown voltage instability on the outer peripheral surface.
[0018]
A composite semiconductor element including a plurality of semiconductor elements each having an annular parallel pn layer may be provided.
The periphery of the composite type semiconductor element may be surrounded by a first conductivity type channel stopper.
The periphery of the parallel pn layer may be surrounded by a high resistivity region of the first conductivity type or the second conductivity type.
[0019]
By enclosing with a high specific resistance region, it is possible to promote the spread of the depletion layer when a reverse voltage is applied.
Further, it is assumed that the periphery of the high specific resistance region is surrounded by a channel stopper having the same conductivity type as that of the high resistance region.
By providing a channel stopper on the outer peripheral portion of the element chip, instability of the breakdown voltage on the outer peripheral surface can be eliminated.
[0020]
A composite semiconductor element including a plurality of semiconductor elements each having a parallel pn layer surrounded by a high specific resistance region of the first conductivity type or the second conductivity type in parallel may be used.
Further, it is assumed that the periphery is surrounded by a channel stopper having the same conductivity type as that of the high specific resistance region.
[0021]
By providing a channel stopper on the outer peripheral portion of the element chip, instability of the breakdown voltage on the outer peripheral surface can be eliminated.
If a channel stopper electrode that contacts the channel stopper is provided, the potential of the channel stopper region is determined.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
[Example 1]
FIG. 2 is a cross-sectional view of the main part of the superjunction vertical MOSFET of the first embodiment of the present invention. The left side of the figure is the center of the chip, and the right side of the figure is the end of the chip.
Instead of the n-type drift layer of a normal vertical MOSFET, there is a parallel pn layer 1 composed of an n-type drift region 1a and a p-type partition region 1b. A p-type base region 3 having an n-type source region 5 therein is formed above the p-type partition region 1b. A gate electrode 7 is provided via a gate oxide film 6 on the surface of the p-type base region 3 sandwiched between the n-type source region 5 and the n-type drift region 1a. A source electrode 9 is provided in common contact with the surfaces of the n-type source region 5 and the p-type base region 3. The source electrode 9 may be extended on the gate electrode 7 through the interlayer insulating film 8 in this way. Below the parallel pn layer 1 is an n + -type drain layer 12, and a drain electrode 13 is provided on the back surface thereof. Reference numeral 11 denotes a peripheral pn layer in which n-type regions 11a and p-type regions 11b are alternately arranged as in the parallel pn layer 1. Reference numeral 14 denotes a channel stopper for the purpose of reducing leakage current, and a channel stopper electrode 15 is provided on the surface thereof. Reference numeral 10 denotes a thick field oxide film on the peripheral region 11.
[0023]
For easy understanding in the figure, the n-type drift region 1a, the p-type partition region 1b, the n-type region 11a and the p-type region 11b of the peripheral pn layer 11 in order from the center side include the active portion and the peripheral structure portion. This number is repeated, but this number can be chosen arbitrarily depending on the element, and is usually much higher.
FIG. 1 is a cross-sectional view of the element taken along the line CC ′ of FIG.
[0024]
Each n-type drift region 1a and p-type partition region 1b of the parallel pn layer 1 are arranged concentrically, and the peripheral pn layer 11 uses a parallel pn structure similar to that of the active portion, and the n-type region 11a and the p-type region 11b is arranged concentrically. Furthermore, the channel stopper 14 is seen around it.
The diameter of the central n-type drift region 1a and the widths of the other n-type drift region 1a, the p-type partition region 1b, the n-type region 11a and the p-type region 11b of the peripheral structure 11 are all the same.
[0025]
However, the outermost ring corresponding to the terminal is a p-type region, which is in contact with the channel stopper 14. In addition, the property of the structure is equivalent even if the layer of the beginning or end of the repetition is an n-type region or a p-type region. These matters apply to all of the following embodiments, and although omitted in each description, the same applies.
[0026]
The impurity concentration of each region, N n1 as shown in FIG impurity concentration of each so as to spread uniformly depletion throughout element, N p1, N n2, ‥ , when the N n5, N p5, N n1 > N p1 > N n2 >...> N n5 > N p5 so that the total amount of impurities in the half of the width of two adjacent rings is equal to each other.
Quantitatively, the following equation holds, where d is the width of the ring and i is an integer.
[0027]
[Expression 1]
Figure 0003731523
1 and 2, the n-type partition region 1a, the p-type partition region 1b, and the n-type region 11a and the p-type region 11b of the peripheral structure are annular and have no end, so that electric field concentration at the terminal portion is avoided. Thus, a high breakdown voltage can be achieved.
[0028]
The n-type region and the p-type region of the parallel pn layer only need to be alternately repeated over the entire element, and the number of repetitions is arbitrarily determined according to the target device characteristics.
The shape of each ring may be essentially any shape, but in order to facilitate the electric field relaxation in the parallel pn layer and the connection optimization between the parallel pn layer and the peripheral structure as much as possible. It is desirable to arrange them concentrically with a shape having good symmetry.
[0029]
The extent of the depletion layer in the pn junction depends on the curvature of the junction surface. Therefore, in the annular parallel pn layer, the pitch width or impurity concentration of each n-type region and the p-type region is such that the pn junction between the adjacent region and the n-type region so that the depletion layer spreads uniformly at all pn junctions. It is determined according to the curvature of the surface.
In this embodiment, the withstand voltage is 600 V class, and the dimensions and impurity concentrations of each part have the following values. The thickness of the parallel pn layer 1 is 40 μm, the diameter of the central n-type drift region 1 a is 8 μm, the impurity concentration is 2.0 × 10 15 cm −3 , the width (d) after the next p-type partition region 1 b is 8 μm, and the impurity concentration is According to the above formula. The n + drain layer 4 has a thickness of 300 μm and an impurity concentration of 2.0 × 10 18 cm −3 .
[0030]
A prototype was actually tested and a breakdown voltage of 600V was confirmed.
[Example 2]
FIG. 4 is a cross-sectional view of the main part of the superjunction vertical MOSFET of the second embodiment of the present invention. The left side of the figure is the center side of the chip, and the right side of the figure is the end of the chip.
2 is different from the MOSFET of the first embodiment in that the center of the parallel pn layer 1 is a high-resistivity intrinsic semiconductor region (hereinafter referred to as i region) 16 and an n-type drift adjacent to the center i region 16. The width of the region 1a is half that of the other part.
[0031]
This is because electrons and holes compensate for each other in the half of the adjacent n-type region and the half of the p-type region, but the central n-type region has no p-type region inside. If the widths are the same, a non-depleted region remains and no breakdown voltage is generated.
In Example 1, the diameter of the central n-type region was equal to the ring width of the outer p-type region and n-type region. However, in Example 1, if the diameter of the central n-type region is too small, it becomes difficult to make a source electrode or a gate electrode formed thereon. On the other hand, when the center is the i region as in the second embodiment, there is an advantage that the degree of freedom in designing the surrounding ring can be improved.
[0032]
The impurity concentration in each region is N n1 > N p1 > N, where N n1 , N p1 , N n2 ,..., N n5 , N p5 so that the depletion layer spreads uniformly throughout the device. n2 >...> Nn5 > Np5 . Quantitatively, the total amount of impurities in half the width of two adjacent rings is made equal to each other as in the first embodiment.
3 is a cross-sectional view taken along the line DD ′ of FIG.
[0033]
Each n-type drift region 1a and p-type partition region 1b of parallel pn layer 1 are concentrically arranged, and a parallel pn layer is used as peripheral structure portion 11 in the same manner as the active portion, and n-type region 11a and p-type region are arranged. 11b is arranged concentrically. Furthermore, the channel stopper 14 is seen around it.
The super-junction MOSFET of the second embodiment also has an n-type partition region 1a and a p-type partition region 1b that are annular and have no ends, so that electric field concentration at the terminal portion can be avoided and high breakdown voltage can be achieved.
[0034]
In this example, the high specific resistance region 20 is used as the peripheral structure portion. Even in such a case, the boundary between the active portion and the peripheral structure portion is only the connection of the ring of the p-type region disposed on the outermost periphery of the active portion and the high resistivity region 20, so that it is easy to avoid electric field concentration. is there.
The central portion that is the intrinsic semiconductor region in the second embodiment may be a high resistance region, an insulator layer, or a layer that combines them. For example, it may be a high resistance region disposed via an insulator layer. Even in such a case, the surrounding parallel pn layer is easily depleted.
[0035]
[Example 3]
FIG. 6 is a cross-sectional view of the main part of the super-junction vertical MOSFET of the third embodiment of the present invention. The left side of the figure is the center side of the chip, and the right side of the figure is the end of the chip.
2 is different from the MOSFET of Example 1 in that the impurity concentrations of the n-type drift region 1a and p-type partition region 1b of the parallel pn layer 1 and the n-type region 11a and p-type region 11b of the peripheral pn layer 11 are constant. Instead, the width of each is gradually narrowed.
[0036]
For easy understanding in the figure, the n-type drift region 1a, the p-type partition region 1b, the n-type region 11a and the p-type region 11b of the peripheral pn layer 11 are arranged in order from the center side, including the active portion and the peripheral structure portion. This number is repeated, but this number can be chosen arbitrarily depending on the element, and is usually much higher.
FIG. 5 is a horizontal sectional view taken along line EE ′ of FIG.
[0037]
Each n-type drift region 1a and p-type partition region 1b of the parallel pn layer 1 are concentrically arranged, and a parallel pn layer is used as the peripheral pn layer 11 in the same manner as the active portion. The n-type region 11a and the p-type region 11b is arranged concentrically. Furthermore, the channel stopper 14 is seen around it.
If the parallel pn layers are annular, the circumference of each region increases toward the outer periphery, so by narrowing the width of each region toward the outer periphery, the depletion layer spreads evenly It is good.
[0038]
[Example 4]
FIG. 8 is a cross-sectional view of the main part of the superjunction vertical MOSFET of the fourth embodiment of the present invention. The left side of the figure is the center side of the chip, and the right side of the figure is the end of the chip.
6 is different from the MOSFET of Example 3 in this example in that the high resistance region 17 is disposed through the insulating layer 18 in the center of the parallel pn layer, and the peripheral structure portion outside the parallel pn layer 1. The high specific resistance region 20 is disposed as a structure for increasing the breakdown voltage in the periphery of the element to avoid the influence of the edge portion and determining the breakdown voltage characteristics on the inner side of the element. The high specific resistance region 20 is immediately depleted and maintains a withstand voltage when a reverse voltage is applied. The same as in the third embodiment, in which the impurity concentration of the n-type drift region 1a and the p-type partition region 1b of the parallel pn layer 1 is constant, and the widths thereof are gradually narrowed instead.
[0039]
Around the central high-resistance region 17, a concentric parallel pn layer 1 having a constant impurity concentration is disposed via an insulator layer 18, that is, the diameter of the central n-type drift region 1a is d n1 , When the widths of the surrounding areas are d p1 , d n2 ,..., D n3 , d p3 , d n1 > d p1 > d n2 >...> D n3 > d p3 . Quantitatively, the depletion layer is uniformly spread over the entire device by making the total amount of impurities in the half of the width of adjacent two rings equal to each other. Here, the width of the n-type region arranged closest to the center is converted to double.
[0040]
FIG. 7 is a horizontal sectional view taken along line FF ′ in FIG.
Each n-type drift region 1a and p-type partition region 1b of the parallel pn layer 1 are concentrically arranged, and a parallel pn layer is used as the peripheral pn layer 11 in the same manner as the active portion. The n-type region 11a and the p-type region 11b is arranged concentrically. Furthermore, the channel stopper 14 is seen around it.
[0041]
In the superjunction MOSFET of Example 4, the n-type partition region 1a, the p-type partition region 1b, and the surrounding n-type region 11a and p-type region 11b are annular and have no end, so that electric field concentration at the termination is avoided. High breakdown voltage can be achieved.
Instead of the central high resistance region 17, an intrinsic semiconductor region, an insulator layer, or a composite layer thereof may be used.
[0042]
[Example 5]
FIG. 9 is a horizontal sectional view of the lower part of the superjunction vertical MOSFET of the fifth embodiment of the present invention.
In this example, a plurality of elements having the same structure as that obtained by removing the channel stopper 14 from the element shown in the second embodiment are arranged in a grid pattern on the plane, and the periphery is surrounded by the channel stopper 14.
[0043]
In the figure, four elements with exactly the same structure are regularly arranged, but the individual elements do not necessarily have the same structure, and the number and arrangement of the elements are arbitrary according to the target device characteristics. Decided.
[0044]
【The invention's effect】
As described above, according to the present invention, the first and second main surfaces and the parallel arrangement in which the first conductivity type regions and the second conductivity type regions are alternately arranged between the first and second main surfaces. In a semiconductor element having a pn layer and a low resistance layer and including first and second main electrodes provided on the first and second main surfaces, respectively, the first conductivity type region of the parallel pn layer and By making the second conductivity type region planarly annular, it is easy to avoid the electric field concentration seen at the boundary between the conventional parallel pn layer and the peripheral structure portion, and a high breakdown voltage can be secured.
[0045]
The impurity concentration of the first conductivity type region and the second conductivity type region of the annular parallel pn layer is decreased as it goes to the outer periphery, or the width of the ring is decreased as it goes to the outer periphery.
This is a super-junction semiconductor device that can greatly improve the trade-off relationship between the breakdown voltage and on-voltage of the vertical semiconductor device, and solves the problem of the boundary with the peripheral structure of the parallel pn layer, and can stably achieve a high breakdown voltage. The invention makes a significant contribution to the spread and development of superjunction semiconductor devices.
[Brief description of the drawings]
1 is a horizontal sectional view of a parallel pn layer portion (line CC ′ in FIG. 2) of a superjunction MOSFET according to Embodiment 1 of the present invention;
FIG. 2 is a partial cross-sectional view of a superjunction MOSFET of Example 1 of the present invention. FIG. 3 is a horizontal cross-sectional view of a parallel pn layer portion (line D-D ′) of the superjunction MOSFET of Example 2 of the present invention.
4 is a partial cross-sectional view of a superjunction MOSFET according to Embodiment 2 of the present invention. FIG. 5 is a horizontal cross-sectional view of a parallel pn layer portion (line E-E ′) of the superjunction MOSFET according to Embodiment 3 of the present invention.
6 is a partial cross-sectional view of a superjunction MOSFET of Embodiment 3 of the present invention. FIG. 7 is a horizontal cross-sectional view of a parallel pn layer portion (line F-F ′ in FIG. 8) of the superjunction MOSFET of Embodiment 4 of the present invention.
8 is a partial cross-sectional view of a superjunction MOSFET of Example 4 of the present invention. FIG. 9 is a horizontal cross-sectional view of a parallel pn layer portion of the superjunction MOSFET of Example 5 of the present invention.
FIG. 10 is a perspective sectional view of a lower portion of a conventional superjunction semiconductor device.
1: Parallel pn layer
1a: n-type drift region
1b: P-type partition area
3: P-type base region
4: Surface n-type drift region
5: n + type source region
6: Gate insulation film
7: Gate electrode
8: Interlayer insulation film
9: Source electrode
10: Field oxide film
11: Peripheral pn layer
11a: Peripheral n-type region
11b: Peripheral P-type region
12: n + type drain region
13: Drain electrode,
14: Channel stopper
15: Channel stopper electrode
16: i area
17: High resistance region
18: Insulator layer
20: High resistivity region

Claims (16)

第一と第二の主面と、その第一と第二の主面間に第一導電型領域と第二導電型領域とを交互に配置した並列ｐｎ層と低抵抗層とを有し、第一と第二の主面にそれぞれ設けられた第一、第二の二つの主電極を備える半導体素子において、並列ｐｎ層の第一導電型領域と第二導電型領域とが平面的に環状であることを特徴とする半導体素子。A first and second main surface, and a parallel pn layer and a low resistance layer in which a first conductivity type region and a second conductivity type region are alternately arranged between the first and second main surfaces; In a semiconductor element including first and second main electrodes provided on the first and second main surfaces, respectively, the first conductivity type region and the second conductivity type region of the parallel pn layer are annular in plan view. A semiconductor element characterized by the above. 前記環状の並列ｐｎ層が、高抵抗領域、真性半導体領域あるいは絶縁体層の一つ、又はそれらを複合した領域を中心にして配置されていることを特徴とする請求項１に記載の半導体素子。2. The semiconductor element according to claim 1, wherein the annular parallel pn layer is arranged centering on one of a high resistance region, an intrinsic semiconductor region or an insulator layer, or a region where they are combined. . 前記環状の並列ｐｎ層が、絶縁体層を介して高抵抗領域を中心にして配置されていることを特徴とする請求項１に記載の半導体素子。The semiconductor element according to claim 1, wherein the annular parallel pn layer is disposed centering on a high resistance region via an insulator layer. 前記並列ｐｎ層の第一導電型領域と第二導電型領域の不純物濃度が外周に行くにしたがって低くなっていることを特徴とする請求項１ないし３のいずれかに記載の半導体素子。4. The semiconductor device according to claim 1, wherein the impurity concentration of the first conductivity type region and the second conductivity type region of the parallel pn layer is decreased toward the outer periphery. 5. 素子の中心の第一導電型領域あるいは第二導電型領域の全幅と、それ以外の第一導電型領域あるいは第二導電型領域の環の幅とが、外周に行くにしたがって小さくなっていることを特徴とする請求項１に記載の半導体素子。The full width of the first conductivity type region or the second conductivity type region at the center of the element and the width of the ring of the other first conductivity type region or the second conductivity type region become smaller toward the outer periphery. The semiconductor element according to claim 1. 素子の中心に最も近い第１導電型領域と、
前記素子の中心に最も近い第１導電型領域の外周に隣接し、素子の中心に最も近い第１導電型領域の環の幅の 2 倍の環の幅を有する第２導電型領域と、
前記並列ｐｎ層が素子の中心に最も近い第１導電型領域の環の幅の 2 倍の環の幅を有する第２導電型領域から外周に行くにしたがって環の幅が小さくなることを特徴とする請求項２または３に記載の半導体素子。A first conductivity type region closest to the center of the element ;
A nearest adjacent to the outer periphery of the first conductivity type region, a second conductivity type region having a width of twice the ring nearest the width of the rings of the first conductivity type region in the center of the element in the center of the element,
And wherein the width of the ring decreases as the parallel pn layer goes to the outer periphery of the second conductivity type region having a width of twice the ring width of the ring closest first conductivity type region in the center of the element The semiconductor element according to claim 2 or 3. 素子の中心または素子の中心に最も近い第一導電型領域あるいは第二導電型領域を除く他の隣接する第一導電型領域と第二導電型領域の環において、内側の環の幅方向における外側半分と、外側の環の幅方向における内側半分とに含まれる不純物量がほぼ等しいことを特徴とする請求項１ないし６のいずれかに記載の半導体素子。In the ring of the inner ring in the width direction of the inner ring in the ring of the first conductive type region or the second conductive type region other than the first conductive type region or the second conductive type region closest to the center of the element. 7. The semiconductor element according to claim 1, wherein the amount of impurities contained in the half and the inner half in the width direction of the outer ring are substantially equal. 前記並列ｐｎ層が同心円状に配置されていることを特徴とする請求項７に記載の半導体素子。The semiconductor element according to claim 7, wherein the parallel pn layers are arranged concentrically. 前記並列ｐｎ層の周囲が第一導電型チャネルストツパで囲まれていることを特徴とする請求項１ないし８のいずれかに記載の半導体素子。9. The semiconductor device according to claim 1, wherein a periphery of the parallel pn layer is surrounded by a first conductivity type channel stopper. 請求項１ないし８のいずれかに記載の半導体素子を、並列に複数個備えていることを特徴とする複合型の半導体素子。9. A composite type semiconductor device comprising a plurality of the semiconductor devices according to claim 1 in parallel. 素子の周囲が第一導電型チャネルストッパで囲まれていることを特徴とする請求項１０に記載の半導体素子。The semiconductor element according to claim 10, wherein the periphery of the element is surrounded by a first conductivity type channel stopper. 前記並列ｐｎ層の周囲が第一導電型または第二導電型の高抵抗領域で囲まれていることを特徴とする請求項１ないし８のいずれかに記載の半導体素子。9. The semiconductor device according to claim 1, wherein a periphery of the parallel pn layer is surrounded by a first resistance type or a second resistance type high resistance region. 高抵抗領域の周囲が高抵抗領域と同じ導電型のチャネルストッパで囲まれていることを特徴とする請求項１２に記載の半導体素子。13. The semiconductor device according to claim 12, wherein the periphery of the high resistance region is surrounded by a channel stopper having the same conductivity type as that of the high resistance region. 請求項１２に記載の半導体素子を、並列に複数個備えていることを特徴とする複合型の半導体素子。A composite semiconductor element comprising a plurality of the semiconductor elements according to claim 12 in parallel. 素子の周囲が、高抵抗領域と同じ導電型のチャネルストッパで囲まれていることを特徴とする請求項１４に記載の半導体素子。15. The semiconductor element according to claim 14, wherein the periphery of the element is surrounded by a channel stopper having the same conductivity type as that of the high resistance region. チャネルストッパに接触するチャネルストッパ電極が設けられていることを特徴とする請求項９、１１、１３、１５のいずれかに記載の半導体素子。The semiconductor device according to claim 9, further comprising a channel stopper electrode that contacts the channel stopper.
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