JP3729082B2 - Semiconductor protection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor protection circuit having an NMOS element as a protection element for protecting an SOI semiconductor circuit from electrostatic discharge (ESD) and electrical over stress (EOS).
[0002]
[Prior art]
A schematic diagram of a conventional typical CMOS (Complementary Metal Oxide Semiconductor) protection circuit is shown in FIG. Here, the case where an NMOS transistor is used as the protection element is illustrated. An NMOS transistor 4 is connected as a protective element between the input / output terminal 1 and the ground terminal (GND) 2 for the input / output terminal (I / O) 1 to be protected from electrostatic stress. An NMOS transistor 5 is also connected as a protection element between the voltage supply terminal (VDD) 3 and the ground terminal 3.
[0003]
In FIG. 7, it is assumed that an ESD stress of a positive voltage is applied to the input / output terminal 1 with respect to the ground terminal 2. Since the protective element that operates at this time is the NMOS transistor 4, in this case, a reverse bias is applied in which no current flows. However, when the voltage applied to the input / output terminal 1 increases and the electric field applied to the drain terminal of the NMOS transistor 4 exceeds a certain amount, the NMOS transistor 4 causes avalanche breakdown. Following this, the NMOS transistor 4 conducts a large current, including the operation of a parasitic npn-type bipolar transistor. This series of operations is generally called a snapback operation (FIG. 8). Due to this characteristic, a large current is applied to the NMOS transistor 4 before the voltage applied to the LSI internal circuit, that is, the voltage at the input / output terminal 1 becomes high. Thus, protection of the internal circuit of the LSI including the input / output circuit is realized.
[0004]
This characteristic is basically the same in both bulk devices and SOI (Silicon on Insulator) devices. The trigger voltage Vt1, the voltage Vt2 at the second snapback point, the current It2, the on-resistance Ron, etc. in FIG. 8 are the main parameters that determine the protection capability of the NMOS transistor.
[0005]
Here, the snapback characteristic shown in FIG. 8 will be described in a little more detail. When the drain voltage Vds increases, an avalanche breakdown occurs, the parasitic npn bipolar transistor of the NMOS transistor is turned on at the trigger voltage Vt1, and a large current flows through the on-resistance Ron. In this region, the NMOS transistor does not fail, and the drain voltage is fixed (clamped) at a substantially constant voltage necessary to pass this current. This is the principle of ESD protection by the snapback operation of the NMOS transistor. When the current further flows through the NMOS transistor, the second snapback point (Vt2, It2) is reached, and the device runs out of heat and breaks down. This point is also called a thermal runaway point, and it can be said that the device has better protection capability as the value of current It2 is larger in the range where the value of Vt2 does not damage the internal circuit.
[0006]
As described above, in the circuit of FIG. 7, when positive ESD stress is applied to the input / output terminal 1 with respect to the ground terminal 2, the circuit is connected between the input / output terminal 1 and the ground terminal 2. The internal circuit is protected by the voltage clamp by the snapback operation of the NMOS transistor 4. When a positive ESD stress is applied to the input / output terminal 1 with respect to the power supply terminal 3, the snap-back operation of the NMOS transistor 4 causes the NMOS transistor 5 connected between the power supply terminal 3 and the ground terminal 2. Forward protection function is added. When a negative surge is applied to the input / output terminal 1 with respect to the power supply terminal 3, the internal circuit is protected by the snapback operation of the NMOS transistor 5 and the forward protection operation of the NMOS transistor 4.
[0007]
In this way, if there is a voltage terminal 3 or a ground terminal 2 shared by all internal circuits, electrostatic discharge will always occur even if electrostatic stress is applied between any external terminals mounted on the LSI. Since it flows through one or more protection elements (4, 5, etc.), the terminal can be protected.
[0008]
By the way, in recent LSIs, in order to reduce the source and drain resistance of MOS transistors, silicidation of the source and drain by a salicide process or metallization by CVD (Chemical Vapor Deposition) (hereinafter, these technologies are referred to as “low resistance”). Is often used.
[0009]
However, lowering the resistance of the source and drain decreases the effective emitter depth in the bipolar operation and causes local concentration of the ESD current in the protection NMOS transistor, which causes deterioration of ESD tolerance. For this reason, in the source and drain regions in the vicinity of the gate of the protective NMOS transistor, it is common to apply a process that suppresses the reduction in resistance. This is called a salicide limiting process (blocking process). In this case, an area where salicide formation is avoided is masked with a salicide limiting mask.
[0010]
FIGS. 9A and 9B are diagrams for schematically explaining a cross section of the SOI-NMOS in the salicide process. FIG. 9A shows a case without salicide restriction, and FIG. 9B shows a case with salicide restriction. In FIG. 9, 21 is a gate, 22 is a source, 23 is a drain, 24 is a body, 25 is a silicide layer, 26 is a buried oxide film, 27 is a gate oxide film, 28 is a silicon substrate, 29 is a gate sidewall oxide film, 30 is a salicide limit mask, and 31 is a salicide limit width.
[0011]
In the SOI element, a source 22, a drain 23, and a body 24, which are active silicon layers, are electrically insulated from a silicon substrate 28 by a buried oxide film 26. Further, in the case of an FD (Fully Depleted) -SOI element in which the body 24 is completely depleted, by applying a voltage to the silicon substrate 28, it is easier to embed oxidation than in a partially depleted SOI-MOS. The interface between the film 26 and the body 24 is inverted. Therefore, the substrate bias effect is effective even in a partially depleted SOI-MOS, but becomes particularly remarkable in an FD-SOI element.
[0012]
[Problems to be solved by the invention]
Problems of the conventional semiconductor protection circuit will be described with reference to FIGS. In an ESD protection circuit in a CMOS LSI, NMOS transistors have excellent protection characteristics. Therefore, NMOS (GGNMOS) transistors 4 and 5 whose gates are grounded are often used as protection circuits as shown in FIG. The protection characteristics of the GGNMOS transistor are often evaluated by snapback characteristics as shown in FIG.
[0013]
In this characteristic, if Vt1 is too large, a high voltage is applied to the internal circuit before the protection circuit operates effectively, which is not preferable. On the other hand, if It2 is too small, the protection circuit itself is destroyed before a sufficient ESD current flows through the protection circuit. If Ron is too large, the voltage at the input / output terminal 1 also increases as the amount of ESD current increases. Therefore, the voltage applied to the internal circuit increases before sufficient ESD current flows through the protection circuit. This is not preferable because it causes destruction. Further, the protective NMOS transistors 4 and 5 are generally configured in a comb-like structure in which a plurality of transistors having a gate width of several tens of μm are connected in parallel (referred to as a multi-finger structure, one by one). A transistor is called a finger.) When Vt1 is too large compared to Vt2, only a specific finger is likely to snap back, resulting in a decrease in ESD resistance. Therefore, it is desirable that Vt1 is as small as possible, It2 is as large as possible, Ron is as small as possible, and Vt1 <Vt2.
[0014]
In SOI devices, especially FD-SOI elements whose bodies are completely depleted, the parasitic active bipolar layer has a smaller Vt1 than the bulk device, but the silicon active layer is thin and the buried oxide film is a heat insulating material. Therefore, It2 is small and the ESD tolerance is smaller than that of a bulk device of the same size. In addition, Ron is reduced due to the low resistance of the source and drain by salicide technology, etc., but only specific fingers are easy to snap back, and moreover, ESD current is likely to be concentrated locally at specific locations in the finger. As a result, since the salicide process reduces the ESD resistance, the ESD resistance of the SOI device using the low resistance process is extremely low. For this reason, as shown in FIG. 9B, a resistance reduction limiting step (salicide limiting step) is essential.
[0015]
However, the low resistance limiting technique requires an additional mask and process, which increases the cost of the digital circuit. In many cases, the output buffer also functions as a protection element. However, it is not preferable in terms of circuit characteristics to use the low resistance limiting step for the high-speed input / output buffer. Thus, it has been a problem to ensure ESD resistance without using the low resistance limiting step.
[0016]
Therefore, in order to overcome the problem of ESD protection in SOI devices that do not use a low resistance limiting process, for example, an ESD stress voltage is applied to the body and gate of the protection transistor to operate the protection circuit as a DTMOS (Dynamic Threshold MOS). And uniforming the snapback operation of the finger to increase the ESD tolerance, or applying the ESD stress voltage to the gate of the protective NMOS transistor through the resistor and the capacitor to make the snapback of the finger uniform as in DTMOS And a method of arranging a resistor that can be formed without using a low resistance limiting step on the drain side of the protective NMOS transistor.
[0017]
In these methods, the former two are methods for improving the snapback characteristics of the protective NMOS transistor, and the latter avoids local concentration of the ESD current by providing a necessary drain resistance without using a low resistance limiting process. It can be said that it is a technique.
[0018]
However, the DTMOS connection is effective for a partially-depleted SOI device, but is not effective for an FD-SOI device. In addition, in the GCNMOS, the parasitic capacitance of the input / output terminals becomes large, and there remains a problem in the high-speed input / output operation. On the other hand, although the method of giving resistance to the drain can make the ESD current uniform, it results in eliminating the benefit of low Ron obtained by the low resistance process, and causes an increase in the area of the protection circuit. .
[0019]
As described above, there has not been an inexpensive technique for improving ESD protection circuit characteristics suitable for an SOI device that does not use the low resistance limiting process in FD-SOI. In the following, an SOI device that does not use the resistance reduction limiting step may be referred to as a fully-coated SOI device.
[0020]
An object of the present invention is to provide a means for applying an appropriate voltage to the silicon substrate of an SOI device by applying an ESD stress to the terminal, thereby improving the snapback characteristics of the protective NMOS element. good It is another object of the present invention to provide a semiconductor protection circuit capable of obtaining a high ESD tolerance even in a fully coated SOI device.
[0021]
[Problems to be solved by the invention]
In order to solve the above-mentioned problems, an invention according to claim 1 provides an SOI semiconductor circuit. Apply to input terminal, output terminal or input / output terminal As a protective element to protect against electrostatic discharge and electrical overstress And an SOI structure in which a gate terminal and a source terminal are connected to a ground terminal and a drain terminal is connected to the input terminal, output terminal or input / output terminal. In a semiconductor protection circuit having an NMOS device, in the process in which the electrostatic discharge or electrical overstress is applied Of the NMOS device The semiconductor protection circuit is characterized in that substrate bias applying means for applying a positive voltage to the substrate is provided.
[0022]
According to a second aspect of the present invention, in the first aspect of the invention, the substrate bias applying means includes a source terminal. The input terminal, output terminal or An input / output terminal is connected, and a gate terminal is connected to the SOI semiconductor circuit. High potential Connected to power terminal, drain terminal is front Register A semiconductor protection circuit comprising a PMOS element connected to the plate.
[0023]
According to a third aspect of the present invention, in the first aspect of the present invention, the substrate bias applying means includes a high voltage End Child The input terminal, output terminal or The input terminal is connected to the input / output terminal, and the input terminal is in the SOI semiconductor circuit. High potential Connected to power terminal, output terminal is front Register Low power connected to the board End Child Said A semiconductor protection circuit comprising a CMOS inverter connected to the ground terminal.
[0024]
According to a fourth aspect of the present invention, there is provided the semiconductor protection circuit according to the second aspect, wherein a first resistor is connected between a drain terminal and a ground terminal of the PMOS element.
[0025]
The invention of claim 5 is the invention of claim 3, wherein the low power End A semiconductor protection circuit is characterized in that a second resistor is connected between a child and the ground terminal.
[0026]
A sixth aspect of the present invention is a semiconductor protection circuit according to the second or fourth aspect of the present invention, wherein the PMOS element is replaced with a capacitor.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor protection circuit of the present invention transmits the ESD stress voltage to the silicon substrate, that is, the back surface of the LSI chip via the substrate voltage applying means, and lowers the threshold voltage of the protection NMOS element by the substrate bias effect (back gate effect) thereby. In other words, the snapback characteristic Vt1 is lowered. This substrate bias effect is effective even in a partially depleted SOI device, but it works particularly significantly in an FD-SOI device because the body is completely depleted. Although there is a technology for supplying voltage to the gate electrode and body in conjunction with the application of ESD stress, the conventional technology is that the voltage is applied to the silicon substrate, and the ESD resistance is improved by the substrate bias effect. And different.
[0028]
[First Embodiment]
A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a semiconductor protection circuit of an SOI device having a substrate bias applying means. In FIG. 1, 1 is an input / output terminal, 2 is a ground terminal, 3 is a power supply terminal, 4 and 5 are NMOS transistors as protective NMOS elements, 6 is a PMOS transistor as substrate bias applying means, and 7 is a resistor.
[0029]
The PMOS transistor 6 has a source connected to the input / output terminal 1, a gate connected to the VDD terminal 8 inside the LSI, and a drain connected to the ground terminal 2 via the resistor 7. Further, the drain (point A) of the PMOS transistor 6 is connected to the back gates 4bg and 5bg (that is, a common silicon substrate) of the NMOS transistors 4 and 5 as protective elements. The value of the resistor 7 needs to be a value at which the PMOS transistor 6 is not destroyed by the voltage of the input / output terminal 1 during the ESD event. Note that the gate terminal of the PMOS transistor 6 is preferably not connected to the external terminal as the independent VDD terminal 8 but connected to an annular power supply line or the like.
[0030]
Assume that a positive ESD stress is applied to the input / output terminal 1 while the ground terminal 2 is actually grounded. In the transient process of the stress application, the VDD terminal 8 is in a floating state, but can be regarded as a potential substantially equal to the ground level, so the PMOS transistor 6 is turned on. Here, the potential at the connection point A between the resistor 7 and the PMOS transistor 6 is a value obtained by dividing the potential at the input / output terminal 1 by the PMOS transistor 6 and the resistor 7. If the value of the resistor 7 is sufficiently large, the potential at the point A becomes substantially equal to a value obtained by dropping the potential of the input / output terminal 1 by the threshold voltage of the PMOS transistor 6.
[0031]
If the connection is made so that the voltage at the point A is supplied to the back surface of the SOI chip, for example, the die of the package, the voltage at the point A is applied to the back gates of the NMOS transistors 4 and 5 serving as ESD protection elements. The buried oxide film is normally about 100 nm, and does not breakdown at a voltage (3 to 6 V) of the snapback trigger voltage Vt1 of the NMOS transistor 4. The application of voltage to the back gate has the same effect as the case where a weak voltage (substantially equivalent to the electric field of the back gate) is applied to the gate 4g of the NMOS transistor 4, and the threshold voltage with Ids-Vgs characteristics (subthreshold characteristics). A decrease is observed. FIG. 2 is a diagram for explaining this relationship. Vsub is a back gate voltage, and when it increases in the positive direction, the threshold value decreases. This lowering of the threshold lowers the trigger voltage Vt1 for turning on the parasitic bipolar transistor. As described above, the voltage application to the back gate lowers the trigger voltage Vt1 of the snapback, so that the fingers in the NMOS transistors 4 and 5 which are multi-finger structure protection elements are promoted to have a uniform snapback and the resistance is reduced. The problems of SOI devices using processes can be overcome.
[0032]
FIG. 3 is a graph showing changes in snapback characteristics due to substrate bias in a fully-covered FD-SOI NMOS transistor whose resistance has been lowered by tungsten CVD. The measurement used the TLP (transmission line pulsing) method. The trigger voltage Vt1 when Vsub = 3V (shown by the solid line) is about 300mV lower than the trigger voltage Vt1 of the characteristic (shown by the dotted line) when the substrate bias Vsub is 0V = 0V. Is shown.
[0033]
An LSI has a plurality of input / output terminals, each of which requires a protection circuit. Therefore, there are a plurality of points A in FIG. If these connection points are connected by LSI wiring and bonded from one or more electrode pads to a package die, the effects of the present invention can be shared by all input / output terminals.
[0034]
In actual use in which the LSI normally operates, the power supply voltage VDD is supplied to the gate terminal of the PMOS transistor 6 and the PMOS transistor 6 is turned off. Therefore, the substrate is fixed at the GND potential, and the NMOS transistor 4 is turned off. Suppresses leakage current. Further, the signal level of the input / output terminal 1 is not particularly limited in the range of the power supply voltage.
[0035]
In addition to the protection circuit (NMOS transistor 4) provided in the input / output terminal 1, the LSI includes the protection circuit (NMOS transistor 5) inserted between the power supply terminal 3 and the ground terminal 2 as described above. Here, the NMOS transistor 5 is called a power line protection circuit. Normally, the power supply line is annularly arranged around the LSI chip, and the protection circuit for the input / output terminal 1 also uses the power supply line as a surge path. Therefore, a part of the ESD current flowing from the input / output terminal 1 is used as the protection circuit between power supply lines. If the flow is divided, an effect equivalent to that obtained when the size of the protective element is increased can be obtained, and the ESD tolerance is increased.
[0036]
Therefore, as shown in FIG. 1, for example, when the diode 9 is provided between the power supply terminal 3 and the input / output terminal 1, a part of the ESD current due to the positive bias applied to the input / output terminal 1 with respect to the ground terminal 2 is It flows into the diode 9 and the NMOS transistor 5. In the present invention, since a positive voltage is simultaneously applied to the back gates of all the protective NMOS transistors, the NMOS transistor 5 can achieve the same effect as the NMOS transistor 4. This effect not only promotes uniform snapback of the power supply line protection circuit, but also promotes bypassing of the ESD current to the power supply line protection circuit. With respect to this point, in the prior art, the same countermeasures as those for the NMOS transistor 4 as described above are required for the NMOS transistor 5 as well. Otherwise, if a specific finger in the NMOS transistor 5 is snapped in advance, there is a possibility that the finger will fail.
[0037]
As described above, according to the present embodiment, by applying a positive voltage to the silicon substrate of the FD-SOI device, the threshold voltage of the NMOS transistor can be lowered, and the snapback operation of the NMOS transistor can be improved. As a result, the ESD tolerance can be remarkably improved even in a fully-coated SOI device in which the ESD current is concentrated on a specific finger and the ESD tolerance is likely to be lowered. Further, the substrate bias applying means can be configured by adding a simple and small-scale circuit using a PMOS transistor and providing a connection structure to the die of the package, and hardly increases the parasitic capacitance of the input / output terminal 1. realizable.
[0038]
The diode 9 can be replaced with a PMOS transistor or the like. Further, even if the diode 9 of FIG. 1 is omitted, the effect of the present invention on the NMOS transistor 4 does not change. The resistor 7 can be omitted depending on the characteristics of the PMOS transistor 6. Further, even if the PMOS transistor 6 is replaced with a capacitor, the same effect can be obtained.
[0039]
[Second Embodiment]
A second embodiment of the present invention will be described with reference to FIG. In this embodiment, an NMOS transistor 10 is used instead of the resistor 7 used in the first embodiment, and the NMOS transistor 10 and the PMOS transistor 6 constitute an inverter as a substrate bias applying means. The input terminal of this inverter is connected to the VDD terminal 8, and the output terminal (point A) is connected to the back gate (silicon substrate). The resistor 7 ′ in this embodiment is inserted in order to prevent the NMOS transistor 10 from snapping back prior to the PMOS transistor 6 and flowing a large current into the inverter, but depending on the characteristics of the PMOS transistor 6. Can be omitted.
[0040]
Also in this embodiment, since the input terminal of the inverter is connected to the VDD terminal 8, when a positive ESD stress is applied to the input / output terminal 1 with respect to the ground terminal 2, the input level of the inverter is transiently changed. This corresponds to the low level, and the ESD voltage is output to the output terminal (point A). By this operation, a positive voltage is applied to the back gates of the protection NMOS transistors 4 and 5 as in the first embodiment, and the ESD tolerance is improved for the same reason as in the first embodiment.
[0041]
[Experimental example]
The difference in HBM (Human Body Model) -ESD tolerance with and without the substrate bias will be described with reference to FIGS. In order to examine the effect of the substrate bias in the same circuit, a conventional LV (Low Voltage) CMOS input circuit that does not include the substrate bias applying means as shown in the first and second embodiments was used. When the same voltage as the ESD stress was applied to the silicon substrate, the input terminal 11 and the silicon substrate 19 were directly connected as shown in FIG. 12 is a protective PMOS transistor, 13 is a protective NMOS transistor, 14 and 15 are protective diodes, 16 is a resistor, 17 is an LVCMOS input circuit, and 18 is a power line protection circuit (NMOS in FIGS. 1 and 4). Corresponds to the transistor 5). The LVCMOS input circuit 17 uses a 0.35 μm FD-SOI process and titanium silicide as a low resistance process.
[0042]
FIG. 6 shows the results of the HBM-ESD test for the completely covered sample (Fu11y salicided) in which the salicide limiting step is omitted and when the substrate bias is applied with the Fu11y salicided sample (Fu11y salicided + back bias). In the present invention, the purpose is to secure the necessary ESD tolerance without limiting salicide, but for comparison, a sample (600 nm blocked) having a salicide limit 31 of 600 nm in FIG. The test was conducted under the same conditions.
[0043]
Each vertex of the bar graph of FIG. 6 shows the ESD stress voltage at the time of failure due to the HBM-ESD test. The failure voltage was the average of 3 samples at each level. In the ESD test, a commercially available test apparatus compliant with EIAJ and ESDA standards was used, and positive HBM-ESD stress was applied to the input terminal 11 with the ground terminal (GND) in FIG. 5 actually grounded. All samples were diced from the same wafer and encapsulated in a ceramic package.
[0044]
The "Fu11y salicided" sample failed at an average of 1,570V, while the "600nm blocked" sample with a 600nm salicide limit, which is considered to be the most effective method of improving ESD resistance in the salicide process, was 3,800 V and withstand amount are increasing, and the effect of salicide restriction appears. On the other hand, in the “Fu11y salicided + back bias” sample, which is the same Fu11y salicided sample, but connected so that the same voltage as the voltage of the input terminal 11 is applied to the silicon substrate 19, it is increased to 3,150V, and the salicide limit The resistance is improved to a level comparable to that of the protection circuit using the. In general, the withstand voltage required for HBM-ESD protection is set to 2,000 V or more, and it can be said that the “Fu11y salicided + back bias” sample to which the substrate bias is applied has greatly cleared this requirement. Thus, the dramatic improvement in the ESD resistance by the application of the substrate bias shows the effectiveness of the present invention.
[0045]
As shown in this experiment, in the LVCMOS input circuit created with the fully-covered (Fu11y salicided) FD-SOI device, when the substrate bias was applied, the HBM-ESD withstand voltage increased by about 1,500V. This means that in a digital LSI in which the internal circuit does not require a resistance reduction limiting process, the conventionally required resistance reduction limiting process for ESD protection can be omitted, and the manufacturing cost can be reduced. means.
[0046]
【The invention's effect】
As described above, according to the present invention, since an effective substrate bias effect is utilized for an SOI device, even when a protective NMOS element of a fully-covered SOI having a multi-finger structure is used, the gap between fingers in the snapback operation can be eliminated. This has the effect of maximizing the ESD tolerance of the protective NMOS device. Low resistance processes such as salicide technology and metal CVD are indispensable for high speed and low power consumption of LSIs, and circuits for enhancing ESD protection tolerance of SOI devices particularly suitable for LSIs by such low resistance processes. As a practical method, the present invention is an inexpensive and effective means.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a semiconductor protection circuit according to a first embodiment of the present invention.
FIG. 2 is a characteristic diagram showing a substrate bias effect of an NMOS transistor of an FD-SOI device.
FIG. 3 is a characteristic diagram showing a difference in snapback characteristics due to a substrate bias of an NMOS transistor of an FD-SOI device.
FIG. 4 is a circuit diagram of a semiconductor protection circuit according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration in which an ESD voltage is directly applied to a silicon substrate in an LVCMOS input circuit.
6 shows the HBM-ESD withstand characteristics in each case when there is no substrate bias and no salicide limit, when there is no substrate bias and there is a salicide limit, and when there is a substrate bias and there is no salicide limitation. It is a characteristic view which shows an experimental result.
FIG. 7 is a circuit diagram of a conventional ESD protection circuit.
FIG. 8 is a snapback characteristic diagram of an NMOS transistor.
FIG. 9 is a cross-sectional view of an SOI-NMOS transistor in a salicide process.
[Explanation of symbols]
1: input / output terminal, 2: ground terminal, 3: power supply terminal, 4, 5: NMOS transistor, 6: PMOS transistor, 7, 7 ′: resistor, 8: power supply terminal, 9: diode, 10: NMOS transistor
11: input / output terminal, 12: PMOS transistor, 12: NMOS transistor, 14, 15: diode, 16: resistor, 17: LVCMOS input circuit, 18: protection circuit between power supply lines, 19: silicon substrate
21: gate, 22: source, 23: drain, 24: body, 25: silicide layer, 26: buried oxide film, 27: gate oxide film, 28: silicon substrate, 29: gate sidewall oxide film, 30: salicide restriction Mask, 31: Salicide limit width

Claims (6)

As a protective element for protecting the SOI semiconductor circuit from electrostatic discharge and electrical overstress applied to the input terminal, output terminal or input / output terminal , the gate terminal and the source terminal are connected to the ground terminal, the drain terminal is the input terminal, In a semiconductor protection circuit having an NMOS element of SOI structure connected to an output terminal or an input / output terminal ,
A semiconductor protection circuit comprising substrate bias applying means for applying a positive voltage to a substrate of the NMOS device in the process of applying the electrostatic discharge or electrical overstress. In claim 1,
The substrate bias applying means, said source terminal input terminal connected to an output terminal or output terminal is connected to a gate terminal to the high potential power supply terminal in the SOI semiconductor circuit, a drain terminal connected before Kimoto plate A semiconductor protection circuit comprising a PMOS device. In claim 1,
The substrate bias applying means, a high electrostatic position pin is an input terminal, connected to the output terminal or output terminal is connected to the input terminal to the high potential power supply terminal in the SOI semiconductor circuit, and an output terminal before Kimoto connected to the plate, the semiconductor protection circuit characterized by comprising a CMOS inverter undervoltage position pin is coupled to the ground terminal. In claim 2,
A semiconductor protection circuit, wherein a first resistor is connected between a drain terminal and a ground terminal of the PMOS element. In claim 3,
Semiconductor protection circuit, characterized in that it connects the second resistor to the ground terminal and the low electric position pin. In claim 2 or 4,
A semiconductor protection circuit, wherein the PMOS element is replaced with a capacitor.

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