TW411610B - Silicon controlled rectifier type electrostatic discharge protecting structure - Google Patents

Abstract

A silicon controlled rectifier type electrostatic discharge protecting structure, is electrically connecting to output/input pad. First, it includes an N-well formed on a certain range of a P-semiconductor substrate. And forming an N-type first doped region and a P-type first doped region in the N-well and electrically connecting to output/input pad. And, forming an N-type second doped region and a P-type second doped region on the P-semiconductor substrate and electrically connecting to a grounded node. In which, the aforesaid structure forms a silicon controlled rectifier. Besides, using an N-type third doped region as a junction capacitor, which is formed within the P-semiconductor substrate and electrically connected to output/input pad. And when an electrostatic stress is invading from the output/input pad, the junction capacitor is used to supply a substrate current to turn on silicon controlled rectifier and release electrostatic stress.

Description

__411610_ V. Description of the invention (1) The present invention relates to electrostatic discharge protection technology, and more particularly to a silicon controlled rectification type electrostatic discharge protection structure. In the application of integrated circuits (ICs), materials such as conductors, semiconductors and insulation layers have been widely used, while thin film deposition, photolithography, and etching are the main Semiconductor technology. The thin film deposition is to deposit the above materials on the wafer surface in layers, and the lithography process is to reproduce (repHcate) the element or circuit pattern to be formed. These patterns are transferred to various layers on the surface of the wafer to be formed to form internal semiconductor elements such as transistors or capacitors. In addition, in order to avoid the invasion of water vapor, alkali metal ions, or mechanical damage, it is necessary to deposit a passivation layer to protect the integrated circuit structure, and it must be defined as an input / output. / output), and the protective layer is excavated in an etching step to expose the surface of the metal pad before the final packaging can be performed. However, in the semiconductor devices completed as described above, electrostatic discharge (ESD) often invades from the I / O pads of the wafer due to contact with the electrostatic body in a dry environment, causing damage to the integrated circuit. Especially after entering the ultra large integrated circuit (ULSI) generation, for example, semiconductor devices formed using deep sub-micron processes below 0,25 / im, such as CMOS ICs' thin gate oxide, short gate oxide, short Channel (short channel length), and S (shall〇w juncti〇n)

C: \ Prograra Files \ Patent \ 0503-3874-E.ptd page 4 411610

Other structural features, or the application of lightly doped (LDD) and salicided diffusion technologies, have seriously weakened the ESD resistance of the transistor and affected its reliability against electrostatic discharge. Li, the fabricated transistor element is extremely sensitive to high voltage discharges because it has a thin gate oxide layer that is easily ruptured. Those who cause electronic component failure due to general electrostatic discharge can be divided into voltage-type damage and current-type damage. According to the human body model, high electrostatic voltage may originate from the human body touching the integrated circuit pins, which may generate more than 2000v. Electric charge, and it appears as a high-current pulse in a short time (100ns); in addition, according to the machine model, high electrostatic voltage may also come from the integrated electrical pins and poor ground conductors, such as the contact of the test machine, which Then it can appear as a high-voltage pulse pattern in a shorter time (0ns). When designing an electrostatic discharge protection structure based on a human body model, its ESD value needs to be as high as 200 0V, and when designing an electrostatic discharge protection structure based on a machine model, its ESD value is about 200 0V. And according to the related conventional technology disclosed so far, such as those using silicon controlled rectifier (SCR: silicon controlled rectifier) as the structure of the electrostatic discharge protection circuit, US Patent No. 5, 012, 317 is taken as an example, as shown in Figure 1. It shows that a semiconductor device generally has an internal circuit 2 and a bonding pad 1 which is electrically connected to the semiconductor device. Among them, a silicon controlled rectification type electrostatic discharge protection structure 3 can be added between the two. First, according to FIG. 1, the conventional silicon controlled rectifier is usually disposed on a p-type semiconductor substrate 10 and is located in a predetermined position of the P-type semiconductor substrate 10.

C: \ Program Files \ Patent \ 0503-3874-E, ptd page 5 411610___ V. Invention system (3 ^ " ~~ 'There is an N-type well area u. Within the range of the n-type well area 丨 丨, A p-type doped region 12 and an N-type doped region 13 are formed; within the P-type semiconductor substrate 10, another N-type doped region 14 and another p-type doped region 15 are formed. Among them, The p-type, doped region 12 and N-type doped region 13 are electrically connected to a bonding pad}. The bonding pad 1 is used as an output / input pad to be coupled to the internal circuit 2. The internal circuit 2 indicates a vulnerable The core circuit caused by electrostatic discharge needs the guarantee of silicon controlled rectifier. The N-type doped region 14 and the P-type doped region 15 are electrically connected to a potential point Vss' § in the normal operation mode (normal operation), this potential node Vss is usually maintained at the ground potential. Accordingly, please refer to FIG. 1 and refer to FIG. 2, where FIG. 2 is the equivalent circuit of FIG.! Because of the P-type doped regions 12, N The well region U and the p-type semiconductor substrate 10 are used to construct an emitter, base, and collector of a PNP parasitic junction carrier transistor 20. The ruled well region H and p-type semiconductor substrate 10 And the N-type doped region 14 constructs the collector, base, and emitter of an NPN parasitic junction junction transistor 21. In the figure, resistors 22 and 23 represent N-type well regions 11 and P, respectively. Spreading resistance of the Si substrate 10 ° ° When there is an electrostatic discharge stress positive to Vss on the bonding pad 1, the p-type doped region 12 and the N-type well region 11 are forward biased. The electrostatic discharge stress is high enough to cause the 1 ^ junction between the N-type well region 11 and the p-type silicon substrate 10 to collapse. Then the P-type silicon substrate 10 and the N-type doped region 14 are also forward biased, so they are turned on. The discharge path from the bonding pad 1 to Vss is used to release the electrostatic discharge stress at the bonding pad 1 to prevent the internal circuit 2 from being damaged by electrostatic discharge. From this, it is known whether the silicon controlled rectifier can be opened to release the bonding pad 1

C: \ Prograra Files \ Patent \ 0503-3874-E.pt (i page 6_411610 V. Description of the invention (4) · " An electrostatic discharge stress is determined by the N-type well area 丨 丨 and? The silicon substrate "interval" junction collapses or not. However, the doping concentration of the N-type well region and the 卩 -type silicon substrate 10 is already quite low, so the trigger voltage for the silicon controlled rectifier to collapse must be about Up to 30 volts or more. However, the gate oxide layer thickness in the 0.6-0.8 micron CMOS process is about 15-20 angstroms as an example. The gate oxide layer used in the internal circuit 2 is in丨 5 ~ 20 volts have already been damaged. Therefore, the conventional silicon controlled rectifier can not exert the effect of electrostatic discharge protection ^ In order to reduce the trigger voltage, US Patent No. 5,465,189 proposes a low voltage triggered silicon controlled rectifier, such as Figure 3. In addition to the structure shown in Figure 1, the low-voltage-triggered silicon-controlled rectifier also includes an N-type doped region 16 and a gate structure 17. Among them, the n-type doped region 16 is It is a heavily doped region 'Partly formed in the N-type well region 11 and partly formed in the p-type silicon substrate Within 10 ′, a PN junction is formed across the N-type well region 11 and the P-type silicon substrate 10. The gate structure 17 is formed on the substrate 10 between the N-type doped regions 16 and 14, where the gate structure 17 includes a gate dielectric layer 18 and a gate electrode layer 19 from bottom to top. The gate dielectric layer 18 is formed on the gate dielectric layer 18 adjacent to the substrate 10 ′, and is connected to the gate dielectric layer 18. Vss. Please refer to FIG. 4 for the equivalent circuit diagram of FIG. 3. The reference numeral 24 in FIG. 4 represents the base portion between the N-type doped regions 16 and 14, and the N-type doped regions 16 and 14. And NMOS semiconductor field-effect transistors built with gate structure 17 and so on. When the electrostatic discharge effect occurs, the breakdown of the drain interface of the metal-oxide half-effect transistor 2 4 triggers the entire silicon control. The rectifier is turned on and on, so the trigger voltage of the electrostatic discharge protection circuit can be reduced to HHI mrai C: \ ProgramFiles \ Patent \ 0503-3874-E.ptd page 7 411610 V. Description of the invention (5) Field effect power The breakdown voltage of crystal 24 'is generally 4 to 7 volts, but according to the current CMOS process that has progressed to 0.18 micron, the gate oxidation The layer thickness has been reduced to about 32 angstroms, so the gate oxide layer used in the internal circuit 2 still cannot withstand the electrostatic discharge voltage. US Patent No. 5, 528, 1 88 proposed another low electric star triggered stone evening rectifier That is, as shown in Figure 5. In addition to the structure shown in Figure 1, the low-voltage-triggered silicon-controlled rectifier also includes an NMOS transistor 25 and an RC circuit 32. Under normal operation, the 'NM0S transistor 25 is turned off. However, when an electrostatic voltage pulse appears on the bonding pad 1 and invades through the conductive path, the electric valley C quickly consumes a gate voltage Vg exceeding the initial voltage vth of the transistor 25, so that the NMOS transistor 25 is in an on state. In addition, it uses the hot carrier effect of the high electric field, so that the hole carrier is generated as a silicon controlled rectifier. The current Isub (for the parasitic bipolar transistor 21: based on the pole ^ Therefore, it can be triggered at low voltage. Purpose of silicon controlled rectifier 3. In view of this, one of the objectives of the present invention is to select a silicon controlled rectification type electrostatic discharge protection circuit, which does not need to pass through the hot carrier effect mechanism, and can directly use a capacitor to replace the metal-oxide semiconductor and the The Rc circuit is used to quickly provide a large amount of substrate current when electrostatic discharge invades, thereby generating the trigger current value required to turn on the silicon controlled rectifier at a low voltage, thereby improving the ESD resistance and avoiding damage to internal circuit components. To achieve the above object, the present invention provides a silicon controlled rectification type electrostatic discharge protection structure electrically connected to a bonding pad, which includes a second type semiconductor layer formed in a predetermined range of a first type semiconductor layer. —The first doped region of the second type and the first doped region of the first type are formed in the second type semiconductor

411610

5. Description of the invention (6) In the layer, it is electrically connected to the bonding pad. On the other hand, a first doped region and a -type-second doped region 'are formed in the IS layer, and are electrically connected to a potential node. Its towel = cow conductor silicon rectifier '3, using a capacitor' It is formed in the range of the second type layer, and it is also electrically connected to the bonding pad, when a * :: can provide a current to turn on the silicon controlled rectifier In the embodiment, the first type semiconductor layer is used as the substrate, and the first + conductor layer is used as a well region. As for the first type, it can be a ρ-type conduction type, and the second type can be N Type conductive type. In addition, the potential node is generally a ground node, and the bonding pad is used as an output / input pad. The electrical internal capacitance can use a second type of third doped region as a junction capacitor 'or gate insulation. Layer to form the isolation capacitor. -In order to make the features and advantages of the above and other objects of the present invention more obvious and easy, the following is a detailed description of a preferred embodiment and the accompanying drawings as follows: ~ _ Brief description of the drawings: Figure 1 It is shown that the conventional silicon-controlled rectifier is not intended to be fabricated on an internal profile of a semiconductor substrate. -Figure 2 shows the equivalent circuit diagram of Figure 1. Fig. 3 is a schematic cross-sectional view showing a conventional low-voltage-triggered silicon controlled rectifier fabricated in a half-conductor substrate. Figure 4 shows the equivalent circuit diagram of Figure 3. Figure 5 shows a conventional low-voltage triggered silicon controlled rectifier connected in parallel.

4ί1β1〇 V. Description of the invention (7) --- 'Schematic diagram of the road. FIG. 6 is a schematic cross-sectional view of a semi-conductive substrate made according to a preferred embodiment of the present invention. FIG. 7 is an equivalent circuit diagram of FIG. 6. Figures 8A to 8C are graphs showing the relationship between substrate current and ESD voltage according to Figure 7. Explanation of symbols: Bu bonding pad; 2 ~ internal circuit; 3 ~ silicon controlled rectifier; 10 ~ p type semiconductor substrate; 114 type well area; 12 ~ P type doped area; 13 ~ N type doped area; 14 ~ N 15 ~ P-type doped region; 1δ ~ N-type doped region; 17 ~ gate structure, 18 ~ gate dielectric layer; 19 ~ gate electrode layer; 20 ~ PNP parasitic double junction Surface transistor; 21 ~ NPN parasitic bipolar junction transistor; 22, 23 ~ resistance; 24, 25 ~ metal-oxide half field effect transistor; 32 ~ RC circuit; 60 ~ ρ type semiconductor substrate; 61 ~ N type Well region; 62 ~ P type doped region type doped region; 64 ~ N type doped region; 65 ~ P type doped region; 66 ~ N type doped region; 70 ~ PNP parasitic junction carrier transistor 71 ~ NPN parasitic bipolar junction transistor; 72, 73 ~ resistance; capacitance ~ cj. Embodiment Please refer to FIG. 6, which illustrates a schematic diagram of a semiconductor structure for avoiding ESD damage by using a silicon controlled rectification type electrostatic discharge protection circuit with a capacitor in an embodiment of the present invention. First, according to FIG. 6, a schematic cross-sectional view of a semiconductor substrate according to a preferred embodiment of the present invention is shown. The electrostatic discharge protection circuit according to the present invention is usually disposed on a P-type semiconductor layer 60, and

C: \ PrograroFiles \ Patent \ 0503-3874-E.ptd page 10 < 11610 V. Description of the invention (8) '-An n-type semiconductor layer μ is formed on the existing position of the body 60, so it is p-type The semiconductor 60 is separated from the N-type semiconductor layer 61) to form a pN junction 67. For example, the p-type semiconductor can be a P-type silicon substrate, and the N-type semiconductor layer 61 is an N-type well region formed in the substrate. A first type doped region 62 and a first p-type doped region 63 are formed within the range of the N-type well region 61 '. In the p-type semiconductor substrate 60, a second N-type doped region 64 and a second P-type doped region 65 are formed. The first P-type doped region 63 and the first N-type doped region 62 are electrically connected to the bonding pad j '. The bonding pad 1 is used as an output / input pad to be coupled to the internal circuit 2σ, wherein The Is circuit 2 is a core circuit that is easily damaged by electrostatic discharge. The second v-type doped region 64 and the second p-type doped region 65 are electrically connected to a potential contact Vss's in a general operating mode (n. The potential contact Vss under rmai 〇 {) erat i〇-n) is usually a ground potential. In addition, a third N-type doped region 66 is formed in the P-type semiconductor substrate 60. For example, the third N-type doped region 66 and the first N-type doped region 62 and The first P-type doped region 63 is electrically connected to the bonding pad 1. According to the description of the structure, and referring to FIG. 7'-p-type doped region μ, N-type well region 61, and P-type semiconductor substrate 60, etc., a vertical PNP parasitic junction junction transistor 7 is constructed respectively. 〇 the emitter, base and collector. The N-type well region 61, the p-type semiconductor substrate 60, and the second n-type doped region 64 are constructed as a collector, a base, and an emitter of a horizontal NPN parasitic junction junction transistor 71, respectively. The 1 ^ -type doped region 66 can be used as a junction capacitor Cj (junction capacitor). Figure 7 shows the equivalent circuit of Figure 6. In the figure, the resistors 72 and 73 respectively represent the distribution of the N-type 丼 region 61 and the P-type semiconductor substrate 60.

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411610 V. Description of the invention (9) Resistance. When an electrostatic discharge stress with a positive Vss occurs at the bonding pad 1, because the second N-type doped region 66 and the P-type semiconductor substrate 60 are used as a junction capacitor, the characteristic of the electrostatic discharge stress is a high-frequency signal. Therefore, the capacitance can be known according to the following formula:

Cj-dQ / dt Therefore, in a very short time, a large substrate current Isub can be quickly generated through the capacitor Cj to the P-type semiconductor substrate 60 to drive the base of the horizontal NpN parasitic junction junction transistor 71. The junction 'causes it to form a positive feedback path with the vertical pNp parasitic bipolar junction transistor 70, thereby turning on the silicon controlled rectifier' and forming a conducting current path between the bonding pads 1 to \ 5, thereby releasing the junction The electrostatic discharge stress at the pad 1 prevents the internal circuit 2 from being damaged by the electrostatic discharge. Therefore, the trigger voltage of the electrostatic discharge protection circuit can be greatly reduced to about 1.2 volts or less. Next, the human body model test machine (HBM) is used to test the NMOS transistor that simulates the electrostatic protection circuit of this embodiment. Please refer to Figures 8A to 眈, where the horizontal drawing represents time (ns) and the vertical axis represents Electricity (v) and current (A), which respectively represent the voltage (solid part) applied to the human body model testing machine (hbm) under the electrostatic voltage (ESD) of 5〇ν, ιοον, and 200V to the substrate The characteristic curve of the current I sub (the dotted line). From Figure 8A, it can be seen that under the electrostatic voltage (ESD) of 50V, a substrate current Isub is generated in a short time. At the same time, the substrate current I sub increases linearly through the capacitor. sub is still not enough to turn on the SCR rectifier SCR, so until the voltage rises to

C: \ ProgramFiles \ Patent \ 0503-3874-E, ptd page 12 411610 Five 'invention description (10) Only when the surface breakdown voltage value (junction breakdown voltage), a large increase in the substrate current Isub, so that the silicon controlled rectifier SCR It is turned on, and a guiding current path is formed between the bonding pads 1 and Vss, thereby releasing the electrostatic discharge stress at the bonding pads 1 to prevent the internal circuit 2 from being damaged by the electrostatic discharge. Similarly, the same applies to the 100V electrostatic voltage (ESD) in Fig. 8B, but because the substrate current I sub rises in a shorter interval, it is sufficient to turn on the silicon controlled rectifier SCR before the junction breakdown voltage occurs. As for the state of 2000V electrostatic voltage (ESD) in Fig. 8C, since this high electrostatic voltage further increases the substrate current I sub rapidly, once the static electricity invades, the silicon-controlled rectifier SCR stands to conduct, so the current and voltage Almost synchronously improves in a linear manner. Therefore, according to this embodiment, not only can the silicon controlled rectifier be triggered in a shorter time under a smaller ESD voltage, avoiding damage to the internal circuit, but also without forming a transistor and an RC circuit. * The amount of material used in the present invention is that it can form an isolation capacitor from various capacitors with appropriate characteristics such as the capacitance divided by the junction capacitance. The materials are not limited to the materials and forming methods cited in the examples, and the gate insulation layer can also be formed. Although the present invention has been disclosed with a preferred embodiment such as iron to limit the present invention, anyone familiar with this technique In addition, within the scope of not using God and scope, it can be modified and retouched slightly, because the scope of protection of the Ming should be defined by the scope of the attached patent application. Invention guarantee

Claims (1)

371 18 more 7 ^ 610 6. Application scope 1. A silicon controlled rectification type electrostatic discharge protection structure electrically connected to a bonding pad, comprising: a first type semiconductor layer; a second type semiconductor layer formed on the first A predetermined range of one type semiconductor layer; a first type doped region of the first type is formed in the second type semiconductor layer and is electrically connected to the bonding pad; a first type doped region of the second type, Formed in the second type semiconductor layer and electrically connected to the bonding pad; a first type second doped region formed in the first type semiconductor layer and electrically connected to a potential node; A second doped region of the second type is formed in the first type semiconductor layer and is electrically connected to the potential node, wherein the first type semiconductor layer, the second type semiconductor layer, and the second type A doped region, a first doped region of the first type, a second doped region of the second type, and a second doped region of the first type constitute a silicon controlled rectifier; and a capacitor, Formed in the range of the first type semiconductor layer, which is electrically connected to the bonding pad for When an electrostatic stress intrudes, a current is provided to turn on the silicon controlled rectifier and release the electrostatic stress. 2. The structure described in item 1 of the scope of patent application, wherein the first type is an N-type conductive type and the second type is a P-type conductive type. 3. The structure described in item 1 of the scope of patent application, wherein the first type is a P-type conductive type and the second type is an N-type conductive type. 4. The structure described in item 1 of the scope of patent application, wherein the potential node C: \ ProgramFiles \ Patent \ 0503-3874-E.ptd page 14 411610 6. Scope of patent application The point is the ground node. 5 ' The structure as described in item 1 of the scope of patent application, wherein the bonding pad is used as an output / input pad, which is electrically connected to an internal i-channel. 6 The structure as described in item 1 of the scope of patent application, wherein the capacitor is a first-type second doped region as a junction capacitor. 7. The structure according to item 6 of the scope of patent application, wherein the second type and the second doped region are closer to the second type and the second type semiconductor layer than the second type doped region of the first type. . 8. The structure described in item 7 of the scope of the patent application, wherein the second doped region of the second type is interposed between the second doped region of the second type and the second type semiconductor layer. '9 · A silicon controlled rectification type electrostatic discharge protection structure electrically connected to a bonding pad, comprising: a first type semiconductor substrate; a second type well region formed in a predetermined range of one of the first type semiconductor substrates; A first doped region of a first type is formed in the second well region and is electrically connected to the bonding pad; a first doped region of a second type is formed in the second well region, It is electrically connected to the bonding pad; a first type second doped region is formed in the first type semiconductor substrate; it is electrically connected to a ground node; a second type second doped region, Formed in the first-type semiconductor substrate and adjacent to the second-type well region than the second-type doped region of the first-type semiconductor; C: \ Program Fiies \ Patent \ 0503-3874-E, ptd page 15 411610 VI. The scope of the patent application is connected to the ground node, where the first type semiconductor substrate, the second type well area, and the second type The first doped region, the first doped region of the first type, the second doped region of the second type, and the second doped region of the first type 'form a silicon controlled rectifier; and A third dopant region of the first type is formed in the first type semiconductor substrate and is interposed between the second doped region of the second type and the second type well region, and is electrically connected to the bonding pad. The N-doped third doped region is used as a junction capacitor 'for when an electrostatic stress invades' to provide a substrate current to turn on the silicon controlled rectifier, thereby releasing the electrostatic stress. 10. The structure described in item 9 of the scope of patent application, wherein the first type is a P-type conductive type and the second type is an N-type conductive type. 11. The structure as described in item 9 of the scope of patent application, wherein the bonding pad is used as an output / input pad, which is electrically connected to an internal circuit. 1 2. A silicon controlled rectification type electrostatic discharge protection structure, electrically connected to an output / input pad, including: a P-type semiconductor substrate; an N-type well region formed in a predetermined range of the p-type semiconductor substrate; a P A first doped region of the N-type well region is formed in the N-type well region and is electrically connected to the output / input region; a first doped region of the N-type region is formed in the N-type well region and the electrical connection is To the wheel out / enter pad; a P-type second doped region is formed in the P-type semiconductor substrate and is electrically connected to a ground node; an N-type second doped region is formed in the p Type semiconductor substrate, which C: \ Prograra Files \ Patent \ 0503-3874-E.ptd page 16 411610 VI. The scope of the patent application is electrically connected to the ground node, where the p-type semiconductor substrate, the N-type well area, and the N-type A doped region, the first doped region of the p-type, the second #doped region of the n-type, and the second doped region of the p-type constitute a silicon controlled rectifier, & an N-type first A three doped region is formed in the p-type semiconductor substrate, and is electrically connected to the output / input pad. The third doped region of the ^^ type is used as a junction capacitor for intrusion of an electrostatic stress. At this time, a substrate current is provided to turn on the silicon controlled rectifier, thereby releasing the electrostatic stress. — C: \ ProgramFiles \ Patent \ 0503-3874-E_ptd page Π