JP3714091B2 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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JP3714091B2
JP3714091B2 JP2000051157A JP2000051157A JP3714091B2 JP 3714091 B2 JP3714091 B2 JP 3714091B2 JP 2000051157 A JP2000051157 A JP 2000051157A JP 2000051157 A JP2000051157 A JP 2000051157A JP 3714091 B2 JP3714091 B2 JP 3714091B2
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circuit
power supply
output
voltage
input
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JP2001244412A (en
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政幸 山田谷
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Description

【0001】
【発明の属する技術分野】
この発明は、電源制御用ICなどの半導体集積回路で、出力短絡検出機能および電源切断機能を付加した半導体集積回路に関する。
【0002】
【従来の技術】
携帯機器などに用いられる電源回路は、パワースイッチング素子などの能動素子とコンデンサやコイルなどの受動素子で構成される主回路と、このパワースイッチング素子を制御・保護するための電源制御用IC(集積回路)で構成される。
【0003】
図4は、この電源回路の一例を示す回路図である。この電源回路50は、nチャネルMOSFET61を用いて、入力電圧Vinを昇圧した電圧を出力する昇圧回路とpチャネルMOSFET62を用いて、入力電圧Vinを降圧して出力する降圧回路で構成される。これらのMOSFET61、62は電源制御用IC51により駆動される。また、昇圧した出力電圧は出力端子68から出力され、降圧した出力電圧は出力端子69から出力され、それぞれの端子68、69は図示されない負荷に接続される。出力端子68、69から出力される出力電圧を、検出回路(抵抗R1、R2、R3、R4で構成される)で検出して、その検出電圧を電源制御用IC51の入力端子53、54に入力する。昇圧出力電圧を検出する検出電圧を第1検出電圧とし、降圧出力電圧を検出する検出電圧を第2検出電圧とし、第1、第2検出電圧は電源制御用IC51の入力端子53、54に入力される第1、第2フィードバック電圧となる。これらの検出電圧の大きさで、nチャネルMOSFET61およびpチャネルMOSFET62を駆動するゲート信号のパルス幅を制御して、電源回路50から安定した直流の出力電圧を出力する。
【0004】
図5は、電源制御用ICの回路図である。電源制御用IC51は、発振器72、第1エラーアンプ73、第2エラーアンプ74、第1コンパレータ75、第2コンパレータ76、第1AND回路77、第2AND回路78、第1バッファ79、第2バッファ80、定電圧回路71、出力短絡検出回路81などで構成される。定電圧回路71は、各ブロックである、発振器72、エラーアンプ73、74、コンパレータ75、76などに電圧を供給するIC内部の電源である。
【0005】
第1フィードバック電圧を入力端子53を経由して第1エラーアンプ73のマイナスに入力し、第1エラーアンプ73のプラスに基準電圧が印加され、第1エラーアンプ73の出力信号と、発振器72から出力される三角波電圧を第1コンパレータ75のプラスに入力し、第1エラーアンプ73の出力信号を出力短絡検出回路81に入力端子82を経由して入力し、第1コンパレータ73の出力信号と、出力短絡検出回路81の出力端子84から出力される出力信号とを第1AND回路77と第2AND回路に入力し、第1AND回路の出力信号をバッファ回路79に入力し、バッファ回路79の出力信号が出力端子55に伝送され、出力端子55から、図4のnチャネルMOSFET61のゲート信号が伝送される。
【0006】
一方、第2フィードバック電圧は入力端子54を経由して第2エラーアンプ74に入力され、各信号の伝送経路は前記と同様である。ただし、最終段の第2バッファ回路80は反転回路である。
図6は、出力短絡検出回路の構成図である。この出力短絡検出回路81は、図5の第1エラーアンプ73と入力端子82を経由して接続する第3コンパレータ85と第2エラーアンプ74と入力端子83を経由して接続する第4コンパレータ86と、これらのコンパレータ85、86の出力信号が入力されるOR回路87と、このOR回路87の出力信号が入力される遅延回路88で構成される。この遅延回路88はOR回路87から信号を基準として一定時間経過した後で、信号を送出する回路であり、カウンタ回路やコンデンサ充電式回路やシフトレジスタ回路などである。この遅延回路88からNOT回路で構成されたバッファ回路89と出力端子84を経由してラッチ信号が出力され、このラッチ信号が図5の第1、第2AND回路77、78へ伝送される。 つぎに、図4、図5および図6を用いて、回路動作を説明する。
【0007】
出力端子68の電圧が低下した場合、第1エラーアンプ73の出力信号である出力電圧は上昇する。この信号と、発振器72から出力される三角波電圧が入力された第1コンパレータ75の出力信号のパルス幅は増大する。このパルス幅が広くなった出力信号は、第1AND回路77、第1バッファ回路79を経由して出力端子55に伝送され、図4のnチャネルMOSFET61のゲートに与えられる。nチャネルMOSFET61の導通パルス幅が延びるために、コンデンサ63が充電され、出力端子68の電圧は上昇し、出力端子68の電圧低下は補償され、一定の電圧が出力端子68から、供給される。
【0008】
例えば、出力端子68に接続する負荷が短絡を起こした場合(出力短絡の場合)、第1検出電圧は零電圧となり、この第1検出電圧が第1エラーアンプ73に入力され、第1エラーアンプ73からHレベルの信号が出力短絡検出回路81に入力され、出力短絡検出回路81からLレベルの信号が出力され、この信号が第1、第2AND回路77、78に入力されるために、第1、第2AND回路77、78からLレベルの信号が出力される。そのため、出力端子55からの出力電圧はLレベル(0V)となり、出力端子56の出力電圧はHレベルの電圧となり、図1のnチャネルMOSFET61、pチャネルMOSFET64はオフし、出力端子68、69に接続する図示しない負荷は切り離される。
【0009】
図7は、従来の電源回路、電源制御補助回路、電源付加回路および負荷で構成される回路である。この回路は、図4の電源回路50に、pチャネルMOSFET91、92、nチャネルMOSFET95、96、コンデンサ93、94で構成する電源付加回路90と、第5コンパレータ97、OR回路98で構成する電源制御補助回路111を付加した回路である。電源付加回路90は電源回路50の出力が2出力であるのに対応して、2系統になっており、入力端子101、102に接続する負荷も個別である。図中では負荷100は1個で示したが、実際は個別の負荷が入力端子101、102にそれぞれ接続される。
【0010】
ここに用いられる電源制御用IC51の出力短絡検出回路81の出力信号は、図5に示すように、第1、第2AND回路77、78の入力信号となるばかりでなく、接続点59から分かれて出力端子57から電源制御用IC51の外へ出力も出力される。
電源電圧は、電源回路50と第3コンパレータ97のマイナスに入力され、電源回路50の出力端子68と出力端子69から出力される出力信号は、電源付加回路90のpチャネルMOSFET91、92のソースに入力され、pチャネルMOSFET91、92のドレインからの出力は、負荷100に入力される。電源制御用IC51の出力短絡検出回路81の出力信号は、出力端子70を経由して、第3コンパレータ97の出力信号と共に、OR回路98に入力し、OR回路98の出力信号はnチャネルMOSFET95、96のゲートに与えられる。
【0011】
出力短絡した場合は、出力端子70からHレベルの信号が入力され、そのため、第3コンパレータ97からHレベル、Lレベルのいづれの信号が出力されても、OR回路98の出力信号はHレベルとなり、nチャネルMOSFET95、96のゲートに高い電圧が印加され、その結果、負荷100の入力端子101、102は接地される。
【0012】
一方、電源が切断された場合、第5コンパレータ97の入力電圧が基準電圧99を下回り、そのため、第5コンパレータ97の出力信号はHレベルとなる。このHレベルの出力信号がOR回路98に入力すると、出力短絡検出回路81の出力端子57(電源回路50の出力端子70)からの出力信号がHレベル、Lレベルに係わらず、OR回路98の出力はHレベルとなる。そのため、nチャネルMOSFET95、96のゲートに高い電圧が印加され、オンし、第5コンパレータ97のHレベルの出力信号がpチャネルMOSFET91、92のゲートに印加され、pチャネルMOSFET91、92はオフする。その結果、コンデンサの電荷が放電し、入力端子101、102が接地され、負荷へ印加される電圧はゼロとなる。また、出力短絡の有無に係わらず、負荷100が電源回路50から切り離される。
【0013】
このように、電源が切断された場合などに対応する機能を持たせるためには、電源回路50に搭載されている電源制御用IC51に、前記のような電源制御補助回路111などを電源制御用ICとは別に、電源回路50の外に追加する必要がある。
【0014】
【発明が解決しようとする課題】
しかし、電源回路を構成する電源制御用ICに、前記した電源制御補助回路を追加すると、回路全体が大型化し、コストが高くなる。
この発明の目的は、前記の課題を解決して、チップ面積の増大を抑制しつつ、電源切断機能と出力短絡検出機能を有し、電源回路の小型化と低コスト化を図ることができる電源制御用ICである半導体集積回路を提供することにある。
【0015】
【課題を解決するための手段】
前記の目的を達成するために、電源電圧が入力される電源回路と、電源回路と負荷との間に接続される電源付加回路と、電源電圧が基準電圧以下のとき、もしくは前記電源回路が出力短絡したとき、前記電源付加回路に前記電源回路と負荷とを切り離させ、且つ、負荷の入力を接地させるための信号を出力する電源制御補助回路を備えた構成とする。
【0016】
前記電源制御補助回路は、前記電源電圧がプラス端子へ、前記基準電圧がマイナス端子へ入力されるコンパレータと、出力短絡検出回路と、前記コンパレータの出力信号と出力検出回路の出力信号が、入力されるOR回路とを具備し、該OR回路の出力信号で前記電源付加回路を構成するスイッチング素子を制御するとよい。
【0017】
前記電源付加回路は、電源回路の出力とソースが接続するpチャネルMOSFETと、該pチャネルMOSFETのドレインと一端が接続し、他端がグランドと接続するコンデンサと、該コンデンサの一端とドレインが接続し、ソースがグランドと接続するnチャネルMOSFETと、を具備し、前記pチャネルMOSFETのソースが前記電源付加回路の入力側となり、前記nチャネルMOSFETのドレインが前記電源付加回路の出力側となり、電源電圧が前記基準電圧以下のとき、もしくは出力短絡のとき、前記OR回路から、前記pチャネルMOSFETをオフし、前記nチャネルMOSFETをオンし、前記電源回路と前記負荷とを切り離し、且つ、該負荷の入力を接地する信号を出力する構成とするとよい。
【0018】
【発明の実施の形態】
図1は、この発明の一実施例の半導体集積回路図である。この電源制御用IC1は、電源切断と出力短絡を検出する回路、および図示しない電源付加回路のスイッチング素子を駆動する駆動回路、過電流保護回路、過電圧保護回路、過熱保護回路などを具備している。
【0019】
この回路は、電源電圧(VDD)がマイナスへ、基準電圧がプラスへ入力されるコンパレータ2と、出力短絡検出回路81と、前記コンパレータ2の出力信号と、出力短絡検出回路81の出力信号が入力されるOR回路4とで構成される。前記出力短絡検出回路の出力段にはバッファ回路が取り込まれている。このコンパレータ2が電源切断検出回路となる。図中の3は基準電圧、6は電源電圧が入力される電源入力端子、7はOR回路4の出力信号を出力する出力端子、11は、従来の電源制御補助回路111に相当する回路、82、83は出力短絡検出回路の入力端子、84は出力短絡検出回路の出力端子である。
【0020】
電源切断があると、コンパレータ2の出力はHレベルが出力され、出力短絡の有無に係わらずOR回路4の出力はHレベルとなる。このHレベルの信号が図示しない電源付加回路に与えられ、電源回路と負荷を切り離し、負荷の入力端子が接地される。
また、電源が正常電圧のときは、コンパレータ2の出力はLレベルとなり、出力短絡した場合のみ、出力短絡検出回路81からHレベルの出力信号がOR回路4へ与えられ、OR回路4の出力はHレベルとなる。勿論、出力が正常のときは、Lレベルとなる。
【0021】
このコンパレータ2とOR回路4が半導体チップに占める面積は、従来の電源制御用IC51の面積の数十分の一であり、極めて小さい。従って、この発明の電源制御用IC1のチップ面積は、従来の電源制御用IC51とほぼ同じである。このように、電源制御用ICのチップ面積の増大を抑制して、電源切断および出力短絡を検出し、その検出信号で、電源回路と負荷を切り離し、負荷を接地する信号(OR回路4のHレベルの出力信号)を、電源付加回路に伝送することができる。
【0022】
図2は、本発明の半導体集積回路を搭載した電源回路と電源付加回路と負荷とを示す回路図である。電源回路21は、電源制御用IC1を除く他の回路は、図4と同一である。また、図7の電源回路50の外に設けられていた電源制御補助回路111を、電源制御用IC1内に取り込んでいる。点線部分の回路11がそれである。また、電源制御用IC1の出力短絡検出回路81は従来の出力短絡検出回路と同じである。電源回路21の出力が2個の場合であり、出力端子25、26に接続する負荷の入力端子34、35には、異なる負荷が接続される。
【0023】
つぎに、回路動作を説明する。電源電圧VDDが、電源回路21の入力端子24、電源制御用IC1の電源入力端子6を経由してコンパレータ2のマイナスに入力される。この電圧が基準電圧3より高い場合は、正常の電源電圧であり、低い場合は異常の電源電圧と判断される。電源切断の場合は、異常の電源電圧ということになる。正常の電源電圧の場合は、コンパレータ2の出力信号はLレベルとなり、電源切断など異常な電源電圧の場合は、コンパレータ2の出力信号はHレベルとなる。このコンパレータ2の出力信号と従来回路と同じ出力短絡検出回路81の出力端子84からの出力信号をOR回路4に入力する。電源切断などの場合は、コンパレータ2からHレベルの出力信号がOR回路4に入力されるために、OR回路4の出力信号は、出力短絡検出回路82の出力信号の状態によらず、つまり、出力短絡の有無によらず、Hレベルの信号が出力端子7から出力される。
【0024】
一方、出力短絡した場合は、出力短絡検出回路82の出力信号はHレベルとなり、正常な電源電圧の場合でも、OR回路4の出力信号はHレベルとなる。
このOR回路4の出力端子7からHレベルの信号が電源回路21の出力端子27を経由してpチャネルMOSFET28、29とnチャネルMOSFET32、33のゲートに与えられると、pチャネルMOSFET28、29はオフし、nチャネルMOSFET32、33はオンする。そのため、電源切断および出力短絡の場合、電源回路21と負荷23は、電源付加回路22により切り離される。また、nチャネルMOSFET32、33を短絡することで、負荷23の入力端子34、35が短絡され、負荷23にノイズや浮遊電位が与えられることを防止する。また、コンデンサ30、31の電荷が放電される。また、nチャネルMOSFET32、33をオンすることで、電源回路21および負荷23が、サージ電圧などの侵入によって破壊することを防止し、安全に電源回路および負荷を動作させることができる。
【0025】
尚、コンパレータ2とOR回路4が半導体チップに占める面積は、電源制御用ICの面積の数十分の一であり、極めて小さく、電源制御用IC1のチップ面積は、従来の電源制御用IC51とほぼ同じである。また、前記のpチャネルMOSFETはpnpトランジスタ、nチャネルMOSFETはnpnトランジスタに置き換えても構わない。
【0026】
このように、電源制御補助回路11を電源制御用ICに組み込むことで、電源制御用ICの面積を抑制して、電源切断検出および出力短絡検出を有する電源制御用ICとすることができる。また前記したように、電源制御補助回路11を電源制御用IC1内に組み入れることで、従来の電源制御補助回路111と電源回路50を合わせた構成部品点数と比べて、部品点数を低減できて、電源回路を小型化および低コスト化することができる。
【0027】
図3、図1のOR回路の出力の形態を示し、同図(a)はダイレクト法、同図(b)はnチャネルMOSFET法、同図(c)はpチャネルMOSFET法である。同図(b)、同図(c)のように、nチャネルMOSFET42、pチャネルMOSFET45のドレインに抵抗42、46とコンデンサ43、47と電源44、48を接続することで、OR回路4の出力信号を任意の時間遅延させて、抵抗42、46とコンデンサ43、47の接続点から電源付加回路を制御する信号を出力端子7から取り出すことができる。このnチャネルMOSFET41およびpチャネルMOSFET45のチップに占める面積は、短絡検出回路の十分の一程度と極めて小さく、電源制御用IC1の面積増大は殆どない。
【0028】
【発明の効果】
この発明によれば、電源切断検出回路を1個のコンパレータで構成し、このコンパレータと1個のOR回路で構成される電源制御補助回路を、電源制御用ICに組み込むことで、チップ面積の増大を抑制しつつ、電源切断と出力短絡を検出できる電源制御用ICとすることができる。また、この電源制御用ICを電源回路に搭載することで、この電源制御補助回路を含めた電源回路の部品点数を低減し、この電源回路の小型化と低コスト化を図ることができる。
【図面の簡単な説明】
【図1】この発明の一実施例の半導体集積回路図
【図2】本発明の半導体集積回路を搭載した電源回路と電源付加回路と負荷とを示す回路図
【図3】図1のOR回路の出力の形態を示し、(a)はダイレクト法、(b)はnチャネルMOSFET法、(c)はpチャネルMOSFET法を説明する図
【図4】従来の電源回路の一例を示す回路図
【図5】従来の電源制御用ICの回路図
【図6】出力短絡検出回路の構成図
【図7】従来の電源回路、電源制御補助回路、電源付加回路および負荷で構成される回路図
【符号の説明】
1 電源制御用IC
2 コンパレータ
3 基準電圧
4 OR回路
6、24 電源入力端子
7、25、26、27、84 出力端子
11 電源制御補助回路
21 電源回路
22 電源付加回路
23 負荷
28、29、45 pチャネルMOSFET
30、31、43、47 コンデンサ
32、33、41 nチャネルMOSFET
34、35、82、83 入力端子
42、46 抵抗
44、48 電源
81 出力短絡検出回路
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit such as a power supply control IC, to which an output short-circuit detection function and a power-off function are added.
[0002]
[Prior art]
The power supply circuit used for portable devices and the like is a main circuit composed of an active element such as a power switching element and a passive element such as a capacitor and a coil, and a power supply control IC (integrated) for controlling and protecting the power switching element. Circuit).
[0003]
FIG. 4 is a circuit diagram showing an example of this power supply circuit. The power supply circuit 50 includes a booster circuit that outputs a voltage obtained by boosting the input voltage Vin using an n-channel MOSFET 61 and a step-down circuit that steps down and outputs the input voltage Vin using a p-channel MOSFET 62. These MOSFETs 61 and 62 are driven by a power supply control IC 51. The boosted output voltage is output from the output terminal 68, and the stepped-down output voltage is output from the output terminal 69. Each of the terminals 68 and 69 is connected to a load (not shown). The output voltage output from the output terminals 68 and 69 is detected by a detection circuit (comprising resistors R1, R2, R3, and R4), and the detected voltage is input to the input terminals 53 and 54 of the power supply control IC 51. To do. The detection voltage for detecting the boosted output voltage is the first detection voltage, the detection voltage for detecting the stepped-down output voltage is the second detection voltage, and the first and second detection voltages are input to the input terminals 53 and 54 of the power supply control IC 51. The first and second feedback voltages are set. The pulse width of the gate signal for driving the n-channel MOSFET 61 and the p-channel MOSFET 62 is controlled by the magnitude of these detection voltages, and a stable DC output voltage is output from the power supply circuit 50.
[0004]
FIG. 5 is a circuit diagram of the power supply control IC. The power control IC 51 includes an oscillator 72, a first error amplifier 73, a second error amplifier 74, a first comparator 75, a second comparator 76, a first AND circuit 77, a second AND circuit 78, a first buffer 79, and a second buffer 80. , A constant voltage circuit 71, an output short circuit detection circuit 81, and the like. The constant voltage circuit 71 is a power supply inside the IC that supplies a voltage to the oscillator 72, the error amplifiers 73 and 74, the comparators 75 and 76, and the like, which are blocks.
[0005]
The first feedback voltage is input to the minus of the first error amplifier 73 via the input terminal 53, the reference voltage is applied to the plus of the first error amplifier 73, the output signal of the first error amplifier 73, and the oscillator 72 The output triangular wave voltage is input to the plus of the first comparator 75, the output signal of the first error amplifier 73 is input to the output short circuit detection circuit 81 via the input terminal 82, the output signal of the first comparator 73, The output signal output from the output terminal 84 of the output short circuit detection circuit 81 is input to the first AND circuit 77 and the second AND circuit, the output signal of the first AND circuit is input to the buffer circuit 79, and the output signal of the buffer circuit 79 is 4 is transmitted to the output terminal 55, and the gate signal of the n-channel MOSFET 61 of FIG.
[0006]
On the other hand, the second feedback voltage is input to the second error amplifier 74 via the input terminal 54, and the transmission path of each signal is the same as described above. However, the second buffer circuit 80 at the final stage is an inverting circuit.
FIG. 6 is a configuration diagram of the output short circuit detection circuit. The output short circuit detection circuit 81 includes a third comparator 85 connected to the first error amplifier 73 of FIG. 5 via the input terminal 82, a fourth comparator 86 connected to the second error amplifier 74 and the input terminal 83 of FIG. And an OR circuit 87 to which the output signals of the comparators 85 and 86 are input, and a delay circuit 88 to which the output signal of the OR circuit 87 is input. The delay circuit 88 is a circuit that sends a signal after a predetermined time has passed from the OR circuit 87 as a reference, and is a counter circuit, a capacitor rechargeable circuit, a shift register circuit, or the like. A latch signal is output from the delay circuit 88 via a buffer circuit 89 constituted by a NOT circuit and an output terminal 84, and this latch signal is transmitted to the first and second AND circuits 77 and 78 of FIG. Next, the circuit operation will be described with reference to FIGS. 4, 5, and 6.
[0007]
When the voltage at the output terminal 68 decreases, the output voltage that is the output signal of the first error amplifier 73 increases. The pulse width of the output signal of the first comparator 75 to which this signal and the triangular wave voltage output from the oscillator 72 are input increases. The output signal having a wide pulse width is transmitted to the output terminal 55 via the first AND circuit 77 and the first buffer circuit 79, and is given to the gate of the n-channel MOSFET 61 in FIG. Since the conduction pulse width of the n-channel MOSFET 61 extends, the capacitor 63 is charged, the voltage at the output terminal 68 rises, the voltage drop at the output terminal 68 is compensated, and a constant voltage is supplied from the output terminal 68.
[0008]
For example, when the load connected to the output terminal 68 is short-circuited (in the case of an output short-circuit), the first detection voltage becomes zero voltage, and this first detection voltage is input to the first error amplifier 73, and the first error amplifier 73, an H level signal is input to the output short circuit detection circuit 81, an L level signal is output from the output short circuit detection circuit 81, and this signal is input to the first and second AND circuits 77 and 78. The first and second AND circuits 77 and 78 output L level signals. Therefore, the output voltage from the output terminal 55 becomes L level (0 V), the output voltage at the output terminal 56 becomes H level voltage, the n-channel MOSFET 61 and the p-channel MOSFET 64 in FIG. A load (not shown) to be connected is disconnected.
[0009]
FIG. 7 shows a circuit including a conventional power supply circuit, a power supply control auxiliary circuit, a power supply additional circuit, and a load. This circuit is different from the power supply circuit 50 shown in FIG. 4 in that a power supply additional circuit 90 including p-channel MOSFETs 91 and 92, n-channel MOSFETs 95 and 96, capacitors 93 and 94, a fifth comparator 97, and an OR circuit 98 is used. A circuit to which an auxiliary circuit 111 is added. The power supply circuit 90 has two systems corresponding to the output of the power supply circuit 50 being two outputs, and the loads connected to the input terminals 101 and 102 are also individual. Although one load 100 is shown in the figure, actually, individual loads are connected to the input terminals 101 and 102, respectively.
[0010]
As shown in FIG. 5, the output signal of the output short circuit detection circuit 81 of the power supply control IC 51 used here is not only the input signal of the first and second AND circuits 77 and 78 but also separated from the connection point 59. An output is also output from the output terminal 57 to the outside of the power supply control IC 51.
The power supply voltage is input to the negative of the power supply circuit 50 and the third comparator 97, and output signals output from the output terminal 68 and the output terminal 69 of the power supply circuit 50 are supplied to the sources of the p-channel MOSFETs 91 and 92 of the power supply additional circuit 90. The output from the drains of the p-channel MOSFETs 91 and 92 is input to the load 100. The output signal of the output short circuit detection circuit 81 of the power control IC 51 is input to the OR circuit 98 through the output terminal 70 together with the output signal of the third comparator 97. The output signal of the OR circuit 98 is an n-channel MOSFET 95, It is given to 96 gates.
[0011]
When the output is short-circuited, an H level signal is input from the output terminal 70. Therefore, even if the third comparator 97 outputs an H level signal or an L level signal, the output signal of the OR circuit 98 is at the H level. A high voltage is applied to the gates of the n-channel MOSFETs 95 and 96, and as a result, the input terminals 101 and 102 of the load 100 are grounded.
[0012]
On the other hand, when the power supply is cut off, the input voltage of the fifth comparator 97 falls below the reference voltage 99, so that the output signal of the fifth comparator 97 becomes H level. When this H level output signal is input to the OR circuit 98, the output signal from the output terminal 57 of the output short circuit detection circuit 81 (the output terminal 70 of the power supply circuit 50) does not depend on the H level or L level. The output becomes H level. Therefore, a high voltage is applied to the gates of the n-channel MOSFETs 95 and 96 to turn them on, an H level output signal of the fifth comparator 97 is applied to the gates of the p-channel MOSFETs 91 and 92, and the p-channel MOSFETs 91 and 92 are turned off. As a result, the charge of the capacitor is discharged, the input terminals 101 and 102 are grounded, and the voltage applied to the load becomes zero. Further, the load 100 is disconnected from the power supply circuit 50 regardless of the presence or absence of an output short circuit.
[0013]
As described above, in order to provide a function corresponding to the case where the power is cut off, the power control IC 51 mounted in the power circuit 50 is provided with the power control auxiliary circuit 111 as described above for power control. Apart from the IC, it is necessary to add it outside the power supply circuit 50.
[0014]
[Problems to be solved by the invention]
However, when the power control auxiliary circuit described above is added to the power control IC that constitutes the power circuit, the entire circuit becomes larger and the cost increases.
An object of the present invention is to solve the above-mentioned problems, and while suppressing an increase in chip area, it has a power-off function and an output short-circuit detection function, and a power supply capable of reducing the size and cost of a power circuit The object is to provide a semiconductor integrated circuit which is a control IC.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, a power supply circuit to which a power supply voltage is input, a power supply additional circuit connected between the power supply circuit and a load, and when the power supply voltage is lower than a reference voltage , or the power supply circuit outputs The power supply additional circuit is configured to include a power supply control auxiliary circuit that outputs a signal for grounding the input of the load when the power supply additional circuit is disconnected from the load when the short circuit occurs.
[0016]
The power control assistance circuit, said to supply voltage positive terminal, a comparator the reference voltage is input to the negative terminal, an output short-circuit detection circuit, the output signal of the output signal and the output detection circuit of the comparator is input And the switching element constituting the power supply circuit may be controlled by an output signal of the OR circuit.
[0017]
The power supply additional circuit includes a p-channel MOSFET connected to the output and source of the power supply circuit, a drain connected to the drain of the p-channel MOSFET, one end connected to the ground, and one end connected to the drain of the capacitor. An n-channel MOSFET whose source is connected to the ground, the source of the p-channel MOSFET is the input side of the power supply circuit, and the drain of the n-channel MOSFET is the output side of the power supply circuit. When the voltage is equal to or lower than the reference voltage , or when the output is short-circuited, the p-channel MOSFET is turned off from the OR circuit, the n-channel MOSFET is turned on, the power supply circuit and the load are disconnected, and the load It may be configured to output a signal for grounding the input.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a semiconductor integrated circuit diagram of one embodiment of the present invention. This power supply control IC 1 includes a circuit for detecting power cut and output short circuit, a drive circuit for driving a switching element of a power supply additional circuit (not shown), an overcurrent protection circuit, an overvoltage protection circuit, an overheat protection circuit, and the like. .
[0019]
In this circuit, the comparator 2 to which the power supply voltage (VDD) is inputted to minus and the reference voltage is inputted to plus, the output short circuit detection circuit 81, the output signal of the comparator 2, and the output signal of the output short circuit detection circuit 81 are inputted. OR circuit 4 to be configured. A buffer circuit is incorporated in the output stage of the output short circuit detection circuit. This comparator 2 serves as a power-off detection circuit. In the figure, 3 is a reference voltage, 6 is a power supply input terminal to which a power supply voltage is inputted, 7 is an output terminal for outputting an output signal of the OR circuit 4, 11 is a circuit corresponding to the conventional power control auxiliary circuit 111, 82 , 83 are input terminals of the output short circuit detection circuit, and 84 is an output terminal of the output short circuit detection circuit.
[0020]
When the power is cut off, the output of the comparator 2 is output at the H level, and the output of the OR circuit 4 is at the H level regardless of whether the output is short-circuited. This H level signal is applied to a power supply additional circuit (not shown), the power supply circuit and the load are disconnected, and the input terminal of the load is grounded.
When the power supply is at a normal voltage, the output of the comparator 2 is L level, and only when the output is short-circuited, the output signal of the H level is given from the output short circuit detection circuit 81 to the OR circuit 4, and the output of the OR circuit 4 is Becomes H level. Of course, when the output is normal, it becomes L level.
[0021]
The area occupied by the comparator 2 and the OR circuit 4 in the semiconductor chip is several tenths of the area of the conventional power supply control IC 51 and is extremely small. Therefore, the chip area of the power control IC 1 of the present invention is almost the same as that of the conventional power control IC 51. In this way, an increase in the chip area of the power supply control IC is suppressed, power supply disconnection and output short circuit are detected, and a signal for disconnecting the power supply circuit from the load and grounding the load with the detection signal (H of the OR circuit 4) Level output signal) can be transmitted to the power supply additional circuit.
[0022]
FIG. 2 is a circuit diagram showing a power supply circuit, a power supply additional circuit, and a load on which the semiconductor integrated circuit of the present invention is mounted. The power supply circuit 21 is the same as that shown in FIG. 4 except for the power supply control IC 1. Further, the power control auxiliary circuit 111 provided outside the power circuit 50 in FIG. 7 is incorporated in the power control IC 1. This is the circuit 11 in the dotted line portion. The output short circuit detection circuit 81 of the power supply control IC 1 is the same as the conventional output short circuit detection circuit. This is a case where the power supply circuit 21 has two outputs, and different loads are connected to the load input terminals 34 and 35 connected to the output terminals 25 and 26.
[0023]
Next, circuit operation will be described. The power supply voltage VDD is input to the minus of the comparator 2 through the input terminal 24 of the power supply circuit 21 and the power supply input terminal 6 of the power supply control IC 1. When this voltage is higher than the reference voltage 3, it is a normal power supply voltage, and when it is low, it is determined as an abnormal power supply voltage. In the case of power off, this is an abnormal power supply voltage. In the case of a normal power supply voltage, the output signal of the comparator 2 is L level, and in the case of an abnormal power supply voltage such as power off, the output signal of the comparator 2 is H level. The output signal from the comparator 2 and the output signal from the output terminal 84 of the same output short circuit detection circuit 81 as in the conventional circuit are input to the OR circuit 4. In the case of power off or the like, since the H level output signal is input from the comparator 2 to the OR circuit 4, the output signal of the OR circuit 4 does not depend on the state of the output signal of the output short circuit detection circuit 82, that is, An H level signal is output from the output terminal 7 regardless of whether or not there is an output short circuit.
[0024]
On the other hand, when the output is short-circuited, the output signal of the output short-circuit detection circuit 82 is H level, and the output signal of the OR circuit 4 is H level even when the power supply voltage is normal.
When an H level signal is applied from the output terminal 7 of the OR circuit 4 to the gates of the p-channel MOSFETs 28 and 29 and the n-channel MOSFETs 32 and 33 via the output terminal 27 of the power supply circuit 21, the p-channel MOSFETs 28 and 29 are turned off. The n-channel MOSFETs 32 and 33 are turned on. Therefore, the power supply circuit 21 and the load 23 are disconnected by the power supply additional circuit 22 in the case of power supply disconnection and output short circuit. Further, by short-circuiting the n-channel MOSFETs 32 and 33, the input terminals 34 and 35 of the load 23 are short-circuited, and noise and floating potential are prevented from being applied to the load 23. Further, the electric charges of the capacitors 30 and 31 are discharged. Further, by turning on the n-channel MOSFETs 32 and 33, it is possible to prevent the power supply circuit 21 and the load 23 from being destroyed due to intrusion of a surge voltage or the like, and to operate the power supply circuit and the load safely.
[0025]
Note that the area occupied by the comparator 2 and the OR circuit 4 in the semiconductor chip is a few tenths of the area of the power control IC, and is extremely small. The chip area of the power control IC 1 is the same as that of the conventional power control IC 51. It is almost the same. The p-channel MOSFET may be replaced with a pnp transistor, and the n-channel MOSFET may be replaced with an npn transistor.
[0026]
Thus, by incorporating the power supply control auxiliary circuit 11 in the power supply control IC, the area of the power supply control IC can be suppressed, and a power supply control IC having a power-off detection and an output short-circuit detection can be obtained. Further, as described above, by incorporating the power supply control auxiliary circuit 11 in the power supply control IC 1, the number of components can be reduced as compared with the number of component parts combining the conventional power supply control auxiliary circuit 111 and the power supply circuit 50. The power supply circuit can be reduced in size and cost.
[0027]
FIGS. 3A and 3B show output forms of the OR circuit, FIG. 3A shows the direct method, FIG. 3B shows the n-channel MOSFET method, and FIG. 3C shows the p-channel MOSFET method. The output of the OR circuit 4 is obtained by connecting resistors 42 and 46, capacitors 43 and 47, and power supplies 44 and 48 to the drains of the n-channel MOSFET 42 and the p-channel MOSFET 45 as shown in FIGS. By delaying the signal for an arbitrary time, a signal for controlling the power supply additional circuit can be taken out from the output terminal 7 from the connection point between the resistors 42 and 46 and the capacitors 43 and 47. The area occupied by the chip of the n-channel MOSFET 41 and the p-channel MOSFET 45 is as small as one tenth of the short circuit detection circuit, and the area of the power supply control IC 1 is hardly increased.
[0028]
【The invention's effect】
According to the present invention, the power cut-off detection circuit is composed of one comparator, and the power control auxiliary circuit composed of this comparator and one OR circuit is incorporated in the power control IC, thereby increasing the chip area. It is possible to provide a power supply control IC that can detect power-off and output short-circuit while suppressing the above. Further, by mounting this power supply control IC on the power supply circuit, the number of parts of the power supply circuit including the power supply control auxiliary circuit can be reduced, and the power supply circuit can be reduced in size and cost.
[Brief description of the drawings]
FIG. 1 is a semiconductor integrated circuit diagram of an embodiment of the present invention. FIG. 2 is a circuit diagram showing a power supply circuit, a power supply additional circuit, and a load on which the semiconductor integrated circuit of the present invention is mounted. (A) is a direct method, (b) is an n-channel MOSFET method, and (c) is a p-channel MOSFET method. FIG. 4 is a circuit diagram showing an example of a conventional power supply circuit. 5 is a circuit diagram of a conventional power supply control IC. FIG. 6 is a block diagram of an output short circuit detection circuit. FIG. 7 is a circuit diagram including a conventional power supply circuit, a power supply control auxiliary circuit, a power supply additional circuit, and a load. Explanation of]
1 Power control IC
2 Comparator 3 Reference voltage 4 OR circuit 6, 24 Power input terminal 7, 25, 26, 27, 84 Output terminal 11 Power control auxiliary circuit 21 Power circuit 22 Power supply additional circuit 23 Load 28, 29, 45 p-channel MOSFET
30, 31, 43, 47 Capacitor 32, 33, 41 n-channel MOSFET
34, 35, 82, 83 Input terminals 42, 46 Resistors 44, 48 Power supply 81 Output short circuit detection circuit

Claims (1)

電源電圧が入力される電源回路と、電源回路と負荷との間に接続される電源付加回路と、電源電圧が基準電圧以下のとき、もしくは前記電源回路が出力短絡したとき、前記電源付加回路に前記電源回路と負荷とを切り離させ、且つ、負荷の入力を接地させるための信号を出力する電源制御補助回路を備え、
前記電源制御補助回路は、前記電源電圧がマイナス端子へ、前記基準電圧がプラス端子へ入力されるコンパレータと、出力短絡検出回路と、前記コンパレータの出力信号と出力検出回路の出力信号が入力されるOR回路とを具備し、該OR回路の出力信号で前記電源付加回路を構成するスイッチング素子を制御し、
前記電源付加回路は、電源回路の出力とソースが接続するpチャネルMOSFETと、該pチャネルMOSFETのドレインと一端が接続し、他端がグランドと接続するコンデンサと、該コンデンサの一端とドレインが接続し、ソースがグランドと接続するnチャネルMOSFETと、を具備し、前記pチャネルMOSFETのソースが前記電源付加回路の入力側となり、前記nチャネルMOSFETのドレインが前記電源付加回路の出力側となり、電源電圧が前記基準電圧以下のとき、もしくは出力短絡のとき、前記OR回路から、前記pチャネルMOSFETをオフし、前記nチャネルMOSFETをオンし、前記電源回路と前記負荷とを切り離し、且つ、該負荷の入力を接地する信号を出力することを特徴とする半導体集積回路。
A power supply circuit to which a power supply voltage is input, a power supply additional circuit connected between the power supply circuit and the load, and when the power supply voltage is lower than a reference voltage or when the output of the power supply circuit is short-circuited, A power control auxiliary circuit that outputs a signal for separating the power supply circuit and the load and grounding the input of the load ;
The power supply control auxiliary circuit receives a comparator in which the power supply voltage is input to the negative terminal and the reference voltage is input to the positive terminal, an output short circuit detection circuit, an output signal of the comparator, and an output signal of the output detection circuit. An OR circuit, and controls a switching element constituting the power supply additional circuit by an output signal of the OR circuit,
The power supply circuit includes a p-channel MOSFET to which the output and source of the power supply circuit are connected, a drain and one end connected to the p-channel MOSFET, the other end connected to the ground, and one end and drain of the capacitor connected to each other. An n-channel MOSFET whose source is connected to the ground, the source of the p-channel MOSFET is the input side of the power supply circuit, and the drain of the n-channel MOSFET is the output side of the power supply circuit. When the voltage is equal to or lower than the reference voltage, or when the output is short-circuited, the p-channel MOSFET is turned off from the OR circuit, the n-channel MOSFET is turned on, the power supply circuit and the load are disconnected, and the load Outputs a signal for grounding the input of the semiconductor integrated circuit.
JP2000051157A 2000-02-28 2000-02-28 Semiconductor integrated circuit Expired - Fee Related JP3714091B2 (en)

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