JP3713289B2 - Digital signal processing method - Google Patents

Abstract

PURPOSE:To suppress clip processing and reduce the influence of a foldover noise by detecting the maximum value of an input signal, calculating its reciprocal as an attenuation coefficient by approximation when the detected maximum value is exceeded, and adding a specific value to a last attenuation coefficient and obtaining a new attenuation coefficient when not. CONSTITUTION:An arithmetic control circuit 7 performs repetition until the value of a register 2 reaches 0, decides that a monitor period ends when the value of the register 2 becomes 0, and stores a value corresponding to the monitor period in the register 2 again. Then the value stored in a register 1 is regarded as the maximum value of the monitor period and stored in a register 3, and the register 1 is cleared. When the maximum value is large, the reciprocal of the found maximum value is stored as an attenuation quantity in a register 6. When the maximum value is small, a certain quantity is added to the attenuation quantity in the register 6 which is set last to obtain a new attenuation quantity. Consequently, the clip processing is suppressed and the influence of the foldover noise is reducible.

Description

[0001]
[Industrial application fields]
The present invention relates to a digital signal processing system, and particularly, in an audio apparatus, a code (digital signal) exceeding a specified scale (for example, 16 bits (bits)) enters a specified scale by signal processing such as equalizing. The present invention relates to a signal processing method.
[0002]
[Prior art]
(1) When a music signal encoded (for example, digitized as a 16-bit binary code) is processed by a processor (Processoer) such as a DSP (Digital Signal Processor), the register length is the input signal in the processor. Since it is sufficiently longer than the code length, there is no problem even if the code length in the register exceeds the code length of the input signal (for example, 16 bits) due to processing. For this reason, it must be within a specified scale (for example, 16 bits). For this reason, conventionally, a so-called clip process is performed in which a portion exceeding the specified scale length is forced to become full scale.
[0003]
(2) When the encoded signal is boosted by filtering or the like, a signal close to full scale may exceed the full scale by filtering. However, in the processor, as in the case of (1) described above, there is no problem if the code length in the register exceeds the code length of the input signal due to processing, but it is specified at the time of output. The clip processing was done because it had to fit within the scale.
[0004]
FIG. 4 is an explanatory diagram of clip processing when the scale length is 8 bits. FIGS. 4A and 4B are examples of codes in the register before and after the input signal is processed. a) shows an example of the code in the register before the clip process, and (b) shows an example of the code in the register after the clip process. In FIG. 4A, the codes “00101111” to “01111111” in the register are “01011111” to “1111111” in 8 bits and do not exceed the specified scale length (8 bits). As shown in FIG. 4B, the codes are “00101111” to “01111111”, and the codes in the register are not converted before and after the clipping process, but the codes “10111100” to “10111” in the register are not converted in FIG. Since “101011000” exceeds the specified scale length (8 bits) and is indicated by 9 bits, the code in the register is converted to full scale “1111111” for 8 bits by clip processing. Therefore, the registers are “01111111” to “01111111” as shown in FIG.
[0005]
[Problems to be solved by the invention]
However, in the case of (1) and (2), in the clip processing method, as shown in FIG. 5 (input / output signal waveform and its spectrum), harmonics having the spectrum of the input signal as a fundamental wave are formed (FIG. 5). (See (b ')). In addition, as the clipped portion increases, the harmonic component becomes larger and becomes a wide range (extends to a high frequency range). Among the components, the frequency component higher than 1/2 of the sampling frequency becomes aliasing noise by D / A conversion, and the sound quality is deteriorated. (In FIG. 5, (a) is the input signal waveform before clip processing, (b) is the input signal waveform after clip processing, and (a ') is the spectrum of the input signal waveform before clip processing.) (B ′) is the spectrum of the input signal waveform after the clip processing). As a workaround for the above problem in the case of (2), there is a method of simply attenuating the signal level of the output signal according to the gain of the equalizer as shown in FIG. 6, but the equalizer is operated. As a result, there was a problem that the volume was lowered.
[0006]
The present invention provides (a) a digital signal processing method that suppresses clip processing when an encoded music signal is processed by a processor such as a DSP and reduces the influence of aliasing noise, and (b) An object of the present invention is to provide a digital signal processing method that can suppress a change in volume feeling as much as possible without performing a clipping process even if an encoded signal exceeds a scale defined by a filter process.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a digital signal processing system of the present invention is a digital signal processing system for converting a digital signal exceeding a scale defined by signal processing as a signal within the specified scale, The following steps (1) to (4) are included.
(1) The maximum value of the input signal within a certain period is detected.
(2) It is determined whether or not the maximum value exceeds a maximum value on a specified scale.
(3) If the maximum value exceeds the maximum value on the specified scale, the reciprocal is approximated to obtain an attenuation coefficient. If not, a new value is added to the previous attenuation coefficient by adding a predetermined value. The damping coefficient is
(4) The attenuation coefficient obtained in step (3) above is multiplied by the input signal to obtain an output signal.
[0008]
[Action]
The digital signal processing method of the present invention detects the maximum value of the input signal within a certain period, and if the maximum value exceeds the maximum value on the specified scale, it calculates the reciprocal of the approximation and attenuates it. If it does not exceed the coefficient, a predetermined value is added to the previous attenuation coefficient to obtain a new attenuation coefficient, so that the part exceeding the scale is attenuated mainly. Further, the attenuation is gradually changed by approximate calculation.
[0009]
【Example】
FIG. 1 is a block diagram of the digital signal processing system of the present invention, and FIG. 2 is an example in which the digital signal processing system of the present invention is applied to a DSP 10 having at least registers 1 to 6 and an arithmetic control circuit 7. These are the flowcharts which show one Example of the calculation and setting process of the weighting coefficient of the digital signal processing system of this invention.
[0010]
The digital signal processing system of the present invention is broadly divided as shown in the block diagram of FIG. 1, and (i) calculation and setting of weighting coefficients (ii) the coefficient set in (i) above is set in the input code X as the arithmetic control circuit 7 The above (ii) is a normal calculation process, so the explanation is omitted, and only (i) is explained according to the flowcharts of FIGS. To do.
[0011]
As shown in FIG. 1, the flow of the weighting coefficient calculation and setting process shown in FIG. 3 is as follows: peak value detection (A), reciprocal calculation of peak value (B), coefficient (attenuation) setting (C ) (See FIG. 3 below). First, the time T for monitoring the peak value is stored in the register 2 as an initial setting (step S0).
[0012]
(A) Detection of peak value (steps S1 to S8)
The arithmetic control circuit 7 inputs the input code X (digital signal) (step S1), and subtracts the input code X from the previous maximum value (initial value is 0 (zero)) stored in the register 1. (Step S2), whether the subtraction result D is positive or negative is determined (Step S3). If the result of the positive / negative determination is negative, the input code X is stored in the register 1 (step S4), and 1 is subtracted from the value of the register 2 (step S5). If the result of the positive / negative determination is positive, 1 is subtracted from the value of the register 2 in step S5. The arithmetic control circuit 7 repeats the processing of the above steps S1 to S5 until the value of the register 2 becomes 0. When the value of the register 2 becomes 0, it determines that the monitoring period is over (step S6). The value corresponding to the monitoring period (monitoring period / sampling cycle) is stored again (step S7), and the value stored in the register 1 is stored in the register 3 as the peak value (maximum value Xmax) of the monitoring period. Then, register 1 is cleared (step S8).
[0013]
(B) Calculation of reciprocal of peak value (step S11)
First, it is assumed that the register 4 stores the previous value (previous calculation value) Wn, and the register 5 stores the constant = 1. The reciprocal calculation of the peak value is realized by an approximate calculation performed by repeating the following equation (1) using the fact that the result of multiplying the original value and the reciprocal thereof becomes 1.
Wn = Wn ₋₁ + α · (1−Wn ₋₁ · (Xmax)) (1)
That is, the arithmetic control circuit 7 multiplies the maximum value Xmax obtained in step S8 (see (A)) and stored in the register 3 by the previous value Wn ₋₁ of the register 4, and then stores it in the register 5. Subtracting the result of multiplying the maximum value Xmax and the previous value Wn ₋₁ of the register 4 from a certain constant = 1, obtaining a difference, and multiplying by the weighting coefficient α (0 <α <1), then the previous value Add Wn ₋₁ and store the result in register 4. The reciprocal 1 / Xmax is obtained by repeating the above process several times. However, these processes are based on the assumption that the full scale is 1.
[0014]
(C) Setting of attenuation (coefficient β) (steps S9 to S13)
The arithmetic control circuit 7 compares the specified scale (full scale) with the maximum value Xmax obtained in step S8 (see (A)) (steps S9 and S10), and if the maximum value Xmax is large, step S11 ( The reciprocal number (see (B)) (the reciprocal number of the maximum value = 1 / Xmax) is stored in the register 6 as the attenuation amount β (step S12). When the maximum value Xmax is smaller, a value obtained by adding a fixed amount δ to the previously set attenuation amount (value of the register 6) is set as a new attenuation amount β (step S13). The attenuation β obtained by the above processing is set as a multiplication coefficient of the input signal X, and in (ii) of the block diagram of FIG.
Y = β · X
The output code Y can be obtained as As a result, since the output code Y is simply attenuated, no harmonic component is generated, and since the portion exceeding the scale is intensively attenuated, the level of the entire signal can be reduced. Furthermore, since the attenuation is gradually changed, the output signal does not fluctuate.
[0015]
【The invention's effect】
As described above, according to the present invention, since the output code is simply attenuated, no harmonic component is generated, and the portion exceeding the scale is mainly attenuated, so that the level of the entire signal is deteriorated. Less. Furthermore, since the attenuation is gradually changed, the output signal does not fluctuate.
[Brief description of the drawings]
FIG. 1 is a block diagram of a digital signal processing system of the present invention.
FIG. 2 is an example in which the digital signal processing method of the present invention is applied to a DSP.
FIG. 3 is a flowchart showing an embodiment of weighting coefficient calculation and setting processing of the digital signal processing method of the present invention.
FIG. 4 is an explanatory diagram of a conventional example (clip processing).
FIG. 5 is a diagram showing input / output signal waveforms and spectrums according to a conventional example (clip processing);
FIG. 6 is an explanatory diagram of a conventional example (a method of simply attenuating a signal level in accordance with an equalizer gain).
[Explanation of symbols]
1 to 6 Register 7 Arithmetic control circuit 10 DSP

Claims (1)

A digital signal processing system for converting a digital signal exceeding a scale specified by signal processing as a signal within the specified scale, comprising the following steps (1) to (4): Digital signal processing method.
(1) The maximum value of the input signal within a certain period is detected.
(2) It is determined whether or not the maximum value exceeds a maximum value on a specified scale.
(3) If the above maximum value exceeds the maximum value on the specified scale, the reciprocal is approximated to obtain an attenuation coefficient. The damping coefficient is
(4) The attenuation coefficient obtained in step (3) above is multiplied by the input signal to obtain an output signal.

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