JP3712516B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device having a charge sweeping unit that discharges excess accumulated charges in a pixel (photocell) and a manufacturing method thereof in order to prevent so-called blooming and to function an electronic shutter.
[0002]
[Prior art]
As a charge sweeping unit in a solid-state imaging device, for example, a CCD (Charge Coupled Device), there are a normal horizontal overflow drain LOD (Lateral Overflow Drain) and a vertical type that controls the well potential to dissipate excess charges to the substrate side. VOD (Vertical Overflow Drain) exists.
The horizontal overflow drain is arranged on the substrate surface adjacent to the charge storage layer in parallel with the potential barrier layer whose potential is changed by the upper control electrode, and takes in the surplus charge according to the applied voltage of the control electrode. The capacity is adjusted.
[0003]
FIG. 10 is a partial plan view of a CCD pixel array showing an example of a horizontal overflow drain. 11 is a cross-sectional view taken along the line DD in FIG. 10, and FIG. 12 is a potential diagram of the cross section taken along the line DD in FIG. 10 showing the operation of the overflow drain.
[0004]
In the pixel array 100 illustrated in FIG. 10, cells (photocells) constituting pixels are arranged in an array. In each photocell, a charge storage unit 102 that mainly receives incident light and temporarily stores it after photoelectric conversion, a region where the transfer electrode 104 is disposed, and a transfer channel that extends in the charge transfer direction perpendicular to the transfer electrode 104 are formed. The channel separation layer C / S is roughly divided into regions where electrical separation is performed between adjacent channels.
As shown in FIG. 11, the channel separation layer C / S is partially divided between the two charge storage portions 102 and 102 of the adjacent photocells, and the divided portion is located between the two adjacent photocells. The charge sweeping-out unit 106 shared by each other is provided.
[0005]
The charge sweeping portion 106 includes a central n ⁺ region 112 provided on the surface side in the n well 110 of the p-type semiconductor substrate 108, its left and right p ⁻ regions 114, and an opening of the first interlayer insulating film 116. And a control electrode 118 connected to the n ⁺ region 112 through a portion 116a. The control electrode 118 is laminated with a pad layer 120 made of a conductive polysilicon film in the same layer as the transfer electrode 104, and a second interlayer insulating layer 122 on the pad layer 120, and the channel separation layer C / S. The pad layer 120 and the metal wiring layer 124 are short-circuited at the center portion of the charge sweeping-out portion 106. Note that reference numeral 102a in FIG. 11 denotes a p ⁺ region that is provided on the surface side of the charge accumulation unit 102 and prevents charge accumulation near the substrate surface to improve characteristics.
In the charge sweeping unit 106 configured as described above, the n ⁺ region 112 is a drain, the charge storage unit 102 is a source, the first interlayer insulating layer 116 is a gate insulating film, the pad layer 120 that constitutes the control electrode 118 is a gate electrode, and the drain And the gate is short-circuited to form a ring-shaped MOSFET.
[0006]
The p ⁻ region 114 located in the ring-shaped channel formation region of the MOSFET functions as a potential barrier layer with respect to the charge storage portion 102, and the potential barrier of the p ⁻ region 114 portion according to the voltage applied to the control electrode 118. The height of the can be changed.
When the control electrode 118 shown in FIG. 12A is in a bias state that is low to some extent, the potential of the p ⁻ region 114 is low and a potential barrier having a predetermined height is formed. Therefore, charges (electrons) can be stored up to a certain amount in the charge storage unit 102 according to the initial height of the potential barrier. That is, the size and concentration profile of the p ⁻ region 114 are set so that the potential barrier height necessary for accumulating a predetermined amount of charge in the charge accumulating unit 102 can be obtained. In this state, for example, when strong light is incident on the CCD, the extra charge is guided to the n ⁺ region 112 through the potential barrier and discarded to the control electrode 118. Blooming is suppressed.
[0007]
On the other hand, the reset operation and the like, in a case to be a charge storage layer 102 empty, by applying a relatively high positive voltage to the control electrode 118, as shown in FIG. 12 (b), p ^- the potential of the region 114 As a result, the potential barrier is crushed, and the charge storage capacity (capacitance) of the charge storage layer 102 becomes almost zero. For this reason, almost all accumulated charges are discharged to the control electrode 118 through the n ⁺ region 112.
When the shutter function is activated and light is allowed to enter for a short time, the voltage applied to the control electrode 118 is adjusted according to the shutter time. As a result of this voltage adjustment, the height of the potential barrier changes and the optimum capacity of the charge storage layer 102 is obtained with respect to the amount of incident light. As a result, both the required charge amount and blooming suppression can be achieved.
[0008]
The above-described charge sweeping portion 106 having a MOSFET structure in which the drain and gate are short-circuited has the advantage that the control electrode 118 also serves as the charge sweeping electrode, and the structure is simplified accordingly.
[0009]
[Problems to be solved by the invention]
However, in this conventional charge sweep-out unit 106, if the ring-shaped p ⁻ region 114 does not have a certain width, the dominant force of the electric field by the pad layer 120 becomes insufficient, and the potential barrier height can be controlled. Will drop significantly. Therefore, the potential barrier defined by the width of the p ⁻ region 114 cannot be structurally made to be a submicron region.
In general, in order to reduce the size of a pixel (photocell), it is important to reduce as much as possible the area occupied by the charge sweeping portion and the channel separation layer that does not have light receiving sensitivity. The charge sweeping unit 106 has a disadvantage that the area of the charge sweeping unit 106 cannot be further reduced due to the width of the p ⁻ region 114.
In many solid-state imaging devices, not limited to CCDs, it is essential to reduce the cell area in order to increase the number of effective pixels. With the current photolithography technology, the width of the channel separation layer C / S and the control electrode can be reduced. Despite being able to be made smaller than a micron, the area of the charge sweep-out portion is not reduced at all due to the above reasons.
[0010]
The present invention has been made in view of such circumstances, and a solid-state imaging device having a charge sweeping portion having a new structure that can easily reduce the occupied area without sacrificing controllability of the charge sweeping function, and a method for manufacturing the same The purpose is to provide.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problems of the prior art and achieve the above-described object, a solid-state imaging device of the present invention includes a first conductivity type charge accumulation unit that generates and accumulates signal charges in a semiconductor layer, A solid-state imaging device having a charge sweeping unit adjacent to the charge storage unit and pulling out the accumulated charge in the charge storage unit to the control electrode in accordance with a voltage applied to the control electrode on the semiconductor layer, A first impurity region of the same first conductivity type as the charge storage portion provided on a surface side in the semiconductor layer that is in contact with the control electrode, and a periphery of the first impurity region in the semiconductor layer. surrounding and forming from said and a second impurity region of the second conductivity type is an opposite conductivity type in contact with the charge storage part, wherein the first impurity region, the second impurity region and said charge storage portion The junction type transistor Controlling the potential barrier height of the load sweep unit.
[0012]
This charge sweeping portion is desirably shared between adjacent pixels in order to reduce the area occupied by the pixel. In this case, the two charge storage units need to be adjacent to each other with the channel separation layer interposed therebetween. As a solid-state imaging device having such a pixel configuration, for example, a charge storage unit (light receiving unit) such as a VPCCD (Virtual Phase CCD) or the like. ) Is a solid-state imaging device that also serves as a transfer channel.
In such a solid-state imaging device, since the charge storage unit is also used as a signal charge transfer channel, a potential that has a potential difference from the charge storage unit on the side to which the transfer charge is sent and prevents backflow of the transfer charge. May have a barrier layer. In this case, it is desirable that the potential barrier layer is in contact with the channel separation layer and the channel separation layer at the contact portion is formed wide. In order to block the flow of charge at the wide part of the channel separation layer so that the flow of electric charge that is sent in large quantities at high speed directly hits the charge sweeping part and does not get over the potential barrier and is wasted. It is.
[0013]
In the solid-state imaging device having such a configuration, an npn-type or pnp-type junction transistor type impurity structure is formed between the first and second impurity regions and the charge storage portion. For this reason, when the voltage applied to the control electrode is increased in the predetermined bias direction, a depletion layer extends from the outer first impurity region and the charge storage portion, and the second impurity region is completely depleted, and so-called punch-through is performed. Current starts to flow (charge moves) due to the phenomenon. The applied voltage value to the control electrode where the movement of the charge starts is mainly determined by the concentration profile of each region constituting the junction transistor. In particular, the concentration profile of the second impurity region is the high potential barrier of the charge sweeping portion. It is one of the important factors that determine the degree. Therefore, when the concentration profile of the second impurity region is made shallower and thinner, the controllability of the barrier height does not drop abruptly as in the prior art. Further, since the second impurity region is formed so as to surround the first impurity region, depletion occurs in a wide area. For the above two reasons, the charge sweep-out unit of the solid-state imaging device according to the present invention particularly replaces the intermediate second impurity region that influences the height of the potential barrier with a conventional intermediate region (for example, the p ⁻ region in FIG. 11). 114), and the area occupied by the charge sweeping portion can be reduced.
[0014]
According to a method of manufacturing a solid-state imaging device of the present invention, a charge accumulation unit that generates and accumulates signal charges in a semiconductor layer, and a voltage applied to a control electrode on the semiconductor layer adjacent to the charge accumulation unit. A method of manufacturing a solid-state imaging device in which a potential barrier is controlled by a junction type transistor to form a charge sweeping unit that extracts a stored charge in the charge storage unit to a control electrode, and as a step of forming the charge sweeping unit A step of forming an opening in an interlayer insulating layer formed on the semiconductor layer, and an impurity of the same first conductivity type as the charge storage portion through the opening of the interlayer insulating layer on the surface side in the semiconductor layer And forming the first impurity region, and surrounding the first impurity region in the semiconductor layer and in contact with the charge storage portion, the first impurity region and the charge Accumulation Constituting the junction type transistor with, and forming a second impurity region of the second conductivity type wherein a first conductivity type and the opposite conductivity type, then, in the interlayer insulating layer, the opening The control electrode is formed so as to be connected to the first impurity region through the portion.
[0015]
In order to form the second impurity region so as to surround the first impurity region in this way, preferably, two types of impurities having opposite conductivity types and different diffusion constants are introduced into the semiconductor layer through the opening. When the heat treatment is performed after the introduction, the first and second impurity regions can be collectively formed.
In addition, the second impurity region can function as a potential barrier even at a higher concentration than the conventional intermediate region (for example, the p ⁻ region 114 in FIG. 11). Can be formed.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a solid-state imaging device according to the present invention will be described in detail with reference to the drawings, taking VPCCD as an example.
FIG. 1 is a partial plan view of a pixel array of a VPCCD according to this embodiment. 2 is a sectional view taken along the line AA in FIG. 1, FIG. 3 is a sectional view taken along the line BB in FIG. 1, and FIG. 4A is taken along the line CC in FIG. 4B is a potential diagram along the line CC in FIG. 1 showing the charge transfer operation of the VPCCD, and FIG. 5 is a line AA in FIG. 1 showing the operation of the charge sweeping unit. It is a potential diagram of a section along.
[0017]
In the pixel array 1 shown in FIG. 1, cells (photocells) constituting pixels are arranged in an array. In each photocell, the charge accumulation unit 2 that mainly receives incident light and temporarily accumulates after photoelectric conversion, the arrangement region of the transfer electrode 4, and both sides of the charge transfer direction perpendicular to the transfer electrode 4 extend thereby. The channel separation layer C / S is roughly divided into regions where electrical separation between transfer channels that can be formed is performed.
The channel separation layer C / S is partially divided between the two charge storage portions 2 and 2 of the adjacent photocells, and the charge sweeping portion shared between the two adjacent photocells is present at the divided portion. 6 is provided.
[0018]
As shown in the cross sections of FIGS. 2 and 3, the charge sweeping portion 6 of the present embodiment includes, for example, a first impurity region (n ⁺⁾ provided on the surface side in the n-well 10 of the p-type semiconductor substrate 8. Region 12), a second impurity region (p region 14) surrounding the n ⁺ region 12 in the substrate, and a control electrode connected to the n ⁺ region 12 through the opening 16a of the interlayer insulating film 16 18. The charge sweep-out unit 6 is in contact with the charge storage unit 2 in the cross-sectional direction of FIG. 2, and is in contact with the channel separation layer C / S in the cross-sectional direction of FIG. The channel isolation layer C / S is composed of ap ⁺ impurity region that penetrates the n-well 10 in the depth direction and reaches the bulk region of the semiconductor substrate. As shown in FIG. 3, the interlayer insulating film 16 in this example includes a lower insulating film 20 and an upper insulating film 22, and the transfer electrode 4 is laminated between the insulating films 20 and 22. The control electrode 18 is wired along the channel separation layer C / S.
The charge accumulating section 2 in the cross section of FIG. 2 accumulates charges (electrons) in the n-well 10 portion, and a p ⁺ region 24 is provided on the n-well 10 surface side. The p ⁺ region 24 prevents electric charges from being accumulated near the surface of the semiconductor layer, whereby the photodiode formed by the n-well 10 and the substrate 8 is a buried channel type.
[0019]
The n ⁺ region 12 and the p region 14 of the charge sweeping unit 6 having the above configuration form an npn type junction transistor impurity structure together with the n well 10 portion of the charge storage unit 2 in the cross-sectional direction of FIG. Among these, in particular, the concentration profile of the p region 14 is an important factor in determining the height of the potential barrier of the charge sweeping portion 6, and in order to obtain an optimum concentration profile, the impurity introduction concentration of the p region 14. And depth is set.
[0020]
By the way, the VPCCD is a single-phase drive type in which charge transfer is performed by one-phase pulse, and has a feature in a cross-sectional structure in the charge transfer direction.
That is, as shown in FIG. 4A, the charge storage portion 2 having the p ⁺ region 24 on the surface and the n well 10 in each of the arrangement regions of the transfer electrode 4 are located on the transfer direction side, and more charges are accumulated. The region is divided into two regions having different potentials, such as a well portion that is easily formed and a barrier portion that serves as a potential barrier with respect to the well portion and prevents reverse flow of charges. The predetermined potential difference is realized, for example, by changing the impurity concentration. The well portion and the barrier portion are referred to as a VW portion and a VB portion in the charge storage portion 2, respectively, and are referred to as a PW portion and a PB portion in the arrangement region of the transfer electrode 4, respectively.
[0021]
In the VPCCD, a charge storage unit (VW unit, VB unit) that mainly photoelectrically converts incident light and stores it also serves as a charge transfer channel together with a pulse control unit (PW unit, PB unit) on both sides of the potential transfer direction. The potential is fixed to the middle of the potential amplitude of the pulse control unit when charge transfer is performed by one-phase pulse.
For this reason, the charge storage unit 2 functions as a virtual gate whose potential is fixed in the charge transfer operation. That is, in the example shown in FIG. 4B, when the applied voltage of the transfer electrode 4 is “high (H)”, the potential of the pulse control unit is higher than that of the charge storage unit 2 and the adjacent charge storage unit Accumulated charges (electrons) are sent from the VW unit to the pulse control unit and stored in the PW unit. Next, when the voltage applied to the transfer electrode 4 is low, the potential of the PW portion becomes lower than the VB portion of the cell adjacent in the transfer direction. Moved to the VW section. In this way, the accumulated charges are sent to the cells (photocells) adjacent in the transfer direction at the applied pulses “H” and “L” of the transfer electrode 4, that is, for each applied pulse. When one frame has been transferred to the memory section that is not to be transferred, this time it is horizontally transferred and output from the VPCCD to the outside.
[0022]
Next, the operation of the charge sweeping unit will be described.
FIG. 5 is a potential diagram of a cross section taken along the line AA of FIG.
The charge sweeping unit 6 functions as a potential barrier layer with respect to the charge storage unit 2 and can change the height of the potential barrier according to the voltage applied to the control electrode 18. That is, since the npn type junction transistor type impurity structure is formed in the charge sweeping portion 6 as described above, when the applied voltage of the control electrode is increased in the predetermined bias direction, the n ⁺ regions 12 on both outer sides are increased. After the depletion layer extends inward from the n well 10 portion of the charge storage portion 2 and the intermediate p region 14 is completely depleted, a current starts to flow (charges move) by a so-called punch-through phenomenon. The voltage value applied to the control electrode 18 at which the charge movement starts is mainly determined by the concentration profile of each region constituting the junction transistor, whereby the potential barrier of the charge sweep-out unit 6 is set to a predetermined height. Yes.
[0023]
When the control electrode 18 shown in FIG. 5A is in a biased state that is somewhat low, the potential of the p region 14 is low and a potential barrier having a predetermined height is formed. Therefore, charges (electrons) can be stored up to a certain amount in the n-well 10 portion of the charge storage unit 2 according to the initial height of the potential barrier. That is, the size and concentration profile of the p region 14 are set so that the potential barrier height necessary for accumulating a predetermined amount of charge in the charge accumulating unit 2 is obtained. In this state, for example, when strong light is incident on the CCD, the extra charge is guided to the n ⁺ region 12 through the potential barrier and discarded to the control electrode 18. Therefore, this excessive charge does not flow into the surrounding photocells and is transferred, and as a result, blooming in which bright portions in the vertical band form on the screen due to the channel transfer of the excess charge is effectively suppressed.
[0024]
On the other hand, when it is desired to empty the charge storage unit 2 such as in a reset operation, when a high positive voltage is applied to the control electrode 18, the potential of the p region 14 increases as shown in FIG. As a result, the potential barrier is crushed and the charge amount (capacity) that can be stored in the charge storage unit 2 becomes almost zero. For this reason, almost all accumulated charges are discharged to the control electrode 18 through the n ⁺ region 12.
When the shutter function is activated and light is allowed to enter for a short time, the voltage applied to the control electrode 18 is adjusted according to the shutter time. As a result of this voltage adjustment, the height of the potential barrier changes and the capacity of the charge storage unit 2 that is optimal for the amount of incident light is obtained. As a result, both the required charge amount and blooming suppression can be achieved.
[0025]
In the conventional charge sweep-out unit, the threshold value of the MOSFET determines the height of the potential barrier. However, since the present invention uses the punch-through phenomenon, a current flows only when a relatively high voltage is applied. That is, in the present invention, a high potential barrier height is easily obtained. In addition, when the concentration profile of the p region 14 is made shallower and thinner, the controllability of the barrier height does not drop abruptly as in the prior art. Furthermore, since the p region 14 is formed surrounding the periphery of the n ⁺ region 12, depletion occurs over a wide area.
For the above reason, the charge sweeping unit 6 can narrow the width of the intermediate p region 14 which is one of the factors that greatly influence the height of the potential barrier, and the charge sweeping unit 6 is more likely to have the conventional structure. There is an advantage that the exclusive area can be reduced.
[0026]
Next, a modified example of the charge sweep-out unit 6 will be described with reference to the drawings.
[0027]
In the arrangement example of FIG. 1, in the manufacturing process of the charge sweeping unit 6, any layer or region constituting the charge sweeping unit 6 is shifted in the left-right direction in FIG. For example, desired characteristics represented by the height of the potential barrier cannot be obtained.
In order to avoid this inconvenience, the charge sweeping unit 6 can be provided on the left and right of each cell as shown in FIG. Since the charge sweep-out section 6 in the present invention is small in size, the exclusive area does not increase so much even with such an arrangement.
Further, the charge sweep-out unit 6 may be provided every other column, but as shown in FIG. 7, it may be provided in a check pattern, that is, every other cell in the row direction and the column direction.
[0028]
In the cross-sectional structure of FIG. 2, the control electrode 18 of the charge sweep-out unit 6 is formed of only the metal layer. However, as shown in FIG. 8, the polypad layer 30 that is simultaneously formed in the same layer as the transfer electrode 4 A poly contact structure interposed between the n ⁺ region 12 may be used.
[0029]
Further, in the modification shown in FIG. 9, the channel separation layer C / S portion on the side into which charges flow is formed so as to surround, for example, part of the periphery of the charge sweeping portion 6, and charge accumulation is performed in this wide portion. The portion 2 is in contact with the potential barrier layer (VB portion). In order to prevent the electric charge flow sent in a large amount at a high speed from directly hitting the charge sweeping unit 6 and overcoming the potential barrier, the electric charge flow is widened in the channel separation layer C / S. This is to block at the part.
[0030]
In the manufacture of the charge sweeping portion 6 having the above configuration, preferably, the n ⁺ region 12 and the p region 14 are simultaneously formed in a self-aligning manner.
First, the n-well 10 is formed on the surface of the prepared p-type semiconductor substrate 8 by, for example, ion implantation, and then the opening 16a is formed in the interlayer insulating layer 16 using a normal photolithography processing technique. Next, for example, ion implantation is performed twice through the opening 16a. At this time, impurities having different diffusion constants, such as arsenic and boron, are selected as introduced impurities in the n ⁺ region 12 and the p region 14. Then, when a predetermined heat treatment is performed, an impurity (for example, boron) having a large diffusion constant reaches the substrate deeper than another impurity (for example, arsenic), and as a result, the n ⁺ region of the double diffusion structure shown in FIG. 12 and p region 14 can be obtained.
Thereafter, the control electrode 18 connected to the n ⁺ region 12 is formed.
In the case of forming the polypad layer 30 (FIG. 8), the polypad layer 30 connected to the n ⁺ region 12 is formed during the formation of the interlayer insulating layer 16, that is, after the lower insulating film 20 is formed and opened, A BPSG film, for example, is formed thereon as an upper insulating film 22 and opened, and then a metal layer (control electrode 18) is formed so as to be connected to the polypad layer 30.
[0031]
The channel separation layer C / S is usually formed by ion implantation or the like performed after the formation of the n well 10 and before the formation of the charge sweeping portion 6, but at the same time as the channel separation layer C / S is formed, p. It is preferable that the region 14 is formed in advance in the sense that the process of forming the charge sweeping portion 6 is simplified. However, since there is no difference between the concentration profiles of the two, if this cannot be ignored in terms of characteristics, it is necessary to perform additional ion implantation into the channel separation layer C / S or to form both separately as described above.
[0032]
The above is an example of a frame transfer method, in particular, a single-layer drive VPCCD, but the CCD transfer method is not limited. The present invention can also be applied to solid-state imaging devices other than CCDs.
[0033]
【The invention's effect】
According to the solid-state imaging device of the present invention, the impurity structure of the junction transistor is formed from the first and second impurity regions of the charge sweep-out unit and the charge storage unit. Therefore, the height of the potential barrier can be made higher than that of the charge sweeping portion of the conventional MOSFET structure, and in particular, the controllability with respect to the height of the potential barrier is rapidly reduced by reducing the width of the second impurity region. As a result, the area occupied by the charge sweeping portion can be made smaller than before.
[Brief description of the drawings]
FIG. 1 is a partial plan view of a pixel array of a VPCCD according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line AA in FIG.
3 is a cross-sectional view taken along line BB in FIG. 1. FIG.
4A is a cross-sectional view taken along the line CC of FIG. 1, and FIG. 4B is a potential diagram taken along the line CC of FIG. 1 showing the charge transfer operation of the VPCCD. .
5 is a potential diagram of a cross section taken along the line AA in FIG. 1 showing the operation of the charge sweeping unit. FIG. 5 (a) shows a low bias state, and FIG. 5 (b) shows a sufficient bias voltage. The applied state is shown.
FIG. 6 is a partial plan view of a pixel array showing a modified example related to the number of arranged charge sweep-out portions.
FIG. 7 is a plan view of a part of a pixel array showing a modification of how to dispose the charge sweeping portion.
FIG. 8 is a cross-sectional view showing a modification of the control electrode structure of the charge sweep-out unit.
FIG. 9 is a partial plan view of a pixel array showing a modification of the surrounding channel separation layer in the charge sweeping portion.
FIG. 10 is a partial plan view of a CCD pixel array showing an example of a conventional horizontal overflow drain.
11 is a cross-sectional view taken along the line DD of FIG.
12 is a potential diagram of a cross section taken along the line DD of FIG. 10 showing the operation of the overflow drain. FIG. 12A is a low bias state, and FIG. 12B is a sufficiently bias voltage applied. Indicates the state.
[Explanation of symbols]
1 ... Pixel array,
2 ... charge storage part,
4 ... Transfer electrode,
6 ... Charge sweeper,
8 ... Semiconductor substrate,
10 ... n-well,
12... N ⁺ region (first impurity region),
14 ... p region (second impurity region),
16 ... interlayer insulating layer, 16a ... opening,
18: Control electrode.

Claims (8)

A charge accumulation unit of a first conductivity type that generates and accumulates signal charges in the semiconductor layer, and an accumulated charge in the charge accumulation unit adjacent to the charge accumulation unit and in accordance with a voltage applied to the control electrode on the semiconductor layer A solid-state imaging device having a charge sweeping unit that pulls out a control electrode,
The charge sweeping portion is
A first impurity region of the same first conductivity type as that of the charge storage portion provided on the surface side in the semiconductor layer in contact with the control electrode;
The surrounds of the first impurity region in the semiconductor layer, and has a second impurity region of the second conductivity type is an opposite conductivity type in contact with the charge storage unit,
A solid-state imaging device that controls a potential barrier height of the charge sweep-out unit by a junction transistor formed from the first impurity region, the second impurity region, and the charge storage unit . The solid-state imaging device according to claim 1, wherein the charge storage unit also serves as a signal charge transfer channel. The solid-state imaging device according to claim 2, wherein a potential barrier layer that has a potential difference from the charge storage unit and prevents backflow of the transfer charge is provided on a side to which the transfer charge of the charge storage unit is sent. The solid-state imaging device according to claim 1, wherein the charge sweep-out unit is disposed between two charge storage units of adjacent pixels. The charge sweeping unit is disposed with a channel separation layer between two charge storage units of adjacent pixels,
The solid-state imaging device according to claim 3, wherein the potential barrier layer is in contact with the channel separation layer on a side where transfer charges are sent to the charge storage unit. The solid-state imaging device according to claim 5, wherein the channel separation layer is formed to have a wide portion in contact with the potential barrier layer. A charge accumulation unit that generates and accumulates signal charges in a semiconductor layer, and a potential barrier height is controlled by a junction type transistor according to a voltage applied to a control electrode on the semiconductor layer adjacent to the charge accumulation unit. A method of manufacturing a solid-state imaging device that forms a charge sweeping unit that draws out the accumulated charge in the charge storage unit to a control electrode,
Forming the openings in an interlayer insulating layer formed on the semiconductor layer as a step of forming the charge sweeping portion;
Introducing a first conductivity type impurity, which is the same as that of the charge storage portion, through the opening of the interlayer insulating layer on the surface side in the semiconductor layer to form a first impurity region;
Forming the junction transistor together with the first impurity region and the charge storage portion at a position surrounding the first impurity region in the semiconductor layer and in contact with the charge storage portion; and a step of forming a mold and a second impurity region of the second conductivity type is an opposite conductivity type,
Thereafter, the control electrode is formed on the interlayer insulating layer so as to be connected to the first impurity region through the opening. A method for manufacturing a solid-state imaging device. The first and second impurity regions are collectively formed by introducing two types of impurities having opposite conductivity types and different diffusion constants into the semiconductor layer through the opening, and then performing a heat treatment. Item 8. A method for manufacturing a solid-state imaging device according to Item 7.

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