JP3706226B2 - Intermediate and manufacturing method of ball grid array package - Google Patents

Intermediate and manufacturing method of ball grid array package Download PDF

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Publication number
JP3706226B2
JP3706226B2 JP17302297A JP17302297A JP3706226B2 JP 3706226 B2 JP3706226 B2 JP 3706226B2 JP 17302297 A JP17302297 A JP 17302297A JP 17302297 A JP17302297 A JP 17302297A JP 3706226 B2 JP3706226 B2 JP 3706226B2
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substrate
grid array
ball grid
array package
manufacturing
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JPH118334A (en
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澄夫 中野
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Sumitomo Metal SMI Electronics Device Inc
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/22—Secondary treatment of printed circuits
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  • Engineering & Computer Science (AREA)
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【０００１】
【技術分野】
本発明は，ボールグリッドアレイパッケージを構成する複数の基板ユニットに分割することのできるボールグリッドアレイパッケージ部品製造用の中間体，並びにボールグリッドアレイパッケージの電子部品の製造方法に関する。
【０００２】
【従来技術】
ボールグリッドアレイパッケージの電子部品９０の基本的な構成は，図４に示すように，基板９２に搭載された半導体チップなどの半導体素子９１と，プリント配線基板９６に接合し且つ電気的に接続するための半田ボール９３とを有し，樹脂モールド９５で半導体素子９１を気密封止したり，絶縁性のキャップを用いて封止したりしている。同図において，符号９４１はボンディングワイヤー，符号９４２は基板９２に形成された導体回路である。
【０００３】
そして，上記ボールグリッドアレイパッケージの電子部品９０を製造する手順は，始めに基板９２と半導体素子９１とをそれぞれ別個の工程で製作し，続いて基板９２に素子９１を接合すると共にボンディングワイヤー９４２で基板９２と素子９１とを接続し，その後，樹脂モールド９５で半導体素子９１を気密封止し，或いは絶縁性のキャップを用いて封止する。
【０００４】
なお，半導体素子の基板９２への接続方法としては，フリップチップ方式のようなボンディングワイヤーを使用しない方法もある。
そして，基板９２の材料は，例えばアルミナ等のセラミックが多く用いられている。また，プリント配線基板９６には，合成樹脂製の基板が多く用いられている。
【０００５】
【解決しようとする課題】
しかしながら，上記ボールグリッドアレイパッケージの電子部品９０の基板９２としてセラミックを用い，合成樹脂製のプリント配線基板９６に搭載した場合には，次のような問題点がある。
【０００６】
それは，セラミック製の基板９２と合成樹脂製のプリント配線基板９６との間の熱膨張係数の差により，電子部品９０とプリント配線基板９６との間に熱応力が働き，半田ボール９３にクラック等が発生して接合信頼性を著しく損なうため，ボールグリッドアレイパッケージの大きさ（面積）が制限されることである。
【０００７】
大きさが制限される理由は，基板９２の面積が大きいほど上記両部間に働く熱応力の大きさも大きくなるからである。その結果，電子部品１個当たりの大きさ（面積）が制限され，ひいては電子部品を搭載するプリントボード及び装置の小型化も妨げられることになる。
例えば，基板９２にアルミナを用い，プリント配線基板９６の材料としてガラスエポキシ等を用いた場合には，上記ボールグリッドアレイパッケージの大きさは２５ｍｍ×２５ｍｍ程度に制限される。
【０００８】
また，第２の問題点として，電子部品９０を製造する中間段階において，基板９２や素子９１を運搬したり保管したりする場合に，基板９２や素子９１が損傷するという問題がある。
【０００９】
本発明は，かかる従来の問題点に鑑みてなされたものであり，電子部品と電子部品を搭載する樹脂製のプリント配線板との間の熱応力を軽減して部品を大型化する第１の課題と，製造段階における基板などの損傷を低減することのできる第２の課題とを解決するボールグリッドアレイパッケージ製造用の中間体の提供，並びに上記課題を解決するボールグリッドアレイパッケージの電子部品の製造方法を提供しようとするものである。
【００１０】
【課題の解決手段】
本願の第１発明は，ボールグリッドアレイパッケージを構成する複数の基板ユニットに分割することのできるパッケージ製造用の中間体であって，外部接続用の半田ボールを備え単一のボールグリッドアレイパッケージに対応する同一の区画を複数個備えた単一の合成樹脂製の樹脂基板と，素子との接続端子を備え上記樹脂基板の各区画に接合される複数のセラミック基板とを有しており，上記セラミック基板の底面と樹脂基板の上面との間は，導電体により電気的に接続すると共に合成樹脂製のアンダーフィルが充填されており，上記アンダーフィルの熱膨張係数は，上記セラミック基板の熱膨張係数と上記樹脂基板の熱膨張係数の中間の値を有していることを特徴とするボールグリッドアレイパッケージ製造用の中間体にある。
【００１１】
本発明において特に注目すべきことの第一点は，中間体を構成する樹脂基板には，半田ボールを備え単一のボールグリッドアレイパッケージを形成する区画が複数個形成されており，上記樹脂基板の各区画にはセラミック基板が接合されていることである。従って，上記樹脂基板を切断し各区画に分割することにより，上記中間体から，単一のボールグリッドアレイパッケージを構成する複数の基板ユニットを得ることができる。そして，上記基板ユニットは，外部接続用の半田ボールを備えた樹脂基板と素子を搭載するセラミック基板とからなる。
【００１２】
上記のように，上記中間体は複数の基板ユニットを一体として保持するから，電子部品を製造する中間段階において，基板ユニットを運搬したり保管したりする場合に，取り扱いが容易になると共に，バラバラの基板ユニットで保持する場合に比べて基板ユニットの損傷が生じにくくなり，製品の品質を向上させることができる。
【００１３】
本発明において特に注目すべきことの第二点は，上記基板ユニットには，素子を搭載するセラミック基板の他に底面に半田ボールを接合した合成樹脂製の樹脂基板がもう一つ設けられており，かつ上記セラミック基板と樹脂基板との間にアンダーフィルを介設させてあること，そして，上記アンダーフィルの熱膨張係数は，上記セラミック基板の熱膨張係数と上記樹脂基板の熱膨張係数の中間の値を有していることである。
【００１４】
その結果，第１の作用効果として，底部に位置する外部との接続用の基板を樹脂基板としたことにより，電子部品が搭載されるプリント配線基板を合成樹脂製の基板とした場合にも，電子部品の底部とプリント配線基板との間に働く熱応力を小さくすることができる。
何故ならば，従来のように電子部品の底部をセラミック基板とした場合に比べて，樹脂製のプリント配線基板とパッケージ底部との間の熱膨張係数の差が少なくなるからである。従って，より面積の大きな大型のボールグリッドアレイパッケージを電子部品用に使用することが可能となり，電子装置の集約度を向上させることができる。
【００１５】
また，第２の作用効果として，パッケージの内部においては，セラミック基板と樹脂基板の間に中間的な熱膨張係数のアンダーフィルを介設させてあるため，上記上下の基板間に働く熱応力は分散されて低減することがある。
その結果，上記のようにボールグリッドアレイパッケージの面積を大きくしても，セラミック基板と樹脂基板との間の強度の低下や信頼性の低下などの不具合が生じにくくなる。
【００１６】
上記のように，本発明によれば，電子部品と電子部品を搭載する樹脂製のプリント配線板との間の熱応力を軽減して部品を大型化する第１の課題と，製造段階における基板などの損傷を低減することのできる第２の課題とを同時に解決するボールグリッドアレイパッケージ製造用の中間体の提供することができる。
【００１７】
なお，複数のユニット（区画）からなる上記中間体は，請求項２に記載のように，更に，セラミック基板に半導体素子を実装し素子シールまたはケーシングを施したものとしてもよい。そして，上記素子付きの中間体を各区画に分割してボールグリッドアレイパッケージ部品の完成体を得る。
【００１８】
また，請求項３に記載のように，セラミック基板の底面と樹脂基板の上面とを接続する導電体を半田部材とした場合には，外部接続用の半田ボールは，前記中継用の半田部材よりも融点が低い共晶半田とすることが好ましい。
これによって，ボールグリッドアレイパッケージのプリント配線板への接続時に，外部接続用の半田ボールを介して，中継用の半田が溶融する不具合を防止することができるからである。その結果，ボールグリッドアレイパッケージ部品をプリント配線板へ搭載する時に加熱されても，セラミック基板と樹脂基板の間の半田部材は溶融したりしないので，セラミック基板と樹脂基板の間の剥離やズレ等の問題は起こらなくなる。
【００１９】
一方，本願の第２発明は，ボールグリッドアレイパッケージの電子部品の製造方法であって，外部接続用の半田ボールを備えた複数の区画からなる単一の合成樹脂製の樹脂基板を製作する第１の工程と，搭載する素子との接続端子を備えたセラミック基板を製作する第２の工程と，上記樹脂基板の各区画に上記セラミック基板を接合する第３の工程と，樹脂基板へ搭載後の上記セラミック基板に素子を実装しシールまたはケーシングを行う第４の工程と，素子実装後の上記樹脂基板を各区画別に切断する第５の工程とからなり，上記第３工程においては，セラミック基板の底面と樹脂基板の上面との間を導電体により電気的に接続すると共に両面間に合成樹脂製のアンダーフィルを充填して接合し，上記アンダーフィルの熱膨張係数を上記セラミック基板の熱膨張係数と上記樹脂基板の熱膨張係数の中間の値に設定することを特徴とするボールグリッドアレイパッケージの電子部品の製造方法にある。
【００２０】
本発明において特に注目すべきことの第一点は，第１工程で製作する樹脂基板には，半田ボールを備え単一のボールグリッドアレイパッケージを形成する区画が複数個形成されており，第３工程において上記樹脂基板の各区画にセラミック基板が接合され，続く第４工程において素子が実装されることである。従って，第５工程において上記樹脂基板を切断し各区画に分割することにより，単一のボールグリッドアレイパッケージを構成する複数のボールグリッドアレイパッケージ部品を得ることができる。
【００２１】
上記のように，第３，第４工程での中間体は複数の基板ユニットを一体として保持するから，電子部品を製造する中間段階において，基板ユニットを運搬したり保管したりする場合に，取り扱いが容易になると共に，バラバラの基板ユニットで保持する場合に比べて基板ユニットの損傷が生じにくくなり，製品の品質を向上させることができる。
【００２２】
本発明において特に注目すべきことの第二点は，上記基板ユニットには，素子を搭載するセラミック基板の他に底面に半田ボールを接合した合成樹脂製の樹脂基板がもう一つ設けられており，かつ上記セラミック基板と樹脂基板との間にアンダーフィルを介設させてあること，そして，上記アンダーフィルの熱膨張係数は，上記セラミック基板の熱膨張係数と上記樹脂基板の熱膨張係数の中間の値を有していることである。
【００２３】
その結果，上記構成から前記第１発明で述べたと同様の第１，第２の作用効果を得ることができる。
従って，本発明によれば，電子部品と電子部品を搭載する樹脂製のプリント配線板との間の熱応力を軽減して部品を大型化する第１の課題と，製造段階における基板などの損傷を低減することのできる第２の課題とを同時に解決するボールグリッドアレイパッケージ部品の製造方法を提供することができる。
【００２４】
そして，請求項５に記載のように，セラミック基板の底面と樹脂基板の上面とを接続する導電体を半田部材とした場合には，外部接続用の半田ボールは，前記中継用の半田部材よりも融点が低い共晶半田とすることが好ましい。
これによって，ボールグリッドアレイパッケージのプリント配線板への接続時に，外部接続用の半田ボールを介して，中継用の半田が溶融する不具合を防止することができるからである。
【００２５】
【発明の実施の形態】
実施形態例
本例は，図１（ｅ）に示すボールグリッドアレイパッケージの電子部品８１の製造方法であって，図２に示すように外部接続用の半田ボール１５を備えた複数の区画１１からなる単一の合成樹脂製の樹脂基板１０を製作する第１の工程と，搭載する半導体素子３１との接続端子２１を備えた図１（ａ）に示すセラミック基板２０を製作する第２の工程と，図１（ｂ），（ｃ）に示すように樹脂基板１０の各区画１１（図２，図３）にセラミック基板２０を接合する第３の工程と，図１（ｄ）に示すように樹脂基板１０へ搭載後のセラミック基板２０に半導体素子３１を実装する第４の工程と，素子３１の実装後の樹脂基板１０を各区画１１別に切断し，図１（ｅ）に示すように単一のボールグリッドアレイパッケージ部品８１を得る第５の工程とからなる。
【００２６】
そして，図１（ｂ），（ｃ）に示すように，上記第３工程においては，セラミック基板２０の底面と樹脂基板１０の上面との間を半田部材２５により電気的に接続すると共に両面間に合成樹脂製のアンダーフィル２７を充填して接合する。そして，アンダーフィル２７の熱膨張係数をセラミック基板２０の熱膨張係数と樹脂基板１０の熱膨張係数の中間の値に設定する。
【００２７】
上記のように，第３工程により製作されたボールグリッドアレイパッケージ部品８１製造用の第１の中間体８５１は，図１（ｃ）に示すように，外部接続用の半田ボール１５を備え単一のボールグリッドアレイパッケージに対応する同一の区画１１を複数個備えた単一の合成樹脂製の樹脂基板１０と，半導体素子３１との接続端子２１を備え樹脂基板１０の各区画１１に接合される複数のセラミック基板２０とを有している。
【００２８】
そして，セラミック基板２０の底面と樹脂基板１０の上面との間は，半田部材２５により電気的に接続すると共に合成樹脂製のアンダーフィル２７が充填されている。また，外部接続用の半田ボール１５は，上記半田部材２５よりも融点が低い共晶半田である。
そして，図１（ｄ），図３に示すように，第４工程終了時における第２中間体８５２には，半導体素子３１が実装されている。
【００２９】
以下それぞれについて説明を補足する。
樹脂基板１０の本体を形成する合成樹脂はガラスエポキシであり，セラミック基板１１との間に充填されるアンダーフィル２７の材料はエポキシ樹脂である。
そして，中継用の半田部材２５は，融点２８０℃ぐらいの高融点半田であり，半田ボール１５は，中継用の半田部材２５よりも融点が低い共晶半田である。
なお図１（ｄ），（ｅ）において，符号３２はボンディングワイヤー，符号１３は半田部材２５と半田ボール１５との間を接続するビアホールである。
【００３０】
そして，上記ボールグリッドアレイパッケージの電子部品８１は，次のような工程により製作される。
始めに図示しない回路パターンとビアホールとを形成したセラミック基板２０と，ビアホール１３を形成した樹脂基板１０とを別個に製作し，図１（ｂ）に示すように，樹脂基板１０とセラミック基板２０とを中継用の半田部材２５で接合する。
【００３１】
その後，同図（ｃ）に示すように，樹脂を注入する方法によりアンダーフィル２７を両基板１０，２０の間に形成し，第１の中間体８５１を得る。その後は，同図（ｄ），図３に示すように，従来と同様の方法により半導体素子３１を搭載し，ボンディングワイヤー３２で接続し，第２の中間体８５２を得る。
上記のように素子３１を実装した後，素子部全体を樹脂４１で封止して樹脂基板１０を各区画１１別に切断し，図１（ｅ）に示すように単一のボールグリッドアレイパッケージ部品８１を得る。
【００３２】
本例の電子部品８１の製造方法においては，第１工程で製作する樹脂基板１０には，半田ボール１５を備え単一のボールグリッドアレイパッケージを形成する区画１１が複数個形成されており，第３工程において上記樹脂基板１０の各区画１１にセラミック基板２０が接合される。そして，続く第４工程において半導体素子３１が実装され，第５工程において上記樹脂基板１０を切断し各区画１１に分割することにより，単一のボールグリッドアレイパッケージ部品８１を得ることができる。
【００３３】
上記のように，第３，第４工程で中間体８５１，８５２を形成し，そこに最終的に分離独立し単一のボールグリッドアレイパッケージを構成する複数の基板ユニットを一体として保持するから，電子部品８１を製造する中間段階において，上記基板ユニットを運搬したり保管したりする場合に，バラバラの基板ユニットで保持する場合に比べて基板ユニットの損傷が生じにくくなり，製品の品質を向上させることができる。
【００３４】
また，上記基板ユニットには，素子３１を搭載するセラミック基板２０の他に底面に半田ボールを接合した外部接続用の樹脂基板１０がもう一つ設けられている。また，上記セラミック基板２０と樹脂基板１０との間にアンダーフィル２７を介設させてあり，アンダーフィル２７の熱膨張係数は，セラミック基板２０の熱膨張係数と樹脂基板１０の熱膨張係数の中間の値を有している。
【００３５】
その結果，外部接続用の基板１０を合成樹脂製としたことにより，電子部品８１が搭載されるプリント配線基板を合成樹脂基板とした場合にも，電子部品８１の底部とプリント配線基板との間に働く熱応力を小さくすることができる。
樹脂製のプリント配線基板と部品８１での接合部（樹脂基板１０）との間の熱膨張係数の差が少なくなるからである。従って，より面積の大きな大型のボールグリッドアレイパッケージを電子部品用にに使用することが可能となり，電子装置の集約度を向上させることができる。
【００３６】
また，パッケージの内部においては，セラミック基板２０と樹脂基板１０の間に両者の中間的な熱膨張係数のアンダーフィル２７を介設させてあるため，上下の基板１０，２０に働く熱応力は分散されて低減する。
その結果，上記のようにボールグリッドアレイパッケージの面積を大きくしても，セラミック基板２０と樹脂基板１０との間の強度の低下や信頼性の低下などの不具合が生じにくくなる。
【００３７】
従って，本例によれば，電子部品８１と電子部品８１を搭載する樹脂製のプリント配線板との間の熱応力を軽減して部品８１を大型化する第１の課題と，製造段階における基板１０，２０の損傷を低減することのできる第２の課題とを同時に解決することのできるボールグリッドアレイパッケージ部品８１の製造方法を提供することができる。
【００３８】
【発明の効果】
上記のように本発明によれば，電子部品と電子部品を搭載する樹脂製のプリント配線板との間の熱応力を軽減して部品を大型化する第１の課題と，製造段階における基板などの損傷を低減することのできる第２の課題とを同時に解決するボールグリッドアレイパッケージ製造用の中間体，並びに上記課題を解決するボールグリッドアレイパッケージの電子部品の製造方法を得ることができる。
【図面の簡単な説明】
【図１】実施形態例の電子部品の製造方法の第３〜第５工程の流れを示す図。
【図２】図１（ｄ）に示す中間体の区画の構成を示す正面断面図。
【図３】図２の平面図。
【図４】ボールグリッドアレイパッケージの電子部品の一例を示す断面図。
【符号の説明】
１０．．．樹脂基板，
１１．．．半田ボール
２０．．．セラミック基板，
２１．．．接続端子，
２５．．．導電体（半田部材），
２７．．．アンダーフィル，
３１．．．素子，
８１．．．ボールグリッドアレイパッケージ部品，
８５１，８５２．．．中間体，[0001]
【Technical field】
The present invention relates to an intermediate for manufacturing a ball grid array package component that can be divided into a plurality of substrate units constituting a ball grid array package, and a method for manufacturing an electronic component of the ball grid array package.
[0002]
[Prior art]
As shown in FIG. 4, the basic configuration of the electronic component 90 of the ball grid array package is bonded to and electrically connected to a semiconductor element 91 such as a semiconductor chip mounted on a substrate 92 and a printed wiring board 96. The semiconductor element 91 is hermetically sealed with a resin mold 95 or sealed with an insulating cap. In the figure, reference numeral 941 denotes a bonding wire, and reference numeral 942 denotes a conductor circuit formed on the substrate 92.
[0003]
The procedure for manufacturing the electronic component 90 of the ball grid array package is as follows. First, the substrate 92 and the semiconductor element 91 are manufactured in separate steps, then the element 91 is bonded to the substrate 92 and the bonding wire 942 is used. The substrate 92 and the element 91 are connected, and then the semiconductor element 91 is hermetically sealed with a resin mold 95 or sealed with an insulating cap.
[0004]
As a method for connecting the semiconductor element to the substrate 92, there is a method that does not use a bonding wire such as a flip chip method.
As the material of the substrate 92, for example, a ceramic such as alumina is often used. Further, as the printed wiring board 96, a board made of synthetic resin is often used.
[0005]
[Problems to be solved]
However, when ceramic is used as the substrate 92 of the electronic component 90 of the ball grid array package and mounted on the printed wiring board 96 made of synthetic resin, there are the following problems.
[0006]
This is because a thermal stress acts between the electronic component 90 and the printed wiring board 96 due to a difference in thermal expansion coefficient between the ceramic substrate 92 and the synthetic resin printed wiring board 96, and the solder balls 93 are cracked. Occurs and the bonding reliability is remarkably impaired, so that the size (area) of the ball grid array package is limited.
[0007]
The reason why the size is limited is that the larger the area of the substrate 92, the greater the magnitude of the thermal stress acting between the two parts. As a result, the size (area) per electronic component is limited, and as a result, miniaturization of the printed board and the device on which the electronic component is mounted is hindered.
For example, when alumina is used for the substrate 92 and glass epoxy is used as the material of the printed wiring board 96, the size of the ball grid array package is limited to about 25 mm × 25 mm.
[0008]
Further, as a second problem, there is a problem that the substrate 92 and the element 91 are damaged when the substrate 92 and the element 91 are transported or stored in an intermediate stage of manufacturing the electronic component 90.
[0009]
The present invention has been made in view of such conventional problems, and is a first method for reducing the thermal stress between an electronic component and a resin printed wiring board on which the electronic component is mounted, thereby increasing the size of the component. An intermediate for manufacturing a ball grid array package that solves the problem and the second problem that can reduce damage to a substrate or the like in the manufacturing stage, and an electronic component of the ball grid array package that solves the above problem A manufacturing method is to be provided.
[0010]
[Means for solving problems]
A first invention of the present application is an intermediate for manufacturing a package that can be divided into a plurality of substrate units constituting a ball grid array package, and includes a solder ball for external connection in a single ball grid array package. A resin substrate made of a single synthetic resin having a plurality of corresponding identical sections, and a plurality of ceramic substrates having connection terminals for elements and bonded to the sections of the resin substrate, The bottom surface of the ceramic substrate and the top surface of the resin substrate are electrically connected by a conductor and filled with a synthetic resin underfill. The thermal expansion coefficient of the underfill is the thermal expansion coefficient of the ceramic substrate. It has an intermediate value between the coefficient and the thermal expansion coefficient of the resin substrate.
[0011]
The first point that should be particularly noted in the present invention is that the resin substrate constituting the intermediate body is formed with a plurality of sections having solder balls and forming a single ball grid array package. That is, a ceramic substrate is bonded to each section. Therefore, a plurality of substrate units constituting a single ball grid array package can be obtained from the intermediate body by cutting the resin substrate and dividing it into sections. The substrate unit includes a resin substrate provided with solder balls for external connection and a ceramic substrate on which elements are mounted.
[0012]
As described above, since the intermediate body integrally holds a plurality of board units, when the board unit is transported or stored in an intermediate stage of manufacturing an electronic component, it is easy to handle and separate. Compared with the case of holding the substrate unit, the substrate unit is less likely to be damaged, and the product quality can be improved.
[0013]
The second point that should be particularly noted in the present invention is that the substrate unit is provided with another synthetic resin resin substrate having solder balls bonded to the bottom surface in addition to the ceramic substrate on which the element is mounted. And an underfill is interposed between the ceramic substrate and the resin substrate, and the thermal expansion coefficient of the underfill is intermediate between the thermal expansion coefficient of the ceramic substrate and the thermal expansion coefficient of the resin substrate. Having a value of.
[0014]
As a result, as a first effect, even when the printed wiring board on which the electronic component is mounted is made of a synthetic resin board by using the resin board as the board for connection with the outside located at the bottom, Thermal stress acting between the bottom of the electronic component and the printed wiring board can be reduced.
This is because the difference in coefficient of thermal expansion between the printed wiring board made of resin and the bottom of the package is reduced as compared with the conventional case where the bottom of the electronic component is a ceramic substrate. Therefore, a large ball grid array package having a larger area can be used for electronic components, and the degree of integration of the electronic device can be improved.
[0015]
As a second effect, since an underfill having an intermediate thermal expansion coefficient is interposed between the ceramic substrate and the resin substrate inside the package, the thermal stress acting between the upper and lower substrates is as follows. May be reduced by dispersion.
As a result, even if the area of the ball grid array package is increased as described above, problems such as a decrease in strength and a decrease in reliability between the ceramic substrate and the resin substrate are less likely to occur.
[0016]
As described above, according to the present invention, the first problem of increasing the size of the component by reducing the thermal stress between the electronic component and the resin printed wiring board on which the electronic component is mounted, and the substrate in the manufacturing stage Thus, it is possible to provide an intermediate for manufacturing a ball grid array package that simultaneously solves the second problem that can reduce damage.
[0017]
In addition, the intermediate body composed of a plurality of units (sections) may further include a semiconductor element mounted on a ceramic substrate and an element seal or casing provided thereon as described in claim 2. Then, the intermediate body with the elements is divided into sections to obtain a completed ball grid array package component.
[0018]
Further, when the conductor connecting the bottom surface of the ceramic substrate and the top surface of the resin substrate is a solder member as described in claim 3, the solder balls for external connection are formed from the relay solder member. It is preferable to use eutectic solder having a low melting point.
This is because it is possible to prevent a problem that the relay solder melts via the external connection solder balls when the ball grid array package is connected to the printed wiring board. As a result, the solder member between the ceramic substrate and the resin substrate does not melt even when heated when the ball grid array package component is mounted on the printed wiring board. The problem no longer occurs.
[0019]
On the other hand, the second invention of the present application is a method for manufacturing an electronic component of a ball grid array package, wherein a single synthetic resin resin substrate comprising a plurality of compartments provided with solder balls for external connection is manufactured. A first step, a second step of manufacturing a ceramic substrate having a connection terminal with an element to be mounted, a third step of bonding the ceramic substrate to each section of the resin substrate, and after mounting on the resin substrate A fourth step of mounting an element on the ceramic substrate and sealing or casing, and a fifth step of cutting the resin substrate after the element is mounted in each section. In the third step, the ceramic substrate The bottom surface of the resin and the top surface of the resin substrate are electrically connected by a conductor, and both surfaces are filled with a synthetic resin underfill and bonded together. In a method of manufacturing an electronic component of a ball grid array package, characterized by setting the intermediate value of the thermal expansion coefficient of the electrochromic substrate and the thermal expansion coefficient of the resin substrate.
[0020]
The first point that should be particularly noted in the present invention is that the resin substrate manufactured in the first step is formed with a plurality of sections having solder balls and forming a single ball grid array package. In the process, the ceramic substrate is bonded to each section of the resin substrate, and the element is mounted in the subsequent fourth process. Therefore, a plurality of ball grid array package parts constituting a single ball grid array package can be obtained by cutting the resin substrate and dividing it into sections in the fifth step.
[0021]
As described above, since the intermediate body in the third and fourth steps holds a plurality of board units as a unit, it must be handled when the board unit is transported or stored in an intermediate stage of manufacturing an electronic component. As a result, the substrate unit is less likely to be damaged as compared with the case where the substrate unit is held apart, and the quality of the product can be improved.
[0022]
The second point that should be particularly noted in the present invention is that the substrate unit is provided with another synthetic resin resin substrate having solder balls bonded to the bottom surface in addition to the ceramic substrate on which the element is mounted. And an underfill is interposed between the ceramic substrate and the resin substrate, and the thermal expansion coefficient of the underfill is intermediate between the thermal expansion coefficient of the ceramic substrate and the thermal expansion coefficient of the resin substrate. Having a value of.
[0023]
As a result, the first and second functions and effects similar to those described in the first invention can be obtained from the above configuration.
Therefore, according to the present invention, the first problem of increasing the size of the component by reducing the thermal stress between the electronic component and the resin-made printed wiring board on which the electronic component is mounted, and damage to the substrate or the like in the manufacturing stage It is possible to provide a method of manufacturing a ball grid array package component that can simultaneously solve the second problem that can reduce the above.
[0024]
When the conductor connecting the bottom surface of the ceramic substrate and the top surface of the resin substrate is used as a solder member as described in claim 5, the external connection solder balls are formed by the relay solder member. It is preferable to use eutectic solder having a low melting point.
This is because it is possible to prevent a problem that the relay solder melts via the external connection solder balls when the ball grid array package is connected to the printed wiring board.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment This embodiment is a method of manufacturing the electronic component 81 of the ball grid array package shown in FIG. 1 (e), and includes a plurality of compartments 11 having solder balls 15 for external connection as shown in FIG. A first step of manufacturing the single synthetic resin resin substrate 10 and a second step of manufacturing the ceramic substrate 20 shown in FIG. 1A having the connection terminals 21 to the semiconductor element 31 to be mounted. As shown in FIGS. 1B and 1C, a third step of bonding the ceramic substrate 20 to each section 11 (FIGS. 2 and 3) of the resin substrate 10 and as shown in FIG. A fourth step of mounting the semiconductor element 31 on the ceramic substrate 20 after mounting on the resin substrate 10 and the resin substrate 10 after mounting of the element 31 are cut into individual sections 11 as shown in FIG. Obtain a single ball grid array package part 81 Consisting of a fifth step.
[0026]
Then, as shown in FIGS. 1B and 1C, in the third step, the bottom surface of the ceramic substrate 20 and the top surface of the resin substrate 10 are electrically connected by the solder member 25 and between both surfaces. Are filled with a synthetic resin underfill 27 and bonded together. The thermal expansion coefficient of the underfill 27 is set to an intermediate value between the thermal expansion coefficient of the ceramic substrate 20 and the thermal expansion coefficient of the resin substrate 10.
[0027]
As described above, the first intermediate 851 for manufacturing the ball grid array package component 81 manufactured by the third step includes a solder ball 15 for external connection as shown in FIG. A resin substrate 10 made of a single synthetic resin having a plurality of the same sections 11 corresponding to the ball grid array package and a connection terminal 21 to the semiconductor element 31 are joined to each section 11 of the resin substrate 10. And a plurality of ceramic substrates 20.
[0028]
The bottom surface of the ceramic substrate 20 and the top surface of the resin substrate 10 are electrically connected by a solder member 25 and filled with an underfill 27 made of synthetic resin. The external connection solder balls 15 are eutectic solder having a melting point lower than that of the solder member 25.
Then, as shown in FIGS. 1D and 3, the semiconductor element 31 is mounted on the second intermediate 852 at the end of the fourth step.
[0029]
The following is a supplementary explanation.
The synthetic resin forming the main body of the resin substrate 10 is glass epoxy, and the material of the underfill 27 filled between the ceramic substrate 11 and the ceramic substrate 11 is epoxy resin.
The relay solder member 25 is a high melting point solder having a melting point of about 280 ° C., and the solder balls 15 are eutectic solder having a melting point lower than that of the relay solder member 25.
1D and 1E, reference numeral 32 denotes a bonding wire, and reference numeral 13 denotes a via hole that connects the solder member 25 and the solder ball 15.
[0030]
The electronic component 81 of the ball grid array package is manufactured by the following process.
First, the ceramic substrate 20 on which a circuit pattern and via holes (not shown) are formed and the resin substrate 10 on which the via holes 13 are formed are manufactured separately, and as shown in FIG. Are joined by a solder member 25 for relay.
[0031]
Thereafter, as shown in FIG. 2C, the underfill 27 is formed between the substrates 10 and 20 by a method of injecting resin to obtain a first intermediate 851. Thereafter, as shown in FIG. 3D and FIG. 3, the semiconductor element 31 is mounted by a method similar to the conventional method and connected by the bonding wire 32 to obtain the second intermediate 852.
After the element 31 is mounted as described above, the entire element portion is sealed with the resin 41, and the resin substrate 10 is cut into each section 11, and a single ball grid array package component as shown in FIG. 81 is obtained.
[0032]
In the method of manufacturing the electronic component 81 of the present example, the resin substrate 10 manufactured in the first step is formed with a plurality of sections 11 having solder balls 15 and forming a single ball grid array package. In three steps, the ceramic substrate 20 is bonded to each section 11 of the resin substrate 10. In the subsequent fourth step, the semiconductor element 31 is mounted, and in the fifth step, the resin substrate 10 is cut and divided into the respective sections 11, whereby a single ball grid array package component 81 can be obtained.
[0033]
As described above, the intermediate bodies 851 and 852 are formed in the third and fourth steps, and finally, a plurality of substrate units constituting a single ball grid array package are held together as a unit. In the intermediate stage of manufacturing the electronic component 81, when the board unit is transported or stored, the board unit is less likely to be damaged than when the board unit is held by different board units, and the product quality is improved. be able to.
[0034]
In addition to the ceramic substrate 20 on which the element 31 is mounted, the substrate unit is provided with another resin substrate 10 for external connection in which solder balls are bonded to the bottom surface. An underfill 27 is interposed between the ceramic substrate 20 and the resin substrate 10, and the thermal expansion coefficient of the underfill 27 is intermediate between the thermal expansion coefficient of the ceramic substrate 20 and the thermal expansion coefficient of the resin substrate 10. Has the value of
[0035]
As a result, since the substrate 10 for external connection is made of synthetic resin, even when the printed wiring board on which the electronic component 81 is mounted is made of a synthetic resin board, the gap between the bottom of the electronic component 81 and the printed wiring board can be reduced. The thermal stress acting on can be reduced.
This is because the difference in coefficient of thermal expansion between the resin printed wiring board and the joint portion (resin substrate 10) at the component 81 is reduced. Therefore, a large ball grid array package having a larger area can be used for electronic components, and the degree of integration of electronic devices can be improved.
[0036]
In the package, since an underfill 27 having an intermediate thermal expansion coefficient between the ceramic substrate 20 and the resin substrate 10 is interposed, thermal stress acting on the upper and lower substrates 10 and 20 is dispersed. Has been reduced.
As a result, even if the area of the ball grid array package is increased as described above, problems such as a decrease in strength and a decrease in reliability between the ceramic substrate 20 and the resin substrate 10 are less likely to occur.
[0037]
Therefore, according to this example, the first problem of increasing the size of the component 81 by reducing the thermal stress between the electronic component 81 and the resin printed wiring board on which the electronic component 81 is mounted, and the substrate in the manufacturing stage It is possible to provide a method of manufacturing the ball grid array package component 81 that can simultaneously solve the second problem that can reduce the damages 10 and 20.
[0038]
【The invention's effect】
As described above, according to the present invention, the first problem of increasing the size of the component by reducing the thermal stress between the electronic component and the resin printed wiring board on which the electronic component is mounted, the substrate in the manufacturing stage, etc. It is possible to obtain an intermediate for manufacturing a ball grid array package that can simultaneously solve the second problem that can reduce the damage of the ball grid array, and a method for manufacturing an electronic component of the ball grid array package that solves the above problem.
[Brief description of the drawings]
FIG. 1 is a diagram showing a flow of third to fifth steps of an electronic component manufacturing method according to an embodiment.
FIG. 2 is a front sectional view showing a configuration of a section of the intermediate shown in FIG.
FIG. 3 is a plan view of FIG. 2;
FIG. 4 is a cross-sectional view showing an example of an electronic component of a ball grid array package.
[Explanation of symbols]
10. . . Resin substrate,
11. . . Solder ball 20. . . Ceramic substrate,
21. . . Connecting terminal,
25. . . Conductor (solder member),
27. . . Underfill,
31. . . element,
81. . . Ball grid array package parts,
851,852. . . Intermediate,

Claims (5)

ボールグリッドアレイパッケージを構成する複数の基板ユニットに分割することのできるパッケージ製造用の中間体であって，
外部接続用の半田ボールを備え単一のボールグリッドアレイパッケージに対応する同一の区画を複数個備えた単一の合成樹脂製の樹脂基板と，素子との接続端子を備え上記樹脂基板の各区画に接合される複数のセラミック基板とを有しており，
上記セラミック基板の底面と樹脂基板の上面との間は，導電体により電気的に接続すると共に合成樹脂製のアンダーフィルが充填されており，上記アンダーフィルの熱膨張係数は，上記セラミック基板の熱膨張係数と上記樹脂基板の熱膨張係数の中間の値を有していることを特徴とするボールグリッドアレイパッケージ製造用の中間体。An intermediate for manufacturing a package that can be divided into a plurality of substrate units constituting a ball grid array package,
A single synthetic resin resin substrate having a plurality of identical partitions corresponding to a single ball grid array package with solder balls for external connection, and each section of the resin substrate having a connection terminal for the element A plurality of ceramic substrates bonded to each other,
The bottom surface of the ceramic substrate and the top surface of the resin substrate are electrically connected by a conductor and filled with an underfill made of synthetic resin, and the thermal expansion coefficient of the underfill is the thermal expansion coefficient of the ceramic substrate. An intermediate for producing a ball grid array package, having an intermediate value between an expansion coefficient and a thermal expansion coefficient of the resin substrate. 請求項１記載の中間体の前記セラミック基板に半導体素子が実装され素子シールまたはケーシングがなされていることを特徴とするボールグリッドアレイパッケージ製造用の素子付き中間体。2. An intermediate body with an element for manufacturing a ball grid array package, wherein a semiconductor element is mounted on the ceramic substrate of the intermediate body according to claim 1 to form an element seal or a casing. 請求項１または請求項２において，前記セラミック基板の底面と樹脂基板の上面とを接続する導電体は半田部材であり，前記外部接続用の半田ボールは，上記半田部材よりも融点が低い共晶半田であることを特徴とするボールグリッドアレイパッケージ製造用の中間体。3. The eutectic crystal according to claim 1, wherein the conductor connecting the bottom surface of the ceramic substrate and the top surface of the resin substrate is a solder member, and the solder ball for external connection has a lower melting point than the solder member. An intermediate for manufacturing a ball grid array package, characterized by being solder. ボールグリッドアレイパッケージの電子部品の製造方法であって，
外部接続用の半田ボールを備えた複数の区画からなる単一の合成樹脂製の樹脂基板を製作する第１の工程と，搭載する素子との接続端子を備えたセラミック基板を製作する第２の工程と，上記樹脂基板の各区画に上記セラミック基板を接合する第３の工程と，樹脂基板へ搭載後の上記セラミック基板に素子を実装しシールまたはケーシングを行う第４の工程と，素子実装後の上記樹脂基板を各区画別に切断する第５の工程とからなり，
上記第３工程においては，セラミック基板の底面と樹脂基板の上面との間を導電体により電気的に接続すると共に両面間に合成樹脂製のアンダーフィルを充填して接合し，上記アンダーフィルの熱膨張係数を上記セラミック基板の熱膨張係数と上記樹脂基板の熱膨張係数の中間の値に設定することを特徴とするボールグリッドアレイパッケージの電子部品の製造方法。A method of manufacturing an electronic component of a ball grid array package,
A first step of manufacturing a single synthetic resin resin substrate composed of a plurality of sections having solder balls for external connection, and a second step of manufacturing a ceramic substrate having connection terminals for mounting elements. A process, a third step of bonding the ceramic substrate to each section of the resin substrate, a fourth step of mounting an element on the ceramic substrate after being mounted on the resin substrate, and sealing or casing, and a step after mounting the element A fifth step of cutting the resin substrate of each section separately,
In the third step, the bottom surface of the ceramic substrate and the top surface of the resin substrate are electrically connected by a conductor, and both surfaces are filled with a synthetic resin underfill and bonded to each other. A method of manufacturing an electronic component of a ball grid array package, wherein an expansion coefficient is set to an intermediate value between a thermal expansion coefficient of the ceramic substrate and a thermal expansion coefficient of the resin substrate. 請求項４において，前記セラミック基板の底面と樹脂基板の上面とを接続する導電体は半田部材であり，前記外部接続用の半田ボールは，上記半田部材よりも融点が低い共晶半田であることを特徴とするボールグリッドアレイパッケージの電子部品の製造方法。5. The conductor connecting the bottom surface of the ceramic substrate and the top surface of the resin substrate is a solder member, and the solder ball for external connection is eutectic solder having a melting point lower than that of the solder member. A method for manufacturing an electronic component of a ball grid array package.
JP17302297A 1997-06-13 1997-06-13 Intermediate and manufacturing method of ball grid array package Expired - Lifetime JP3706226B2 (en)

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BR0012273A (en) * 1999-07-08 2002-04-02 Sunstar Engineering Inc Underfill material for semiconductor packaging
FR2796497B1 (en) * 1999-07-13 2001-09-07 Thomson Csf Detexis PERFECTED INTERCONNECTION BETWEEN AN ELECTRONIC COMPONENT AND A CARD
US6492715B1 (en) 2000-09-13 2002-12-10 International Business Machines Corporation Integrated semiconductor package
US7604833B2 (en) 2003-08-29 2009-10-20 Koa Corporation Electronic part manufacturing method
JP2007250764A (en) 2006-03-15 2007-09-27 Elpida Memory Inc Semiconductor device and manufacturing method therefor

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