JP3702163B2 - Wireless reception system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a radio reception system, and more particularly to a radio reception system based on a communication method such as PDMA (Path Division Multiple Access), CDMA (Code Division Multiple Access), etc., and removing interference signal components from other users from a received signal The present invention relates to a wireless reception system capable of performing the above.
[0002]
[Prior art]
In recent years, various mobile channel allocation methods have been proposed for effective use of frequencies in mobile communication systems such as mobile phones that are rapidly developing, some of which have been put into practical use.
[0003]
FIG. 12 is an arrangement diagram of channels in various communication systems of FDMA (Frequency Division Multiple Access), TDMA (Time Division Multiple Access), and PDMA. First, FDMA, TDMA, and PDMA will be briefly described with reference to FIG.
[0004]
FIG. 12A is a diagram showing a channel arrangement of FDMA, in which analog signals of users 1 to 4 are transmitted by being frequency-divided with radio waves of different frequencies f1 to f4, and the signals of users 1 to 4 are frequency filters. Separated by.
[0005]
FIG. 12 (b) is a diagram showing a TDMA channel arrangement, and each user's digitized signal is transmitted with radio waves of different frequencies f1 to f4 and time-divided at fixed time intervals (time slots). The signals of the users 1 to 8 are separated by the frequency filter and the time synchronization between the base station and each user mobile terminal device.
[0006]
On the other hand, recently, a PDMA system has been proposed in order to increase the frequency use efficiency of radio waves by the spread of mobile phones. In this PDMA system, as shown in FIG. 12C, one time slot at the same frequency is spatially divided to transmit data of a plurality of users. In this PDMA, each user's signal is separated using a frequency filter, time synchronization between the base station and each user mobile terminal device, and a signal extraction device such as an adaptive array.
[0007]
FIG. 13 is a diagram showing a conventional receiving system for a PDMA base station. In this example, four antennas 3 to 6 are provided in order to distinguish between users 1 and 2, and the outputs of the respective antennas are given to the frequency conversion circuit 7, and the corresponding local oscillation signals Lo are respectively provided. Is converted into a digital signal by an A / D converter 8 and supplied to a digital signal processor (DSP) 10.
[0008]
The DSP 10D includes adaptive arrays 11 and 12, a received signal vector calculator 13, a memory 14, a correlation value calculator 15, and a channel allocation device 16. The adaptive arrays 11 and 12 extract only a specific user signal from the reception signal output from the A / D converter 8. Each adaptive array is designated by the channel allocation device 16 to be described later depending on a weight vector calculation method such as a method using a preamble included in a time slot or a method using a property in which an envelope of a modulation signal is constant. User signal is extracted.
[0009]
The received signal vector calculator 13 receives the received signal from the A / D converter 8 and the output signals of the adaptive arrays 11 and 12, calculates received signal vectors corresponding to all users, and stores them in the memory 14. The channel allocation device 16 designates two users for the memory 14 and the correlation value calculator 15. The correlation value calculator 15 calculates the cross-correlation value of the received signal vectors of the two specified users among the received signal vectors stored in the memory 14. The channel allocator 16 receives the calculated cross-correlation value of the received signal vectors of the two users. If the cross-correlation value is equal to or less than a certain value, the two users are path-multiplex connected to the time slot at the same time.
[0010]
[Problems to be solved by the invention]
The adaptive arrays 11 and 12 shown in FIG. 13 extract the signals of the corresponding users 1 and 2, respectively. However, in addition to the users 1 and 2, for example, when the user 3 transmits a signal from the same direction as the user 1, the adaptive arrays 11 and 12 The signals of the user 1 and the user 3 are mixed and output from the array 11. However, the conventional adaptive array 11 cannot separate the signals of the users 1 and 3 and cannot extract only the signal of the user 1.
[0011]
Therefore, a main object of the present invention is to provide a radio reception system capable of improving communication quality by increasing the accuracy of interference cancellation and canceling unnecessary user signals.
[0012]
[Means for Solving the Problems]
  According to the first aspect of the present invention, there is provided a wireless reception system capable of receiving signals from a plurality of users using a plurality of antennas, and performing predetermined signal processing on the signals received by the plurality of antennas. And a plurality of first signal extraction means for extracting signal components respectively corresponding to the plurality of users based on signals output from the signal processing means,
  A plurality of first estimating means for estimating a fading speed related to the relationship of the signal component extracted by the first signal extracting means with respect to the signal output from the signal processing means;Based on signals received by the plurality of antennas, first interference cancellation determination means for determining whether to perform interference cancellation in consideration of the fading speed estimated by the corresponding first estimation means;
Interference removal is performed by the interference removal determination means from the signal output from the signal processing means.WhenThe extracted signal component determinedTheFirst calculating means for subtracting.
[0013]
According to the second aspect of the present invention, the first interference cancellation determination unit determines whether each performs interference cancellation based on the signal components corresponding to the plurality of users extracted by the first signal extraction unit. Determine whether.
[0015]
  According to a third aspect of the present invention, a plurality of first error determination means for determining whether signal components corresponding to a plurality of users extracted by the first signal extraction means each include a demodulation error. And a signal output from the signal processing means,By the interference removal determination meansConsidering the corresponding fading speedPerform interference cancellationWhenThe extracted signal component determined and determined not to include a demodulation error by the first error determination meansTheAnd a first calculating means for subtracting.
[0016]
  Claim4According to the invention described in the above, based on the signal output from the first calculation means, a plurality of signal components respectively corresponding to users determined to contain a demodulation error by the first error determination means And a signal component extracted by the second signal extracting means with respect to a signal output from the first calculating means.Fading speedA plurality of second estimation means for estimating the signal and (4) whether or not each performs interference cancellation based on the signal components corresponding to the plurality of users extracted by the second signal extraction means. And a plurality of second error determination means for determining whether each of the signal components extracted by the second signal extraction means includes a demodulation error. .
[0017]
  According to the fifth aspect of the present invention, the first and second error determination means do not include a demodulation error and the first and second interference removal from the signal output from the signal processing means.JudgmentBy meansConsidering the corresponding fading speedSignal components extracted by the first and second signal extraction means determined to perform interference cancellationTheAnd a second calculating means for subtracting.
[0018]
  According to the sixth aspect of the present invention, the signal output from the first calculation means is extracted by the second signal extraction means determined by the second error determination means as not including a demodulation error. Signal componentsTheAnd a third calculating means for subtracting.
[0019]
  Claim7According to the present invention, in the radio reception system according to any one of claims 1 to 6, signals from a plurality of users are signals transmitted by the PDMA communication method.
[0020]
  Claim8According to the present invention, in the radio reception system according to any one of claims 1 to 6, signals from a plurality of users are signals transmitted by a CDMA communication system.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a receiving system for a PDMA base station proposed as a multistage interference canceller which is a premise of the present invention. The proposed receiving system which is the premise of the present invention is a signal S from m (m is an integer of 2 or more) users 1,..., K,.₁(T), ..., S_k(T), ..., S_m(T) is separated from each other and taken out in parallel.
[0022]
In FIG. 1, as in the conventional example of FIG. 13, the receiving system of the PDMA base station is provided with four antennas 3 to 6, a frequency conversion circuit 7, and an A / D converter 8. . Input signal vector X output from the A / D converter 8₁(T) shows the first stage arithmetic unit 101 and the first stage adaptive array AA.₁₁, ..., AA_k1, ..., AA_m1And the first stage parameter estimator PE₁₁, ..., PE_k1, ..., PE_m1And given to. Details of the adaptive array will be described later.
[0023]
Adaptive array AA₁₁, ..., AA_k1, ..., AA_m1To the user signal Y which is a complex signal that includes the signal component of the corresponding user most strongly (in addition to the interference signal component from other users).₁₁(T), ..., Y_k1(T), ..., Y_m1(T) is output and provided to the first stage arithmetic unit 101, and the corresponding detector DE is also provided.₁₁, ..., DE_k1, ..., DE_m1It is detected at.
[0024]
Parameter estimator PE₁₁, ..., PE_k1, ..., PE_m1Are respectively the input signal vectors X₁(T) and detector DE₁₁, ..., DE_k1, ..., DE_m1And a corresponding response output H of the corresponding user based on the corresponding detection output of₁₁, ..., H_k1, ..., H_m1Is estimated and given to the first stage arithmetic unit 101. More specifically, each parameter estimator includes how much the corresponding user signal component is included in the input signal vector, how much the corresponding user signal component is phase rotated with respect to the input signal vector, Etc.
[0025]
The first stage arithmetic unit 101 calculates the input signal vector X for each user i (i = 1, 2,..., M).₁By subtracting the signal components of all other users except the user i from (t), the interference signal component is removed, and the further input signal vector X of the user i_i2(T) is calculated and output. The operation of the arithmetic unit 101 will be described in detail later with reference to FIG.
[0026]
The first-stage arithmetic unit 101 corresponds to each user with the input signal vector X₁₂(T), ..., X_k2(T), ..., X_m2(T) is output and the corresponding second-stage adaptive array AA is output.₁₂, ..., AA_k2, ..., AA_m2To give.
[0027]
Second-tier adaptive array AA₁₂, ..., AA_k2, ..., AA_m2User signal Y output from₁₂(T), ..., Y_k2(T), ..., Y_m2(T) is given to the second stage arithmetic circuit 102 and the corresponding detector DE₁₂, ..., DE_k2, ..., DE_m2It is detected at.
[0028]
Parameter estimator PE₁₂, ..., PE_k2, ..., PE_m2Are respectively the input signal vectors X₁(T) and detector DE₁₂, ..., DE_k2, ..., DE_m2And a corresponding response output H of the corresponding user based on the corresponding detection output of₁₂, ..., H_k2, ..., H_m2Is estimated and given to the second stage arithmetic unit 102. The arithmetic unit 102 is further connected to a further input signal vector X₁₃(T), ..., X_k3(T), ..., X_m3(T) is output, and the corresponding third-stage adaptive array AA (not shown) is output.₁₃, ..., AA_k3, ..., AA_m3To give.
[0029]
As described above, by providing a plurality of stages (from the first stage to the L-th stage) of interference cancellers including the adaptive array, the parameter estimator, and the arithmetic unit in series, the interference signals are included in the user signals output from the respective stages. The ratio of other user signal components is gradually reduced to further eliminate interference. As a result, communication characteristics can be further improved.
[0030]
FIG. 2 is a specific block diagram of the arithmetic device 101 as an example of the multi-stage arithmetic device shown in FIG. In FIG. 2, the arithmetic unit 101 includes a multiplier MP.₁, ..., MP_k-1, MP_{k + 1}, ..., MP_mAnd adder AD_kIt consists of and. Although not shown for simplification of explanation, in addition to the illustrated multiplier and adder, the multiplier MP_kAnd adder AD₁, ..., AD_k-1, AD_{k + 1}, ..., AD_mIs built in the arithmetic unit 101.
[0031]
Multiplier MP₁, ..., MP_k-1, MP_{k + 1}, ..., MP_mEach has an adaptive array AA₁₁, ..., AA_k-1, AA_{k + 1}, ..., AA_mUser signal Y from₁₁(T), ..., Y_{(k-1) 1}(T), Y_{(k + 1) 1}(T), ..., Y_m1(T) and the parameter estimator PE₁₁, ..., PE_{(k-1) 1}, PE_{(k + 1) 1}, ..., PE_m1Received response vector H from₁₁, ..., H_{(k-1) 1}, H_{(k + 1) 1}, ..., H_m1And is given.
[0032]
Multiplier MP₁, ..., MP_k-1, MP_{k + 1}, ..., MP_mOutput of adder AD_kInput signal vector X₁(T) is the adder AD_kGiven to the positive input. As a result, the input signal vector X₁A signal component corresponding to a user other than the user k is subtracted from (t) to obtain a signal component X corresponding to the user k._k2(T) is the adder AD_kWill be output. As described above, the adaptive array, the parameter estimator, and the arithmetic device as a whole constitute a one-stage interference canceller.
[0033]
As a result, a considerable interference signal component is removed. Then, a new input vector signal X from which the interference signal component is considerably removed by the arithmetic unit 101 in this way._k2By giving (t) to the interference cancellers in the second and subsequent stages, the user signal S that is finally output is displayed._kThe ratio of interference signal components from other users included in (t) can be sufficiently reduced, and good communication characteristics can be realized.
[0034]
Adder AD_kSimilarly to each of the adders (not shown) in parallel, the multiplier MP₁, ..., MP_k, ..., MP_mOutput from the other than the multiplier corresponding to the adder, and the input signal vector X₁(T) is given. Each of these adders outputs a new input signal vector shown in FIG. 1 and gives it to the second and subsequent interference cancellers.
[0035]
Next, a more specific operation of the apparatus shown in FIGS. 1 and 2 will be described. Assuming that the number of antenna elements is n and the number of users who are talking simultaneously is m, the input signal vector X output from the A / D converter 8₁(T) is expressed by the following equation.
[0036]
X₁(T) = [x₁(T), x₂(T), ... x_n(T)]^T  (1)
x_j(T) = h_j1S₁(T) + h_j2S₂(T) + ... + h_jiS_i(T) + ... + h_jmS_m(T) + n_j(T), (j = 1, 2,..., N) (2)
When the above expressions (1) and (2) are converted into vector notation, the following expression (3) is obtained.
[0037]
X₁(T) = H₁S₁(T) + H₂S₂(T) + ... + H_iS_i(T) + ... + H_mS_m(T) + N (t) (3)
H_i= [H_1i, H_2i, ..., h_ni]^T, (I = 1, 2,..., M) (4)
N (t) = [n₁(T), n₂(T), ..., n_n(T)]^T  (5)
[0038]
Next, a new input signal vector X from the arithmetic unit 101 in FIG._k2The operation of outputting (t) will be described in further detail.
[0039]
Parameter estimator PE₁₁, ..., PE_k1, ..., PE_m1H_iIt is assumed that (i = 1, 2,..., M) can be estimated. The first stage adaptive array AA₁₁, ..., AA_k1, ..., AA_m1If it works relatively well, Y_i1(T) ≒ S_i(T).
[0040]
At this stage, all user signals and reception response vectors of all user signals are obtained. Here, the input signal vector X used for the signal detection of the user k at the second stage_k2(T) can be obtained from the expression (6).
[0041]
X_k2(T) = X₁(T) -H₁S₁(T) -...- H_k-1S_k-1(T) -H_{k + 1}S_{k + 1}(T) -...- H_mS_m(T) ... (6)
Substituting equation (3) into equation (6) yields equation (7).
[0042]
X_k2(T) = H_kS_k(T) + N (t) (7)
X₁(T) and X_k2When comparing (t), X_k2(T) is S_kInterference component S other than (t)_i(T) (i = 1, 2,..., M, i ≠ k) decreases, and the second-stage adaptive array becomes easier to operate.
[0043]
As shown in FIG. 1, in a multistage interference canceller configured by connecting multiple stages of interference cancellers, a received signal is separated for each user by an adaptive array, and a signal of a user other than the user is used as an interference wave from the received signal. The result obtained by the removal is given to the next-stage interference canceller as an input signal of the user. As a result, in the next stage interference canceller, a user signal with good communication characteristics can be obtained as much as the interference wave of the input user signal is small. Then, by repeating such interference wave removal in a plurality of stages, the interference wave removal further proceeds, the CIR (Carrier to Interference Ratio) is further improved, and it becomes easier to extract a desired user signal.
[0044]
However, if the multistage interference canceller as described above is used, the removal of the interference wave certainly proceeds, but the following problems arise.
[0045]
(1) The example of the multistage interference canceller described above is configured to remove the user signal extracted by each adaptive array from the received signal as an interference wave component without determining the presence or absence of the demodulation error. . Therefore, if there is a demodulation error in the user signal extracted by the adaptive array and the signal has some deformed waveform, for example, an impulse waveform, the signal component including such an error is subtracted from the received signal. As a result, the output of each arithmetic device (input signal to the interference canceller at the next stage) has an influence such as impulsive noise due to the influence of a demodulation error.
[0046]
(2) In signal restoration, restoration accuracy deteriorates under adverse conditions such as low received power of a restoring user, fast fading (large Doppler frequency), and many interference signals. If interference cancellation is performed on a signal with poor restoration accuracy, unnecessary signal components may be removed.
[0047]
When interference cancellation is performed using such a restored signal, the accuracy of the signal after interference cancellation (the input signal carried over to the next stage) is deteriorated, so that a desired signal can be obtained even when transitioning to the next stage. Therefore, the effect of the multistage interference canceller cannot be seen.
[0048]
The present invention is intended to solve the above problems (1) and (2).
[0049]
[Embodiment 1]
FIG. 3 is a block diagram showing a receiving system for a PDMA base station according to Embodiment 1 of the present invention.
[0050]
In FIG. 3, the arithmetic unit 101 ′ and the first gate unit GA, the interference removing unit IC, and the second gate unit GB provided for each of a plurality of users constitute the basic configuration of the first stage interference canceller. There is no.
[0051]
Although omitted for simplification of illustration, the first gate unit GA and the interference canceling unit are arranged in the same manner as the first stage interference canceller for each of a plurality of users in the subsequent stage of the arithmetic unit 102 ′. It is assumed that the IC and the second gate portion GB are provided, and the second stage interference canceller is configured by the arithmetic unit 102 ′ and these constituent elements GA, IC, GB (not shown).
[0052]
Although not shown, the second stage interference canceller is configured in exactly the same manner as the first stage interference canceller (computing device, first and second gate units, and interference cancellation). It is assumed that there are multiple stages of interference cancellers consisting of
[0053]
Therefore, the receiving system of FIG. 3 is configured as a multistage interference canceller as a whole, and a second gate unit GB (not shown) provided for each of a plurality of users of the final stage interference canceller. The output becomes the final output of the receiving system.
[0054]
First, as in the receiving system of FIG. 1, the A / D converter 8 receives an input signal vector X₁(T) is output and given to the first stage interference canceller arithmetic unit 101 ′, and a plurality of interference removal units provided corresponding to a plurality of users in the previous stage of the first stage interference canceller IC₁₁, ..., IC_k1, ..., IC_m1Is also given in common.
[0055]
In the example of this embodiment, four antennas 3 to 6 are provided, and the outputs of the respective antennas are given to the frequency conversion circuit 7 and are frequency-converted by the corresponding local oscillation signals Lo, respectively. It is converted into a digital signal by the D converter 8 and given to the reception power detection unit 9.
[0056]
The received power detection unit 9 obtains the magnitude of the received power of the user from the digital outputs from the four antennas given from the A / D converter 8, and gives it to the interference removal selector 10. As will be described later, this interference cancellation selector 10 is given the reception response vector H of each user calculated by the interference cancellation unit IC, and estimates the SNR. Further, as will be described later, the interference cancellation selector 10 detects the fading speed (FD) and the degree of interference signal (SIR: signal-to-interference wave ratio) based on the calculated reception response vector H. Then, based on the obtained data, it is determined whether or not interference removal is performed in the stage.
[0057]
In the receiving system of FIG. 3, all of the interference canceling units IC have the same configuration. As an example, the interference canceling unit IC_k1The configuration is shown in FIG.
[0058]
In FIG. 4, the interference removing unit IC_k1Input signal vector X input to₁(T) to adaptive array AA_k1The complex signal of user k extracted in step_k1Is converted into a bit information signal. This bit information signal is supplied from the error determination device ED._k1And the remodulator RM_k1Also given to.
[0059]
Error judgment device ED_k1Is the demodulator DM_k1Based on the bit information signal from the adaptive array AA_k1It is determined whether or not there is a demodulation error in the extracted signal. If it is determined that there is a demodulation error, an L level error determination signal E_k1Is provided to the arithmetic unit 101 ′ of the first stage interference canceller.
[0060]
Remodulator RM_k1Is the demodulator DM_k1The bit information signal from the user signal Y which is a complex signal again._k1(T), and is supplied to the first stage interference canceller arithmetic unit 101 ′, and the parameter estimator PE_k1To give.
[0061]
Parameter estimator PE_k1Is the input signal vector X₁(T) and the user signal Y_k1(T) and the corresponding user reception response vector H_k1Is calculated and given to the first stage interference canceller arithmetic unit 101 '. Furthermore, the parameter estimator PE_k1Is the calculated reception response vector H_k1Is provided to the interference cancellation selector 10.
[0062]
The interference cancellation selector 10 calculates the calculated reception response vector H_k1Based on the above, it is determined whether or not the estimation accuracy of the response vector is high, and a control signal is output so that only the restoration signal of the user with high estimation accuracy performs interference removal at the stage. That is, it is determined whether or not the estimation accuracy of the response vector is high, and if it is determined that the signal has a rank that does not perform interference cancellation, the L level selection signal I_k1Are given to the arithmetic units 101 'of each interference canceller and the gates GA and GB.
[0063]
In this interference cancellation selector 10, a method for selecting a user with high response vector estimation accuracy is performed as follows. A simulation is performed in advance, and a response vector corresponding to each condition of the received power of the user (SNR: signal to noise ratio), fading speed (FD), and degree of interference signal (SIR: signal to interference wave ratio) The estimation accuracy is acquired, ranked, and stored in a table. And the calculated response vector H_k1FD and SIR are detected based on the above, and the SNR is estimated based on the signal from the received power detector 9, and it is determined whether or not to cancel the interference at the stage. If the estimation accuracy of the response vector is high, the accuracy of the replica signal for removing the interference is improved, so that the accuracy of the signal input to the next stage is increased. As a result, the probability of error-free in the next stage increases.
[0064]
As described above, the table holds each condition of the received power level (SNR: signal-to-noise ratio), fading speed (FD), and interference signal level (SIR: signal-to-interference wave ratio) of the user. Then, based on these rankings, it is configured to determine whether or not to perform interference removal at the stage. However, in consideration of the processing speed or the like, the determination may be performed according to any of the conditions. good. For example, the ranking of the interference signal according to the value of the interference signal (SIR: signal-to-interference wave ratio) is held in a table, and the response vector H calculated according to the ranking value is stored._k1It may be configured to determine whether or not to perform interference removal at the stage.
[0065]
FIG. 5 is a block diagram showing a configuration of the interference cancellation selector 10 according to the embodiment of the present invention. The operation of the interference selector 10 according to the embodiment of the present invention will be described with reference to FIG.
[0066]
Here, for example, a total of 8 slots, each consisting of 4 slots on the upper and lower lines, is defined as one frame. Such frames are continuously communicated in time series so that communication between the upper and lower lines is alternately performed.
[0067]
Interference canceler IC_k1Parameter estimator PE_k1Is the received signal or input signal vector X₁(T) and the user signal Y_k1Based on (t), the reception response vector H in the slot of the current frame_k1Is calculated and given to the correlation calculation and each condition estimation circuit 101 and the memory 102 of the interference cancellation selector 10.
[0068]
The correlation calculation and each condition estimation circuit 101 includes a parameter estimator PE._k1The correlation value between the reception response vector in the slot of the current frame estimated in step 1 and the reception response vector in the corresponding slot of the previous frame stored in the memory 102 is calculated.
[0069]
Note that the correlation value α of the reception response vectors of two frames preceding and following in time is defined by the following equation.
[0070]
α = │h₁h₂ ^H│ / │h₁││h₂│
Where h₂ ^HIs h₂The complex conjugate of each component is taken and further transposed.
[0071]
H_i(I = 1, 2) is a reception response vector (h) having phase amplitude information for each antenna element in frame i as an element.₁₁, H₁₂, H₁₃, H₁₄).
[0072]
Although it is difficult to obtain an exact correspondence between the correlation value calculated in this way and the Doppler frequency (fading speed), an approximate correspondence can be empirically obtained through experiments. For example, if the correlation value is in the range of 1 to 0.95, the Doppler frequency FD is estimated to be FD = 0 Hz. If the correlation value is in the range of 0.95 to 0.80, it is estimated that FD = 10 Hz.
[0073]
Thus, the approximate correspondence between the reception response vector correlation value and the Doppler frequency FD obtained empirically is stored in advance in the correlation calculation and each condition estimation circuit 101, and the vectors calculated by the above formula are From the correlation value, the corresponding Doppler frequency FD is output to the presence / absence determination circuit 104.
[0074]
The calculation of the received power level (SNR: signal-to-noise ratio) of the user will be described. Since the signal from the reception power detection unit 9 is a composite signal for all users, it must be converted into reception power for each user. For this purpose, the calculated reception response vector H is required.
[0075]
Basically, the sum of the squares of the I component and Q component of the response vector (complex number) of each user is the power of each user, but the absolute magnitude is not known from the magnitude of the response vector. for that reason. Based on the received power from the received power detection unit 9, the received power is distributed to each user's received power. It is distributed as follows.
[0076]
User i received power = (received power × user i response vector magnitude (sum of squares) / (sum of response vectors of all users (sum of squares)))
[0077]
For example, at the time of 2 multiplexing, the power from the received power detection unit 9 is 50 [dBμV], the response vector size of the user 2 is 30, the response vector size of the user 1 is 70, and all the user responses If the magnitude of the vector is 100 (= 30 + 70), the received power of user 1 is 35 [dBμV] and the received power of user 2 is 15 [dBμV].
[0078]
If the signal from the received power detector 9 does not contain noise, the above value is the value of the S (desired wave) signal. Therefore, in order to convert to SNR, a ratio with noise must be taken. Assuming that noise is slightly different for each base station, but measured in advance,
SNR = 10 · log_Ten(Desired wave power / noise power)
Calculated by
[0079]
Calculation of the degree of interference signal (SIR: signal-to-interference wave ratio) will be described. Unlike SNR, SIR does not require absolute received power from received power detector 9, and is calculated by the ratio of received power for each user. Therefore, the received power of each user can be calculated from the response vector of each user by the above-described method, and the ratio between them can be calculated.
SIR = 10 · log_Ten(Desired wave power / interference wave power)
Calculated by
[0080]
In this way, each condition estimation circuit 101 performs the reception response vector, the reception response vector correlation value, the magnitude of the received power of the user (SNR: signal to noise ratio), the degree of interference signal (SIR: signal to interference wave ratio). ) And the value is output to the presence / absence determination circuit 104.
[0081]
A simulation is performed in advance, and a response vector corresponding to each condition of the received power of the user (SNR: signal to noise ratio), fading speed (FD), and degree of interference signal (SIR: signal to interference wave ratio) The estimated accuracy is obtained and the ranking is stored in the table memory 103.
[0082]
Whether the presence / absence determination circuit 104 refers to the table memory 103 using the SNR, SIR, and FD given from the correlation calculation and each condition estimation circuit 101 as arguments, and performs interference removal at that stage based on these rankings. Determine whether or not, and output the result.
[0083]
As described above, the interference cancellation selector 10 determines whether or not to perform interference cancellation at the corresponding stage according to the reception response vector calculated by the interference cancellation unit IC, and the result is described below. Output to GA, GB and arithmetic unit.
[0084]
The processing shown in FIG. 5 is usually executed in software using, for example, a digital signal processor (DSP).
[0085]
Further, the array including the adaptive array, demodulator, error determiner, remodulator, parameter estimator and interference signal cancellation selector as shown in FIG. 4 is common to all the interference cancellation units IC in FIG. Therefore, further explanation will not be repeated.
[0086]
FIG. 6 is a block diagram showing a specific configuration of a computing device 101 ′ of the first-stage interference canceller as an example of the multi-stage interference canceller constituting the reception system of FIG. In FIG. 6, the arithmetic unit 101 ′ includes a multiplier MP.₁, ..., MP_k-1, MP_k, MP_{k + 1}, ..., MP_mAND gate AND₁, ..., AND_k-1, AND_k, AND_{k + 1}, ..., AND_mAnd an adder AD.
[0087]
Multiplier MP₁, ..., MP_k-1, MP_k, MP_{k + 1}, ..., MP_mRespectively, the interference canceling part IC in the previous stage₁₁, ..., IC_{(k-1) 1}, IC_k1, IC_{(k + 1) 1}, ..., IC_m1User signal Y from₁₁(T), ..., Y_{(k-1) 1}(T), Y_k1(T), Y_{(k + 1) 1}(T), ..., Y_m1(T) and response vector H₁₁, ..., H_{(k-1) 1}, H_k1, H_{(k + 1) 1}, ..., H_m1And is given.
[0088]
Multiplier MP₁, ..., MP_k-1, MP_k, MP_{k + 1}, ..., MP_mOutput is a corresponding three-input AND gate AND₁, ..., AND_k-1, AND_k, AND_{k + 1}, ..., AND_mThe second input of these AND gates is connected to the previous stage interference canceller IC.₁₁, ..., IC_{(k-1) 1}, IC_k1, IC_{(k + 1) 1}, ..., IC_m1Corresponding error judgment signal E from₁₁, ..., E_{(k-1) 1}, E_k1, E_{(k + 1) 1}, ..., E_m1Is entered. The third input of these AND gates has a previous stage interference canceler IC.₁₁, ..., IC_{(k-1) 1}, IC_k1, IC_{(k + 1) 1}, ..., IC_m1The interference cancellation selection signal I calculated by the interference cancellation selector 10 corresponding to the received response vector of₁₁, ..., I_{(k-1) 1}, I_k1, I_{(k + 1) 1}, ..., I_m1Is entered.
[0089]
3-input AND gate AND₁, ..., AND_k-1, AND_k, AND_{k + 1}, ..., AND_mIs supplied to the negative input of the adder AD, and the input signal vector X from the A / D converter 8 is supplied.₁(T) is given to the positive input of the adder AD.
[0090]
The output of the adder AD is the input signal vector X₂(T) is output from the arithmetic unit 101 ′, and as shown in FIG. 3, the first gate GA corresponding to each of a plurality of users is provided.₁₂, ..., GA_k2, ..., GA_m2Commonly given to.
[0091]
In addition, although not shown in the block diagram of the arithmetic unit 101 ′ in FIG.₁₁, ..., IC_k1, ..., IC_m1Received response vector H output from₁₁, ..., H_k1, ..., H_m1, Error determination signal E₁₁, ..., E_k1, ..., E_m1, And user signal Y₁₁(T), ..., Y_k1(T), ..., Y_m1(T) passes through the arithmetic unit 101 ′ as it is, and the first gate unit GA corresponding to the first stage interference canceller for each user.₁₂, ..., GA_k2, ..., GA_m2Is given as is.
[0092]
Here, referring to FIG. 6, as described above, the user signal determined to have a demodulation error and / or not to perform interference cancellation by the interference cancellation selector 10 in the previous interference cancellation unit, for example, Y₁₁Interference remover IC corresponding to (t)₁₁Error judgment device ED₁₁To L level error determination signal E₁₁And / or the L level selection signal I from the interference cancellation selector 10._k1Is the corresponding AND gate AND of the arithmetic unit 101 ′.₁To the other input. As a result, the AND gate is closed and the corresponding multiplier MP₁Received response vector H output from₁₁And user signal Y₁₁The product of (t), that is, the input of the replica signal to the adder AD is blocked.
[0093]
As a result, the input signal vector X₁Interference wave components (replicas) corresponding to user signals including demodulation errors and / or user signals determined not to perform interference removal from the interference wave components (replica signals) of the respective users to be subtracted from (t) Signal) is excluded. For this reason, the input signal vector X output from the arithmetic unit 101 ′ of the first stage interference canceller₂For example, impulse noise is not included in (t).
[0094]
In the first stage interference canceller, the first gate unit GA corresponding to each user, for example, the gate unit GA corresponding to the user 1₁₂In the selection control input, the interference canceler IC in the previous stage₁₁Error signal E passed through the arithmetic unit 101 'from₁₁And an interference cancellation selection signal I from the interference cancellation selector 10.₁₁Is given.
[0095]
And the previous stage interference canceling unit IC₁₁When it is determined that there is an error and / or interference removal is not performed in the first gate portion GA,₁₂Is an error determination signal E₁₁And / or interference cancellation selection signal I₁₁In accordance with the high-accuracy input signal vector X which is newly calculated by the arithmetic unit 101 ′ and does not contain noise.₂(T) is selected and the interference removal unit IC₁₂To give.
[0096]
This interference canceler IC₁₂Is the IC of FIG._k1This input signal vector X₂Based on (t), the reception response vector H₁₂And error determination signal E₁₂And the user signal Y₁₂(T) is newly calculated and the second gate portion GB is calculated.₁₂To give.
[0097]
On the other hand, the previous stage interference canceler IC₁₁When it is determined that there is no error and the interference removal selector 10 performs interference removal, the first gate portion GA₁₂Is an error determination signal E₁₁And interference cancellation selection signal I₁₁In response to the reception response vector H that has passed through the arithmetic unit 101 ′.₁₁, Error judgment signal E₁₁, User signal Y₁₁Select the second gate portion GB₁₂Give to.
[0098]
Second gate part GB₁₂The selection control input of the first gate portion GA₁₂And error determination signal E in common₁₁And interference cancellation selection signal I₁₁Is given. Second gate part GB₁₂Is the previous stage interference canceler IC₁₁When it is determined that there is an error and / or the interference cancellation selector 10 does not perform interference cancellation, an error determination signal E₁₁And / or interference cancellation selection signal I₁₁Depending on the interference canceling unit IC₁₂The reception response vector H newly calculated by₁₂, Error judgment signal E₁₂And user signal Y₁₂(T) is selected and output, and is provided to the arithmetic unit 102 'constituting the second stage interference canceller.
[0099]
On the other hand, the second gate portion GB₁₂Is the previous stage interference canceler IC₁₁When it is determined that there is no error and the interference cancellation selector 10 determines that interference cancellation is to be performed, the error determination signal E₁₁And interference cancellation selection signal I₁₁In accordance with the first gate portion GA₁₂Received response vector H sent from₁₁, Error judgment signal E₁₁And user signal Y₁₁(T) is selected and output as it is, and the reception response vector H₁₂, Error judgment signal E₁₂And user signal Y₁₂(T) is given to the arithmetic unit 102 ′ constituting the second-stage interference canceller. This arithmetic unit 102 'includes a reception response vector H₁₂The interference cancellation selection signal I determined by the interference cancellation selector 10 based on₁₂Is given.
[0100]
Since the gate units GA and GB and the interference removal unit IC corresponding to other users other than the user 1 perform exactly the same operation, the description thereof is omitted.
[0101]
To summarize the above operation, the input signal vector X₁Regarding the user determined to perform no error and interference cancellation among the previous stage interference canceller ICs having received (t), the reception response vector H calculated by the interference canceler IC, the error determination signal E, The user signal Y (t) passes through the first stage interference canceller arithmetic unit 101 ′, the first gate part GA, and the second gate part GB, and the second stage interference. Given to a canceller. That is, for a user who has been determined to perform error elimination and interference cancellation once by the interference canceling unit IC, it is no longer given to the interference canceling unit IC of the subsequent interference canceller, and the reception response vector H, error determination signal E, The user signal Y (t) is not newly calculated.
[0102]
On the other hand, the input signal vector X₁Among the previous-stage interference canceller ICs that have received (t), for the user who has an error and / or is determined not to perform interference cancellation by the interference cancellation selector 10, the first-stage interference canceller computing device 101. The input signal vector X from which the interference wave is removed with high accuracy without introducing noise at ′₂Based on (t), the interference removal unit IC of the first-stage interference canceller recalculates the reception response vector H, the error determination signal E, and the user signal Y (t), and becomes the second-stage interference canceller. give. Also, the interference cancellation selector 10 determines the presence / absence of interference cancellation based on the calculated reception response vector H, and provides the interference cancellation selection signal I to the second-stage interference canceller.
[0103]
The second-stage interference canceller arithmetic unit 102 'has the same configuration as the first-stage interference canceller arithmetic unit 101', and performs the same operation as that described with reference to FIG. Execute. That is, the initial input signal vector X₁Only the replica signal corresponding to the user signal not including the demodulation error is subtracted from (t), and the next input signal vector X₂(T) is output from the adder AD (FIG. 6).
[0104]
That is, the preceding stage interference canceler IC₁₁, ..., IC_k1, ..., IC_m1In the case of a user who has been determined to perform error-free and interference cancellation in step (1), the replica signal is the initial input signal vector X in any subsequent stage of the interference canceller.₁It is a target of subtraction from (t).
[0105]
On the other hand, once the interference canceling unit IC in the previous stage₁₁, ..., IC_k1, ..., IC_m1In the first stage interference canceller arithmetic unit 101 ', and it is determined that there is an error and / or no interference cancellation is performed.₁Even if the user is excluded from the subtraction target from (t), the interference removal unit IC of the first-stage interference canceller₁₂, ..., IC_k2, ..., IC_m2Any of the interference cancellers in the subsequent stage, the replica signal is the initial input signal vector X₁It is a target of subtraction from (t).
[0106]
As a result, in the second stage interference canceller arithmetic unit 102 ′, the input signal vector X that has been subjected to interference wave removal with higher accuracy without introducing noise._Three(T) is obtained.
[0107]
The operation of the second stage interference canceller including the arithmetic device 102 'is performed by the arithmetic device 101' and the first gate portion GA.₁₂, ..., GA_k2, ..., GA_m2, Interference canceler IC₁₂, ..., IC_k2, ..., IC_m2, Second gate part GB₁₂, ..., GB_k2, ..., GB_m2Is exactly the same as the operation of the first-stage interference canceller.
[0108]
Such interference cancellers are connected in series in a plurality of stages, and the initial input signal vector X₁By subtracting only the replica signal of the user determined to perform error elimination and interference removal from (t), it is possible to remove interference waves with high accuracy in each stage of the interference canceller.
[0109]
For a user once determined to have no error in the interference removal unit IC in any stage including the previous stage and to perform interference removal in the interference removal selector 10, the received signal vector H calculated by the interference removal unit IC is used. And the error determination signal E and the user signal Y (t) are output from the second gate portion GB (not shown) of the final stage interference canceller, and the user signal Y (t) of them has no final error. It is extracted as a user signal and output from the receiving system.
[0110]
By the way, for the response vector, frequency offset information is added to the error-free user's remodulated signal (frequency offset is inversely compensated), and the correlation between the remodulated signal after frequency offset inverse compensation and the received signal (antenna input signal) is correlated. Estimated by the ensemble average of If an error is included in the response vector, incorrect information will be removed when removing interference, and as a result, necessary information will be removed and noise will be inserted. Is done. That is, when the accuracy of the response vector is poor, the accuracy of interference removal is degraded, and the accuracy of extracting a desired signal is degraded in the next stage.
[0111]
As described above, according to the present invention, if the response vector estimation accuracy is high, it is determined whether or not to cancel the interference according to the result of the simulation in advance. As a result, it is easy to be error-free.
[0112]
On the other hand, for a user who has been determined to have an error and / or not to perform interference cancellation in the interference cancellation unit IC in all stages, the received signal coefficient vector H and the error calculated by the interference cancellation unit IC of the interference cancellation unit in the final stage The determination signal E, the interference cancellation selection signal I, and the user signal Y (t) are output from the second gate unit GB, and the user signal Y (t) is finally extracted as a user signal with an error, and the reception It will be output from the system.
[0113]
The effect of the first embodiment will be described more specifically. In the first embodiment described above, the initial input signal X is calculated in the arithmetic unit for each stage of the multistage interference canceller.₁From (t), an interference component corresponding to each user, that is, a replica signal is removed. With the configuration of the first embodiment, the following effects can be obtained.
[0114]
For example, in the case of obtaining the received signal of the user 4 among four users, the interference removal unit IC in the previous stage₁₁And IC_{twenty one}When it is determined that only users 1 and 2 have no demodulation error, only the replica signals of users 1 and 2 are input to the initial input signal vector X in the first stage interference canceller arithmetic unit 101 ′.₁Subtracted from (t). As a result, the received signal X relating to the user 4 of the first stage interference canceller₂(T)
Initial input signal-(user 1 replica signal + user 2 replica signal)
It becomes.
[0115]
In addition, when interference cancellation is selected, the probability of an error is small, and the accuracy of the restored signal for interference cancellation is also increased.
[0116]
Next, the interference canceller IC of the first stage interference canceller₃₂When it is determined that there is no demodulation error for user 3 in addition to users 1 and 2, the replica signals of user 1, user 2, and user 3 are initially set in the second stage interference canceller computing device 102 ′. Input signal X₁Subtracted from (t). As a result, the received signal X relating to the user 4 of the second stage interference canceller_Three(T)
Initial input signal − (user 1 replica signal + user 2 replica signal + user 3 replica signal).
[0117]
[Embodiment 2]
FIG. 7 is a block diagram showing a receiving system for a PDMA base station according to Embodiment 2 of the present invention. The receiving system according to the second embodiment has an initial input signal vector X in each stage of the interference canceller arithmetic unit.₁Unlike the reception system in the first embodiment of FIG. 3 in which the replica signal is subtracted from (t), the interference corresponding to each user from the input signal vector newly calculated by the operation device of the interference canceller at each stage. The component, that is, the replica signal is configured to be subtracted.
[0118]
The receiving system according to the second embodiment shown in FIG. 7 is different from the receiving system according to the first embodiment shown in FIG. 3 in the following points. That is, the arithmetic unit 101 ′ in FIG.₁₂, ..., GA_k2, ..., GA_m2Interference canceler IC₁₂, ..., IC_k2, ..., IC_m2Are input signal vectors X output from the arithmetic unit 101.₂(T) is X in FIG.₁Instead of (t), it is given to the arithmetic unit 102 'of the second stage interference canceller. Further, in FIG. 7, the second gate unit GB of FIG. 3 is not provided, and the reception response vector H, the error signal E, the user signal Y (t), which are the outputs of the interference canceling unit IC, and the gate unit GA. The reception response vector H, the error determination signal E, the interference cancellation signal I, and the user signal Y (t) that have passed through the interference cancellation unit IC in the previous stage via the first stage are connected in parallel to the arithmetic apparatus 102 ′ of the second stage interference canceller. Is given to.
[0119]
Further, the second stage interference canceller arithmetic unit 102 ′ (and the subsequent stage interference canceller arithmetic unit) has a configuration as shown in FIG. 8 instead of the configuration shown in FIG. Yes.
[0120]
In the arithmetic unit 102 ′ shown in FIG. 8, the interference canceller IC of the preceding stage interference canceller, for example, the interference canceller IC₁₂Received response vector H from₁₂, Error judgment signal E₁₂, Interference cancellation selection signal I from interference cancellation selector 10₁₂And user signal Y₁₂(T) and the interference removal unit IC in the previous stage₁₁Received response vector H that has passed through the first stage interference canceller₁₁, Error determination signal E₁₁, And interference cancellation selection signal I₁₁And user signal Y₁₁(T) is the gate part GC₁Given to.
[0121]
Gate part GC₁The error determination signal E is input to the selection control input.₁₁And interference cancellation selection signal I₁₁And an error determination signal E₁₁No error, interference cancellation selection signal I₁₁Indicates that interference cancellation is performed, the interference cancellation unit IC₁₁Received response vector H from₁₁, Error judgment signal E₁₁, Interference cancellation selection signal I from interference cancellation selector 10₁₁, User signal Y₁₁Select (t) and receive response vector H₁₂, Error judgment signal E₁₂, Interference cancellation selection signal I_{12 ,}User signal Y₁₂(T) is output as an error determination signal E₁₁Has error and / or interference cancellation selection signal I₁₁Does not perform interference removal, the interference removal unit IC₁₂Received response vector H from₁₂, Error judgment signal E₁₂, Interference cancellation selection signal I from interference cancellation selector 10_{12 ,}User signal Y₁₂Select (t) and output.
[0122]
On the other hand, the interference canceller IC of the first stage interference canceller₁₂Received response vector H from₁₂And user signal Y₁₂(T) and multiplier MP₁And the output is AND gate AND₁To the first input. AND gate AND₁In the second input, the interference canceller IC₁₂Error judgment signal E from₁₂Is given. AND gate AND₁Of the interference cancellation selection signal I from the interference cancellation selector 10.₁₂Is given.
[0123]
AND gate AND₁Between the gate AD and the adder AD₁Is provided, and the gate part GD₁The error determination signal E is input to the selection control input._{11 ,}Interference cancellation selection signal I₁₁Indicates no error and interference cancellation, the gate portion GD₁Closed and AND gate AND₁Is not given to the negative input of the adder AD. On the other hand, error determination signal E₁₁Indicates that there is an error and / or interference cancellation selection signal I₁₁Does not perform interference cancellation, the gate part GD₁Open and AND gate₁Is supplied to the negative input of the adder AD.
[0124]
The positive input of the adder AD has an input signal vector X as in the first embodiment.₁Instead of (t), the input signal vector X calculated by the preceding interference canceller arithmetic unit 101 ′ is used.₂(T) is input.
[0125]
The above is the description of the configuration corresponding to the user 1, but the arithmetic device 102 ′ includes the same configuration from the user 1 to the user m.
[0126]
The operation of the receiving system of the second embodiment having the above configuration will be described. Input signal vector X₁The previous stage interference canceling unit IC receiving (t)₁₁, ..., IC_k1, ..., IC_m1Among these, for the user determined to perform no error and interference cancellation, the received signal vector H calculated by the interference cancellation unit IC, the error determination signal E, and the interference cancellation selection signal from the interference cancellation selector 10 I and the user signal Y (t) directly pass through the first stage interference canceller arithmetic unit 101 ′, the gate unit GA, and the gate unit GC of the second stage interference canceller arithmetic unit 102 ′. It passes through and is given to the gate part GA (not shown) of the second stage interference canceller.
[0127]
That is, a user who has been determined that there is no error in the interference removal unit IC in the previous stage and that interference removal is performed in the interference removal selector 10 is not given to the interference removal unit IC in the subsequent stage.
[0128]
On the other hand, the input signal vector X₁The previous stage interference canceling unit IC receiving (t)₁₁, ..., IC_k1, ..., IC_m1For users who are determined to have errors and / or not to perform interference removal, an input signal that has been subjected to high-precision interference wave removal without introducing noise by the first-stage interference canceller arithmetic unit 101 ′. Vector X₂Based on (t), the interference removal unit IC of the second-stage interference canceller recalculates the reception response vector H, the error determination signal E, and the user signal Y (t). This is given to the arithmetic unit 102 ′ (FIG. 7) of the interference canceller. Further, the interference cancellation selection signal I determined based on the reception response vector H calculated by the interference cancellation selection unit IC is supplied to the second stage interference canceller arithmetic unit 102 '.
[0129]
In the second stage interference canceller arithmetic unit 102 ′, the input signal vector X output from the preceding stage interference canceller arithmetic unit 101 ′.₂From (t), only the replica signal corresponding to the user determined by the interference canceller IC of the preceding stage (first stage) interference canceller that no demodulation error is included is input signal vector X₂Subtracted from (t).
[0130]
Here, the interference removal unit IC of the previous stage has already been₁₁, ..., IC_k1, ..., IC_m1For example, the interference canceling unit IC₁₁For the user 1 determined to have no error and to perform interference cancellation by the interference cancellation selector 10, the replica signal is already the arithmetic unit 101 ′ and the initial input signal vector X₁The input signal vector X that has been subtracted from (t) and is given to the adder AD of the arithmetic unit 102 '₂(T) is no longer included. For the user 1 determined to perform such error-free and interference removal, the gate unit GA of the first-stage interference canceller₁₂In the previous stage, the interference canceler IC₁₁Received response vector H which is the output of₁₁, Error determination signal E₁₁, Interference cancellation selection signal I₁₁, User signal Y₁₁(T) is selected and the gate part GC of the arithmetic unit 102 'is further selected.₁Is output to the subsequent stage. Therefore, the interference removal unit IC of the first stage interference canceller corresponding to the user 1₁₂X₂(T) is not given, and reception response vector H₁₂, Error determination signal E₁₂, User signal Y₁₂(T) is not output.
[0131]
Therefore, for user 1 already determined to perform error-free and interference cancellation, the multiplier MP₁AND gate AND₁Is not performed, and the input signal vector X by the adder AD₂Excluded from subtraction from (t). However, the interference canceler IC₁₂Input X₂Even if (t) is 0, the interference removing unit IC₁₂Some noise is generated by the operation of the multiplier MP.₁AND gate AND₁In order to prevent an error from being input to the adder AD, the gate unit GD₁Closes, AND gate AND₁To the adder AD is completely cut off.
[0132]
The effect of the second embodiment will be described more specifically. According to the second embodiment, the interference canceller at each stage converts the replica signal to the next stage from the input signal vector calculated by its own arithmetic unit. It is comprised so that it may remove with an arithmetic unit.
[0133]
For example, in the case of obtaining the received signal of the user 4 among four users, the interference removal unit IC in the previous stage₁₁And IC_{twenty one}When it is determined that only users 1 and 2 perform error-free and interference cancellation, the received signal vector X related to user 4 of the first stage interference canceller₂(T)
Initial input signal-(user 1 replica signal + user 2 replica signal)
It becomes.
[0134]
Next, in the second embodiment, the received signal related to the user 4 in the second stage interference canceller is as follows.
X₂(T)-(Replica signal of user 3)
It becomes.
[0135]
That is, in the first embodiment described above, the initial input signal vector X in the arithmetic unit of the interference canceller at each stage.₁Since the replica signal is subtracted from (t), the user replica signal once subtracted as having no error needs to be subtracted from the input signal vector repeatedly at each subsequent stage. Then, for a user who has already been subtracted from the input signal vector as having no error, it is no longer necessary to redo the subtraction from the input signal vector at a later stage. Therefore, according to the second embodiment, it is possible to greatly reduce the amount of calculation processing.
[0136]
[Embodiment 3]
Incidentally, the embodiment shown in FIGS. 3 to 8 relates to a receiving system of a PDMA base station. In recent years, in addition to this PDMA communication method, a CDMA communication method has been proposed and already put into practical use.
[0137]
In this CDMA communication system, a transmitting side multiplies a digital data symbol to be transmitted by a predetermined spreading code and transmits it as a signal having a much higher frequency, and a receiving side despreads the received signal using the above spreading code. By doing so, the data is demodulated.
[0138]
Here, if different types of spreading codes that are not correlated with each other are used, even if a plurality of data signals having the same frequency are spread and transmitted, despreading is performed with the spreading code corresponding to the transmission time. As a result, only the signal of the desired user can be reliably separated and extracted. Therefore, it is possible to further increase the communication capacity by using this CDMA communication system. Since such a CDMA communication system has already been put into practical use and is well known in the art, a detailed description thereof will be omitted.
[0139]
In the embodiment described below, the radio reception system according to the present invention is applied to a CDMA communication system.
[0140]
FIG. 9 is a block diagram showing a CDMA base station reception system according to Embodiment 3 of the present invention. FIGS. 10 and 11 are specific diagrams of the interference cancellation unit and the arithmetic unit shown in FIG. 9, respectively. It is a block diagram.
[0141]
The CDMA receiving system of the third embodiment shown in FIGS. 9 to 11 is the same as the PDMA receiving system of the first embodiment shown in FIGS. 3 to 5 except for the following points.
[0142]
That is, the configuration of the interference cancellation unit IC of the receiving system of the first embodiment shown in FIG. 3 is changed from the configuration of the first embodiment shown in FIG. 4 to the configuration of the third embodiment shown in FIG. . The interference canceller shown in FIG. 10 (interference canceler IC as an example_K1′), The despreader IS for despreading the signal transmitted by the CDMA communication system and received by the antennas 3 to 6 is preceded by the adaptive array and the parameter estimator._k1Is provided. The received signal despread for each user by the despreader in each interference canceling unit is given to the corresponding adaptive array and parameter estimator, and each user signal is extracted by the same operation as in the first embodiment. hand,
It is given to the arithmetic unit of the interference canceller at the subsequent stage.
[0143]
The computing device 101a of the first stage interference canceller shown in FIG.₁, ..., MP_k-1, MP_k, MP_{k + 1}, ..., MP_mDiffuser S₁₁, ..., S_{(k-1) 1}, S_k1, S_{(k + 1) 1}, ..., S_m15 is the same as the arithmetic unit 101 ′ shown in FIG.
[0144]
That is, the input signal vector X that has been spread by the CDMA communication system.₁In order to perform subtraction from (t), the output of each multiplier is again spread by the corresponding spreading code.
[0145]
Then, the output of each spreader, that is, the output of the arithmetic unit 101a is despread again by the despreader of the corresponding interference removal unit in the subsequent stage, and is given to the adaptive array and the parameter estimator.
[0146]
The computing device 102a of the second stage interference canceller has the same configuration as the computing device 101a shown in FIG. Other operations are the same as those of the first embodiment shown in FIGS.
[0147]
In each of the above-described embodiments, the error cancellation signal IC is obtained by the interference removal unit IC and the interference removal selection signal I is obtained by the interference removal selector 10, and the next stage of interference removal operation is performed using both signals. However, the interference cancellation unit IC does not perform error determination, the interference cancellation selector 10 obtains the interference cancellation selection signal I, and determines whether or not to perform the next-stage interference cancellation operation using only this signal. You may comprise. In this case, the accuracy cannot be denied a little, but if a signal with a high accuracy of a restoration signal for performing interference removal is selected in advance as a condition, a signal with a high restoration accuracy can be obtained sufficiently.
[0148]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0149]
【The invention's effect】
As described above, according to the present invention, the interference user signal component extracted by the signal extraction unit corresponding to the user is removed from the input signal vector by the interference removal unit, so that the desired user signal component is converted into the interference component. Extraction can be performed in a more suppressed state, and communication quality in a radio communication system such as a mobile communication system can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram of a receiving system for a PDMA base station as a premise of the present invention.
FIG. 2 is a block diagram showing a configuration of the arithmetic device shown in FIG.
FIG. 3 is a block diagram of a receiving system for a PDMA base station according to Embodiment 1 of the present invention;
4 is a block diagram illustrating a configuration of an interference removal unit illustrated in FIG. 3;
FIG. 5 is a block diagram showing a configuration of an interference cancellation selector according to the embodiment of the present invention.
6 is a block diagram showing a configuration of the arithmetic device shown in FIG. 3;
FIG. 7 is a block diagram of a receiving system for a PDMA base station according to Embodiment 2 of the present invention;
8 is a block diagram showing a configuration of the arithmetic device shown in FIG.
FIG. 9 is a block diagram of a receiving system for a CDMA base station according to Embodiment 3 of the present invention.
10 is a block diagram showing a configuration of an interference removal unit shown in FIG.
11 is a block diagram showing a configuration of the arithmetic device shown in FIG. 9;
FIG. 12 is a channel allocation diagram of user signals in FDMA, TDMA, and PDMA communication systems.
FIG. 13 is a block diagram showing a conventional PDMA base station reception system.
[Explanation of symbols]
1, 2 users, 3-6 antennas, 7 frequency conversion circuit, 8 A / D converter, 9 power detection unit, 10 interference cancellation selector, 11, 12, AA adaptive array, IC interference cancellation unit, DM demodulator, RM remodulator, ED error determiner, PE parameter estimator, MP multiplier, AD adder, AND AND gate, GA, GB, GC, GD, GE, GF, GG, GH gate unit, S diffuser, IS Despreader.

Claims (8)

A wireless reception system capable of receiving signals from a plurality of users using a plurality of antennas,
Signal processing means for performing predetermined signal processing on signals received by the plurality of antennas;
A plurality of first signal extraction means for extracting signal components respectively corresponding to the plurality of users based on signals output from the signal processing means;
A plurality of first estimating means for estimating a fading speed related to the relationship of the signal component extracted by the first signal extracting means with respect to the signal output from the signal processing means;
Based on signals received by the plurality of antennas, first interference cancellation determination means for determining whether to perform interference cancellation in consideration of the fading speed estimated by the corresponding first estimation means;
Radio receiver being characterized in that a first arithmetic means for subtracting the signal from the signal output from the processing means, the extracted signal component is determined to perform the interference removed by the interference cancellation determining means system.  The said 1st interference removal determination means determines whether interference removal is performed based on the signal component corresponding to the some user extracted by the said 1st signal extraction means. The wireless reception system described. A plurality of first error determination means for determining whether or not each of the signal components corresponding to the plurality of users extracted by the first signal extraction means includes a demodulation error, from the signal processing means; The extracted signal , which is determined to be subjected to interference cancellation in consideration of the corresponding fading speed by the interference cancellation determination unit and is determined not to include a demodulation error by the first error determination unit , from the output signal The wireless reception system according to claim 1, further comprising a first calculation unit that subtracts a signal component. A plurality of second signal extraction means for extracting signal components respectively corresponding to users determined to contain demodulation errors by the first error determination means based on the signal output from the first calculation means; ,
A plurality of second estimating means for estimating a fading speed related to the relationship of the signal components extracted by the second signal extracting means with respect to the signal output from the first calculating means;
Second interference cancellation determination means for determining whether to perform interference cancellation based on signal components corresponding to a plurality of users extracted by the second signal extraction means;
4. The radio according to claim 3, further comprising a plurality of second error determination units that determine whether or not each of the signal components extracted by the second signal extraction unit includes a demodulation error. Receiving system. Interference from the signal output from the signal processing means in consideration of the fading speed which does not include a demodulation error by the first and second error determination means and which corresponds by the first and second interference removal determination means. radio reception system according to claim 4, further comprising a second calculating means for subtracting the signal component extracted by determined as said first and second signal extraction means for removing. A third calculation for subtracting the signal component extracted by the second signal extraction unit that is determined not to include a demodulation error by the second error determination unit from the signal output from the first calculation unit The wireless reception system according to claim 5, further comprising means.  7. The radio reception system according to claim 1, wherein the signals from the plurality of users are signals transmitted by a PDMA communication method.  7. The radio reception system according to claim 1, wherein the signals from the plurality of users are signals transmitted by a CDMA communication system.

Images