JP3653457B2 - Wireless reception system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a radio reception system, and more particularly to a radio reception system based on a communication method such as PDMA (Path Division Multiple Access), CDMA (Code Division Multiple Access), etc., and removing interference signal components from other users from a received signal The present invention relates to a wireless reception system capable of performing the above.
[0002]
[Prior art]
In recent years, various mobile channel allocation methods have been proposed for effective use of frequencies in mobile communication systems such as mobile phones that are rapidly developing, some of which have been put into practical use.
[0003]
FIG. 12 is an arrangement diagram of channels in various communication systems of FDMA (Frequency Division Multiple Access), TDMA (Time Division Multiple Access), and PDMA. First, FDMA, TDMA, and PDMA will be briefly described with reference to FIG.
[0004]
FIG. 12A is a diagram showing a channel arrangement of FDMA, in which analog signals of users 1 to 4 are transmitted by being frequency-divided with radio waves of different frequencies f1 to f4, and the signals of users 1 to 4 are frequency filters. Separated by.
[0005]
FIG. 12 (b) is a diagram showing a TDMA channel arrangement, and each user's digitized signal is a radio wave having a different frequency f1 to f4 and is time-divisionally transmitted every certain time (time slot). The signals of the users 1 to 8 are separated by the frequency filter and the time synchronization between the base station and each user mobile terminal device.
[0006]
On the other hand, recently, a PDMA system has been proposed in order to increase the frequency use efficiency of radio waves by the spread of mobile phones. In this PDMA system, as shown in FIG. 12C, one time slot at the same frequency is spatially divided to transmit data of a plurality of users. In this PDMA, each user's signal is separated using a frequency filter, time synchronization between the base station and each user mobile terminal device, and a signal extraction device such as an adaptive array.
[0007]
FIG. 13 is a diagram showing a conventional receiving system for a PDMA base station. In this example, four antennas 3 to 6 are provided in order to distinguish between users 1 and 2, and the outputs of the respective antennas are given to the frequency conversion circuit 7, and the corresponding local oscillation signals Lo are respectively provided. Is converted into a digital signal by the A / D converter 8 and supplied to the digital signal processor (DSP) 10D.
[0008]
The DSP 10D includes adaptive arrays 11 and 12, a received signal vector calculator 13, a memory 14, a correlation value calculator 15, and a channel allocation device 16. The adaptive arrays 11 and 12 extract only a specific user signal from the reception signal output from the A / D converter 8. Each adaptive array is designated by the channel allocation device 16 to be described later depending on a weight vector calculation method such as a method using a preamble included in a time slot or a method using a property in which an envelope of a modulation signal is constant. User signal is extracted.
[0009]
The received signal vector calculator 13 receives the received signal from the A / D converter 8 and the output signals of the adaptive arrays 11 and 12, calculates received signal vectors corresponding to all users, and stores them in the memory 14. The channel allocation device 16 designates two users for the memory 14 and the correlation value calculator 15. The correlation value calculator 15 calculates the cross-correlation value of the received signal vectors of the two specified users among the received signal vectors stored in the memory 14. The channel allocator 16 receives the calculated cross-correlation value of the received signal vectors of the two users. If the cross-correlation value is equal to or less than a certain value, the two users are path-multiplex connected to the time slot at the same time.
[0010]
[Problems to be solved by the invention]
The adaptive arrays 11 and 12 shown in FIG. 13 extract the signals of the corresponding users 1 and 2, respectively. However, in addition to the users 1 and 2, for example, when the user 3 transmits a signal from the same direction as the user 1, the adaptive arrays 11 and 12 The signals of the user 1 and the user 3 are mixed and output from the array 11. However, the conventional adaptive array 11 cannot separate the signals of the users 1 and 3 and cannot extract only the signal of the user 1.
[0011]
Therefore, a main object of the present invention is to provide a radio reception system capable of improving communication quality by canceling unnecessary user signals using an interference canceller with a small hardware configuration.
[0012]
Furthermore, the present invention performs processing by a self-loop with one hardware configuration when an interference canceller or the like is configured by a DSP, and performs efficient processing even in such processing to shorten the signal processing time. Objective.
[0013]
[Means for Solving the Problems]
  According to the first aspect of the present invention, there is provided a wireless reception system capable of receiving signals from a plurality of users using a plurality of antennas, and performing predetermined signal processing on the signals received by the plurality of antennas. And signal processing means for receiving the signals received by the plurality of antennasOf the previous frameSelection means for selecting a user to be preferentially processed based on a signal, and first signal extraction means for extracting a signal component corresponding to the selected user based on a signal output from the signal processing means First estimation means for estimating parameter information relating to the relationship of the signal components extracted by the first signal extraction means with respect to the signal output from the signal processing means, and the signal output from the signal processing means First calculating means for subtracting with a signal considering the parameter information corresponding to the selected user.
[0014]
According to a second aspect of the present invention, each means is configured by a number smaller than the number of antennas.
[0015]
  According to a third aspect of the present invention, the selecting means isUser signal with high received power in previous frame, user signal error free in previous frame, user signal with less fading in previous frame, or array in previous frame Either the user's signal with a small processing error, or the user's signal with high accuracy of response vector estimation in the previous frameA user is selected based on the selection.
[0016]
According to a fourth aspect of the present invention, in the wireless reception system according to any one of the first to third aspects, signal components corresponding to a plurality of users extracted by the first signal extraction unit are respectively provided. A plurality of first error determination means for determining whether or not a demodulation error is included, and a signal output from the signal processing means is determined not to include a demodulation error by the first error determination means. And a first calculation means for subtracting the extracted signal component in consideration of the corresponding parameter information.
[0017]
According to the fifth aspect of the present invention, in the wireless reception system according to any one of the first to fourth aspects, the signals from the plurality of users are signals transmitted by the PDMA communication method.
[0018]
According to a sixth aspect of the present invention, in the radio reception system according to any one of the first to fourth aspects, signals from a plurality of users are signals transmitted by a CDMA communication method.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a receiving system for a PDMA base station proposed as a multistage interference canceller which is a premise of the present invention. The proposed receiving system which is the premise of the present invention is a signal S from m (m is an integer of 2 or more) users 1,..., K,.₁(T), ..., S_k(T), ..., S_m(T) is separated from each other and taken out in parallel.
[0020]
In FIG. 1, as in the conventional example of FIG. 13, the receiving system of the PDMA base station is provided with four antennas 3 to 6, a frequency conversion circuit 7, and an A / D converter 8. . Input signal vector X output from the A / D converter 8₁(T) shows the first stage arithmetic unit 101 and the first stage adaptive array AA.₁₁, ..., AA_k1, ..., AA_m1And the first stage parameter estimator PE₁₁, ..., PE_k1, ..., PE_m1And given to. Details of the adaptive array will be described later.
[0021]
Adaptive array AA₁₁, ..., AA_k1, ..., AA_m1To the user signal Y which is a complex signal that includes the signal component of the corresponding user most strongly (in addition to the interference signal component from other users).₁₁(T), ..., Y_k1(T), ..., Y_m1(T) is output and provided to the first stage arithmetic unit 101, and the corresponding detector DE is also provided.₁₁, ..., DE_k1, ..., DE_m1It is detected at.
[0022]
Parameter estimator PE₁₁, ..., PE_k1, ..., PE_m1Are respectively the input signal vectors X₁(T) and detector DE₁₁, ..., DE_k1, ..., DE_m1And a corresponding response output H of the corresponding user based on the corresponding detection output of₁₁, ..., H_k1, ..., H_m1Is estimated and given to the first stage arithmetic unit 101. More specifically, each parameter estimator includes how much the corresponding user signal component is included in the input signal vector, how much the corresponding user signal component is phase rotated with respect to the input signal vector, Etc.
[0023]
The first stage arithmetic unit 101 calculates the input signal vector X for each user i (i = 1, 2,..., M).₁By subtracting the signal components of all other users except the user i from (t), the interference signal component is removed, and the further input signal vector X of the user i_i2(T) is calculated and output. The operation of the arithmetic unit 101 will be described in detail later with reference to FIG.
[0024]
The first-stage arithmetic unit 101 corresponds to each user with the input signal vector X₁₂(T), ..., X_k2(T), ..., X_m2(T) is output and the corresponding second-stage adaptive array AA is output.₁₂, ..., AA_k2, ..., AA_m2To give.
[0025]
Second-tier adaptive array AA₁₂, ..., AA_k2, ..., AA_m2User signal Y output from₁₂(T), ..., Y_k2(T), ..., Y_m2(T) is given to the second stage arithmetic circuit 102 and the corresponding detector DE₁₂, ..., DE_k2, ..., DE_m2It is detected at.
[0026]
Parameter estimator PE₁₂, ..., PE_k2, ..., PE_m2Are respectively the input signal vectors X₁(T) and detector DE₁₂, ..., DE_k2, ..., DE_m2And a corresponding response output H of the corresponding user based on the corresponding detection output of₁₂, ..., H_k2, ..., H_m2Is estimated and given to the second stage arithmetic unit 102. The arithmetic unit 102 is further connected to a further input signal vector X₁₃(T), ..., X_k3(T), ..., X_m3(T) is output, and the corresponding third-stage adaptive array AA (not shown) is output.₁₃, ..., AA_k3, ..., AA_m3To give.
[0027]
As described above, by providing a plurality of stages (from the first stage to the L-th stage) of interference cancellers including the adaptive array, the parameter estimator, and the arithmetic unit in series, the interference signals are included in the user signals output from the respective stages. The ratio of other user signal components is gradually reduced to further eliminate interference. As a result, communication characteristics can be further improved.
[0028]
FIG. 2 is a specific block diagram of the arithmetic device 101 as an example of the multi-stage arithmetic device shown in FIG. In FIG. 2, the arithmetic unit 101 includes a multiplier MP.₁, ..., MP_k-1, MP_{k + 1}, ..., MP_mAnd adder AD_kIt consists of and. Although not shown for simplification of description, in addition to the multiplier and adder shown, the multiplier MP_kAnd adder AD₁, ..., AD_k-1, AD_{k + 1}, ..., AD_mIs built in the arithmetic unit 101.
[0029]
Multiplier MP₁, ..., MP_k-1, MP_{k + 1}, ..., MP_mEach has an adaptive array AA₁₁, ..., AA_k-1, AA_{k + 1}, ..., AA_mUser signal Y from₁₁(T), ..., Y_{(k-1) 1}(T), Y_{(k + 1) 1}(T), ..., Y_m1(T) and the parameter estimator PE₁₁, ..., PE_{(k-1) 1}, PE_{(k + 1) 1}, ..., PE_m1Received response vector H from₁₁, ..., H_{(k-1) 1}, H_{(k + 1) 1}, ..., H_m1And is given.
[0030]
Multiplier MP₁, ..., MP_k-1, MP_{k + 1}, ..., MP_mOutput of adder AD_kInput signal vector X₁(T) is the adder AD_kGiven to the positive input. As a result, the input signal vector X₁A signal component corresponding to a user other than the user k is subtracted from (t) to obtain a signal component X corresponding to the user k._k2(T) is the adder AD_kWill be output. As described above, the adaptive array, the parameter estimator, and the arithmetic unit as a whole constitute a one-stage interference canceller.
[0031]
As a result, a considerable interference signal component is removed. Then, a new input vector signal X from which the interference signal component is considerably removed by the arithmetic unit 101 in this way._k2By giving (t) to the interference cancellers in the second and subsequent stages, the user signal S that is finally output is displayed._kThe ratio of interference signal components from other users included in (t) can be sufficiently reduced, and good communication characteristics can be realized.
[0032]
Adder AD_kSimilarly to each of the adders (not shown) in parallel, the multiplier MP₁, ..., MP_k, ..., MP_mOutput from the other than the multiplier corresponding to the adder, and the input signal vector X₁(T) is given. Each of these adders outputs a new input signal vector shown in FIG. 1 and gives it to the second and subsequent interference cancellers.
[0033]
Next, a more specific operation of the apparatus shown in FIGS. 1 and 2 will be described.
Assuming that the number of antenna elements is n and the number of users who are talking simultaneously is m, the input signal vector X output from the A / D converter 8₁(T) is expressed by the following equation.
[0034]
X₁(T) = [x₁(T), x₂(T), ... x_n(T)]^T  (1)
x_j(T) = h_j1S₁(T) + h_j2S₂(T) + ... + h_jiS_i(T) + ... + h_jmS_m(T) + n_j(T), (j = 1, 2,..., N) (2)
When the above expressions (1) and (2) are converted into vector notation, the following expression (3) is obtained.
[0035]
X₁(T) = H₁S₁(T) + H₂S₂(T) + ... + H_iS_i(T) + ... + H_mS_m(T) + N (t) (3)
H_i= [H_1i, H_2i, ..., h_ni]^T, (I = 1, 2,..., M) (4)
N (t) = [n₁(T), n₂(T), ..., n_n(T)]^T  (5)
[0036]
Next, a new input signal vector X from the arithmetic unit 101 in FIG._k2The operation of outputting (t) will be described in further detail.
[0037]
Parameter estimator PE₁₁, ..., PE_k1, ..., PE_m1H_iIt is assumed that (i = 1, 2,..., M) can be estimated. The first stage adaptive array AA₁₁, ..., AA_k1, ..., AA_m1If it works relatively well, Y_i1(T) ≒ S_i(T).
[0038]
At this stage, all user signals and reception response vectors of all user signals are obtained. Here, the input signal vector X used for the signal detection of the user k at the second stage_k2(T) can be obtained from the expression (6).
[0039]
X_k2(T) = X₁(T) -H₁S₁(T) -...- H_k-1S_k-1(T) -H_{k + 1}S_{k + 1}(T) -...- H_mS_m(T) ... (6)
Substituting equation (3) into equation (6) yields equation (7).
[0040]
X_k2(T) = H_kS_k(T) + N (t) (7)
X₁(T) and X_k2When comparing (t), X_k2(T) is S_kInterference component S other than (t)_i(T) (i = 1, 2,..., M, i ≠ k) decreases, and the second-stage adaptive array becomes easier to operate.
[0041]
As shown in FIG. 1, in a multistage interference canceller configured by connecting multiple stages of interference cancellers, a received signal is separated for each user by an adaptive array, and a signal of a user other than the user is used as an interference wave from the received signal. The result obtained by the removal is given to the next-stage interference canceller as an input signal of the user. As a result, in the next stage interference canceller, a user signal with good communication characteristics can be obtained as much as the interference wave of the input user signal is small. Then, by repeating such interference wave removal in a plurality of stages, the interference wave removal further proceeds, the CIR (Carrier to Inference Ratio) is further improved, and it becomes easier to extract a desired user signal.
[0042]
However, if the multistage interference canceller as described above is used, the removal of the interference wave certainly proceeds, but the following problems arise.
[0043]
(1) In the example of the above-described multistage interference canceller (hereinafter referred to as MIC), the user signal extracted by each adaptive array is used as an interference wave component from the received signal without determining the presence or absence of the demodulation error. Configured to remove. Therefore, if there is a demodulation error in the user signal extracted by the adaptive array and the signal has some deformed waveform, for example, an impulse waveform, the signal component including such an error is subtracted from the received signal. As a result, the output of each arithmetic device (input signal to the interference canceller at the next stage) has an influence such as impulsive noise due to the influence of a demodulation error.
[0044]
(2) The MIC process described above has a problem that the processing amount is large. Therefore, hardware with high performance in terms of hardware is required, and cost performance is reduced.
[0045]
(3) If the system has only one user that can be processed in one stage due to factors such as hardware, in order to go to the next stage, the user must be an error-free user.
[0046]
(4) For example, even if there are two users that can be processed in one stage, the user who processes first tends to be error-free, that is, it is better that interference can be removed with the restored signal of the processed user. In this way, in the next stage, the signal-to-interference ratio (SIR) of the user who has not yet become error-free can be ensured, and error-free can be facilitated.
[0047]
The present invention is intended to solve the above problems (1) to (4). In this invention, the user who is likely to be error-free is selected as the selection condition of the user to be processed first. As a guideline that is likely to be error-free, “(1) users with high received power (SNR), (2) users who became error-free in the previous frame, (3) users with low fading (FD), and (4) arrays User with small MSE (Mean Square Error) in processing, and (5) user with high response vector estimation accuracy ”.
[0048]
When the user's received power is high, that is, the signal-to-noise ratio (SNR) is high, the desired signal can be easily extracted, and therefore error-free. If there is no error in the previous frame, there is a high probability that no error will occur in that frame. When the FD is small, the desired signal can be easily extracted, and therefore error free.
[0049]
The MSE is output by array processing and is as follows. That is, in the array processing in the adaptive array, the optimum weight is determined so that the array output y (t) is as close as possible to the reference signal d (t). As a criterion for evaluating how close to the reference signal, the mean square error between the array output and the reference signal is defined by the following equation.
[0050]
MSE = E [│d (t) -y (t) │²]
Here, d (t) represents a reference signal at time t, and y (t) represents an array output signal at time t. E [] represents an ensemble averaging operation.
[0051]
From the above, the smaller the MSE, the better the extraction of the desired signal, and the more likely it is error free.
[0052]
Furthermore, the fact that the response vector estimation accuracy is good means that a desired signal has been extracted, and it is likely to be error-free. In addition, since interference can be removed with high accuracy, a desired signal can be efficiently extracted even when the next stage is entered.
[0053]
[Embodiment 1]
FIG. 3 is a block diagram showing a receiving system for a PDMA base station according to Embodiment 1 of the present invention. In the first embodiment, the above-mentioned “(1) user with high received power” is used as a standard that is likely to be error-free, and there is only one user that can be processed in one stage.
[0054]
As shown in FIG. 3, in the example of this embodiment, four antennas 3 to 6 are provided, and the outputs of the respective antennas are given to the frequency conversion circuit 7, and the corresponding local oscillation signals Lo are respectively provided. Is converted into a digital signal by the A / D converter 8 and supplied to the received power detector 9.
[0055]
The received power detection unit 9 obtains the magnitude of received power of the user from the digital output from the four antennas given from the A / D converter 8 and gives it to the priority user selector 10. As will be described later, this priority user selector 10 is provided with the reception response vector H in the previous frame of each user calculated by the interference removal unit IC, and estimates the SNR.
[0056]
In addition, “(2) user who became error-free in the previous frame”, “(3) user with small fading (FD)”, “(4) MSE (Mean Square Error in array processing) ) “Small user” and “(5) user with high response vector estimation accuracy”, the priority user selector 10 receives data from the interference removal unit IC or the like, calculates data as described later, A priority user is selected based on this data. For example, the FD is obtained based on the calculated reception response vector H. Further, the MSE is obtained based on the data calculated by the adaptive array of the interference removal unit IC based on the above-described formula. When a user who has become error free in the previous frame is stored and a user who has become error free in the previous frame is used, an error free user is selected from the stored data. Furthermore, when a user with high response vector estimation accuracy is preferentially processed, an estimation is made based on the FD, SNR, and interference signal level (SIR: signal-to-interference wave ratio) of the previous frame, and the user is selected. .
[0057]
As shown in FIG. 3, in order to select a user who is likely to be error-free, priority is given by the output from the received power detection unit 9 and the data such as the response vector H of the previous frame, error information, etc. given from the interference removal unit IC. The user selector 10 selects a priority user and instructs the adaptive array unit in the interference removal unit IC to select a user signal having priority. The interference canceler IC and the arithmetic unit 101 ′ form the basic configuration of an interference canceller.
[0058]
The interference removal unit IC1 outputs a desired signal Y1 (instructed user signal), a response vector H1, and an error determination signal E1 in accordance with an instruction from the priority user selector 10. The response vector H1 and the error determination signal E1 are output to the priority user selector 10 for the next priority user selection. Although it is not always necessary to output the error determination signal E1 to the priority user selector 10, it is assumed that, for example, although the user 1 is selected in the first stage, the processing results in an error. In the second stage, it is assumed that the user with the next highest power is selected without selecting user 1. As a result, it is assumed that the error becomes free. In such a case, it is conceivable that the selected user in the third stage selects the next highest power user or the user who has been selected so far but had an error. When the latter process is performed, the user error determination result processed in the previous stage is required. In order to perform such processing, an error determination signal E1 is output to the priority user selector 10.
[0059]
Although omitted for simplification of illustration, it is assumed that the interference canceller is configured in exactly the same manner as the second-stage interference canceller at the subsequent stage of the arithmetic unit 102 ′.
[0060]
Therefore, the receiving system of FIG. 3 is configured as a multistage interference canceller as a whole, and the output from the final stage interference canceller becomes the final output of the receiving system.
[0061]
In the receiving system of FIG. 3, all of the interference canceling units IC have the same configuration. As an example, the interference canceling unit IC_kThe configuration is shown in FIG.
[0062]
In FIG. 4, the interference removing unit IC_kInput signal vector X input to₁(T) to adaptive array AA_kThe complex signal of user k extracted in step_kIs converted into a bit information signal. This bit information signal is supplied from the error determination device ED._kAnd the remodulator RM_kAlso given to. Adaptive array AA_kIs given an instruction signal for selecting a user to be selected from the priority user selector 10. As will be described later, the MSE is an adaptive array AA._kWhen this MSE is used as a guideline that is likely to be error-free, the adaptive array AA is used._kThe MSE is sent to the priority user selector 10.
[0063]
Error judgment device ED_kIs the demodulator DM_kBased on the bit information signal from the adaptive array AA_kIt is determined whether or not there is a demodulation error in the extracted signal. If it is determined that there is a demodulation error, an L level error determination signal E_kIs provided to the arithmetic unit 101 ′ of the first stage interference canceller.
[0064]
Remodulator RM_kIs the demodulator DM_kThe bit information signal from the user signal Y which is a complex signal again._k(T), and is supplied to the first stage interference canceller arithmetic unit 101 ′, and the parameter estimator PE_kTo give.
[0065]
Parameter estimator PE_kIs the input signal vector X₁(T) and the user signal Y_k(T) and the corresponding user reception response vector H_kIs calculated and given to the first stage interference canceller arithmetic unit 101 '.
[0066]
As shown in FIG. 4, an array including an adaptive array, a demodulator, an error determiner, a remodulator, a parameter estimator, and an interference signal cancellation selector is common to all the interference cancellation units IC in FIG. 3. Further explanation will not be repeated.
[0067]
Next, this receiving system will be described based on the operation. First, as in the receiving system of FIG. 1, the A / D converter 8 receives an input signal vector X₁(T) is output and provided to the interference cancellation IC and the reception power detection unit 9.
[0068]
In the example of this embodiment, four antennas 3 to 6 are provided, and the outputs of the respective antennas are given to the frequency conversion circuit 7 and are frequency-converted by the corresponding local oscillation signals Lo, respectively. It is converted into a digital signal by the D converter 8 and given to the reception power detection unit 9.
[0069]
The received power detector 9 gives the received power to the priority user selector 10 based on the digital output from the four antennas given from the A / D converter 8. The priority user selector 10 determines which user's reception power is high, and gives a selection signal so that the interference cancellation unit IC selects the one with the maximum reception power. The interference removal unit IC performs interference removal processing according to the given selection signal. The interference removal unit IC to which the priority user signal is given outputs the desired signal Y1 (instructed user signal), the response vector H1, and the error determination signal E1. The desired signal Y1 (instructed user signal), the response vector H1, and the error determination signal E1 are input to the calculation unit 101 'and processed based on the determination of interference removal.
[0070]
Further, in order to notify the user information as the final output, the desired signal Y1 (instructed user signal), the response vector H1 and the error determination signal E1 are notified together with U1 indicating what the user has processed here. The In addition, as shown above, an error was determined as an error. However, when adaptive array processing is performed again as a priority user, a plurality of final data will be output. Takes precedence.
[0071]
Next, in the priority user selector 10, the user who is most likely to be error-free is selected using the conditions (1) to (5) described above. First, a method of selecting according to a user with high reception power will be described.
[0072]
The calculation of the received power level (SNR: signal-to-noise ratio) of the user will be described. Since the signal from the reception power detection unit 9 is a composite signal for all users, it must be converted into reception power for each user. For this purpose, the calculated reception response vector H_kNeed.
[0073]
Basically, the sum of the squares of the I component and Q component of the response vector (complex number) of each user is the power of each user, but the absolute magnitude is not known from the magnitude of the response vector. for that reason. Based on the received power from the received power detection unit 9, the received power is distributed to each user's received power. It is distributed as follows.
[0074]
User i received power = (received power × user i response vector magnitude (sum of squares) / (sum of response vectors of all users (sum of squares)))
[0075]
For example, at the time of 2 multiplexing, the power from the received power detection unit 9 is 50 [dBμV], the response vector size of the user 2 is 30, the response vector size of the user 1 is 70, and all the user responses If the magnitude of the vector is 100 (= 30 + 70), the received power of user 1 is 35 [dBμV] and the received power of user 2 is 15 [dBμV].
[0076]
Assuming that the signal from the received power detection unit 9 does not include noise, the above value is the value of the S (desired wave) signal. Therefore, in order to convert to SNR, a ratio with noise must be taken. Assuming that noise is slightly different for each base station, but measured in advance,
SNR = 10 · log_Ten(Desired wave power / noise power)
Calculated by
[0077]
With the above method, the priority user selector 10 obtains the magnitude of received power of each user. Then, the priority user selector 10 stores the obtained order of the received power level of each user in the memory, and first performs interference removal processing on the user with the largest received power in the stored order. A selection signal is given to the interference cancellation IC. The reason why the order of magnitude of received power of each user is stored in the memory is that it is used to select which user's signal is used for interference cancellation in the processing after the next stage.
[0078]
Note that the priority user selector 10 may be configured to select the signal having the highest received power in the order of the user number from those having a power higher than that known to be error-free. Good.
[0079]
FIG. 5 is a block diagram showing a specific configuration of the arithmetic apparatus 101 ′ of the first stage interference canceller as an example of the multistage interference canceller configuring the reception system of FIG. In FIG. 5, the arithmetic unit 101 ′ includes a multiplier MP.₁AND gate AND₁And an adder AD.
[0080]
Multiplier MP₁Respectively, the interference canceling part IC in the previous stage₁User signal Y from₁(T) and response vector H₁And is given.
[0081]
Multiplier MP₁Output of AND gate AND₁The second input of these AND gates is connected to the previous stage interference canceller IC.₁Corresponding error judgment signal E from₁Is entered.
[0082]
AND gate AND₁Is supplied to the negative input of the adder AD, and the input signal vector X from the A / D converter 8 is supplied.₁(T) is given to the positive input of the adder AD.
[0083]
The output of the adder AD is the input signal vector X₂(T) is output from the arithmetic unit 101 ′, and as shown in FIG. 3, an interference canceling IC corresponding to the next user.₂Given to.
[0084]
Although not shown in the block diagram of the arithmetic unit 101 ′ in FIG.₁Received response vector H output from₁, Error determination signal E₁, And user signal Y₁(T) Passes through the arithmetic unit 101 'as it is and is given to, for example, a processing unit for obtaining a transmission weight.
[0085]
Here, with reference to FIG. 5, the case where it is determined that there is a demodulation error in the interference removing unit as described above will be described. Determined user signal, eg Y₁Interference remover IC corresponding to (t)₁Error judgment device ED₁To L level error determination signal E₁AND gate AND of the arithmetic unit 101 ′₁To the other input. As a result, the AND gate is closed and the corresponding multiplier MP₁Received response vector H output from₁And user signal Y₁The product of (t), that is, the input of the replica signal to the adder AD is blocked.
[0086]
As a result, the input signal vector X₁The interference wave component (replica signal) corresponding to the user signal including the demodulation error is not subtracted from (t).
[0087]
Previous stage interference canceler IC₁In this embodiment, when it is determined that there is an error, the priority user selector 10 selects the second user who is most likely to be error-free, and the selection signal U is used as the interference removal unit IC in the next stage.₂To give. Interference canceler IC₂Extracts the selected user signal (Y) based on the given selection signal U.
[0088]
This interference canceler IC₂Is the IC of FIG._kThis input signal vector X₂(T) and (If it is determined that there is an error in the previous stage, the input signal vector X₁(T) is received) based on the user input signal not selected in the previous stage, the reception response vector H₂And error determination signal E₂And the user signal Y₂(T) is newly calculated and given to the arithmetic unit 102 ', and the above-described operation is performed.
[0089]
On the other hand, the previous stage interference canceler IC₁When it is determined that there is no error, the error determination signal E₁In response to the input signal X obtained by subtracting the corresponding user replica signal from the input signal vector in the arithmetic unit 101 ′.₂(T) is the interference removal unit IC.₂Given to. This interference canceler IC₂Then, the input signal of the user selected next and the input signal X from the arithmetic unit 101 ′₂From (t), the reception response vector H₂, Error judgment signal E₂, User signal Y₂Are newly calculated and given to the arithmetic unit 102 ', and the above-described operation is performed.
[0090]
To summarize the above operation, the input signal vector X₁Among the previous stage interference canceller ICs that have received (t), for users without errors, the reception response vector H calculated by the interference canceler IC, the error determination signal E, and the user signal Y (t) Is sent to the next signal processor as it is. In the next stage interference canceller IC, the input signal vector X₁A signal obtained by subtracting an interference wave component (replica signal) corresponding to a user signal not including an error from (t) is given.
[0091]
On the other hand, the input signal vector X₁Regarding the user determined to have an error in the preceding stage interference canceller IC receiving (t), the input signal vector X₁The interference wave component (replica signal) corresponding to the user signal including the demodulation error is not subtracted from (t).
[0092]
The second-stage interference canceller arithmetic unit 102 'has the same configuration as the first-stage interference canceller arithmetic unit 101', and performs the same operation as that described with reference to FIG. Execute. That is, the input signal vector X₂Only the replica signal corresponding to the user signal not including the demodulation error is subtracted from (t), and the next input signal vector X_Three(T) is output from the adder AD (FIG. 5).
[0093]
As a result, in the second stage interference canceller arithmetic unit 102 ′, the input signal vector X that has been subjected to interference wave removal with higher accuracy without introducing noise._Three(T) is obtained.
[0094]
The operation of the second-stage interference canceller including the arithmetic device 102 ′ is exactly the same as the operation of the first-stage interference canceller of the arithmetic device 101 ′.
[0095]
Such interference cancellers are connected in a plurality of stages in series, and the input signal vector X_nBy subtracting only the replica signal of the user determined as having no error from (t), it is possible to remove the interference wave with high accuracy in the interference canceller at each stage.
[0096]
For a user once determined to have no error by the interference removal unit IC in any stage including the previous stage, the received signal vector H calculated by the interference removal unit IC, the error determination signal E, and the user signal Y (T) and the priority selection signal U are given from the interference removal unit IC of each stage to the final output.
[0097]
In the above-described example, the priority user selection circuit 10 selects a priority user based on the magnitude of the received power. However, when a priority user is obtained for the above conditions (2) to (5), the following is performed. You can go to
[0098]
In the case of “(2) user who becomes error free in the previous frame”, the priority user may be selected based on the error determination E of the previous frame.
[0099]
In the case of “(3) user with small fading (FD)”, the FD may be estimated from the response vectors of the frames before and after being input to the priority user selector 10 and the priority user may be selected based on the FD.
[0100]
In the case of “(4) user with small MSE (Mean Square Error) in array processing”, the MSE is input to the priority user selector 10 from the adaptive array unit of the interference cancellation IC, and the priority user is selected based on the MSE. That's fine.
[0101]
In the case of “(5) user with high response vector estimation accuracy”, the priority user selector 10 determines the response vector estimation accuracy and selects the priority user with this estimation accuracy.
[0102]
The above operation will be described with reference to the flowchart of FIG. First, a priority user is determined (step S101). One user is selected based on a determination condition such as a user with high received power. Then, synchronization processing is performed according to the selected user signal (step S102).
[0103]
Subsequently, array processing is performed to extract a desired signal from the received signal (step S103). Then, demodulation processing is performed, and desired phase information is changed to bit information (step S104).
[0104]
Thereafter, demodulation error determination is performed (step S105). That is, it is determined whether the demodulated signal is correct, and whether it is an error is recorded.
[0105]
Next, a transition determination to the next stage is performed. That is, based on the demodulation error determination result, it is determined whether or not it is possible to transit to the next stage (step S106). Then, it is determined whether or not to go to the next stage (step S107). When going to the next stage, the process proceeds to step S108, and when not going to the next stage, the operation is finished.
[0106]
In step S108, remodulation processing is performed, and the demodulated bit information is modulated again to phase information. Then, the response vector is estimated, and the phase amplitude information of the user to be removed (remodulated user) is estimated (step S109).
[0107]
Subsequently, a replica signal is generated. That is, a user replica signal to be removed from the remodulated signal and the response vector is generated (step S110).
[0108]
Thereafter, the replica signal is removed from the received signal (step S111). And it returns to step S101 and repeats the above-mentioned operation | movement.
[0109]
The effect of the first embodiment will be described more specifically. In the first embodiment described above, the input signal X is input to the arithmetic unit for each stage of the multistage interference canceller._nFrom (t), an interference component corresponding to an error-free user, that is, a replica signal is removed. With the configuration of the first embodiment, the following effects can be obtained.
[0110]
For example, when obtaining the received signal of the user 4 out of four users, the received signal of the user 1 having a very high probability of being error-free is selected, and the interference removing unit IC in the previous stage is selected.₁When the user 1 is determined to have no demodulation error, the replica signal of the user 1 is transmitted to the initial input signal vector X in the first stage interference canceller arithmetic unit 101 ′.₁Subtracted from (t). As a result, the received signal X relating to the user 4 of the first stage interference canceller₂(T)
Initial input signal-(User 1 replica signal)
It becomes.
[0111]
Next, the reception signal of the user 2 having the next highest probability of error-free is selected, and the interference removal unit IC in the previous stage is selected.₂When the user 2 is determined not to have a demodulation error, the replica signal of the user 2 is transmitted to the next input signal vector X in the second stage interference canceller arithmetic unit 102 ′.₂Subtracted from (t). As a result, the received signal X related to the user 4 of the second stage interference canceller_Three(T)
Receive signal X₂(T)-(Replica signal of user 2)
It becomes.
[0112]
Then, the reception signal of the user 3 with the next highest probability of error-free is selected, and the previous interference removal unit IC_ThreeWhen the user 3 is determined not to have a demodulation error, the replica signal of the user 3 is transmitted to the next input signal vector X in the third stage interference canceller arithmetic unit 103 ′._ThreeSubtracted from (t). As a result, the received signal X relating to the user 4 of the third stage interference canceller_Four(T)
Receive signal X_Three(T)-(Replica signal of user 3)
It becomes.
[0113]
In this way, even with a single interference removal hardware configuration, interference removal can be reliably performed. Further, by preferentially processing from an error-free user, interference can be removed without waste, and when configured with a DSP, processing steps can be reduced, that is, processing time can be shortened.
[0114]
[Embodiment 2]
FIG. 7 is a block diagram showing a receiving system for a PDMA base station according to Embodiment 2 of the present invention. In the first embodiment described above, a “user with high received power” is used as a standard that is likely to be error-free, and there is only one user that can process in one stage. In the second embodiment, two users are selected from among users who are prone to error-free selection conditions for the user to be processed first. As a guideline that is likely to be error-free, “users with high received power, users who became error-free in the previous frame, users with slow fading (FD), users with small MSE (Mean Square Error) in array processing, response vector estimation Judgment is made based on a plurality of conditions such as “accurate user”. The number of users that can be processed in one stage is a system for two users.
[0115]
In FIG. 7, the arithmetic device 101 ′ and the interference canceller IC provided for each of two users constitute the basic configuration of the first-stage interference canceller.
[0116]
Although omitted for simplification of illustration, it is assumed that a plurality of stages of interference cancellers continue in the same manner as the first stage interference canceller for each of a plurality of users at the subsequent stage of the arithmetic unit 102 ″. To do.
[0117]
Therefore, the receiving system of FIG. 7 is configured as a multistage interference canceller as a whole, and the output from the final stage interference canceller becomes the final output of the receiving system.
[0118]
First, as in the receiving system of FIG. 3, the A / D converter 8 receives an input signal vector X₁(T) is output and provided to the first stage interference canceller arithmetic unit 101 ', and a plurality of interference cancellation units IC provided corresponding to the first stage interference canceller.₁₁, IC₁₂Is also given in common.
[0119]
In the reception system of FIG. 7, the interference removal unit IC has the same configuration as that shown in FIG.
[0120]
In the example of this embodiment, four antennas 3 to 6 are provided, and the outputs of the respective antennas are given to the frequency conversion circuit 7 and are frequency-converted by the corresponding local oscillation signals Lo, respectively. It is converted into a digital signal by the D converter 8 and given to the reception power detection unit 9.
[0121]
The received power detector 9 gives the received power to the priority user selector 10 based on the digital output from the four antennas given from the A / D converter 8. The priority user selector 10 selects two users that are likely to be error-free, and gives selection signals to the interference canceling unit IC. The interference removal unit IC performs interference removal processing in accordance with the given selection signal.
[0122]
In this embodiment, as an indication that error-free is likely to occur, in addition to “(1) large received power”, “(2) user who became error-free in the previous frame” and “(3) fading (FD)” Using “small user”, “(4) user with small MSE (Mean Square Error) in array processing”, and “(5) user with high response vector estimation accuracy”, users who are likely to be free of two errors from these data Is configured to select.
[0123]
FIG. 8 is a block diagram showing the configuration of the priority user selector according to the embodiment of the present invention. The operation of the priority user selector 10 according to the embodiment of the present invention will be described with reference to FIG.
[0124]
The priority user selector 10 determines which user is likely to be error-free based on the received power and the calculated reception response vector H, and performs interference removal at the corresponding stage only on the restoration signal of the user who is likely to be error-free. The control signal is output as follows.
[0125]
In the priority user selector 10, a user who is likely to become an error-free user is selected based on the user's SNR, FD, MSE, and information on a user who has become error-free in the previous frame, or response vector estimation accuracy Select whether it is easy to become an error-free user based on a good user.
[0126]
In order to select a user with good response vector estimation accuracy, a simulation is performed in advance to obtain response vector estimation accuracy corresponding to each condition of SNR, FD, and the degree of interference signal (SIR: signal to interference wave ratio). Then, rank it and keep it in the table. Then, the FD and SIR are detected based on the calculated response vector H, and the SNR is estimated based on the signal from the received power detection unit 9 to select the priority user at the stage. If the estimation accuracy of the response vector is high, the accuracy of the replica signal for removing the interference is improved, so that the accuracy of the signal input to the next stage is increased. As a result, the probability of error-free in the next stage increases.
[0127]
As described above, the table includes each of the received power of the user (SNR: signal to noise ratio), fading speed (FD), MSE, degree of interference signal (SIR: signal to interference wave ratio), etc. It may be configured to hold all the conditions and select the priority user at the stage based on these rankings. However, in consideration of the processing speed, etc., the determination is made according to any of the conditions. Also good.
[0128]
Interference cancellation IC_kThen, the reception response vector H in the calculated frame slot is supplied to the correlation calculation and condition estimation circuit 101 and the memory 102 of the priority user selector 10.
[0129]
The correlation calculation and each condition estimation circuit 101 calculates a correlation value between the reception response vector in the slot of the current frame and the reception response vector in the corresponding slot of the previous frame stored in the memory 102.
[0130]
Note that the correlation value α of the reception response vectors of two frames preceding and following in time is defined by the following equation.
[0131]
α = │h₁h₂ ^H│ / │h₁││h₂│
Where h₂ ^HIs h₂The complex conjugate of each component is taken and further transposed.
[0132]
H_i(I = 1, 2) is a reception response vector (h) having phase amplitude information for each antenna element in frame i as an element.₁₁, H₁₂, H₁₃, H₁₄).
[0133]
Although it is difficult to obtain an exact correspondence between the correlation value calculated in this way and the Doppler frequency (fading speed), an approximate correspondence can be empirically obtained through experiments. For example, if the correlation value is in the range of 1 to 0.95, the Doppler frequency FD is estimated to be FD = 0 Hz. If the correlation value is in the range of 0.95 to 0.80, it is estimated that FD = 10 Hz.
[0134]
Thus, the approximate correspondence between the received response vector correlation value and the Doppler frequency FD obtained empirically is stored in advance in the correlation calculation and each condition estimation circuit 101, and the vectors calculated by the above-described calculation formulas The corresponding Doppler frequency FD is output to the priority user determination unit 104 from the correlation value.
[0135]
The calculation of the received power level (SNR: signal-to-noise ratio) of the user will be described. Since the signal from the reception power detection unit 9 is a composite signal for all users, it must be converted into reception power for each user. For that purpose, the reception response vector H is required.
[0136]
Basically, the sum of the squares of the I component and Q component of the response vector (complex number) of each user is the power of each user, but the absolute magnitude is not known from the magnitude of the response vector. for that reason. Based on the received power from the received power detection unit 9, the received power is distributed to each user's received power.
[0137]
Calculation of the degree of user interference signal (SIR: signal-to-interference wave ratio) will be described. Unlike SNR, SIR does not require absolute received power from received power detector 9, and is calculated by the ratio of received power for each user. Therefore, the received power of each user can be calculated from the response vector of each user by the above-described method, and the ratio between them can be calculated.
SIR = 10 · log_Ten(Desired wave power / interference wave power)
Calculated by
[0138]
In this way, the correlation calculation and each condition estimation circuit 101 performs the reception response vector, the reception response vector correlation value, the magnitude of the received power of the user (SNR: signal to noise ratio), the degree of interference signal (SIR: signal pair). Interference wave ratio) is obtained, and the value is output to the priority user decision unit 104.
[0139]
A simulation is performed in advance, and a response vector corresponding to each condition of the received power of the user (SNR: signal to noise ratio), fading speed (FD), and degree of interference signal (SIR: signal to interference wave ratio) The estimated accuracy is obtained and the ranking is stored in the table memory 103.
[0140]
The memory 102 stores user data that has become error free in the previous frame.
[0141]
When the priority user determination unit 104 selects a priority user with response vector estimation accuracy, the table memory 103 is referred to using the SNR, SIR, and FD given from the correlation calculation and each condition estimation circuit 101 as arguments. Based on the ranking, which user is prioritized is selected and the result is output.
[0142]
When the priority user determination unit 104 selects priority users in descending order of received power, the table memory 103 is referred to using the SNR given from the correlation calculation and each condition estimation circuit 101 as an argument, and these rankings are determined. Based on the above, the user to be prioritized is selected and the result is output.
[0143]
When the priority user determination unit 104 selects a priority user for a user who has become error-free in the previous frame, the correlation calculation and each condition estimation circuit 101 are performed based on the information of the previous frame stored in the memory 102. Select which user is given priority and output the result.
[0144]
In addition, when the priority user determination unit 104 selects a priority user by MSE, the MSE given from the adaptive array is used as an argument, the table memory 103 is referred to, and which user has priority based on the ranking. Is selected and the result is output.
[0145]
As described above, the priority user is selected according to the above conditions (1) to (5). However, the priority user may be selected in consideration of the plurality of conditions. From (1) to (5), the reasons that are likely to be error-free are summarized below.
[0146]
When the SNR is high, the desired signal can be easily extracted, so that it is likely to be error free in the interference removing unit. The SNR can be calculated by the method described above.
[0147]
If there are few errors in the previous frame, there is a high probability that no error will occur even in that frame. Therefore, the error status of the previous frame is stored, and the error status may be confirmed before processing by the interference removal unit.
[0148]
The fact that the FD is small means that a desired signal can be easily extracted and error free at the interference removal unit.
[0149]
The smaller the MSE, the better the extraction of the desired signal.
[0150]
That the estimation accuracy of the response vector is good means that a desired signal has been extracted, and error-free is likely to occur. Also, since interference can be removed with high accuracy, a desired signal can be efficiently extracted even when the next stage is entered.
[0151]
As described above, when the priority user selector 10 selects a priority user with response vector estimation accuracy, the table memory 103 is stored using the SNR, SIR, and FD given from the correlation calculation and each condition estimation circuit 101 as arguments. The priority user is determined based on these rankings, and the result is output to the interference cancellation IC.
[0152]
As described above, the receiving system according to the second embodiment shown in FIG. 7 is different from the receiving system according to the first embodiment shown in FIG. 3 in that two users can perform processing in one stage.
[0153]
Further, the first stage interference canceller arithmetic unit 101 ′ (and the subsequent stage interference canceller arithmetic unit) has a configuration as shown in FIG. 9 instead of the configuration shown in FIG. Yes.
[0154]
In the arithmetic unit 101 ′ shown in FIG. 9, the interference removal unit IC of the previous stage interference canceller, for example, the interference removal unit IC₁₁Received response vector H from₁₁, Error judgment signal E₁₁, And user signal Y₁₁(T) and an interference canceling unit IC₁₂Received response vector H from₁₂, Error determination signal E₁₂And user signal Y₁₂(T) is given.
[0155]
Interference canceller IC of the first stage interference canceller₁₁Received response vector H from₁₁And user signal Y₁₁(T) and multiplier MP₁And the output is AND gate AND₁To the first input. AND gate AND₁In the second input, the interference canceller IC₁₁Error judgment signal E from₁₁Is given.
[0156]
Also, the interference removal unit IC of the first stage interference canceller₁₂Received response vector H from₁₂And user signal Y₁₂(T) and multiplier MP₂And the output is AND gate AND₂To the first input. AND gate AND₂The second input includes an interference canceler IC₁₂Error judgment signal E from₁₂Is given.
[0157]
AND gate AND₁AND gate AND₂Is supplied to the negative input of the adder AD.
[0158]
The positive input of the adder AD has an input signal vector X as in the first embodiment.₁(T) is input.
[0159]
The above is the description of the configuration corresponding to the first priority user selected by the priority user selector 10, but the arithmetic device 101 ′ is similar from the first priority user to the second priority user. Includes configuration.
[0160]
The operation of the receiving system of the second embodiment having the above configuration will be described. Input signal vector X₁The previous stage interference canceling unit IC receiving (t)_{11 ,}IC_{twenty one}Among these, for the user determined as having no error, the received signal vector H, the error determination signal E, and the user signal Y (t) calculated by the interference canceling unit IC are directly used in the first stage interference. It is given to the arithmetic unit 101 'of the canceller. Further, the received signal vector H, the error determination signal E, the user signal Y (t), and the priority signal U calculated by the interference removing unit IC are given to the final output.
[0161]
In other words, a user once determined to have no error by the preceding interference removing unit IC is not given to the subsequent interference removing unit IC.
[0162]
On the other hand, the input signal vector X₁The previous stage interference canceling unit IC receiving (t)_{11 ,}IC_{twenty one}Among these, the user who is determined to have an error is not subjected to interference removal in the first stage interference canceller arithmetic unit 101 ′.
[0163]
In the second stage interference canceller arithmetic unit 102 ′, the input signal vector X output from the preceding stage interference canceller arithmetic unit 101 ′.₂From (t), only the replica signal corresponding to the user determined by the interference canceller IC of the preceding stage (first stage) interference canceller that no demodulation error is included is input signal vector X₂Subtracted from (t).
[0164]
Here, the interference removal unit IC of the previous stage has already been₁₁, IC_{twenty one}For example, the interference canceling unit IC₁₁For the user 1 for which no error has been determined in step 1, the replica signal is already the arithmetic unit 101 'and the initial input signal vector X₁The input signal vector X that has been subtracted from (t) and is given to the adder AD of the arithmetic unit 102 '₂(T) is no longer included.
[0165]
Then, the user signal that was not selected in the first stage is selected and given to the second stage interference cancellation IC by the priority user selector 10.
[0166]
The effect of the second embodiment will be described more specifically. For example, in the case of obtaining the reception signal of the user 3 among the four users, the interference removal unit IC in the previous stage₁₁And IC_{twenty one}When it is determined that there is no error in users 1 and 2, the received signal vector X related to user 3 of the first stage interference canceller₂(T)
Initial input signal-(user 1 replica signal + user 2 replica signal)
It becomes.
[0167]
That is, in the second embodiment, for a user who has already been subtracted from the input signal vector as having no error, it is no longer necessary to redo the subtraction from the input signal vector at a later stage. Therefore, according to the second embodiment, it is possible to greatly reduce the amount of calculation processing.
[0168]
[Embodiment 3]
Incidentally, the embodiment shown in FIGS. 3 to 9 relates to a receiving system of a PDMA base station. In recent years, in addition to this PDMA communication method, a CDMA communication method has been proposed and already put into practical use.
[0169]
In this CDMA communication system, a transmitting side multiplies a digital data symbol to be transmitted by a predetermined spreading code and transmits it as a signal having a much higher frequency, and a receiving side despreads the received signal using the above spreading code. By doing so, data is demodulated.
[0170]
Here, if a plurality of different spreading codes that are not correlated with each other are used, even if a plurality of data signals having the same frequency are spread and transmitted, despreading is performed with the spreading code corresponding to the transmission time. As a result, only the signal of the desired user can be reliably separated and extracted. Therefore, it is possible to further increase the communication capacity by using this CDMA communication system. Since such a CDMA communication system has already been put into practical use and is well known in the art, a detailed description thereof will be omitted.
[0171]
In the embodiment described below, the radio reception system according to the present invention is applied to a CDMA communication system.
[0172]
FIG. 10 is a block diagram showing a main part of a receiving system for a CDMA base station according to Embodiment 3 of the present invention, and FIG. 11 is a specific block diagram of an arithmetic unit.
[0173]
The CDMA receiving system of the third embodiment shown in FIGS. 10 and 11 is the same as the PDMA receiving system of the second embodiment shown in FIGS. 7 to 9 except for the following points.
[0174]
That is, the configuration of the interference removing unit IC of the receiving system of the second embodiment shown in FIG. 7 is changed to the configuration of the third embodiment shown in FIG. The interference canceller shown in FIG. 10 (interference canceler IC as an example_K1′), The despreader IS for despreading the signal transmitted by the CDMA communication method and received by the antennas 3 to 6 is placed before the adaptive array and the parameter estimator._k1Is provided. The received signal despread for each user by the despreader in each interference canceling unit is given to the corresponding adaptive array and parameter estimator, and each user signal is extracted by the same operation as in the second embodiment. Then, it is given to the arithmetic unit of the interference canceller at the subsequent stage.
[0175]
The computing device of the first stage interference canceller is a multiplier MP.₁, MP_k-1Diffuser S₁₁, S₁₂Is the same as the arithmetic unit 101 ′ shown in FIG.
[0176]
That is, the input signal vector X that has been spread by the CDMA communication system.₁In order to perform subtraction from (t), the output of each multiplier is again spread by the corresponding spreading code.
[0177]
Then, the output of each spreader, that is, the output of the arithmetic unit is despread again by the despreader of the corresponding interference removal unit in the subsequent stage, and is provided to the adaptive array and the parameter estimator.
[0178]
The computing device of the second stage interference canceller has the same configuration as the computing device of the first stage. Other operations are the same as those of the second embodiment shown in FIGS.
[0179]
In the above-described embodiment, the error determination is performed by the interference removal IC. However, since a user with a very high probability of being error-free can be preferentially selected, a certain degree of accuracy can be obtained even if the error determination is omitted. It is done.
[0180]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0181]
【The invention's effect】
As described above, according to the present invention, it is possible to select a user who is likely to be error-free for the first user and efficiently eliminate interference, so that the processing speed can be improved and the hardware having a high processing speed can be obtained. The interference user signal component extracted by the signal extraction means corresponding to the user can be removed from the input signal vector by the interference removal means without improving the communication quality in a radio communication system such as a mobile communication system. Can be planned. Moreover, since the scale can be reduced, the cost performance is excellent.
[0182]
[Brief description of the drawings]
FIG. 1 is a block diagram of a receiving system for a PDMA base station as a premise of the present invention.
FIG. 2 is a block diagram showing a configuration of the arithmetic device shown in FIG.
FIG. 3 is a block diagram of a receiving system for a PDMA base station according to Embodiment 1 of the present invention;
FIG. 4 is a block diagram showing a configuration of an interference canceller according to Embodiment 1 of the present invention.
5 is a block diagram showing a configuration of the arithmetic device shown in FIG. 3. FIG.
FIG. 6 is a flowchart for explaining the operation of the first embodiment of the present invention.
FIG. 7 is a block diagram of a receiving system for a PDMA base station according to Embodiment 2 of the present invention;
FIG. 8 is a block diagram showing a configuration of a priority user selector according to the embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of the arithmetic device shown in FIG. 7;
FIG. 10 is a block diagram showing a configuration of an interference canceller of a CDMA base station reception system according to Embodiment 3 of the present invention;
FIG. 11 is a block diagram showing a configuration of an arithmetic unit of a receiving system of a CDMA base station according to Embodiment 3 of the present invention.
FIG. 12 is a channel arrangement diagram of user signals in FDMA, TDMA, and PDMA communication systems.
FIG. 13 is a block diagram showing a conventional PDMA base station reception system.
[Explanation of symbols]
1, 2 users, 3 to 6 antennas, 7 frequency conversion circuit, 8 A / D converter, 10 priority user selector AA adaptive array.

Claims (6)

A wireless reception system capable of receiving signals from a plurality of users using a plurality of antennas,
Signal processing means for performing predetermined signal processing on signals received by the plurality of antennas;
Selection means for selecting a user to be preferentially processed based on a signal of a previous frame received by the plurality of antennas;
First signal extraction means for extracting a signal component corresponding to the selected user based on a signal output from the signal processing means;
First estimation means for estimating parameter information related to the relationship of the signal components extracted by the first signal extraction means with respect to the signal output from the signal processing means;
A wireless reception system comprising: first calculation means for subtracting a signal output from the signal processing means by a signal considering the parameter information corresponding to the selected user.  2. The wireless reception system according to claim 1, wherein each of the means is configured by a number smaller than the number of antennas. The selection means is a signal of a user whose reception power was high in the previous frame, a signal of a user who became error-free in the previous frame, a signal of a user whose fading was small in the previous frame, or 2. The user is selected based on either a user signal having a small array processing error in a previous frame or a user signal having a high response vector estimation accuracy in a previous frame. Or the radio | wireless receiving system of 2. A plurality of first error determination means for determining whether or not signal components corresponding to a plurality of users extracted by the first signal extraction means each include a demodulation error;
Further comprising
A first calculation for subtracting the extracted signal component determined not to include a demodulation error by the first error determination unit from the signal output from the signal processing unit in consideration of the corresponding parameter information The wireless receiving system according to claim 1, further comprising: means.  5. The radio reception system according to claim 1, wherein the signals from the plurality of users are signals transmitted by a PDMA communication system.  5. The radio reception system according to claim 1, wherein the signals from the plurality of users are signals transmitted by a CDMA communication system.

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