JP3700831B2 - Clock supply method and circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock supply method and circuit, and more particularly, to a method and circuit for supplying a clock signal to a clock terminal such as a data latch unit that inserts a damping resistor in a clock line at a predetermined timing to prevent noise.
[0002]
[Prior art]
In a digital circuit such as a data latch unit (or latch circuit), a clock signal is indispensable as a reference for circuit operation, and such a clock signal is generated and supplied by a crystal oscillator or the like. A conventional clock supply circuit for generating such a clock signal and related techniques are disclosed in, for example, “Clock transmission control circuit” in Japanese Patent Laid-Open No. 11-95857, “Bit synchronization circuit” in Japanese Patent Laid-Open No. 10-247903, and Japanese Patent Laid-Open No. Disclosed in “Phase Adjuster” of Japanese Patent No. -48414.
[0003]
FIG. 5 shows an example of a conventional digital circuit using a clock signal. This digital circuit includes a data latch unit 100, and digital data is input from the data input terminal 101 to the data terminal of the data latch unit 100 via the buffer circuit 102. On the other hand, the clock signal is generated by the oscillator 103 which is a crystal oscillation circuit, for example, and is input to the clock terminal of the data latch unit 100 via the clock line 105. With such a configuration, digital data input from the data input terminal 101 is latched by the data latch unit 100 by the clock signal generated by the oscillator 103.
[0004]
As shown in FIG. 5, when the clock signal input at the time of data latching is in a state where the noise is not so great as to affect the operation thereof, noise countermeasures have not been taken on the clock line 105, that is, an oscillator. The clock signal output from 103 is directly input to the clock terminal of the data latch unit 100. Further, as a countermeasure for clock signal processing when overshoot and undershoot are conspicuous and countermeasures against reflected waves of the clock signal, generally, a damping resistor 104 is inserted in series with the clock line 105 to “smooth” the waveform. . In consideration of the delay of the “smoothed” clock signal in this way, by inserting a delay element such as the buffer 102 in the data line, the timing of the data and the clock signal in the data latch unit 100 is matched, The data latch unit 100 performs data latching.
[0005]
[Problems to be solved by the invention]
In the conventional clock supply circuit as shown in FIG. 5, the frequency component may be a problem during EMI evaluation, particularly when evaluating radiated noise, particularly when no noise countermeasure is taken in the clock unit. Therefore, it is necessary to take measures such as adding a damping resistor 104 to the clock line 105. In addition, it is necessary to measure the delay amount of the clock signal in association with such noise countermeasures, and to add a delay element such as the buffer 102 to the data line and to determine the resistance value of the damping resistor 104 according to the degree of noise. there were.
[0006]
OBJECT OF THE INVENTION
Accordingly, an object of the present invention is to bring the change point of the data latch timing by “smoothing” the clock waveform by noise countermeasures or the like closer to the design value data and the clock latch timing without changing the data line. It is to provide a clock supply method and circuit.
[0007]
[Means for Solving the Problems]
In order to solve the above-described conventional problems, the clock supply method according to the present invention latches the data input to the data input terminal of the data latch unit so that the clock signal generated by the oscillator is latched via the damping resistor. A step of converting the clock signal generated by the oscillator into a plurality of phase-advanced clock signals, the optimum clock signal being selected from the phase-advanced clock signal, and the damping. comprising the step of outputting the resistance. In a preferred embodiment, the selection control signal for the advanced clock signal is obtained by comparing the clock signals on the input and output sides of the damping resistor.
[0008]
In addition, the clock supply circuit of the present invention latches data input to the data input terminal of the data latch unit, and thus supplies a clock signal generated by the oscillator to the clock terminal of the data latch unit via the damping resistor. A phase change clock output unit that converts a clock from the oscillator into a plurality of advanced phase clock signals between the oscillator and the damping resistor, a clock selection unit that selects an output of the phase change clock output unit, and a damping resistor A delay detection unit including a plurality of delay determination units that compare the clock signals at both ends and generate a selection control signal of the clock selection unit. According to a preferred embodiment, the delay determination unit is configured by a D-type flip-flop in which the output of the damping resistor and the input side clock signal are input to the input terminal D and the clock terminal C, respectively. In addition, a plurality of data latch units are provided, and a clock selection unit, a delay detection unit, and a damping resistor are individually provided for each data latch unit, and an oscillator and a phase change clock output unit are shared.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the above-described clock supply method and circuit according to the present invention will be described in detail.
[0010]
First, FIG. 1 is a block diagram of a digital circuit including a first embodiment of a clock supply circuit according to the present invention. The specific example shown in FIG. 1 includes a data latch unit 4 to which data and a clock signal are input. Data to the data latch unit 4 is directly input from the data input terminal 5 through the data line 6. On the other hand, the clock signal to the crack terminal of the data latch unit 4 is generated by the oscillator 1 and supplied via the clock supply circuit 2 and the damping resistor 3.
[0011]
The clock supply circuit 2 selects and controls the phase change clock output unit 2A to which the output clock signal of the oscillator 1 is input, and the clock selection unit 2B and the clock selection unit 2B connected to the output side of the phase change clock output unit 2A. The delay detection unit 2C includes a plurality of delay determination units 2D. As will be described later, the clock signals at both ends of the damping resistor 3 are input to each delay determination unit 2D constituting the delay detection unit 2C. The latch output of the data latch unit 4 is output from the output terminal 7.
[0012]
Next, the operation of the embodiment shown in FIG. 1 will be described. The oscillator 1 supplies the clock supply circuit 2 with a clock signal a that is the source of the data latch clock. The phase change clock output unit 2A of the clock supply circuit 2 is shifted in phase forward (ie, the phase is advanced) with respect to the clock signal a input from the oscillator 1 at an arbitrary time from the rising change point. Several phase advance clock signals b1, b2,..., Bn are output to the clock selection unit 2B. Therefore, the clock selection unit 2B has one phase advance based on the selection signal e output from the delay detection unit 2C from several phase advance clock signals b1, b2,..., Bn input from the phase change clock output unit 2A. The clock signal c is selected and output. The delay detection unit 2C receives two clock signals, that is, a phase advance clock signal c output from the clock selection unit 2B and an output clock signal d of the noise reduction damping resistor 3. Each delay determination unit 2D of the delay detection unit 2C compares the clock signal delayed in advance with respect to the advanced clock signal c directly input from the clock selection unit 2B and the output clock signal d of the damping resistor 3. The comparison result by the delay determination unit 2D is output to the clock selection unit 2B as a selection control signal e.
[0013]
Next, FIG. 2 shows a specific configuration of a plurality of delay discriminating units 2D constituting the delay detecting unit 2C in FIG. In the specific example illustrated in FIG. 2, the delay determination unit 2 </ b> D includes a D flip-flop circuit (DF / F) 20. The output side clock signal d1 of the damping resistor 3 in FIG. 1 is directly input from the input terminal 21 to the input terminal D of the DF / F 20. On the other hand, the input side clock signal c1 of the damping resistor 3 in FIG. 1 is input from the clock input terminal 22 through the resistor 23 to the clock terminal C of the DF / F 20. A selection control signal e1 which is one of the selection control signals e shown in FIG. 1 is output from the output terminal 24 connected to the output terminal Q of the DF / F 20. As shown in FIG. 1, switching control of the clock selection unit 2B is performed by m selection control signals e1 to em of a plurality (m) of delay determination units 2D.
[0014]
The operation of the embodiment of the clock supply circuit 2 shown in FIG. 1 will be described below with reference to the timing chart of FIG. 3A shows an output clock signal a from the oscillator 1. FIG. (B1), (b2), (b3),..., (Bn) respectively indicate a plurality of advanced phase clock signals b1, b2, b3,..., Bn from the phase change clock output unit 2A. (C1) is an input clock signal c1 to the clock input terminal 22 of the DF / F 20 shown in FIG. (D1) is a clock signal (or an output side clock signal of the damping resistor 3 in FIG. 1) d1 inputted to the input terminal 21 of the DF / F 20 in FIG. (E) is output from the DF / F 20 of FIG. 2 (or a selection control signal input from the first delay determination unit (1) of the delay determination unit 2D of FIG. 1 to the clock selection unit 2B) e. is there. (C2) and (d2) are the clock signals on the input side and output side of the damping resistor 3, respectively, output from the clock selection unit 2B. (F) is data f inputted to the data latch unit 4 from the data input terminal 5 of FIG. Finally, (g) is output data output from the data latch unit 4 of FIG.
[0015]
As apparent from the timing chart of FIG. 3, the clock signal (a) that is the basis of the latch clock signal output from the oscillator 1 is input to the phase change clock output unit 2 </ b> A in the clock supply circuit 2. The phase change clock output unit 2A generates n phase-advanced clock signals (b1) to (bn) whose rising change points are out of phase by an arbitrary time before the input clock signal (a). To the clock selection unit 2B. The clock selection unit 2B outputs (b1) as an output clock signal (c1) as an initial state from the input advanced clock signals (b1) to (bn). The clock signal (c1) is output to the clock terminal of the data latch unit 4 as the normal data latch clock signal (d). However, the rising time of the clock signal (c1) is changed (“smoothed”) by the noise reducing damping resistor 3, and a substantially trapezoidal waveform is obtained as shown in FIG. These two clock signals (c1) and (d1) are input to the delay detector 2C.
[0016]
Next, in the delay detection unit 2C, the clock signal (c1) is input to the m delay determination units 2D that perform comparison with the m clock signals delayed every arbitrary time. Compare with clock (d1). Each of the m delay determination units 2D outputs a determination result signal (e), decodes the determination result signal (e), and outputs it as a selection signal to the clock selection unit 2B. As a result, the clock selection unit 2B selects an arbitrary clock (c2) corresponding to the delay time of the clock signal (d1) with respect to the clock signal (c1) as an output clock and outputs it to the damping resistor 3. The clock signal (d2) output via the damping resistor 3 with respect to the clock signal (c2) is data at substantially the same timing as the clock signal (c1) which is the data latch timing at the time of design before the insertion of the damping resistor 3. Latching is performed.
[0017]
Next, FIG. 4 is a block diagram of a second embodiment of the clock supply circuit according to the present invention. For convenience of explanation, the same reference numerals are used for the components corresponding to the first embodiment shown in FIG. In the first embodiment shown in FIG. 1, the number of data latch units 4 is one. However, the number of data latch units 4 is not limited to one and may be plural. The second embodiment shown in FIG. 4 is an embodiment where the data latch unit is included in two devices (devices A and B). In such a case, each device (A and B) includes not only the data latch unit but also the damping resistor 3 and the delay detection unit 2C. In the clock supply circuit 2, an oscillator 1, a phase change clock output unit 2A, and a plurality (two in this case) of clock selection units 2B are provided for the devices A and B. In other words, the oscillator 1 and the phase change clock output unit 2A are shared, and the clock selection unit 2B, the delay detection unit 2C, and the damping resistor 3 are individually provided for the data latch unit 4.
[0018]
The operation of the second embodiment shown in FIG. 4 is the same as that of the first embodiment described above with reference to basic FIGS. For the device A, the clock signal of the data latch unit 4 is generated by the oscillator 1 of the clock supply circuit 2, the phase change clock output unit 2A, the one clock selection unit 2B, and the damping resistor 3 and the delay detection unit 2C in the device A. Then, the data input from the data input terminal 5 is latched by the data latch unit 4 and output from the output terminal 7. Similarly, for the device B, the oscillator 1 of the clock supply circuit 2, the phase change clock output unit 2A, the other clock selection unit 2B, the damping resistor 3 and the delay detection unit 2C in the device B, and the clock of the data latch unit 4 are used. Generate a signal. For example, data input from a data input terminal (not shown) is latched.
[0019]
As shown in FIG. 4, even when the clock supply circuit 2 and the data latch unit span between a plurality of devices, the delay detection unit and the damping resistor of the clock supply circuit are individually provided for each of the devices A and B, and each device A , B, the clock signal is generated at the optimum timing that matches the impedance of the clock line, so that the data latch timing as designed can be realized.
[0020]
The configuration and operation of the preferred embodiment of the clock supply circuit according to the present invention have been described in detail above. However, such an embodiment is merely an example of the present invention and does not limit the present invention. Those skilled in the art can easily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.
[0021]
【The invention's effect】
As understood from the above description, according to the clock supply method and circuit of the present invention, the following remarkable effects can be obtained in practical use. First of all, it is possible to generate a clock signal and latch data at an optimum timing according to a design value without revising the clock timing by taking noise reduction measures (inserting a damping resistor in the clock line). it can. Second, since the latch timing can be maintained without adding a delay element or the like to the data line, the hardware configuration becomes small and inexpensive.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of a clock supply circuit according to the present invention;
FIG. 2 is a specific block diagram of a delay discriminating unit constituting the clock supply circuit of FIG.
FIG. 3 is a timing chart for explaining the operation of the clock supply circuit shown in FIG. 1;
FIG. 4 is a block diagram showing a configuration of a second embodiment of a clock supply circuit according to the present invention.
FIG. 5 is a block diagram showing a configuration of a conventional clock supply circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Oscillator 2 Clock supply circuit 2A Phase change clock output part 2B Clock selection part 2C Delay detection part 2D Delay determination part 3 Damping resistor 4 Data latch part 5 Data input terminal 7 Output terminal

Claims (5)

In a clock supply method for latching data input to a data input terminal of a data latch unit, a clock signal generated by an oscillator is supplied to a clock terminal of the data latch unit via a damping resistor.
A step of converting the phase of the clock signal generated by the oscillator into a plurality of phase-advanced clock signals, and a step of selecting an optimum clock signal from the phase-advanced clock signal and outputting the selected signal to the damping resistor. A clock supply method characterized by the above.   2. The clock supply method according to claim 1, wherein the selection control signal of the phase advance clock signal is obtained by comparing clock signals on the input / output side of the damping resistor. In the clock supply circuit for latching the data input to the data input terminal of the data latch unit, the clock signal generated by the oscillator is supplied to the clock terminal of the data latch unit via a damping resistor.
A phase change clock output unit that converts a clock signal from the oscillator into a plurality of advanced phase clock signals between the oscillator and the damping resistor; a clock selection unit that selects an output of the phase change clock signal output unit; and the damping clock supply circuit, characterized in that it comprises a delay detection unit for comparing the both ends of the clock signal of the resistor having a plurality of delay Determination unit for generating a selection control signal of the clock selection section. The delay Determination unit, a clock according to claim 3, characterized in that it is composed of a D-type flip-flop output and an input-side clock signal of each of said damping resistor is input to the input terminal D and a clock terminal C Supply circuit.   A plurality of the data latch units are provided, the clock selection unit, the delay detection unit, and the damping resistor are individually provided for the plurality of data latch units, and the oscillator and the phase change clock output unit are shared. The clock supply circuit according to claim 3 or 4, characterized by the above-mentioned.

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