JP3691144B2 - Scan campus configuration circuit - Google Patents

Description

【００５６】
まず通常動作について説明を行う。通常動作時にはテスト制御信号ＴＥＳＴを“０”とする。テスト制御信号ＴＥＳＴが“０”のとき、セレクタ５，６はデータ入力０端子に入力されるデータを出力するので、保持制御信号ＨＬＤ０がテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとして入力側及び出力側のテスト回路ＴＣに与えられる。このとき、保持制御信号ＨＬＤ０が“０”ならば、入力側では入力データＩＮが入力側の接続回路ＣＣを介してデータ回路１の入力端子ＤＩに取り込まれる。出力側では出力データＤＯが出力側の接続回路ＣＣを介してデータ出力端子ＯＵＴに出力される。保持制御信号ＨＬＤ０が“１”ならば、入力データＩＮ及び出力データＤＯは接続回路ＣＣにおいてそれぞれ保持される。
【００５７】
次にスキャンテスト動作について説明する。スキャンテスト時には、テストパターンのシフトイン、実行、テスト結果のシフトアウトを順に行う。スキャンテスト時にはテスト制御信号ＴＥＳＴを“１”とする。テスト制御信号ＴＥＳＴが“１”のとき、シフトモード制御信号ＳＭの反転論理及びシフトモード制御信号ＳＭがそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとして、入力側及び出力側のテスト回路ＴＣに与えられる。
【００５８】
１．テストパターンのシフトイン
データ回路１にテストパターンを入力する準備として、入力側の接続回路ＣＣにテストパターンをシフトインする。シフトモード制御信号ＳＭを“１”とすると、データ回路１に入力するテストパターンをスキャンイン端子ＳＩからシフトインすることが可能である。本実施の形態のデータ回路１は４ビットであるので、４ビットのテストパターンがシフトインされる。テストパターンは入力側の接続回路ＣＣ［０］→ＣＣ［１］→ＣＣ［２］→ＣＣ［３］の順でシフトされ、入力側の接続回路ＣＣ［０］〜［３］にテストパターンが入力される。シフトモード制御信号ＳＭによって入力側及び出力側のテスト回路ＴＣは同時に制御されるので、出力側の接続回路ＣＣ［０］〜ＣＣ［３］においてもデータのシフトが起こる。
【００５９】
２．実行
シフトモード制御信号ＳＭを“０”とする。このとき、入力側あるいは出力側のそれぞれの接続回路ＣＣを介して、入力データＩＮが入力端子ＤＩに取り込まれ、データ回路１のテスト結果である出力データＤＯはデータ出力端子ＯＵＴに出力される。
【００６０】
３．テスト結果のシフトアウト
シフトモード制御信号ＳＭを“１”とする。このときテスト結果を順にスキャンアウト端子ＳＯからシフトアウトする。
【００６１】
以上が図１に示される回路の回路動作である。図２に示されるセレクタ２，３のデータ入力０端子とデータ入力１端子をそれぞれ入れ替え、かつセレクタ２，３のそれぞれの制御端子に入力されるテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍの“０”と”１”をそれぞれ入れ換えても、本発明の試験回路の回路動作は変わらない。
【００６２】
図１に示される制御回路ＣＴＬ１を用いると、以下に記す利点が生ずる。
【００６３】
図４はデータ回路１，１ａ及び１ｂの入力側及び出力側においてテスト回路ＴＣがそれぞれ設けられスキャンパスが構成される回路を示す回路図である。データ回路１ａ及び１ｂは論理回路であり、データ回路１は図示されない制御回路ＣＴＬ１によって制御される。データ回路１の入力側及び出力側のＴＣに入力される保持制御信号ＨＬＤ０はデータ回路１ａから出力される。
データ回路１ａ，１及び１ｂが順に並べられ、スキャンパスは、スキャンイン端子ＳＩ→データ回路１ａの入力側のテスト回路ＴＣ→データ回路１ａの出力側のテスト回路ＴＣ→データ回路１の入力側のテスト回路ＴＣ→データ回路１出力側のテスト回路ＴＣ→データ回路１ｂの入力側のテスト回路ＴＣ→データ回路１ｂの出力側のテスト回路ＴＣ→スキャンアウト端子ＳＯ、のように構成されている。
【００６４】
上述のように、図４に示される回路においては保持制御信号ＨＬＤ０がデータ回路１ａからデータ回路１の入力側及び出力側のテスト回路ＴＣにそれぞれ与えられる。制御回路ＣＴＬ１においては、テスト制御信号ＴＥＳＴによって保持端子ＨＬＤ０とシフトモード端子ＳＭのどちらが選択されるかが制御される。従って、データ回路１の入力側及び出力側のテスト回路ＴＣを制御回路ＣＴＬ１によって制御することによって、データ回路１のスキャンテストをデータ回路１ａから与えられる保持制御信号ＨＬＤ０とは独立に行うことができ、テストパターンの生成が単純となる。
【００６５】
図５に示されるように、スキャンイン端子ＳＩをスキャンフリップフロップＨＳＦＦを介して入力側のテスト回路ＴＣのスキャンイン端子ｓｉに接続することも可能である。
【００６６】
図６はスキャンフリップフロップＨＳＦＦを示す回路図である。スキャンフリップフロップＨＳＦＦはセレクタ１４及びフリップフロップ１５から成る回路である。テスト回路ＴＣを制御する制御回路に入力される保持制御信号ＨＬＤを確認するためにスキャンフリップフロップＨＦＳＳは設けられる。保持制御信号ＨＬＤは保持制御信号ＨＬＤ０を含む信号である。セレクタ１４はデータ入力０端子及びデータ入力１端子、出力端子ならびに制御端子を有する。制御端子にはセレクタ１４を切替えるためのシフトモード制御信号ＳＭが入力される。データ入力０端子はシフトモード制御信号ＳＭが“０”のときに選択され出力端子に接続される。一方、データ入力１端子はシフトモード制御信号ＳＭが“１”のときに選択され出力端子に接続される。よって、セレクタ１４に入力されるシフトモード制御信号ＳＭの“１”，“０”を切替えることによって、セレクタ１４から出力されるデータを選択することが可能となる。セレクタ１４のデータ入力１端子にはスキャンイン端子ＳＩが接続され、データ入力０端子には保持端子ＨＬＤが接続される。セレクタ１４の出力端子はフリップフロップ１５の入力端子に接続される。フリップフロップ１５の出力端子はスキャンフリップフロップＨＳＦＦのスキャンアウト端子ＳＯとなる。フリップフロップ１５はＤフリップフロップあるいはＤフリップフロップと同様の働きを有するフリップフロップである。
【００６７】
保持制御信号ＨＬＤは制御回路に入力される信号である。制御回路に入力される保持制御信号ＨＬＤはテスト回路ＴＣの制御を行う信号であり、詳しくはテスト回路ＴＣに含まれるセレクタ２の接続を切り換えるための信号であるので、保持制御信号ＨＬＤ自体が出力データとしてデータ回路１から、あるいはスキャンパスから出力されることはない。従って、スキャンフリップフロップＨＳＦＦを設けない場合には直接的に保持制御信号ＨＬＤを観察することは困難である。保持制御信号ＨＬＤが所望の論理をとらないならば、保持制御信号ＨＬＤによって制御されるテスト回路ＴＣは所望の動作を行わず、論理回路の動作試験を信頼することは不可能となる。従って、保持制御信号ＨＬＤを直接観察する必要が生ずる。スキャンフリップフロップＨＳＦＦを用いることによって、保持制御信号ＨＬＤを直接観察することが可能となる。
【００６８】
スキャンフリップフロップＨＳＦＦのデータ入力０端子に保持制御信号ＨＬＤを入力し、シフトモード制御信号ＳＭを“０”とすることによって、フリップフロップ１５に保持制御信号ＨＬＤの値を記憶させることが可能となる。前述の通り、セレクタ１４はシフトモード制御信号ＳＭによって制御される。しかし、テスト回路ＴＣの制御に関係しない制御端子を新たに設け、この制御端子から出力される制御信号によってセレクタ１４を制御することも可能である。
【００６９】
スキャンフリップフロップＨＳＦＦのフリップフロップ１５に記憶された値を観察する方法について説明する。図５において、スキャンフリップフロップＨＳＦＦのセレクタ１４のデータ入力０端子に入力される保持制御信号ＨＬＤは保持制御信号ＨＬＤ０である。図５に示される構成では、スキャンフリップフロップＨＦＳＳに保持されたデータが入力側のテスト回路ＴＣのスキャンイン端子ｓｉに入力されるので、保持制御信号ＨＬＤ０をスキャンパスからスキャンアウトデータＳＯとして取りだした後に観察することが可能となる。
【００７０】
図５においてスキャンフリップフロップＨＳＦＦはスキャンイン端子ＳＩと入力側のテスト回路ＴＣのスキャンイン端子ｓｉとの間に挿入されるが、入力側のテスト回路ＴＣのスキャンアウト端子ｓｏと出力側のテスト回路ＴＣのスキャンイン端子ｓｉとの間に挿入されても同じ作用が得られ、保持制御信号ＨＬＤの観察が可能となる。また、出力側のテスト回路ＴＣのスキャンアウト端子ｓｏとスキャンアウト端子ＳＯとの間に挿入されても同じ作用が得られる。
【００７１】
以上の記述から明らかなように、スキャンフリップフロップＨＦＳＳはデータ回路１の動作試験のために直接必要となるものではない。以後、本実施の形態及び他の実施の形態において、特に必要とされない限りスキャンフリップフロップＨＳＦＦは図示及び説明を省略されるものとする。
【００７２】
次に、本実施の形態に従う別の制御回路についての説明を行う。図７は図１にて示される制御回路ＣＴＬ１の代わりに用いられる制御回路ＣＴＬ２を示す回路図である。
【００７３】
制御回路ＣＴＬ２について説明を行う。制御回路ＣＴＬ２はシフトモード制御信号ＳＭ及び保持制御信号ＨＬＤ０を入力され、テスト回路ＴＣにテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを出力する回路である。
【００７４】
制御回路ＣＴＬ２は、シフトモード制御信号ＳＭが“０”のとき、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとして保持制御信号ＨＬＤ０を出力する。シフトモード制御信号ＳＭが“１”のとき、テスト保持制御信号ｔｈｌｄとして“０”を、シフトモード制御信号ｓｍとして“１”を制御回路ＣＴＬ２は出力する。
【００７５】
制御回路ＣＴＬ２の構成について図７に基づき説明を行う。制御回路ＣＴＬ２は二つのゲートを用いて構成可能である。それぞれのゲートは二つの入力端子と一つの出力端子を有する。一方のゲートはゲート２０であり、他方のゲートはＯＲゲート２１である。ゲート２０は反転入力端子ｒｅに入力される入力信号ｒｅの反転論理と入力端子ｇｅに入力される入力信号ｇｅとの論理積を取るゲートである。ＯＲゲート２１はＯＲゲート２１に入力される二つの入力信号の論理和を取るゲートである。
【００７６】
制御回路ＣＴＬ２の接続状態について説明を行う。保持端子ＨＬＤ０はゲート２０の入力端子ｇｅ及びＯＲゲート２１の一方の入力端子に共通に接続される。シフトモード端子ＳＭはゲート２０の反転入力端子ｒｅ及びＯＲゲート２１の他方の入力端子に共通に接続される。ゲート２０の出力端子はテスト回路ＴＣにテスト保持制御信号ｔｈｌｄを出力し、ＯＲゲート２１の出力端子はテスト回路ＴＣにシフトモード制御信号ｓｍを出力する。制御回路ＣＴＬ１と異なる点とは、制御回路ＣＴＬ２にはテスト端子ＴＥＳＴが備えられないことである。
【００７７】
図７に示される制御回路の回路動作を以下にまとめる。回路動作としては、通常動作の制御及びスキャンテスト動作の制御が存在する。通常動作及びスキャンテストにおける制御回路ＣＴＬ２に関するそれぞれの信号及びデータの最適な設定値を表２に示す。
【００７８】
【表２】

【００７９】
まず通常動作について説明を行う。通常動作時にはシフトモード制御信号ＳＭを“０”とする。シフトモード制御信号ＳＭが“０”のとき、ゲート２０及びＯＲゲート２１は、保持制御信号ＨＬＤ０の論理をテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとして入力側及び出力側のテスト回路ＴＣに与える。このとき、保持制御信号ＨＬＤ０が“０”ならば入力側では入力データＩＮが入力側の接続回路ＣＣを介してデータ回路１の入力端子ＤＩに取り込まれる。出力側では出力データＤＯが出力側の接続回路ＣＣを介してデータ出力端子ＯＵＴに出力される。保持制御信号ＨＬＤ０が“１”ならば、入力データＩＮ及び出力データＤＯは接続回路ＣＣにおいてそれぞれ保持される。
【００８０】
次にスキャンテスト動作について説明する。スキャンテスト時には、テストパターンのシフトイン、実行、テスト結果のシフトアウトを順に行う。
【００８１】
１．テストパターンのシフトイン
シフトモード制御信号ＳＭを“１”とすると、データ回路１に入力するテストパターンをスキャンイン端子ＳＩからシフトインすることが可能である。
【００８２】
２．実行
シフトモード制御信号ＳＭを“０”とする。シフトモード制御信号ＳＭが“０”なので、回路動作は通常動作と等しい。このとき、入力側あるいは出力側のそれぞれの接続回路ＣＣを介して、入力データＩＮが入力端子ＤＩに取り込まれ、データ回路１のテスト結果である出力データＤＯはデータ出力端子ＯＵＴに出力される。
【００８３】
３．テスト結果のシフトアウト
シフトモード制御信号ＳＭを“１”とする。このときテスト結果を順にスキャンアウト端子ＳＯからシフトアウトする。
【００８４】
以上が図７に示される回路の回路動作である。
【００８５】
図７に示される制御回路ＣＴＬ２を、図９に示されるＣＴＬ２ａと交換しても同一の回路動作が得られる。制御回路ＣＴＬ２ａについて説明を行う。制御回路ＣＴＬ２と同様に、制御回路ＣＴＬ２ａはシフトモード制御信号ＳＭ及び保持制御信号ＨＬＤ０を入力され、テスト回路ＴＣにテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを出力する回路である。
【００８６】
制御回路ＣＴＬ２ａは、シフトモード制御信号ＳＭが“０”のとき、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとして保持制御信号ＨＬＤ０を出力する。シフトモード制御信号ＳＭが“１”のとき、テスト保持制御信号ｔｈｌｄとして“０”を、シフトモード制御信号ｓｍとして“１”を制御回路ＣＴＬ２ａは出力する。
【００８７】
制御回路ＣＴＬ２ａの構成について図９に基づき説明を行う。制御回路ＣＴＬ２ａは二つのゲートを用いて構成可能である。それぞれのゲートは二つの入力端子と一つの出力端子を有する。一方のゲートはゲート２０ａであり、他方のゲートはＯＲゲート２１ａである。ゲート２０ａ及びＯＲゲート２１ａはそれぞれゲート２０及びＯＲゲート２１と同一の構成及び働きを有するゲートである。
【００８８】
制御回路ＣＴＬ２ａの接続状態について説明を行う。保持端子ＨＬＤ０はゲート２０ａの入力端子ｇｅに接続される。シフトモード端子ＳＭはゲート２０ａの反転入力端子ｒｅ及びＯＲゲート２１ａの一方の入力端子に共通に接続される。ゲート２０ａの出力端子はテスト回路ＴＣのテスト保持端子ｔｈｌｄ及びゲート２１ａの他方の入力端子に共通に接続される。ＯＲゲート２１ａの出力端子はテスト回路ＴＣのシフトモード端子ｓｍに接続される。
【００８９】
テスト制御信号ＴＥＳＴを受けない制御回路ＣＴＬ２及び２ａを用いると、図４に示される回路において、データ回路１のスキャンテストをデータ回路１ａから与えられる保持制御信号ＨＬＤ０とは独立に行うことが不可能となる。しかし、制御回路ＣＴＬ１においてはセレクタ５，６という二つのセレクタが用いられている。二入力のセレクタは図８に示されるように、三つのゲートによって構成される。三つのゲートのうち、一つはＡＮＤゲートＧ１であり、一つはＯＲゲートＧ２であり、残る一つは反転入力端子ｒｅ及び入力端子ｇｅを有するゲートＧ３である。従って、セレクタ５，６をゲート２０及びＯＲゲート２１という二つのゲートに交換することによって、回路面積が縮小される。
【００９０】
実施の形態２．
本実施の形態においては、試験結果を保持して圧縮する機能が付加される、論理回路の試験回路を示す。また、本実施の形態においては、論理回路の動作試験時にデータの保持を可能とする制御回路を示す。さらに、本実施の形態においては、入力側の試験回路と出力側の試験回路とを独立に制御する試験回路を示す。
【００９１】
図１０は論理回路及び本実施の形態に従う試験回路を示す回路図である。実施の形態１にて示された回路等と同一の構成、働き等を有するものに対しては同一の参照符号を付け、説明は省略するものとする。
【００９２】
同図に示されるとおり、データ回路１はテスト回路ＴＣによって入力の制御が行われ、テスト回路ＣＴＣによって出力の制御が行われる。
【００９３】
テスト回路ＣＴＣについて説明を行う。テスト回路ＣＴＣはデータ出力端子ＯＵＴとデータ回路１の出力端子ＤＯとの間に挿入される。テスト回路ＣＴＣは、テスト回路ＴＣと同様に入力端子ｄ［０］〜［３］、出力端子ｑ［０］〜［３］、スキャンイン端子ｓｉ、テスト保持端子ｔｈｌｄ、シフトモード端子ｓｍ及び、スキャンアウト端子ｓｏを備え、さらに期待データ端子ｅｘｐ及び比較端子ｃｍｐｅｎを備える回路である。テスト回路ＣＴＣは、実際にデータ回路１がテストパターンに対して出力するデータＤＯと期待データとＥＸＰを比較する機能を有し、さらに比較結果を保持してテスト結果を圧縮する機能を有する。ここで期待データＥＸＰとは、正常に動作するデータ回路１がデータ回路１に入力されるテストパターンに対して固有に出力する出力データパターンのことである。期待データＥＸＰは期待データ端子ｅｘｐに入力される。
【００９４】
ここでテスト結果の圧縮について説明する。テスト開始前に、テスト回路ＣＴＣにおいて“０”が保持されないように設定しておく。比較されるデータが一致しないとテスト回路ＣＴＣにおいて一度も判定されなければ、テスト回路ＣＴＣ内にて“０”は保持されない。テスト回路ＣＴＣにおいて比較されるデータが一致しないと一度でも判定されたならば、テスト回路ＣＴＣ内にて“０”が保持される。一旦“０”が保持されると、“０”が続いて保持される。以上がテスト結果の圧縮である。
【００９５】
また、圧縮テストとはテスト結果の圧縮を利用する試験を表す。テスト終了後にテスト回路ＣＴＣ内に“０”が保持されていないことが確認されたならば、全ての期待される出力データと同一のデータをデータ回路１が出力したことが観察され、データ回路１が正常に動作したことが確認される。テスト回路ＣＴＣ内に“０”が保持されていることが確認されたならば、データ回路１が期待される出力データとは異なるデータを少なくとも一度は出力したことが観察され、データ回路１が正常に動作しなかったことが確認される。従って、テストパターンをデータ回路１に入力する度にテスト結果を観察する必要がなくなる。複数のテストパターンを順にデータ回路１に入力すると同時にテスト回路ＣＴＣにてテスト結果を圧縮させ、圧縮されたテスト結果を圧縮テスト終了後に観察することのみによって、データ回路１の動作試験を行うことが可能となる。
【００９６】
テスト保持端子ｔｈｌｄ、シフトモード端子ｓｍ、比較端子ｃｍｐｅｎ及び期待データ端子ｅｘｐにそれぞれ入力される、テスト保持制御信号ｔｈｌｄ、シフトモード制御信号ｓｍ、比較イネーブル信号ＣＭＰＥＮ及び期待データＥＸＰによるテスト回路ＣＴＣの動作について説明する。
【００９７】
テスト回路ＣＴＣは期待データＥＸＰと入力データｄとを比較する機能を有する回路である。シフトモード制御信号ｓｍが“０”のとき、テスト回路ＣＴＣは入力端子ｄに入力されるデータを取り込み、そのまま出力端子ｑから出力する。シフトモード制御信号ｓｍが“１”であり、かつテスト保持制御信号ｔｈｌｄが“０”のとき、テスト回路ＣＴＣはスキャンイン端子ｓｉからデータを取り込み、スキャンアウト端子ｓｏからデータを出力する。シフトモード制御信号ｓｍが“１”、テスト保持制御信号ｔｈｌｄが“１”であり、かつ比較イネーブル信号ＣＭＰＥＮが“０”のとき、テスト回路ＣＴＣは圧縮されたテスト結果を保持する。シフトモード制御信号ｓｍが“１”、テスト保持制御信号ｔｈｌｄが“１”であり、かつ比較イネーブル信号ＣＭＰＥＮが“１”のとき、テスト回路ＣＴＣは入力される期待データＥＸＰと入力データｄとの比較結果を圧縮して保持する。
【００９８】
以上のような動作を行うテスト回路ＣＴＣは、図１１に示される接続回路ＣＣＣを用いることによって得られる。接続回路ＣＣＣについて説明を行う。接続回路ＣＣＣは、入力端子ｃｄ、スキャンイン端子ｃｓｉ、テスト保持端子ｃｔｈｌｄ、シフトモード端子ｃｓｍ、スキャンアウト端子ｃｓｏ、期待データ端子ｃｅｘｐ及び比較端子ｃｃｍｐｅｎを備える回路である。セレクタ２，３、フリップフロップ４、Ｅｘ−ＯＲゲート３０、ＮＡＮＤゲート３１及びＡＮＤゲート３２によって接続回路ＣＣＣは構成される。
【００９９】
セレクタ２，３はデータ入力０端子及びデータ入力１端子、出力端子ならびに制御端子をそれぞれ有するセレクタである。セレクタ２はテスト保持制御信号ｃｔｈｌｄによって、セレクタ３はシフトモード制御信号ｃｓｍによって切替の制御が行われる。入力端子ｃｄはＥｘ−ＯＲゲート３０の一方の入力端子及びセレクタ３のデータ入力０端子に共通に接続される。期待データ端子ｃｅｘｐはＥｘ−ＯＲゲート３０の他方の入力端子に接続される。Ｅｘ−ＯＲゲート３０の出力端子はＮＡＮＤゲート３１の一方の入力端子に接続され、ＮＡＮＤゲート３１の他方の入力端子には比較端子ｃｃｍｐｅｎが接続される。ＮＡＮＤゲート３１の出力端子はＡＮＤゲート３２の一方の入力端子に接続され、フリップフロップ４の出力端子がＡＮＤゲート３２の他方の入力端子に接続される。ＡＮＤゲート３２の出力端子はセレクタ２のデータ入力１端子に接続され、スキャンイン端子ｃｓｉはセレクタ２のデータ入力０端子に接続される。セレクタ２の出力端子はセレクタ３のデータ入力１端子に接続され、前述のように入力端子ｃｄがセレクタ３のデータ入力０端子に接続される。セレクタ３の出力端子はフリップフロップ４の入力端子に接続される。フリップフロップ４の出力データは前述の如くＡＮＤゲート３２の他方の入力端子に入力され、また接続回路ＣＣＣのスキャンアウト端子ｃｓｏに接続される。
【０１００】
接続回路ＣＣＣの回路動作について説明を行う。
【０１０１】
１．接続回路ＣＣＣは、シフトモード制御信号ｃｓｍが“０”のとき、入力端子ｃｄに入力される信号をセレクタ３及びフリップフロップ４を介して出力する。
【０１０２】
２．シフトモード制御信号ｃｓｍが“１”であり、かつテスト保持制御信号ｃｔｈｌｄが“０”のとき、接続回路ＣＣＣはスキャンイン端子ｃｓｉに入力されるデータをセレクタ２，３及びフリップフロップ４を介してスキャンアウト端子ｃｓｏから出力する。
【０１０３】
３．シフトモード制御信号ｃｓｍが“１”であり、テスト保持制御信号ｃｔｈｌｄが“１”のときの回路動作について以下に説明を行う。
【０１０４】
比較端子ｃｃｍｐｅｎから入力される比較イネーブル信号ｃｃｍｐｅｎが“０”のとき、ＮＡＮＤゲート３１はＥｘ−ＯＲゲート３０からの出力データに関わりなく“１”をＡＮＤゲート３２に出力する。このときゲート３２はフリップフロップ４の出力データをセレクタ２，３を介してフリップフロップ４に出力する。従って、接続回路ＣＣＣはフリップフロップ４のデータを保持し続ける。
【０１０５】
比較端子ｃｃｍｐｅｎから入力される比較イネーブル信号ｃｃｍｐｅｎが“１”のとき、ＮＡＮＤゲート３１はＥｘ−ＯＲゲート３０の出力データの反転論理を出力する。Ｅｘ−ＯＲゲート３０は期待データｅｘｐと入力データｃｄが一致するときには“０”を出力し、一致しないときには“１”を出力する。従って、Ｅｘ−ＯＲゲート３０において期待データｅｘｐと入力データｃｄが一致するときには、ＮＡＮＤゲート３１は“１”をＡＮＤゲート３２に出力する。このときゲート３２はフリップフロップ４の出力データをセレクタ２，３を介してフリップフロップ４に出力する。従って、接続回路ＣＣＣはフリップフロップ４のデータを保持し続ける。Ｅｘ−ＯＲゲート３０において期待データｅｘｐと入力データｃｄが一致しないときには、ＮＡＮＤゲート３１は“０”をＡＮＤゲート３２に出力する。このとき、ＡＮＤゲート３２は“０”をセレクタ２，３を介してフリップフロップ４に出力し、フリップフロップ４はＡＮＤゲート３２に“０”を出力する。これによって、ＡＮＤゲート３２、セレクタ２，３及びフリップフロップ４において“０”が保持される状態が続く。
【０１０６】
接続回路ＣＣＣを用いることによって、上述のテスト回路ＣＴＣの回路動作が得られる。
【０１０７】
データ入力端子ｄ［０］〜［３］と出力端子ｑ［０］〜［３］との間に接続回路ＣＣＣ［０］〜［３］がそれぞれ挿入され接続されて４ビットのテスト回路ＣＴＣが構成される。テスト回路ＣＴＣを図１３に示す。
【０１０８】
テスト回路ＣＴＣの構成について詳細に述べると以下のようになる。接続回路ＣＣＣ［Ｎ］の入力端子ｃｄ［Ｎ］、テスト保持端子ｃｔｈｌｄ［Ｎ］、シフトモード端子ｃｓｍ［Ｎ］、スキャンアウト端子ｃｓｏ［Ｎ］、期待データ端子ｃｅｘｐ［Ｎ］及び比較端子ｃｃｍｐｅｎ［Ｎ］はそれぞれテスト回路ＣＴＣの入力端子ｄ［Ｎ］、テスト保持端子ｔｈｌｄ、シフトモード端子ｓｍ、出力端子ｑ［Ｎ］、期待データ端子ｅｘｐ及び比較端子ｃｍｐｅｎに接続される。さらに、接続回路ＣＣＣ［Ｎ］のスキャンアウト端子ｃｓｏ［Ｎ］は接続回路ＣＣＣ［Ｎ＋１］のスキャンイン端子ｃｓｉ［Ｎ＋１］に接続される。但しＮ＝３のとき、接続回路ＣＣＣ［３］のスキャンアウト端子ｃｓｉ［３］はテスト回路ＣＴＣのスキャンアウト端子ｓｏに接続される。また、接続回路ＣＣＣ［０］のスキャンイン端子ｃｓｉ［０］はテスト回路ＣＴＣのスキャンイン端子ｓｉに接続される。
【０１０９】
論理回路及び本実施の形態に従う試験回路を含んで成る回路について、図１０を用いて説明を行う。
【０１１０】
まず通常動作に必要である、データ入力端子ＩＮ及びデータ出力端子ＯＵＴならびにデータ回路１とテスト回路ＴＣ，ＣＴＣとの接続について説明を行う。データ回路１の入力側においては、テスト回路ＴＣの入力端子ｄ［Ｎ］及び出力端子ｑ［Ｎ］がデータ入力端子ＩＮ［Ｎ］及びデータ回路１の入力端子ＤＩ［Ｎ］とそれぞれ接続される。出力側においても同様に、テスト回路ＣＴＣの入力端子ｄ［Ｎ］及び出力端子ｑ［Ｎ］がデータ回路１の出力端子ＤＯ［Ｎ］及びデータ出力端子ＯＵＴ［Ｎ］と接続される。
【０１１１】
次にスキャンテストを行う際に用いられる、スキャンイン端子ＳＩ及びテスト回路ＴＣ，ＣＴＣのそれぞれのスキャンイン端子ｓｉならびにスキャンアウト端子ＳＯ及びテスト回路ＴＣ，ＣＴＣのそれぞれのスキャンアウト端子ｓｏの接続について説明を行う。スキャンイン端子ＳＩはテスト回路ＴＣのスキャンイン端子ｓｉに接続される。テスト回路ＴＣのスキャンアウト端子ｓｏはテスト回路ＣＴＣのスキャンイン端子ｓｉに接続される。テスト回路ＣＴＣのスキャンアウト端子ｓｏはスキャンパスの最終の出力端子であるスキャンアウト端子ＳＯに接続される。
【０１１２】
本実施の形態においては、図１０にて示されるように、テスト回路ＴＣのシフトモード端子ｓｍに保持制御信号ＨＬＤ０及びシフトモード制御信号ＳＭのうちのいずれかが与えられる。テスト回路ＣＴＣのシフトモード端子ｓｍに保持制御信号ＨＬＤ１及びシフトモード制御信号ＳＭのうちのいずれかが与えられる。また、テスト回路ＴＣのテスト保持端子ｔｈｌｄには保持制御信号ＨＬＤ０及びテスト保持制御信号ＴＨＬＤ０のうちのいずれかが与えられる。テスト回路ＣＴＣのテスト保持端子ｔｈｌｄには保持制御信号ＨＬＤ１及びテスト保持制御信号ＴＨＬＤ１のうちのいずれかが与えられる。テスト回路ＣＴＣの期待データ端子ｅｘｐ及び比較端子ｃｍｐｅｎにはそれぞれ期待データＥＸＰ及び比較イネーブル信号ＣＭＰＥＮを与えて制御を行う。
【０１１３】
以上記述したような制御信号を与える制御回路を図１４に示す。図１４はテスト回路ＴＣを制御する制御回路ＣＴＬ３及びテスト回路ＣＴＣを制御する制御回路ＣＣＴＬ３の設けられる回路を示す回路図である。
【０１１４】
制御回路ＣＴＬ３は、保持制御信号ＨＬＤ０、テスト保持制御信号ＴＨＬＤ０、シフトモード制御信号ＳＭ及びテスト制御信号ＴＥＳＴを受けて、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍをテスト回路ＴＣに与える。制御回路ＣＴＬ３と同様に、制御回路ＣＣＴＬ３は、保持制御信号ＨＬＤ１、テスト保持制御信号ＴＨＬＤ１、シフトモード制御信号ＳＭ及びテスト制御信号ＴＥＳＴを受けて、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍをテスト回路ＣＴＣに与える。シフトモード制御信号ＳＭ及びテスト制御信号ＴＥＳＴは共通に制御回路ＣＴＬ３及びＣＣＴＬ３に与えられる。また、制御回路ＣＣＴＬ３とは独立に、期待データＥＸＰ及び比較イネーブル信号ＣＭＰＥＮがテスト回路ＣＴＣに与えられる。
【０１１５】
まず、制御回路ＣＴＬ３の回路動作について説明を行う。制御回路ＣＴＬ３は、テスト制御信号ＴＥＳＴが“０”のとき、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとして保持制御信号ＨＬＤ０を出力する。テスト制御信号ＴＥＳＴが“１”のとき、テスト保持制御信号ｔｈｌｄとしてテスト保持制御信号ＴＨＬＤ０を、シフトモード制御信号ｓｍとしてシフトモード制御信号ＳＭを制御回路ＣＴＬ３は出力する。
【０１１６】
次に、制御回路ＣＣＴＬ３の回路動作について説明を行う。制御回路ＣＣＴＬ３の回路動作は制御回路ＣＴＬ３の回路動作と同様である。制御回路ＣＣＴＬ３は、テスト制御信号ＴＥＳＴが“０”のとき、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとして保持制御信号ＨＬＤ１を出力する。テスト制御信号ＴＥＳＴが“１”のとき、テスト保持制御信号ｔｈｌｄとしてテスト保持制御信号ＴＨＬＤ１を、シフトモード制御信号ｓｍとしてシフトモード制御信号ＳＭを制御回路ＣＣＴＬ３は出力する。
【０１１７】
制御回路ＣＴＬ３の構成について図１４に基づき説明を行う。セレクタ５，６によって制御回路ＣＴＬ３は構成される。セレクタ５，６はデータ入力０端子及びデータ入力１端子、出力端子ならびに制御端子をそれぞれ有するセレクタである。セレクタ５，６の制御端子にはセレクタ５，６を同時に切替えるためのテスト制御信号ＴＥＳＴが入力される。データ入力０端子はテスト制御信号ＴＥＳＴが“０”のときに選択され出力端子に接続される。一方、データ入力１端子はテスト制御信号ＴＥＳＴが“１”のときに選択され出力端子に接続される。よって、セレクタ５，６に入力されるテスト制御信号ＴＥＳＴの“１”，“０”を切替えることによって、セレクタ５，６からそれぞれ出力されるデータを選択することが可能となる。セレクタ５，６のそれぞれのデータ入力０端子には保持端子ＨＬＤ０が共通に接続される。セレクタ５のデータ入力１端子にはテスト保持端子ＴＨＬＤ０が接続され、セレクタ６のデータ入力１端子にはシフトモード端子ＳＭが接続される。セレクタ５の出力端子はテスト回路ＴＣのテスト保持端子ｔｈｌｄに接続される。セレクタ６の出力端子はテスト回路ＴＣのシフトモード端子ｓｍに接続される。
【０１１８】
制御回路ＣＣＴＬ３の構成について図１４に基づき説明を行う。制御回路ＣＣＴＬ３の接続は制御回路ＣＴＬ３の接続と同様である。制御回路ＣＴＬ３を
セレクタ５，６→セレクタ７，８
保持端子ＨＬＤ０→保持端子ＨＬＤ１
テスト保持端子ＴＨＬＤ０→テスト保持端子ＴＨＬＤ１
のように変換して制御回路ＣＣＴＬ３は構成される。
【０１１９】
図１４に示される制御回路の回路動作を以下にまとめる。回路動作としては、通常動作、通常のスキャンテスト動作及びテスト結果の圧縮機能を用いるスキャンテスト動作が存在する。通常のスキャンテスト動作とは、実施の形態１において示されるスキャンテスト動作である。テスト結果の圧縮機能を用いるスキャンテスト動作とは、実際の論理回路の出力データと期待される論理回路の出力データとを論理回路の出力側において比較し、比較結果を保持する事によってテスト結果を圧縮し、圧縮した後にデータをスキャンアウトするという動作である。通常動作、通常のスキャンテスト及びテスト結果の圧縮機能を用いるスキャンテストにおける、それぞれの信号及びデータの最適な設定値を表３に示す。
【０１２０】
【表３】

【０１２１】
まず通常動作について説明を行う。通常動作時にはテスト制御信号ＴＥＳＴを“０”とし、比較イネーブル信号ＣＭＰＥＮを“０”とする。初めに入力側について説明を行う。テスト制御信号ＴＥＳＴが“０”のときにセレクタ５，６はデータ入力０端子に入力されるデータを出力するので、保持制御信号ＨＬＤ０がテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣに与えられる。このとき、保持制御信号ＨＬＤ０が“０”ならば、入力データＩＮがテスト回路ＴＣを構成する接続回路ＣＣを介してデータ回路１の入力端子ＤＩに取り込まれる。保持制御信号ＨＬＤ０が“１”ならば、入力データＩＮは接続回路ＣＣにおいて保持される。出力側においては、セレクタ７，８がデータ入力０端子に入力されるデータを出力するので、保持制御信号ＨＬＤ１がテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＣＴＣに与えられる。このとき、保持制御信号ＨＬＤ１が“０”ならば、出力データＤＯがテスト回路ＣＴＣを構成する接続回路ＣＣＣを介してデータ出力端子ＯＵＴに出力される。保持制御信号ＨＬＤ１が“１”ならば、比較イネーブル信号ＣＭＰＥＮが“０”なので、出力データＤＯは接続回路ＣＣＣにおいて保持される。
【０１２２】
通常動作、通常のスキャンテスト及びテスト結果の圧縮機能を用いるスキャンテストにおいては、テスト制御信号ＴＥＳＴを“１”とする。テスト制御信号ＴＥＳＴが“１”のとき、制御回路ＣＴＬ３を構成するセレクタ５，６及び制御回路ＣＣＴＬ３を構成するセレクタ７，８はデータ入力１端子に入力されるデータをそれぞれ出力する。このとき、入力側においては、テスト保持制御信号ＴＨＬＤ０及びシフトモード制御信号ＳＭがそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣに出力される。出力側においては、テスト保持制御信号ＴＨＬＤ１及びシフトモード制御信号ＳＭがそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＣＴＣに出力される。
【０１２３】
次に通常のスキャンテスト動作について説明する。通常のスキャンテスト時には比較イネーブル信号ＣＭＰＥＮを“０”とする。通常のスキャンテスト時には、テストパターンのシフトイン、実行、テスト結果のシフトアウトを順に行う。また、接続回路ＣＣ，ＣＣＣにおいてデータの保持を行うことが可能である。
【０１２４】
１．テストパターンのシフトイン
データ回路１にテストパターンを入力する準備として、入力側の接続回路ＣＣにテストパターンをシフトインする。テスト保持制御信号ＴＨＬＤ０を“０”、かつシフトモード制御信号ＳＭを“１”とすると、データ回路１に入力するテストパターンをスキャンイン端子ＳＩからシフトインすることが可能である。本実施の形態のデータ回路１は４ビットであるので、４ビットのテストパターンがシフトインされる。テストパターンは入力側の接続回路ＣＣ［０］→ＣＣ［１］→ＣＣ［２］→ＣＣ［３］の順でシフトされ、入力側の接続回路ＣＣ［０］〜［３］にテストパターンが入力される。
【０１２５】
２．実行
シフトモード制御信号ＳＭを“０”とする。このとき、入力側では接続回路ＣＣを介して入力データＩＮが入力端子ＤＩに取り込まれ、出力側では接続回路ＣＣＣを介してデータ回路１のテスト結果である出力データＤＯがデータ出力端子ＯＵＴに出力される。
【０１２６】
３．テスト結果のシフトアウト
テスト保持制御信号ＴＨＬＤ１を“０”、かつシフトモード制御信号ＳＭを“１”とする。このときテスト結果を順にスキャンアウト端子ＳＯからシフトアウトする。
【０１２７】
スキャンテストの途中でデータの保持を行いたいときには、シフトモード制御信号ＳＭを“１”とする。保持制御信号ＴＨＬＤ０が“１”ならば、入力側において接続回路ＣＣがデータを保持する。保持制御信号ＴＨＬＤ１が“１”ならば、出力側において接続回路ＣＣＣがデータを保持する。
【０１２８】
もちろん、出力側のテスト回路ＣＴＣをテスト回路ＴＣに置き換えても、上述の通常動作及び通常のスキャンテストを行うことは可能である。また、通常動作時のデータの保持及び通常のスキャンテスト時のデータの保持を接続回路ＣＣあるいはＣＣＣにて兼用して行うので、回路のオーバーヘッドを縮小し、回路面積を小さくすることが可能である。
【０１２９】
スキャンテスト動作における実行時に、入力端子ＤＩに取り込まれた入力データＩＮを保持することによって、一つのスキャンパスで複数の論理回路のスキャンテストを行うことが可能となる。以下に説明を行う。
【０１３０】
図１５はデータ回路１ｉｎの入力側、データ回路１ｉｎの出力側とデータ回路１の入力側との間、データ回路１の出力側とデータ回路１ｏｕｔの入力側との間及びデータ回路１ｏｕｔの出力側においてテスト回路ＴＣａ，ＴＣ，ＴＣｂ及びＴＣｃがそれぞれ設けられ、スキャンパスが構成される回路を示す回路図である。データ回路１ｉｎ及び１ｏｕｔはそれぞれ論理回路である。データ回路１ｉｎはデータ回路１に入力データＩＮを与える。データ回路１はデータ回路１ｏｕｔに出力データＯＵＴを与える。テスト回路ＴＣａ，ＴＣ，ＴＣｂ及びＴＣｃはそれぞれ、図示されない制御回路ＣＴＬＴＣａ，ＣＴＬ３，ＣＴＬＴＣｂ及びＣＴＬＴＣｃによって制御される。テスト回路ＴＣａはテスト回路ＴＣと同様の働きを有するテスト回路である。テスト回路ＴＣｂ及びＴＣｃはテスト回路ＴＣあるいはＣＴＣと同様の構成及び働きを有するテスト回路である。
【０１３１】
データ回路１ｉｎ，１及び１ｏｕｔが順に並べられ、スキャンパスは、スキャンイン端子ＳＩ→テスト回路ＴＣａ→テスト回路ＴＣ→テスト回路ＴＣｂ→テスト回路ＴＣｃ→スキャンアウト端子ＳＯのように構成されている。
【０１３２】
データ回路１の入力端子ＤＩに実行時に取り込まれたデータ回路１ｉｎからの入力データＩＮをテスト回路ＴＣによって保持する後にシフトアウトしてスキャンアウト端子ＳＯから取り出す。同様の操作をテスト回路ＴＣｂあるいはＴＣｃにて行うことが可能である。
【０１３３】
上述の操作を行えば、一つのスキャンパスで複数の論理回路のスキャンテストを行うことが可能となる。
【０１３４】
通常のスキャンテストにおいては、テストパターンの数だけ１〜３に記述される動作を繰り返さねばならない。次に、全てのパターンに対して一回のシフトアウトを行えば足りるというスキャンテスト、すなわちテスト結果の圧縮機能を用いるスキャンテスト動作について説明する。
【０１３５】
テスト結果の圧縮機能を用いるスキャンテスト動作について図１４を用いて説明する。テスト結果の圧縮機能を用いるスキャンテスト時には、初期設定の後に、テストパターンのシフトインと比較及び圧縮とを交互に行う。全ての所望のテストパターンに対する比較及び圧縮が済んだ後に、圧縮されたテスト結果のシフトアウトを行う。
【０１３６】
テスト結果の圧縮機能を用いるスキャンテスト時には比較イネーブル信号ＣＭＰＥＮは“０”と“１”の両方の値を採る。
【０１３７】
１．初期設定
初期設定として、テスト回路ＣＴＣを構成する接続回路ＣＣＣに含まれる全てのフリップフロップ４に“１”を設定する。シフトモード制御信号ＳＭを“１”、テスト保持制御信号ＴＨＬＤ０，ＴＨＬＤ１をそれぞれ”０”に設定して、スキャンイン端子ＳＩから“１”をシフトインするとフリップフロップ４に“１”が設定される。比較イネーブル信号ＣＭＰＥＮは“０”に設定する。
【０１３８】
２．テストパターンのシフトインならびに比較及び圧縮
データ回路１にテストパターンを入力する準備として、入力側の接続回路ＣＣにテストパターンをシフトインする。このとき、初期設定において接続回路ＣＣＣのフリップフロップ４に設定された“１”を保持するために、テスト保持制御信号ＴＨＬＤ１を“１”にする。テスト保持制御信号ＴＨＬＤ０及びシフトモード制御信号ＳＭのそれぞれの値は初期設定時の値と等しい。すなわち、テスト保持制御信号ＴＨＬＤ０が“０”、テスト保持制御信号ＴＨＬＤ１が“１”であり、かつシフトモード制御信号ＳＭが“１”という状態で、データ回路１に入力するテストパターンをスキャンイン端子ＳＩからシフトインする。
【０１３９】
本実施の形態のデータ回路１は４ビットであるので、４ビットのテストパターンがシフトインされる。テストパターンは入力側の接続回路ＣＣ［０］→ＣＣ［１］→ＣＣ［２］→ＣＣ［３］の順でシフトされ、入力側の接続回路ＣＣ［０］〜［３］にテストパターンが入力される。例えばテストパターンとして４次の全周期系列を与える。ここで、全周期系列とは、Ｍ系列に全てのビットが“０”であるデータを付け加えたものでる。従って、全周期系列は全ての組み合わせのデータを発生する。従って、テストパターンとして全周期系列を与えることによって、全ての組み合わせのテストパターンを効率よく接続回路ＣＣに設定することが可能となる。また、マーチングパターンにおいて順次“０”“１”が繰り返されるように、テスト保持制御信号ＴＨＬＤ０が“０”のときにテストパターンをシフトインして、次にテスト保持制御信号ＴＨＬＤ０を”１”としてテストパターンを接続回路ＣＣにて保持することを繰り返しながらデータ回路１にテストパターンを入力することによって、データ回路１に効率よくテストパターンを入力することが可能となる。
【０１４０】
期待データＥＸＰが入力される状態において、テストを行いたいテストパターンに対してのみ比較イネーブル信号ＣＭＰＥＮを“１”とする事によってデータ回路１の出力データと期待データＥＸＰを比較する。テスト回路ＣＴＣの上述の回路動作によって、比較結果は圧縮される。
【０１４１】
３．テスト結果のシフトアウト
テスト保持制御信号ＴＨＬＤ１を“０”、かつシフトモード制御信号ＳＭを“１”とする。このとき、接続回路ＣＣＣにて圧縮されたテスト結果を順にスキャンアウト端子ＳＯからシフトアウトする。
【０１４２】
以上が図１４に示される回路の回路動作である。図１１に示される接続回路ＣＣＣの代わりに、図１２に示される接続回路ＣＣＣｒを用いても同様の回路動作を得ることが可能である。接続回路ＣＣＣｒにおいては、フリップフロップに通常備わるリセット端子が有効に活用されることが特徴となっている。接続回路ＣＣＣｒについて、接続回路ＣＣＣとの違いをふまえながら説明を行う。
【０１４３】
接続回路ＣＣＣｒは、接続回路ＣＣＣの備える端子と同一の働きを有する端子を備え、さらにクロック端子ｔを備える。すなわち、接続回路ＣＣＣｒに備わる入力端子ｃｄｒ、スキャンイン端子ｃｓｉｒ、テスト保持端子ｃｔｈｌｄｒ、シフトモード端子ｃｓｍｒ、スキャンアウト端子ｃｓｏｒ、期待データ端子ｃｅｘｐｒ及び比較端子ｃｃｍｐｅｎｒはそれぞれ、接続回路ＣＣＣに備わる入力端子ｃｄ、スキャンイン端子ｃｓｉ、テスト保持端子ｃｔｈｌｄ、シフトモード端子ｃｓｍ、スキャンアウト端子ｃｓｏ、期待データ端子ｃｅｘｐ及び比較端子ｃｃｍｐｅｎと同一の働きを有する。
【０１４４】
また、接続回路ＣＣＣｒはセレクタ２，３、フリップフロップ４ｒ、Ｅｘ−ＯＲゲート３０ｒ、及びゲート３１ｒによって構成される。Ｅｘ−ＯＲゲート３０ｒはＥｘ−ＯＲゲート３０と同一の構成及び働きを有し、ゲート３１ｒは二つの入力端子にそれぞれ入力される信号と、一つの反転入力端子に入力される信号の反転信号との否定論理積をとり、出力端子から出力する回路である。
【０１４５】
フリップフロップ４にはリセット端子及びクロック端子が備わっていたがこれまでの実施の形態においては特別な機能を果たす必要はなかった。よって、それらの説明及び図示は省略されていた。接続回路ＣＣＣｒにおいては、リセット端子を有効に活用し、さらにクロック端子に入力される信号を利用することによって同期をとり、テスト結果の圧縮を行う。従って、接続回路ＣＣＣｒにおいてのみフリップフロップ４ｒのリセット端子とクロック端子の図示を特に行う。これに伴い、テスト回路ＣＴＣにもクロック端子Ｔを付け加え、接続回路ＣＣＣｒのクロック端子ｔと接続させることが必要となる。しかし、テスト回路ＣＴＣに置けるクロック端子Ｔの図示は省略するものとする。
【０１４６】
接続回路ＣＣＣｒと接続回路ＣＣＣとの主たる違いとは、
１．ゲート３１ｒとＮＡＮＤゲート３１及びＡＮＤゲート３２との違い、
２．フリップフロップ４とセレクタ２との接続と、フリップフロップ４ｒとセレクタ２との接続との違い
３．クロック端子ｔの存在及び接続から生ずる違い
である。他の接続は同様であるので、説明は省略する。
【０１４７】
Ｅｘ−ＯＲゲート３０ｒの出力端子はゲート３１ｒの一方の入力端子に接続され、ゲート３１ｒの他方の入力端子には比較端子ｃｃｍｐｅｎｒが接続される。ゲート３１ｒの反転入力端子にはクロック端子ｔが接続され、同時にクロック端子ｔはフリップフロップ４ｒのクロック端子にも共通に接続される。ゲート３１ｒの出力端子はフリップフロップ４ｒのリセット端子に接続される。フリップフロップ４ｒのリセット端子は“０”を受けたときに、自身の中に記憶されるデータをリセットする。フリップフロップ４ｒの出力端子はセレクタ２のデータ入力１端子に接続され、また接続回路ＣＣＣｒのスキャンアウト端子ｃｓｏｒに接続される。
【０１４８】
接続回路ＣＣＣｒの回路動作について説明を行う。接続回路ＣＣＣｒを用いても、接続回路ＣＣＣの回路動作１，２と全く同一の回路動作が得られ、また接続回路ＣＣＣの回路動作３と同様の回路動作が得られる。そこで、接続回路ＣＣＣｒを用いる場合の回路動作３について、説明を以下に行う。
【０１４９】
比較イネーブル信号ｃｃｍｐｅｎｒが“０”のとき、ゲート３１ｒはＥｘ−ＯＲゲート３０ｒからの出力データとクロック端子ｔに入力されるクロック信号ｔとに関わりなく“１”をフリップフロップ４ｒのリセット端子に出力する。従ってフリップフロップ４ｒにおいてデータはリセットされず、接続回路ＣＣＣｒはフリップフロップ４ｒのデータを保持し続ける。
【０１５０】
比較イネーブル信号ｃｃｍｐｅｎｒが“１”であり、かつクロック端子ｔから入力されるクロック信号ｔが“０”のとき、ゲート３１ｒはＥｘ−ＯＲゲート３０ｒの出力データの反転論理を出力する。従って、Ｅｘ−ＯＲゲート３０ｒにおいて期待データｅｘｐｒと入力データｃｄｒが一致する場合には、ゲート３１ｒは“１”をフリップフロップ４ｒのリセット端子に出力する。従って、接続回路ＣＣＣｒはフリップフロップ４ｒのデータを保持し続ける。
【０１５１】
このとき、Ｅｘ−ＯＲゲート３０ｒにおいて期待データｅｘｐｒと入力データｃｄｒとが一致しない場合には、ゲート３１ｒは“０”をフリップフロップ４ｒのリセット端子に出力する。従って、フリップフロップ４ｒにおいてデータはリセットされるので、セレクタ２，３及びフリップフロップ４ｒにおいて“０”が保持される状態が続く。
【０１５２】
すなわち、期待データｅｘｐｒと入力データｃｄｒとが一致するときにはフリップフロップ４ｒのデータを保持し、一致しないときにはフリップフロップ４ｒにて“０”を保持し続けるという回路機能を接続回路ＣＣＣｒは有する。この回路機能は接続回路ＣＣＣの回路機能と同一である。しかし、特に接続回路ＣＣＣｒを用いることによって、以下の利点を得ることが可能となる。
【０１５３】
接続回路ＣＣＣにおいては、データの保持をセレクタ２，３、フリップフロップ４及びＡＮＤゲート３２によって形成されるループによって行っていた。しかし接続回路ＣＣＣｒにおいてはセレクタ２，３及びフリップフロップ４ｒのみによって形成されるループによってデータの保持を行うので、余計なノイズ等によってデータが影響を受ける可能性が低減される。
【０１５４】
また接続回路ＣＣＣｒにおいては、クロック信号ｔによって同期をとっているが、ゲート３１ｒから反転入力端子を取り除くことによってゲート３１ｒをＮＡＮＤゲートとして、クロック信号による同期をとらないようにしても良い。
【０１５５】
以上の説明から明らかなように、接続回路ＣＣＣを用いる場合と同様に、接続回路ＣＣＣｒを用いてテスト回路ＣＴＣを構成することが可能である。
【０１５６】
テスト回路ＣＴＣをデータ回路１の出力側に設け、テスト結果の圧縮機能を用いるスキャンテストを行うことによって、複数のテストパターンに対するテスト結果のシフトアウトが一回ですむという利点が生ずる。従って、複数のテストパターンに対して通常のスキャンテストを複数回行う為に要する時間よりも、複数のテストパターンに対してテスト結果の圧縮機能を用いるスキャンテストを行うために要する時間の方が短い。すなわち、テスト時間を短縮可能である。
【０１５７】
図１４に示される制御回路ＣＴＬ３を用いると、実施の形態１にて記述された効果と同様の効果が生ずる。制御回路ＣＴＬ３においては、テスト制御信号ＴＥＳＴによって保持端子ＨＬＤ０とテスト保持端子ＴＨＬＤ０及びシフトモード端子ＳＭとのうちどちらが選択されるかが制御される。従って、制御回路ＣＴＬ３を用いることによって、図４に示される回路においてデータ回路１のスキャンテストをデータ回路１ａから与えられる保持制御信号ＨＬＤ０とは独立に行うことが可能となる。
【０１５８】
制御回路ＣＴＬ３と制御回路ＣＣＴＬ３との構成の違いとは、入力される制御信号による違いのみであり、テスト制御信号ＴＥＳＴによって同時に制御されるので、セレクタ５，６の動作とセレクタ７，８の動作は同一である。すなわち、制御回路の構成に関する発明に関しては、テスト回路ＴＣを制御する制御回路の説明を行い、この説明をテスト回路ＣＴＣを制御する制御回路の説明に替えることが可能である。従って、データ回路１の出力側の回路を省略して、図１４に示される回路を図１７のように図示することが可能である。今後は特に必要とされるとき以外はデータ回路１の出力側の回路の図示及び説明は省略するものとする。
【０１５９】
本実施の形態においては、入力側の制御回路に入力される保持制御信号ＨＬＤ０と、出力側の制御回路に入力される保持制御信号ＨＬＤ１とは異なる。従って、複数のスキャンフリップフロップを保持制御信号確認のために用いる必要が生ずる。複数の保持制御信号を確認するために用いられるスキャンフリップフロップに関して図１６を用いて以下に説明を行う。図１６は複数の保持制御信号を確認するために用いられるスキャンフリップフロップの接続の状態を示す図であり、テスト保持端子、期待データ端子及び比較端子等の図示は同図においては省略されている。
【０１６０】
保持制御信号ＨＬＤ０，ＨＬＤ１を確認する場合を考える。スキャンイン端子ＳＩとテスト回路ＴＣのスキャンイン端子ｓｉとの間に、スキャンフリップフロップＨＳＦＦ及びＨＳＦＦａを挿入する。スキャンフリップフロップＨＳＦＦはセレクタ１４及びフリップフロップ１５から成る回路である。同様に、スキャンフリップフロップＨＳＦＦａはセレクタ１４ａ及びフリップフロップ１５ａから成る回路である。テスト回路ＴＣを制御する制御回路に入力される保持制御信号ＨＬＤ０を確認するためにスキャンフリップフロップＨＦＳＳは設けられる。同様に、テスト回路ＣＴＣを制御する制御回路に入力される保持制御信号ＨＬＤ１を確認するためにスキャンフリップフロップＨＦＳＳａは設けられる。セレクタ１４，１４ａはデータ入力０端子及びデータ入力１端子、出力端子ならびに制御端子をそれぞれ有する。それぞれの制御端子にはセレクタ１４，１４ａを切替えるためのシフトモード制御信号ＳＭが入力される。データ入力０端子はシフトモード制御信号ＳＭが“０”のときに選択され出力端子に接続される。一方、データ入力１端子はシフトモード制御信号ＳＭが“１”のときに選択され出力端子に接続される。よって、セレクタ１４，１４ａに入力されるシフトモード制御信号ＳＭの“１”，“０”を切替えることによって、セレクタ１４，１４ａから出力されるデータを選択することが可能となる。セレクタ１４のデータ入力１端子にはスキャンイン端子ＳＩが接続される。セレクタ１４のデータ入力０端子には保持端子ＨＬＤ０が接続される。セレクタ１４の出力端子はフリップフロップ１５の入力端子に接続される。フリップフロップ１５の出力端子はセレクタ１４ａのデータ入力１端子に接続される。セレクタ１４ａのデータ入力０端子には保持端子ＨＬＤ１が接続される。フリップフロップ１５ａの出力端子はテスト回路ＴＣのスキャンイン端子ｓｉに接続される。フリップフロップ１５，１５ａはＤフリップフロップあるいはＤフリップフロップと同様の働きを有するフリップフロップである。
【０１６１】
以上のようなスキャンフリップフロップＨＳＦＦ，ＨＳＦＦａにおいてシフトモード制御信号ＳＭを“０”とすることによって、フリップフロップ１５，１５ａに保持制御信号ＨＬＤ０，ＨＬＤ１の値をそれぞれ記憶させることが可能となる。図１６に示される構成では、スキャンフリップフロップＨＳＦＦ，ＨＳＦＦａの出力端子がテスト回路ＴＣのスキャンイン端子ｓｉに接続される。従って、シフトモード制御信号ＳＭを“１”、テスト保持制御信号ＴＨＬＤ０，ＴＨＬＤ１をそれぞれ“０”として、シフトモード制御信号ＳＭが“０”のときにスキャンフリップフロップＨＳＦＦ，ＨＳＦＦａに記憶された保持制御信号ＨＬＤ０，ＨＬＤ１の論理をスキャンパスからスキャンアウトデータＳＯとして取りだした後に観察を行えば良い。例えばテスト保持制御信号ＴＨＬＤ０，ＴＨＬＤ１のような他の制御信号の観察も、同様の構成を用いることによって可能となる。
【０１６２】
前述の通り、セレクタ１４，１４ａはシフトモード制御信号ＳＭによって制御されるが、テスト回路ＴＣ，ＣＴＣの制御に関係しない制御端子を新たに設け、この制御端子から出力される制御信号によってセレクタ１４，１４ａを制御することも可能である。しかし、前述のようにシフトモード制御信号ＳＭを用いてセレクタ１４，１４ａの制御を兼用することによって、以下の利点が生ずる。
【０１６３】
本実施の形態のテスト回路ＴＣ，ＣＴＣにおいては、テスト制御信号ＴＥＳＴが“１”のとき、シフトモード制御信号ＳＭを“０”とすることによって、入力側では接続回路ＣＣを介して入力データＩＮが入力端子ＤＩに取り込まれる。このとき、出力側では接続回路ＣＣＣを介してデータ回路１のテスト結果である出力データＤＯがデータ出力端子ＯＵＴに出力される。シフトモード制御信号ＳＭが“０”のときには、セレクタ１４，１４ａにおいては制御信号ＨＬＤ０，ＨＬＤ１がスキャンフリップフロップＨＳＦＦ，ＨＳＦＦａにおいて記憶されるが、テスト回路ＴＣにはシフトインされない。スキャンテストにおいて、テストパターンのシフトインあるいはテスト結果のシフトアウトを行うときには、シフトモード制御信号ＳＭが“１”と設定される。従って、セレクタ１４，１４ａにおいてはスキャンイン端子ＳＩからシフトインされるテストパターンが導通されるので、スキャンフリップフロップＨＳＦＦ，ＨＳＦＦａはテストパターンのシフトインあるいはテスト結果のシフトアウトを阻害しない。セレクタ１４，１４ａの制御をシフトモード制御信号ＳＭによって行ってもスキャンテスト動作に悪影響を及ぼすことはないので、シフトモード制御信号ＳＭを兼用することによって、スキャンフリップフロップＨＳＦＦ，ＨＳＦＦａに制御信号を与える制御端子を減らすことが可能である。
【０１６４】
また、図１６においてスキャンフリップフロップＨＳＦＦ，ＨＳＦＦａはスキャンイン端子ＳＩとテスト回路ＴＣのスキャンイン端子ｓｉとの間に挿入されるが、テスト回路ＴＣのスキャンアウト端子ｓｏとテスト回路ＣＴＣのスキャンイン端子ｓｉとの間に挿入されても同じ作用が得られ、保持制御信号ＨＬＤ０，ＨＬＤ１の観察が可能となる。また、テスト回路ＣＴＣのスキャンアウト端子ｓｏとスキャンアウト端子ＳＯとの間に挿入されても同じ作用が得られる。
【０１６５】
以上の説明においては観察を行う制御信号の数は二つであるが、観察可能な制御信号の数は二つに限られるものではない。観察を行いたい制御信号が複数個存在するときには、同複数個のスキャンフリップフロップを直列に接続すれば良いことは明らかである。
【０１６６】
本実施の形態に従うテスト回路ＴＣ，ＣＴＣのホールド機能を兼用して通常動作時とスキャンテスト動作時に用いることが可能であるので、オーバーヘッドを無くすことによって回路面積を小さくすることが可能である。
【０１６７】
次に、本実施の形態に従う他の制御回路についての説明を行う。図１８は図１７にて示される制御回路ＣＴＬ３と同様に構成され同一の働きを持つ制御回路ＣＴＬ３ａを示す回路図である。
【０１６８】
制御回路ＣＴＬ３ａと制御回路ＣＴＬ３との違いとは、構成の違いのみである。構成の違いとは、セレクタ６のデータ入力０端子に接続される端子の違いであり、セレクタ６のデータ入力０端子にはセレクタ５の出力端子が接続される。
【０１６９】
制御回路ＣＴＬ３ａの回路動作について説明を行う。上述の構成の違いを鑑みると、テスト制御信号ＴＥＳＴが“０”のときのみを考えれば良い。テスト制御信号ＴＥＳＴが“０”のとき、セレクタ５の出力をセレクタ６は出力するので、保持制御信号ＨＬＤ０がセレクタ６の出力端子から出力されることとなる。
【０１７０】
従って、制御回路ＣＴＬ３ａの回路動作は制御回路ＣＴＬ３の回路動作と同一である。
【０１７１】
図１７においては、制御回路ＣＴＬ３は保持端子ＨＬＤ０，テスト保持端子ＴＨＬＤ０及びシフトモード制御信号ＳＭに直接接続されている。セレクタ１４の制御端子に入力されるシフトモード制御信号ＳＭを通常動作時に“０”としておくことによって、図１９に示される回路のようにスキャンフリップフロップＨＳＦＦを介して保持端子ＨＬＤ０を制御回路ＣＴＬ３に接続することも可能である。
【０１７２】
次に、スキャンフリップフロップの構成を変更することによって得ることができる、本実施の形態に従う試験回路について説明を行う。既述の回路等と同一の構成、働き等を有するものに対しては同一の参照符号を付け、説明は省略するものとする。
【０１７３】
図２０は論理回路及び本実施の形態に従う試験回路を示す回路図である。本実施の形態に従うテスト回路ＴＣＳは、テスト回路ＴＣの代わりに用いることが可能な回路である。本実施の形態に従う試験回路ＴＣＳもテスト回路ＴＣと同様に、フリップフロップ４、保持機能切り換え用のセレクタ２及びスキャンモード切り換え用のセレクタ３によって構成される。セレクタ２はテスト保持制御信号ｔｈｌｄによって制御され、セレクタ３はシフトモード制御信号ｓｍによって制御される。
【０１７４】
テスト回路ＴＣとテスト回路ＴＣＳとの違いとは、保持機能切り換え用のセレクタ２とスキャンモード切り換え用のセレクタ３との順が入れ替わっていることである。
【０１７５】
テスト回路ＴＣＳについて説明を行う。テスト回路ＴＣＳはデータ回路１の入力側及び出力側のいずれにも用いることが可能である。出力側に用いられるテスト回路ＴＣＳの動作は入力側に用いられるテスト回路ＴＣＳの動作と同様である。従って、同図においては入力側のみ図示されており、また説明も必要とされるときを除いて入力側についてのみ行う。
【０１７６】
データ回路１はテスト回路ＴＣＳによって入力の制御が行われる。テスト回路ＴＣＳはデータ入力端子ＩＮとデータ回路１の入力端子ＤＩとの間に挿入される。テスト回路ＴＣＳは入力データＩＮ［０］〜［３］を入力するための入力端子ｄ［０］〜［３］及びデータ回路１の入力端子ＤＩに出力するための出力端子ｑ［０］〜［３］、ならびにスキャンイン端子ｓｉ、テスト保持端子ｔｈｌｄ、シフトモード端子ｓｍ及びスキャンアウト端子ｓｏを備える回路である。
【０１７７】
テスト保持端子ｔｈｌｄ及びシフトモード端子ｓｍにそれぞれ入力されるテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍによるテスト回路ＴＣＳの動作について説明する。シフトモード制御信号ｓｍが“０”であり、かつテスト保持制御信号ｔｈｌｄが“０”のとき、テスト回路ＴＣＳはを入力端子ｄに入力されるデータ取り込み、そのまま出力端子ｑから出力する。シフトモード制御信号ｓｍが“１”であり、かつテスト保持制御信号ｔｈｌｄが“０”のとき、テスト回路ＴＣＳはスキャンイン端子ｓｉに入力されるデータを取り込んでスキャンアウト端子ｓｏから出力する。テスト保持制御信号ｔｈｌｄが“１”のとき、テスト回路ＴＣＳ中にてデータが保持される。
【０１７８】
以上のような動作を行うテスト回路ＴＣＳは以下のように構成される。セレクタ３［Ｎ］のデータ入力１端子にはフリップフロップ４の出力端子［Ｎ−１］が接続される。但し、特にＮ＝０のときには、セレクタ３［０］のデータ入力１端子にはスキャンイン端子ｓｉが接続される。セレクタ３［Ｎ］のデータ入力０端子にはデータ入力端子ＩＮが接続される。セレクタ３［Ｎ］の出力端子はセレクタ２［Ｎ］のデータ入力０端子に接続される。セレクタ２［Ｎ］のデータ入力１端子にはフリップフロップ４［Ｎ］の出力端子が接続される。セレクタ２［Ｎ］の出力端子はフリップフロップ４［Ｎ］の入力端子に接続される。フリップフロップ４［Ｎ］の出力端子は前述の如くセレクタ２［Ｎ］のデータ入力１端子に接続され、さらにデータ回路１の入力端子ＤＩ［Ｎ］及びセレクタ３［Ｎ＋１］に共通に接続される。但し、特にＮ＝３のときには、フリップフロップ４［３］の出力端子はセレクタ２［３］のデータ入力１端子、入力端子ＤＩ［３］及びテスト回路ＴＣＳのスキャンアウト端子ｓｏに共通に接続される。
【０１７９】
データ回路１の出力側にテスト回路ＴＣＳを設けるときには、以上の説明において、
データ入力端子ＩＮ → 出力端子ＤＯ
入力端子ＤＩ → データ出力端子ＯＵＴ
のように変換して考えれば良い。
【０１８０】
上述のテスト回路ＴＣＳによっても、通常動作及びスキャンテスト動作を行うことが可能である。
【０１８１】
次にテスト回路ＴＣＳにテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える、本実施例に従う制御回路ＣＴＬ４について説明を行う。制御回路ＣＴＬ４はテスト制御信号ＴＥＳＴ、シフトモード制御信号ＳＭ、テスト保持制御信号ＴＨＬＤ０及び保持制御信号ＨＬＤ０を入力され、テスト回路ＴＣＳにテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを出力する回路である。
【０１８２】
制御回路ＣＴＬ４は、シフトモード制御信号ｓｍとしてシフトモード制御信号ＳＭを常時出力する。テスト制御信号ＴＥＳＴが“０”のとき、制御回路ＣＴＬ４はテスト保持制御信号ｔｈｌｄとして保持制御信号ＨＬＤ０を出力する。テスト制御信号ＴＥＳＴが“１”のとき、テスト保持制御信号ｔｈｌｄとしてテスト保持制御信号ＴＨＬＤ０を出力する。
【０１８３】
制御回路ＣＴＬ４の接続について図２０に基づき説明を行う。制御回路ＣＴＬ４はセレクタ５という一つのセレクタを含んで構成される。セレクタ５の制御端子にはテスト制御信号ＴＥＳＴが入力される。
【０１８４】
セレクタ５のデータ入力０端子には保持端子ＨＬＤ０が接続される。セレクタ５のデータ入力１端子にはテスト保持制御端子ＴＨＬＤ０が接続される。セレクタ５の出力端子はテスト回路ＴＣＳのテスト保持端子ｔｈｌｄに接続される。シフトモード制御信号ＳＭはテスト回路ＴＣＳのシフトモード端子ｓｍに直接接続される。
【０１８５】
データ回路１の出力側に用いられる制御回路ＣＴＬ４に関しては、以上の説明において、
保持端子ＨＬＤ０ → 保持端子ＨＬＤ１
テスト保持端子ＴＨＬＤ０ → テスト保持端子ＴＨＬＤ１
のように変換して考えれば良い。
【０１８６】
上述のテスト回路ＴＣＳによっても、通常動作及びスキャンテスト動作を行うことが可能である。
【０１８７】
図２０に示される回路の回路動作を以下にまとめる。データ回路１の入力側及び出力側にテスト回路ＴＣＳを設ける場合について説明を行う。回路動作としては、通常動作及びスキャンテスト動作が存在する。
【０１８８】
通常動作時の回路動作は制御回路ＣＴＬ１，ＣＴＬ２あるいはＣＴＬ３とテスト回路ＴＣとからなる回路の回路動作と同一である。
【０１８９】
次にスキャンテスト動作について説明する。実行時とデータの保持時においてのみ、制御回路ＣＴＬ４とテスト回路ＴＣＳとからなる回路の操作は制御回路ＣＴＬ３とテスト回路ＴＣとからなる回路の操作と異なる。従って、実行時とデータの保持時についてのみ説明を行う。
【０１９０】
１．実行時
シフトモード制御信号ＳＭを“０”、テスト保持制御信号ＴＨＬＤ１を“０”とすることによって、制御回路ＣＴＬ３とテスト回路ＴＣとからなる回路と同一の回路動作が得られる。
【０１９１】
２．保持時
スキャンテストの途中でデータの保持を入力側にて行いたいときには、テスト保持制御信号ＴＨＬＤ０を“１”とすれば良い。データの保持を出力側にて行いたいときには、テスト保持制御信号ＴＨＬＤ１を“１”とする。
【０１９２】
以上が図２０に示される制御回路の回路動作である。データ回路１の入力側及び出力側にテスト回路ＴＣＳをそれぞれ設けるとき、入力側と出力側のテスト回路ＴＣＳをシフトモード制御信号ＳＭで同時に制御可能である。
【０１９３】
上述のテスト回路ＴＣＳにて構成されるスキャンパスについて述べる。データ回路１の入力側においてテスト回路ＴＣＳを設ける場合には、データ入力端子ＩＮと論理回路の入力端子ＤＩとの間にはセレクタ２，３という二つのセレクタが含まれる。同様に、データ回路１の出力側においてテスト回路ＴＣＳを設ける場合には、出力端子ＤＯとデータ出力端子ＯＵＴとの間にはセレクタ２，３という二つのセレクタが含まれる。従って通常動作時において、従来技術に従う試験回路と同様の動作速度しか得られない。
【０１９４】
しかし、テスト回路ＴＣＳを制御する制御回路ＣＴＬ４にはセレクタ５という一つのセレクタしか含まれないので、回路面積を縮小することは可能である。また、テスト回路ＴＣＳにおいても、テスト回路ＴＣＳのホールド機能を兼用して通常動作時とスキャンテスト動作時に用いることが可能であるので、オーバーヘッドを無くすことによって回路面積を小さくすることは可能である。
【０１９５】
実施の形態３．
本実施の形態に従う発明は、試験回路を制御する制御回路に関する。
【０１９６】
本実施の形態に従う制御回路はテスト回路ＴＣあるいはＣＴＣの制御を行う制御回路であり、実施の形態１，２において示される制御回路よりも構成の簡単な制御回路である。テスト回路ＴＣあるいはＣＴＣの制御を行う制御回路は、テスト回路ＴＣあるいはＣＴＣにテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える回路である。以下、テスト回路ＴＣにおいてもテスト回路ＣＴＣにおいても、制御回路の有する構成及び働きは変わらないので、制御される回路をテスト回路ＴＣに限って説明を行うこととする。データ回路１の入力側に関して以下の説明を行うが、出力側に関しても同様である。
【０１９７】
図２１は本実施の形態に従う制御回路ＣＴＬ５を示す回路図である。制御回路ＣＴＬ５は、保持制御信号ＨＬＤ０、テスト保持制御信号ＴＨＬＤ０、シフトモード制御信号ＳＭ及びテスト制御信号ＴＥＳＴを受けて、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍをテスト回路ＴＣに与える。通常動作時にテスト保持制御信号ＴＨＬＤ０を“０”とすることによって、制御回路ＣＴＬ５は実施の形態２に示される制御回路よりも回路面積が少なくなっている。出力側のテスト回路ＴＣに制御回路ＣＴＬ５を設けるときには、
保持制御信号ＨＬＤ０ → 保持制御信号ＨＬＤ１
テスト保持制御信号ＴＨＬＤ０ → テスト保持制御信号ＴＨＬＤ１
のように変換すれば良い。
【０１９８】
制御回路ＣＴＬ５の構成について図２１に基づき説明を行う。制御回路ＣＴＬ５は三つのゲートを用いて構成可能である。それぞれのゲートは二つの入力端子と一つの出力端子を有する。一つのゲートはゲート４１であり、残る二つはＯＲゲート４２，４３である。
【０１９９】
ゲート４１は入力端子ｇｅ及び反転入力端子ｒｅを有する。ゲート４１は反転入力端子ｒｅに入力される入力信号ｒｅの反転論理と入力端子ｇｅに入力される入力信号ｇｅとの論理積を取るゲートである。ＯＲゲート４２，４３はそれぞれ、入力される二つの入力信号の論理和を取るゲートである。
【０２００】
制御回路ＣＴＬ５の接続状態について説明を行う。ゲート４１の反転入力端子にはテスト端子ＴＥＳＴが接続される。ゲート４１の入力端子ｇｅには保持端子ＨＬＤ０が接続される。ゲート４１の出力端子はＯＲゲート４２，４３のそれぞれの一方の入力端子に共通に接続される。ＯＲゲート４２の他方の入力端子にはテスト保持端子ＴＨＬＤ０が接続される。ＯＲゲート４３の他方の入力端子にはシフトモード端子ＳＭが接続される。ＯＲゲート４２の出力端子はテスト回路ＴＣにテスト保持制御信号ｔｈｌｄを出力し、ＯＲゲート４３の出力端子はテスト回路ＴＣにシフトモード制御信号ｓｍを出力する。
【０２０１】
図２１に示される制御回路の回路動作を以下にまとめる。回路動作としては、通常動作の制御及びスキャンテスト動作の制御が存在する。通常動作及びスキャンテストにおける、制御回路ＣＴＬ５に関するそれぞれの信号及びデータの最適な設定値を表４に示す。
【０２０２】
【表４】

【０２０３】
通常動作における制御回路ＣＴＬ５の回路動作と制御回路ＣＴＬ３の回路動作の違いについて説明を行う。通常動作時には制御回路ＣＴＬ３における設定と同様にテスト制御信号ＴＥＳＴを“０”と設定するが、とくに制御回路ＣＴＬ５ではシフトモード制御信号ＳＭ及びテスト保持制御信号ＴＨＬＤ０をそれぞれ“０”とする。以上の設定によって、通常動作時における制御回路ＣＴＬ５の回路動作は制御回路ＣＴＬ３の回路動作と同一となる。
【０２０４】
スキャンテスト動作における制御回路ＣＴＬ５の回路動作は制御回路ＣＴＬ３の回路動作と同一であるので、説明は省略する。
【０２０５】
制御回路ＣＴＬ５を用いてテスト回路ＴＣの制御を行っても、実施の形態２において示される通常動作の制御及びスキャンテスト動作の制御を得ることが可能である。
【０２０６】
制御回路ＣＴＬ５は三つのゲートから構成されるので、テスト保持制御信号を“０”として制御回路ＣＴＬ５を用いて制御を行うことによって、半導体装置の回路面積を縮小することが可能である。
【０２０７】
制御回路ＣＴＬ５と同様に構成され、同一の働きを持つ制御回路ＣＴＬ５ａを図２２に示す。
【０２０８】
制御回路ＣＴＬ５ａの構成及び接続についての説明を、制御回路ＣＴＬ５の構成との違いをふまえて行う。制御回路ＣＴＬ５ａは制御回路ＣＴＬ５と同様に、ゲート４１ａ及びＯＲゲート４２ａ，４３ａという三つのゲートを用いて構成可能である。ゲート４１ａ及びＯＲゲート４２ａ，４３ａはそれぞれ、ゲート４１及びＯＲゲート４２，４３と同一の構成及び働きを有する。
【０２０９】
制御回路ＣＴＬ５においてはＯＲゲート４３の一方の入力端子にはゲート４１の出力端子が接続されていたが、制御回路ＣＴＬ５ａにおいてはＯＲゲート４３ａの一方の入力端子にはＯＲゲート４２ａの出力端子が接続される。
【０２１０】
以上の接続の違いによって制御回路ＣＴＬ５の回路動作と制御回路ＣＴＬ５ａの回路動作に違いは生じないので、回路動作に関する説明は省略する。
【０２１１】
制御回路ＣＴＬ５ａは制御回路ＣＴＬ５と同様に構成され、制御回路ＣＴＬ５ａの回路動作は制御回路ＣＴＬ５の回路動作と同一である。従って、制御回路ＣＴＬ５ａを用いることによって、制御回路ＣＴＬ５と同様の効果を得ることが可能である。
【０２１２】
次に、実施の形態１において示される制御回路ＣＴＬ２と同様に、テスト制御信号ＴＥＳＴを受けずにテスト回路ＴＣ，ＣＴＣを制御できる制御回路ＣＴＬ６について説明を行う。
【０２１３】
図２３は本実施の形態に従う制御回路ＣＴＬ６を示す回路図である。制御回路ＣＴＬ５においてはシフトモード制御信号ＳＭを“０”と設定したが、さらにスキャンテスト動作時に保持制御信号ＨＬＤ０を“０”とすることによって、制御回路ＣＴＬ６においてはテスト端子ＴＥＳＴが省略されている。
【０２１４】
出力側のテスト回路ＴＣに制御回路ＣＴＬ６を設けるときには、
保持制御信号ＨＬＤ０ → 保持制御信号ＨＬＤ１
テスト保持制御信号ＴＨＬＤ０ → テスト保持制御信号ＴＨＬＤ１
のように変換すれば良い。
【０２１５】
制御回路ＣＴＬ６の構成について図２３に基づき説明を行う。制御回路ＣＴＬ６はセレクタ５とＯＲゲート４５によって構成される。
【０２１６】
制御回路ＣＴＬ６の接続状態について説明を行う。セレクタ５はデータ入力０端子及びデータ入力１端子、出力端子ならびに制御端子を有するセレクタである。保持端子ＨＬＤ０はセレクタ５のデータ入力０端子及びＯＲゲート４５の一方の入力端子に共通に接続される。セレクタ５のデータ入力１端子にはテスト保持端子ＴＨＬＤ０が接続される。シフトモード端子ＳＭはセレクタ５の制御端子及びＯＲゲート４５の他方の入力端子に共通に接続される。セレクタ５の出力端子はテスト回路ＴＣにテスト保持制御信号ｔｈｌｄを出力し、ＯＲゲート４５の出力端子はテスト回路ＴＣにシフトモード制御信号ｓｍを出力する。
【０２１７】
図２３に示される制御回路の回路動作を以下にまとめる。回路動作としては、通常動作の制御及びスキャンテスト動作の制御が存在する。通常動作及びスキャンテストにおける、制御回路ＣＴＬ６に関するそれぞれの信号及びデータの最適な設定値を表５に示す。
【０２１８】
【表５】

【０２１９】
通常動作においては、シフトモード制御信号ＳＭを“０”とすることによって、制御回路ＣＴＬ３，ＣＴＬ５の回路動作と同一の回路動作を得ることが可能となる。
【０２２０】
次に、スキャンテスト動作における制御回路ＣＴＬ６の回路動作について説明を行う。スキャンテスト動作においては、テストパターンのシフトイン、テスト結果のシフトアウト及びデータの保持を行うときには、シフトモード制御信号ＳＭを“１”とする。このときの制御回路ＣＴＬ６の回路動作は制御回路ＣＴＬ３，ＣＴＬ５の回路動作と同一である。スキャンテスト動作において、実行を行うときには、シフトモード制御信号ＳＭを“０”、かつ保持制御信号ＨＬＤ０を“０”とすることによって、制御回路ＣＴＬ６の回路動作は制御回路ＣＴＬ３，ＣＴＬ５の回路動作と同一となる。
【０２２１】
従って、制御回路ＣＴＬ６を用いてテスト回路ＴＣの制御を行っても、実施の形態２において示される通常動作の制御及びスキャンテスト動作の制御を得ることが可能である。
【０２２２】
スキャンテスト動作時に保持制御信号ＨＬＤ０を“０”と設定することによって、テスト端子ＴＥＳＴを用いることなく制御回路ＣＴＬ６はテスト回路ＴＣの制御を行うことが可能である。テスト端子ＴＥＳＴを省くことができるので、本実施の形態に従う制御回路を用いると半導体装置の回路面積が縮小される。
【０２２３】
制御回路ＣＴＬ６と同様に構成され、同一の働きを持つ制御回路ＣＴＬ６ａを図２４に示す。
【０２２４】
制御回路ＣＴＬ６ａの構成について図２４に基づき説明を行う。制御回路ＣＴＬ６を構成するセレクタ５とＯＲゲート４５と同一の構成及び働きを有するセレクタ５ａとＯＲゲート４５ａによって制御回路ＣＴＬ６ａは構成される。
【０２２５】
制御回路ＣＴＬ６では、ＯＲ回路４５の一方の入力端子には保持端子ＨＬＤ０が接続されていたが、制御回路ＣＴＬ６ａではセレクタ４５ａの一方の入力端子にはセレクタ５ａの出力端子が接続されている。この接続状態の違いによっては回路動作の違いは生じず、制御回路ＣＴＬ６ａの回路動作は制御回路ＣＴＬ６の回路動作と同一であり、制御回路ＣＴＬ６ａを用いても制御回路ＣＴＬ６と同様の動作を行うことが可能である。
【０２２６】
従って、制御回路ＣＴＬ６ａを用いてテスト回路ＴＣの制御を行っても、実施の形態２において示される通常動作の制御及びスキャンテスト動作の制御を得ることが可能である。また、制御回路ＣＴＬ６による効果と同一の効果を制御回路ＣＴＬ６ａを用いることによって得ることが可能である。
【０２２７】
次に、本実施の形態にて示される制御回路の構成をさらに簡易化する事によって得られる制御回路を示す。
【０２２８】
図２５は本実施の形態に従う制御回路ＣＴＬ７を示す回路図である。制御回路ＣＴＬ７に備えられる端子は制御回路ＣＴＬ６に備えられる端子と同一である。また、制御回路ＣＴＬ７の回路構成は制御回路ＣＴＬ５の回路構成と酷似している。通常動作及びスキャンテストにおける、制御回路ＣＴＬ７に関するそれぞれの信号及びデータの最適な設定値を表６に示す。
【０２２９】
【表６】

【０２３０】
制御回路ＣＴＬ７においては、通常動作時にシフトモード制御信号ＳＭ及びテスト保持制御信号ＴＨＬＤ０をそれぞれ“０”とし、スキャンテスト動作時には保持制御信号ＨＬＤ０を“０”と設定することによって、少ない回路構成でも制御回路ＣＴＬ５，ＣＴＬ６と同一の回路動作が得られる。
【０２３１】
制御回路ＣＴＬ７の構成及び接続状態について図２５に基づき説明を行う。制御回路ＣＴＬ７は制御回路ＣＴＬ５と同様に、ゲート５０及びＯＲゲート５１，５２という三つのゲートを用いて構成可能である。ゲート５０は制御回路ＣＴＬ５を構成するゲート４１と同一の構成及び働きを有する。
【０２３２】
制御回路ＣＴＬ７の接続状態について、制御回路ＣＴＬ５との違いをふまえて説明を行う。制御回路ＣＴＬ５においては、ゲート４１の反転入力端子ｒｅにテスト端子ＴＥＳＴが接続され、ＯＲゲート４３の一方の入力端子に保持端子ＨＬＤ０が接続されていた。ゲート５０の反転入力端子にはシフトモード端子ＳＭが接続され、ＯＲゲート５２の一方の入力端子に保持端子ＨＬＤ０が接続される。他の端子の接続は制御回路ＣＴＬ５と制御回路ＣＴＬ７において同様である。
【０２３３】
制御回路ＣＴＬ７の回路動作を理解するためには、テスト保持端子ＴＥＳＴの代わりにシフトモード制御端子ＳＭが反転入力端子ｒｅに接続されるゲート５０の動作と、また一方の入力端子に保持端子ＨＬＤ０が接続されるＯＲゲート５２の動作について理解をすれば足りる。
【０２３４】
まずゲート５０の動作について説明を行う。制御回路ＣＴＬ５を用いる制御動作においては、通常動作及びスキャンテスト動作時にテスト制御信号ＴＥＳＴとシフトモード制御信号ＳＭの値が異なるのは、スキャンテストの実行時のみである。そこで、反転入力端子ｒｅにシフトモード端子ＳＭが接続されるゲート５０については、スキャンテストの実行時のみを考えれば良い。しかし、スキャンテスト実行時には、セレクタ３の制御端子に出力端子が接続されるＯＲゲート５２が“０”を出力すれば良いだけであり、制御回路ＣＴＬ７においてはスキャンテスト動作時に保持制御信号ＨＬＤ０が“０”、スキャンテストの実行時にはシフトモード制御信号ＳＭが“０”と設定されるので、この条件は満足される。従って、ゲート５０の動作はスキャンテストの実行には影響を与えない。
【０２３５】
次にＯＲゲート５２の動作について説明を行う。シフトモード制御信号ＳＭが“１”ならば必ずＯＲゲート５２は“１”を出力し、ＯＲゲート４３の動作と同一である。よって、シフトモード制御信号ＳＭが“０”となる通常動作時とスキャンテストの実行時についてのみ理解すれば良い。スキャンテストの実行時に関する説明については既にゲート５０の動作の説明時に成されている。通常動作時にはＯＲゲート５２は“０”を出力すれば良く、通常動作時に保持制御信号ＨＬＤ０は“０”と設定されるのでこの条件は満足される。
【０２３６】
上述の説明より、制御回路ＣＴＬ７の回路動作と制御回路ＣＴＬ５の回路動作は同一であることがわかる。
【０２３７】
従って、制御回路ＣＴＬ７を用いてテスト回路ＴＣの制御を行っても、実施の形態２において示される通常動作の制御及びスキャンテスト動作の制御を得ることが可能である。
【０２３８】
制御回路ＣＴＬ７は三つのゲートから構成されるので、テスト保持制御信号ＴＨＬＤ０を“０”として制御回路ＣＴＬ７を用いて制御を行うことによって、制御回路ＣＴＬ６を用いて制御する場合よりも半導体装置の回路面積を縮小することが可能である。
【０２３９】
また、スキャンテスト動作時に保持制御信号ＨＬＤ０を“０”と設定することによって、テスト端子ＴＥＳＴを用いることなく制御回路ＣＴＬ７はテスト回路ＴＣの制御を行うことが可能である。テスト端子ＴＥＳＴを省くことができるので、本実施の形態に従う制御回路を用いると半導体装置の回路面積がさらに縮小される。
【０２４０】
制御回路ＣＴＬ７と同様に構成され同一の働きを持つ、制御回路ＣＴＬ７ａを図２６に、制御回路ＣＴＬ７ｂを図２７に示す。図２６は本実施の形態に従う制御回路ＣＴＬ７ａを示す回路図であり、図２７は本実施の形態に従う制御回路ＣＴＬ７ｂを示す回路図である。
【０２４１】
制御回路ＣＴＬ７ａ，ＣＴＬ７ｂの構成と制御回路ＣＴＬ７の構成との違いについて図２６，２７に基づき説明を行う。ゲート５０ａ及びＯＲゲート５１ａ，５２ａによって制御回路ＣＴＬ７ａは構成され、ゲート５０ｂ及びＯＲゲート５１ｂ，５２ｂによって制御回路ＣＴＬ７ｂは構成される。ゲート５０ａ，５０ｂ、ＯＲゲート５１ａ，５１ｂ及びＯＲゲート５２ａ，５２ｂはそれぞれ、ゲート５０、ＯＲゲート５１及びＯＲゲート５２と同一の働き及び構成を有する。
【０２４２】
制御回路ＣＴＬ７ａ，ＣＴＬ７ｂの接続状態について、制御回路ＣＴＬ７との違いをふまえながら説明を行う。制御回路ＣＴＬ７においては、ＯＲ回路５２の一方の入力端子には保持端子ＨＬＤ０が接続されている。制御回路ＣＴＬ７ａにおいては、ＯＲゲート５２ａの一方の入力端子にはゲート５０ａの出力端子が接続されている。制御回路ＣＴＬ７ｂにおいては、ＯＲゲート５２ｂの一方の入力端子にはＯＲゲート５１ｂの出力端子が接続されている。
【０２４３】
上述の接続の違いによって、制御回路ＣＴＬ７，ＣＴＬ７ａ，ＣＴＬ７ｂの回路動作には違いは生じず、制御回路ＣＴＬ７ａ，ＣＴＬ７ｂを制御回路ＣＴＬ７の代わりに用いてテスト回路ＴＣの制御を行うことが可能である。
【０２４４】
本実施の形態にて示される様々な制御回路を用いることによって、テスト回路ＴＣの制御が可能となる。
【０２４５】
実施の形態４．
本実施の形態においては、実施の形態２において示されるテスト回路ＴＣとテスト回路ＣＴＣを用いてスキャンパスを構成し、ＲＡＭの動作試験に用いる。
【０２４６】
図２８は試験回路を設けられるＲＡＭを示す回路図である。実施の形態１〜３にて示された回路等と同一の構成、働き等を有するものに対しては同一の参照符号を付けるものとする。
【０２４７】
同図に示されるとおり、試験回路であるテスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣによって論理回路であるＲＡＭ１１は入出力の制御を行われる。
【０２４８】
まずＲＡＭ１１について説明する。ＲＡＭ１１への書き込みのために、アドレス書き込みのためのアドレス入力端子Ａ０［０］〜［２］及びデータ入力のための入力端子ＤＩ０［０］〜［２］をＲＡＭ１１は備える。さらに、ＲＡＭ１１からの読み出しのために、アドレス書き込みのためのアドレス入力端子Ａ１［０］〜［２］及びデータ出力のための入力端子ＤＯ１［０］〜［２］をＲＡＭ１１は備える。
【０２４９】
ＲＡＭ１１はアドレス入力端子Ａ０［０］〜［２］に与えられる入力データＡ０［０］〜［２］に対する固有の番地に入力端子ＤＩ０［０］〜［２］に与えられる入力データＤＩ０［０］〜［２］を書き込む回路である。また、ＲＡＭ１１はアドレス入力端子Ａ１［０］〜［２］に与えられる入力データＡ１［０］〜［２］に対応する固有の番地に入力されているデータを出力端子ＤＯ１［０］〜［２］から出力する回路である。本実施の形態において示されるＲＡＭ１１は３ビットであるが、どのようなビット数のＲＡＭに対しても本実施の形態に従う試験回路を適用することは可能である。
【０２５０】
アドレス入力端子Ａ０［０］〜［２］にデータを入力するための端子はデータ入力端子ＩＮＡ０［０］〜［２］であり、入力端子ＤＩ０［０］〜［２］にデータを入力するための端子はデータ入力端子ＩＮＤＩ［０］〜［２］である。アドレス入力端子Ａ１［０］〜［２］にデータを入力するための端子はデータ入力端子ＩＮＡ１［０］〜［２］である。出力端子ＤＯ１［０］〜［２］から出力するデータを出力するための端子はデータ出力端子ＯＵＴ［０］〜［２］である。
【０２５１】
次にテスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣに関する説明を行う。テスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡは、テスト回路ＴＣと同様の構成を持ち、同様の動作を行う試験回路である。アドレス入力端子Ａ０［０］〜［２］とＩＮＡ０［０］〜［２］との間にはテスト回路ＴＣＡ０が挿入される。入力端子ＤＩ０［０］〜［２］とＩＮＤＩ［０］〜［２］との間にはテスト回路ＴＣＤＩが挿入される。アドレス入力端子Ａ１［０］〜［２］とＩＮＡ１［０］〜［２］との間にはテスト回路ＴＣＡ１が挿入される。出力端子ＤＯ１［０］〜［２］とＯＵＴ［０］〜［２］との間にはテスト回路ＣＴＣが挿入される。
【０２５２】
次にスキャンテストを行う際に用いられるスキャンイン端子ＳＩ及びスキャンアウト端子ＳＯとテスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣとの接続について説明を行う。
【０２５３】
図２８においては、スキャンイン端子ＳＩ→スキャンフリップフロップ７０，７１→テスト回路ＴＣＡ０のスキャンイン端子ｓｉ→テスト回路ＴＣＡ０のスキャンアウト端子ｓｏ→テスト回路ＴＣＤＩのスキャンイン端子ｓｉ→テスト回路ＴＣＤＩのスキャンアウト端子ｓｏ→テスト回路ＴＣＡ１のスキャンイン端子ｓｉ→テスト回路ＴＣＡ１のスキャンアウト端子ｓｏ→テスト回路ＣＴＣのスキャンイン端子ｓｉ→テスト回路ＣＴＣのスキャンアウト端子ｓｏ→スキャンアウト端子ＳＯのようにスキャンパスは構成されている。スキャンフリップフロップ７０，７１はテスト回路ＴＣＡ０とテスト回路ＴＣＤＩとの間、テスト回路ＴＣＤＩとテスト回路ＴＣＡ１との間、テスト回路ＴＣＡ１とテスト回路ＣＴＣとの間、及びテスト回路ＣＴＣとスキャンアウト端子ＳＯとの間のうちのいずれに設けられても良い。
【０２５４】
スキャンフリップフロップ７０，７１について説明を行う。スキャンフリップフロップ７０，７１はそれぞれ、保持制御信号ＨＬＤ０，ＨＬＤ１を観察するために用いられるスキャンフリップフロップである。スキャンフリップフロップ７０，７１は図６に示されるスキャンフリップフロップＨＳＦＦと同様に、一つのセレクタと一つのフリップフロップによって構成される。スキャンフリップフロップＨＳＦＦを構成するセレクタ１４のデータ入力端子０端子、データ入力１端子及び制御端子をスキャンフリップフロップＨＳＦＦ自体のデータ入力端子０端子、データ入力１端子及び制御端子とみなすことが可能である。同様に、スキャンフリップフロップ７０，７１はデータ入力０端子及びデータ入力１端子、出力端子ならびに制御端子をそれぞれ備える。制御端子に入力される信号に応じて、スキャンフリップフロップ７０，７１はそれぞれ、データ入力０端子に入力される信号とデータ入力１端子に入力される信号とのうちからいずれか一方を出力する。
【０２５５】
テスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣにはそれぞれテスト保持端子ｔｈｌｄ及びシフトモード端子ｓｍが備えられ、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍがそれぞれ与えられる。また、テスト回路ＣＴＣには比較端子ｃｍｐｅｎ及び期待端子ｅｘｐ［０］〜［２］がさらに備えられ、比較イネーブル信号ＣＭＰＥＮ及び期待データＥＸＰ［０］〜［２］がそれぞれ与えられる。
【０２５６】
テスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣにそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える回路について説明を行う。セレクタ６０〜６５を用いて、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える回路を構成する。
【０２５７】
セレクタ６０〜６５はそれぞれ、データ入力０端子、データ入力１端子、出力端子及び制御端子を備えるセレクタである。セレクタ６０〜６５の制御端子にはテスト端子ＴＥＳＴが共通に接続される。
【０２５８】
セレクタ６０，６１の出力端子はそれぞれテスト回路ＴＣＡ０，ＴＣＤＩのそれぞれのテスト保持端子ｔｈｌｄに接続され、テスト保持制御信号ｔｈｌｄを互いに独立に与える。セレクタ６２の出力端子はテスト回路ＴＣＡ０，ＴＣＤＩのそれぞれのシフトモード端子ｓｍに共通に接続され、シフトモード制御信号ｓｍを共通に与える。同様に、セレクタ６３，６４の出力端子はそれぞれテスト回路ＴＣＡ１，ＣＴＣのそれぞれのテスト保持端子ｔｈｌｄに接続され、テスト保持制御信号ｔｈｌｄを互いに独立に与える。セレクタ６５の出力端子はテスト回路ＴＣＡ１，ＣＴＣのそれぞれのシフトモード端子ｓｍに共通に接続され、シフトモード制御信号ｓｍを共通に与える。
【０２５９】
次に保持端子について説明を行う。保持端子ＨＬＤ０はスキャンフリップフロップ７０及びセレクタ６０〜６２のそれぞれのデータ入力０端子に共通に接続される。同様に、保持端子ＨＬＤ１はスキャンフリップフロップ７１及びセレクタ６３〜６５のそれぞれのデータ入力０端子に共通に接続される。シフトモード端子ＳＭはセレクタ６２，６５のそれぞれのデータ入力１端子及びスキャンフリップフロップ７０，７１のそれぞれの制御端子に共通に接続される。セレクタ６０，６１のそれぞれのデータ入力１端子にはテスト保持端子ＴＨＬＤＡ０，ＴＨＬＤＤＩ０がそれぞれ接続される。セレクタ６３，６４のそれぞれのデータ入力１端子にはテスト保持端子ＴＨＬＤＡ１，ＴＨＬＤＤＯ１がそれぞれ接続される。
【０２６０】
図２８に示される回路の回路動作について説明を行う。回路動作としては、通常動作及びテスト動作が存在する。テスト動作とは通常のスキャンテスト動作及びテスト結果の圧縮機能を用いるスキャンテスト動作を含む動作である。
【０２６１】
まず、通常動作について説明を行う。通常動作時にはテスト制御信号ＴＥＳＴを“０”とし、比較イネーブル信号ＣＭＰＥＮを“０”とする。テスト制御信号ＴＥＳＴが“０”のときにセレクタ６０〜６５はデータ入力０端子に入力されるデータをそれぞれ出力する。従って、保持制御信号ＨＬＤ０がテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣＡ０，ＴＣＤＩに与えられる。保持制御信号ＨＬＤ１はテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣＡ１，ＣＴＣに与えられる。このとき、保持制御信号ＨＬＤ０が“０”ならば、入力データＩＮＡ０，ＩＮＤＩがそれぞれテスト回路ＴＣＡ０，ＴＣＤＩを介してＲＡＭ１１のアドレス入力端子Ａ０及び入力端子ＤＩに取り込まれる。保持制御信号ＨＬＤ０が“１”ならば、入力データＩＮＡ０，ＩＮＤＩがテスト回路ＴＣＡ０，ＴＣＤＩにて保持される。同様に、保持制御信号ＨＬＤ１が“０”ならば、入力データＩＮＡ１がテスト回路ＴＣＡ１を介してＲＡＭ１１のアドレス入力端子Ａ１に取り込まれる。出力データＤＯ１はテスト回路ＣＴＣを介してデータ出力端子ＯＵＴに出力される。保持制御信号ＨＬＤ１が“１”ならば、入力データＩＮＡ１及び出力データＤＯ１がテスト回路ＴＣＡ１，ＣＴＣにて保持される。
【０２６２】
すなわち、通常動作においては、保持制御信号ＨＬＤ０によってテスト回路ＴＣＡ０，ＴＣＤＩにおけるデータの保持を同時に制御する。また、保持制御信号ＨＬＤ１によってテスト回路ＴＣＡ１，ＣＴＣにおけるデータの保持を同時に制御する。従って、書き込み用のアドレス入力端子Ａ０及び入力端子ＤＩ０におけるデータの保持と、読み出し用のアドレス入力端子Ａ１及び出力端子ＤＯ１におけるデータの保持とが独立に制御される。
【０２６３】
次にテスト動作について説明する。テスト動作時にはテスト制御信号ＴＥＳＴを“１”とし、比較イネーブル信号ＣＭＰＥＮを“０”とする。テスト制御信号ＴＥＳＴが“１”のとき、セレクタ６０〜６５はデータ入力１端子に入力されるデータをそれぞれ出力する。このとき、テスト保持制御信号ＴＨＬＤＡ０及びシフトモード制御信号ＳＭがそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣＡ０に入力される。テスト保持制御信号ＴＨＬＤＤＩ０及びシフトモード制御信号ＳＭがそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣＤＩに入力される。また、テスト保持制御信号ＴＨＬＤＡ１及びシフトモード制御信号ＳＭがそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣＡ１に入力される。テスト保持制御信号ＴＨＬＤＤＯ１及びシフトモード制御信号ＳＭがそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＣＴＣに入力される。
【０２６４】
テスト動作における制御をまとめる。シフトモード制御信号ＳＭがテスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣに共通にシフトモード制御信号ｓｍとして入力され、テスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣにおいて入力されるデータの選択が制御される。テスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣにおけるデータの保持は、テスト保持制御信号ＴＨＬＤＡ０，ＴＨＬＤＤＩ０，ＴＨＬＤＡ１，ＴＨＬＤＤＯ１によってそれぞれ独立に成される。
【０２６５】
それぞれのテスト回路におけるデータの保持を独立に行うことによって、以下に述べる利点が生ずる。
【０２６６】
ＲＡＭ１１のアドレス入力端子Ａ０，Ａ１及び入力端子ＤＩから出力端子ＤＯまでのパスには、入力端子側の一つのフリップフロップ及び出力端子側の一つのフリップフロップから成る合計２個のフリップフロップが含まれると考える。ここで、ＲＡＭ１１を同期させなければならない論理回路１２が存在する場合を考える。論理回路１２の入力端子と出力端子の間のパスに、例えば三つのフリップフロップが含まれるとする。ＲＡＭ１１と論理回路１２との同期をとるためには、一個のフリップフロップをデータが通過するのに要する時間分だけＲＡＭ１１においてデータを保持すると良い。すなわち、パスに含まれるフリップフロップの数の違う分だけデータを保持することによって同期をとることが可能である。
【０２６７】
図２８に示される回路では、通常動作時において、書き込み用のアドレス入力端子Ａ０及び入力端子ＤＩにおけるデータの保持と、読み出し用のアドレス入力端子Ａ１及び出力端子ＤＯにおけるデータの保持とが独立に制御される。従って、同期をとらねばならない論理回路１２に含まれパスを形成するフリップフロップの数に柔軟に対応して、ＲＡＭ１１の出力を同期させることが可能である。
【０２６８】
試験動作時には、アドレス入力端子Ａ０におけるデータの保持と、入力端子ＤＩにおけるデータの保持と、アドレス入力端子Ａ１におけるデータの保持と、出力端子ＤＯにおけるデータの保持とが、それぞれ独立に制御される。従って、効率よくＲＡＭ１１の動作試験を行うことが可能である。
【０２６９】
次に、通常動作時においても、アドレス入力端子Ａ０におけるデータの保持と、入力端子ＤＩにおけるデータの保持と、アドレス入力端子Ａ１におけるデータの保持と、出力端子ＤＯにおけるデータの保持とを、それぞれ独立に制御することが可能な回路を図２９に示す。
【０２７０】
図２９は試験回路が設けられるＲＡＭを示す回路図である。図２８において示される回路と同様に、同図においては、試験回路であるテスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣによって論理回路であるＲＡＭ１１は入出力の制御を行われる。
【０２７１】
通常動作時においてデータの保持を独立に制御するために、図２８に示される保持端子を、
保持端子ＨＬＤ０→保持端子ＨＬＤＡ０，ＨＬＤＤＩ０
保持端子ＨＬＤ１→保持端子ＨＬＤＡ１，ＨＬＤＤＯ１
のように変換している。保持端子の変換に伴い、セレクタ及びスキャンフリップフロップに関しても、
セレクタ６２→セレクタ６２ａ，６２ｂ
セレクタ６５→セレクタ６５ａ，６５ｂ
スキャンフリップフロップ７０→スキャンフリップフロップ７０ａ，７０ｂ
スキャンフリップフロップ７１→スキャンフリップフロップ７１ａ，７１ｂ
のような変換が施されている。セレクタ６２ａ，６２ｂ，６５ａ，６５ｂはセレクタ６２，６５と同一の構成及び働きをそれぞれ有するセレクタである。同様に、スキャンフリップフロップ７０ａ，７０ｂ，７１ａ，７１ｂはスキャンフリップフロップ７０，７１と同一の構成及び働きをそれぞれ有するスキャンフリップフロップである。図２８に示される回路と異なる部分についてのみ、図２９に示される回路について以下に説明を行う。
【０２７２】
スキャンフリップフロップ７０ａ，７０ｂ，７１ａ，７１ｂについて説明を行う。スキャンフリップフロップ７０ａ，７０ｂ，７１ａ，７１ｂはそれぞれ、保持制御信号ＨＬＤＡ０，ＨＬＤＤＩ０，ＨＬＤＡ１，ＨＬＤＤＯ１を観察するために用いられるスキャンフリップフロップである。スキャンフリップフロップ７０ａ，７０ｂ，７１ａ，７１ｂはデータ入力０端子及びデータ入力１端子、出力端子ならびに制御端子をそれぞれ備える。制御端子に入力される信号に応じて、スキャンフリップフロップ７０ａ，７０ｂ，７１ａ，７１ｂはそれぞれ、データ入力０端子に入力される信号とデータ入力１端子に入力される信号とのうちからいずれか一方を出力する。
【０２７３】
テスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣにそれぞれテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える回路について説明を行う。セレクタ６０，６１，６２ａ，６２ｂ，６３，６４，６５ａ，６５ｂを用いて、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える回路を構成する。
【０２７４】
セレクタ６０，６１，６２ａ，６２ｂ，６３，６４，６５ａ，６５ｂはそれぞれ、データ入力０端子、データ入力１端子、出力端子及び制御端子を備えるセレクタである。これらのセレクタの制御端子にはテスト端子ＴＥＳＴが共通に接続される。
【０２７５】
セレクタ６０，６２ａのそれぞれの出力端子はテスト回路ＴＣＡ０のテスト保持端子ｔｈｌｄ及びシフトモード端子ｓｍに接続され、テスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える。同様の接続によって、セレクタ６１，６２ｂはテスト回路ＴＣＤＩにテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える。セレクタ６３，６５ａはテスト回路ＴＣＡ１にテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える。セレクタ６４，６５ｂはテスト回路ＣＴＣにテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍを与える。
【０２７６】
次に保持端子について説明を行う。保持端子ＨＬＤＡ０はスキャンフリップフロップ７０ａ及びセレクタ６０，６２ａのそれぞれのデータ入力０端子に共通に接続される。保持端子ＨＬＤＤＩ０はスキャンフリップフロップ７０ｂ及びセレクタ６１，６２ｂのそれぞれのデータ入力０端子に共通に接続される。同様に、保持端子ＨＬＤＡ１はスキャンフリップフロップ７１ａ及びセレクタ６３，６５ａのそれぞれのデータ入力０端子に共通に接続される。保持端子ＨＬＤＤＯ１はスキャンフリップフロップ７１ｂ及びセレクタ６３，６５ｂのそれぞれのデータ入力０端子に共通に接続される。シフトモード端子ＳＭはセレクタ６２ａ，６２ｂ，６５ａ，６５ｂのそれぞれのデータ入力１端子及びスキャンフリップフロップ７０ａ，７０ｂ，７１ａ，７１ｂのそれぞれの制御端子に共通に接続される。セレクタ６０，６１のそれぞれのデータ入力１端子にはテスト保持端子ＴＨＬＤＡ０，ＴＨＬＤＤＩ０がそれぞれ接続される。セレクタ６３，６４のそれぞれのデータ入力１端子にはテスト保持端子ＴＨＬＤＡ１，ＴＨＬＤＤＯ１がそれぞれ接続される。
【０２７７】
図２９に示される回路の回路動作について説明を行う。図２８に示される回路と同じく、回路動作としては通常動作及びテスト動作が存在する。
【０２７８】
まず、通常動作について説明を行う。通常動作時にはテスト制御信号ＴＥＳＴを“０”とし、比較イネーブル信号ＣＭＰＥＮを“０”とする。テスト制御信号ＴＥＳＴが“０”のときにセレクタ６０，６１，６２ａ，６２ｂ，６３，６４，６５ａ，６５ｂはデータ入力０端子に入力されるデータをそれぞれ出力する。従って、保持制御信号ＨＬＤＡ０がテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣＡ０に与えられる。保持制御信号ＨＬＤＤＩ０がテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣＤＩに与えられる。同様に、保持制御信号ＨＬＤＡ１がテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＴＣＡ１に与えられる。保持制御信号ＨＬＤＤＯ１がテスト保持制御信号ｔｈｌｄ及びシフトモード制御信号ｓｍとしてテスト回路ＣＴＣに与えられる。
【０２７９】
従って、保持制御信号ＨＬＤＡ０，ＨＬＤＤＩ０，ＨＬＤＡ１，ＨＬＤＤＯ１の“０”，“１”をそれぞれ切り換えることによって、テスト回路ＴＣＡ０，ＴＣＤＩ，ＴＣＡ１，ＣＴＣにおける入力データＩＮＡ０，ＩＮＤＩ，ＩＮＡ１の入力及びＯＵＴの出力とデータの保持との切替を互いに独立に制御することが可能となる。
【０２８０】
次にテスト動作について説明する。テスト動作時にはテスト制御信号ＴＥＳＴを“１”とし、比較イネーブル信号ＣＭＰＥＮを“０”とする。テスト制御信号ＴＥＳＴが“１”のとき、セレクタ６０，６１，６２ａ，６２ｂ，６３，６４，６５ａ，６５ｂはデータ入力１端子に入力されるデータをそれぞれ出力する。前述のように、シフトモード端子ＳＭがセレクタ６２ａ，６２ｂ，６５ａ，６５ｂのそれぞれのデータ入力１端子に共通に接続される。また、図２８に示される回路と同様に、セレクタ６０，６１のそれぞれのデータ入力１端子にはテスト保持端子ＴＨＬＤＡ０，ＴＨＬＤＤＩ０がそれぞれ接続され、セレクタ６３，６４のそれぞれのデータ入力１端子にはテスト保持端子ＴＨＬＤＡ１，ＴＨＬＤＤＯ１がそれぞれ接続される。従って、テスト動作時における回路動作は、図２８に示される回路の回路動作と同一である。
【０２８１】
すなわち、図２９に示される回路においては、テスト動作時には図２８に示される回路の回路動作と同一の回路動作が得られる。通常動作時には、アドレス入力端子Ａ０におけるデータの保持と、入力端子ＤＩにおけるデータの保持と、アドレス入力端子Ａ１におけるデータの保持と出力端子ＤＯにおけるデータの保持とをそれぞれ独立に制御することが可能であり、さらに優れた効果が得られる。
【０２８２】
【発明の効果】
請求項１〜６に記載の構成によると、接続回路用入力端子と接続回路用出力端子との間に含まれる切替回路は一つである。従って、通常動作用の端子を接続回路用入力端子に接続することによってセットアップが小さくなり、通常動作時の回路速度が向上する。
【０２８３】
また、請求項１に記載の構成によると、制御回路用第１制御入力信号と制御回路用第２制御入力信号とのいずれか一方の論理を、制御回路用試験信号を受けることによって接続回路の制御において無視する制御回路が用いられる。従って、無視される制御入力信号の論理とは独立に接続回路の制御を行うことが可能となる。
【０２８４】
また、請求項２に記載の構成によると、制御回路用第１制御入力信号と制御回路用第２制御入力信号とを受けることによって接続回路を制御する制御回路が用いられる。従って、請求項１に記載される制御信号よりも少ない制御信号によって接続回路の制御を行うことが可能となる。
【０２８５】
また、請求項３に記載の構成によると、制御回路用第１及び第３制御入力信号と制御回路用第２制御入力信号とのいずれか一方を、制御回路用試験信号を受けることによって接続回路の制御において無視する制御回路が用いられる。従って、無視される制御入力信号の論理とは独立に接続回路の制御を行うことが可能となる。
【０２８６】
また、請求項４に記載の構成によると、制御回路用試験信号が第１論理をとるときには制御回路用第１及び第３制御入力信号も第１論理をとるという設定の元で、制御回路用第１及び第３制御入力信号と制御回路用第２制御入力信号とのいずれか一方を、制御回路用試験信号を受けることによって接続回路の制御において無視する制御回路が用いられる。従って、無視される制御入力信号の論理とは独立に接続回路の制御を行うことが可能となる。
【０２８７】
また、請求項５に記載の構成によると、通常動作時には制御回路用第１制御入力信号が第１論理をとるという設定の元で、制御回路用第１及び第３制御入力信号と制御回路用第２制御入力信号とのいずれか一方を、制御回路用第１制御入力信号を受けることによって接続回路の制御において無視する制御回路が用いられる。従って、無視される制御入力信号の論理とは独立に接続回路の制御を行うことが可能となる。
【０２８８】
また、請求項６に記載の構成によると、通常動作時には制御回路用第１及び第３制御入力信号がそれぞれ第１論理をとるという設定の元で、制御回路用第１及び第３制御入力信号と制御回路用第２制御入力信号とのいずれか一方を、制御回路用第１制御入力信号を受けることによって接続回路の制御において無視する制御回路が用いられる。従って、無視される制御入力信号の論理とは独立に接続回路の制御を行うことが可能となる。
【０２８９】
請求項７及び８に記載の構成によると、接続回路用第１及び第２制御入力信号が第２論理をとるときに、接続回路は信号の保持と試験結果の圧縮とを行う。従って、試験結果を圧縮することによって試験結果の観察回数を減少させることが可能となる。
【０２９０】
請求項９及び１０に記載の構成によると、接続回路用第１及び第２制御入力信号が第２論理をとるときに、比較信号の論理を切り換えることによって記憶回路に記憶されるデータの保持と試験結果の圧縮とを行う。従って、試験結果を圧縮することによって試験結果の観察回数を減少させることが可能となる。
【０２９１】
請求項１１に記載の構成によると、書き込み用制御回路による制御と読み出し用制御回路による制御は独立である。従って、書き込み用端子における同期動作と読み出し用端子における同期動作とを独立に制御することが可能となる。
【０２９２】
請求項１２に記載の構成によると、書き込みアドレス用制御回路による制御、書き込み入力用制御回路による制御、読み出しアドレス用制御回路による制御及び読み出し出力用制御回路による制御はそれぞれ独立である。従って、書き込み用アドレス端子における同期動作、書き込み用入力端子における同期動作、読み出し用アドレス端子における同期動作及び読み出し用出力端子における同期動作とをそれぞれ独立に制御することが可能となる。
【図面の簡単な説明】
【図１】 本発明の実施の形態１に従う、テスト回路ＴＣからなる試験回路及び制御回路ＣＴＬ１の備えられる論理回路を示す回路図である。
【図２】 接続回路ＣＣを示す回路図である。
【図３】 本発明に従うテスト回路ＴＣを示す回路図である。
【図４】 テスト回路ＴＣからなるスキャンパスが備えられる複数の論理回路を示す回路図である。
【図５】 スキャンフリップフロップＨＳＦＦが備えられる回路を示す回路図である。
【図６】 本発明に従うスキャンフリップフロップＨＳＦＦを示す回路図である。
【図７】 制御回路ＣＴＬ２を示す回路図である。
【図８】 ２入力のセレクタの構成を示す回路図である。
【図９】 制御回路ＣＴＬ２ａを示す回路図である。
【図１０】 実施の形態２に従うテスト回路ＣＴＣを含んでなる試験回路が備えられる論理回路を示す回路図である。
【図１１】 接続回路ＣＣＣを示す回路図である。
【図１２】 接続回路ＣＣＣｒを示す回路図である。
【図１３】 接続回路ＣＣＣによって構成されるテスト回路ＣＴＣを示す回路図である。
【図１４】 試験回路ＴＣ，ＣＴＣをそれぞれ制御する制御回路ＣＴＬ３，ＣＣＴＬ３を示す回路図である。
【図１５】 複数の論理回路にスキャンパスが備えられる構成を持つ回路を示す回路図である。
【図１６】 スキャンフリップフロップＨＳＦＦ，ＨＳＦＦａの備えられる回路を示す回路図である。
【図１７】 図１４に示される回路を入力側においてのみ示す回路図である。
【図１８】 制御回路ＣＴＬ３と同一の働きを有する制御回路ＣＴＬ３ａを示す回路図である。
【図１９】 スキャンフリップフロップＨＳＦＦを介して保持端子ＨＬＤ０が制御回路ＣＴＬ３に接続される構成を持つ回路を示す回路図である
【図２０】 実施の形態２に従うテスト回路ＴＣＳを示す回路図である。
【図２１】 実施の形態３に従う制御回路ＣＴＬ５を示す回路図である。
【図２２】 制御回路ＣＴＬ５ａを示す回路図である。
【図２３】 制御回路ＣＴＬ６を示す回路図である。
【図２４】 制御回路ＣＴＬ６ａを示す回路図である
【図２５】 制御回路ＣＴＬ７を示す回路図である。
【図２６】 制御回路ＣＴＬ７ａを示す回路図である。
【図２７】 制御回路ＣＴＬ７ｂを示す回路図である。
【図２８】 実施の形態４に従うスキャンパスが設けられるＲＡＭを示す回路図である。
【図２９】 図２８に示される回路がさらに改良されて構成される回路を示す回路図である。
【図３０】 保持機能付きの論理回路を示す回路図である。
【図３１】 フリップフロップ４をスキャン変換する様子を示す回路図である。
【図３２】 図３０に示されるフリップフロップがスキャン変換されて構成される回路を示す回路図である。
【図３３】 接続回路ＰＣＣを示す回路図である。
【符号の説明】
２，３，６０〜６５ セレクタ、４，４ｒ フリップフロップ、１１ ＲＡＭ、３０，３０ｒ Ｅｘ−ＯＲゲート、３１ ＮＡＮＤゲート、３１ｒ ゲート、３２ ＡＮＤゲート、Ａ０，１ アドレス入力端子、ＣＣ，ＣＣＣ，ＣＣＣｒ 接続回路、ＣＭＰＥＮ，ｃｃｍｐｅｎ，ｃｃｍｐｅｎｒ 比較端子，比較イネーブル信号、ＣＴＬ１〜７ 制御回路、ＤＩ，ｄ，ｃｄ，ｃｄｒ 入力端子，入力データ、ＤＯ 出力端子，出力データ、ＥＸＰ，ｅｘｐ，ｃｅｘｐ，ｃｅｘｐｒ 期待端子，期待データ、ＨＬＤ０，ＨＬＤ１ 保持端子，保持制御信号、ｑ 出力端子，シリアル入力データ、ＳＩ，ｓｉ，ｃｓｉ，ｃｓｉｒ スキャンイン端子、ＳＭ，ｓｍ，ｃｓｍ，ｃｓｍｒ シフトモード端子，シフトモード制御信号、ＳＯ，ｓｏ，ｃｓｏ，ｃｓｏｒ スキャンアウト端子、Ｔ，ｔ クロック端子、ＴＣ，ＴＣＡ０，ＴＣＡ１，ＴＣＤＩ，ＣＴＣ テスト回路、ＴＥＳＴ テスト端子，テスト制御信号、ＴＨＬＤ０，ＴＨＬＤ１，ｔｈｌｄ，ｃｔｈｌｄ，ｃｔｈｌｄｒ テスト保持端子，テスト保持制御信号。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test circuit, and more particularly to a scan path configuration circuit that configures a scan path provided around a logic circuit in order to test a logic circuit provided in a semiconductor device.
[0002]
[Prior art]
Conventionally, a design for providing a test facilitating circuit has been applied to a semiconductor device for an operation test of a logic circuit provided in the semiconductor device.
[0003]
Before describing the scan test based on the design for testability, first, the data circuit as the logic circuit and the input / output operation of the data circuit will be described with reference to FIG.
[0004]
FIG. 30 is a circuit diagram showing the data circuit 1 and a circuit for inputting / outputting data of the data circuit 1.
[0005]
Hereinafter, in the present specification, alphabetical reference marks representing data or signals and terminals are also used. For example, IN [0] may represent input data or a data input terminal.
[0006]
First, the data circuit 1 will be described. The data circuit 1 includes input terminals DI [0] to [3] and output terminals DO [0] to [3]. The data circuit 1 outputs unique output data DO [0] to [3] to the output terminals DO [0] to [3] with respect to the input data DI [0] to [3] given to the input terminals DI [0] to [3]. This is a circuit that outputs from [3]. Examples of the data circuit 1 include a combinational circuit or a storage circuit such as a RAM (Random Access Memory). Data input terminals IN [0] to [3] are connected to input terminals DI [0] to [3], data output terminals OUT [0] to [3] are connected to output terminals DO [0] to [3], which will be described later. The selectors 102 [0] to [3] and the flip-flops 4 [0] to [3] are connected to each other. Here, [number] added to data or a terminal represents a bit number of data. As described above, the data input to the terminal or the data output from the terminal is associated with the bit number. Therefore, when data or terminals are collectively called, or when it is not necessary to consider the difference due to the bit number, the bit number is omitted hereinafter. Even when the bit number is omitted, each data corresponds to a terminal of each bit number.
[0007]
Next, a circuit related to data input / output will be described. A selector 102 and a flip-flop 4 are inserted between the input terminal DI and the data input terminal IN of the data circuit 1 and between the output terminal DO and the data output terminal OUT in order to hold input or output data. The All the selectors 102 are simultaneously controlled by a holding control signal HLD0 input from the holding terminal HLD0. The flip-flop 4 is a D flip-flop or a flip-flop having the same function as the D flip-flop. The functions of the selector 102 and the flip-flop 4 are the same regardless of the bit number, and the functions do not change between the input side and the output side. Therefore, the selector 102 and the flip-flop 4 on the input side will be described below, but the output side is the same as the input side.
[0008]
The connection state will be described. The selector 102 has two data input terminals. One is a data input 0 terminal selected and connected when the holding control signal HLD0 is “0”, and the other is a data input 1 terminal selected and connected when the holding control signal HLD0 is “1”. A data input terminal IN is connected to the data input 0 terminal, and an output terminal of the flip-flop 4 is connected to the data input 1 terminal. The output terminal of the selector 102 is connected to the input terminal of the flip-flop 4. The output terminal of the flip-flop 4 is commonly connected to the input terminal DI and the data input 1 terminal of the selector 102 as described above.
[0009]
The circuit operation in the above connection state will be described. When the holding control signal HLD0 is “0”, data input to the data input 0 terminal of the selector 102 is connected to the output terminal of the selector 102. Accordingly, the input data IN is given to the input terminal DI via the selector 102 and the flip-flop 4. Since the data input 1 terminal is selected when the holding control signal HLD0 is “1”, data output from the output terminal of the flip-flop 4 is applied to the input terminal of the flip-flop 4 via the selector 102. Therefore, the data of the flip-flop 4 is retained.
[0010]
The circuit operations in the circuit shown in FIG. 30 are summarized as follows for the input side and the output side. When the holding control signal HLD0 is “0”, the input data IN is input to the input terminal DI, and the output data DO is output from the data output terminal OUT. That is, the input and output are synchronized. When the holding control signal HLD0 is “1”, the selector 102 and the flip-flop 4 hold the input data DI and the output data DO, respectively.
[0011]
Next, the scan test will be described.
[0012]
What is a scan test?
1. Provide a scan path in the circuit to be tested,
2. A test pattern is given to the circuit from the scan path,
3. The output data output by the circuit for the test pattern is captured again in the scan path,
4). Analyze the results
That's it. A scan test is a method for design for testability. Scan campus is realized by converting a flip-flop connected to an input or output terminal of a circuit to be tested into a scan flip-flop.
[0013]
FIG. 31 is a circuit diagram showing how the flip-flop 4 is converted into a scan flip-flop SFF. The scan conversion in this case is to connect the selector 103 to the input terminal of the flip-flop 4. The output of the selector 103 is switched by a shift mode signal SM. Data D is input to the data input 0 terminal of the selector 103, and scan-in data SI is input to the data input 1 terminal. When the shift mode signal SM is “0”Data DIs selected and when it is “1”Scan-in data SIIs selected and input to the flip-flop 4.
[0014]
FIG. 32 is a circuit diagram showing the data circuit 1 provided with a scan path. A connection circuit PCC [0] to [3] composed of the selectors 102 and 103 and the flip-flop 4 is connected between the data input terminals IN [0] to [3] and the input terminals DI [0] to [3] on the input side. Connected to each. Similarly, on the output side, connection circuits PCC [0] to [3] are inserted between the output terminals DO [0] to [3] and the data output terminals OUT [0] to [3], respectively. The connection circuit PCC is shown in FIG.
[0015]
Since the function of the connection circuit PCC is the same between the input side and the output side, the connection state of the connection circuit PCC shown in FIG. 33 will be described by taking the input side as an example as in FIG.
[0016]
The data input terminal IN of the selector 102 is connected to the data input terminal IN, and the data input 1 terminal is connected to the output terminal of the flip-flop 4. The output terminal of the selector 102 is connected to the data input 0 terminal of the selector 103. A scan-in terminal SI is connected to the data input 1 terminal of the selector 103. The output terminal of the selector 103 is connected to the input terminal of the flip-flop 4, the output data of the flip-flop 4 is input to the data input 1 terminal of the selector 102 as described above, and the scan-out data SO or serial input data of the connection circuit PCC. Q is output.
[0017]
Here, as shown in FIG. 32, the scan-out data SO becomes the scan-in data SI of the connection circuit PCC having the next bit number, and is applied to the scan-in terminal SI of the connection circuit PCC.inputIs done. Here, the scan-out data SO of the input-side connection circuit PCC [3] becomes the scan-in data SI of the output-side connection circuit PCC [0], and the scan-out data SO of the output-side connection circuit PCC [3] is the scan path. It is output as the entire scan-out data SO.
[0018]
Next, circuit operation will be described. As the operation of the circuit shown in FIG. 32, there are a normal operation and a scan test operation.
[0019]
First, the normal operation will be described. The normal operation of the circuit shown in FIG. 32 is the same as the operation of the circuit shown in FIG.
[0020]
During normal operation, the shift mode control signal SM is set to “0”. At this time, if the holding control signal HLD0 is “0”, the input data IN is taken into the input terminal DI of the data circuit 1 via the connection circuit PCC on the input side. On the output side, the output data DO is output to the data output terminal OUT via the connection circuit PCC. If the holding control signal HLD0 is “1”, the input data IN and the output data DO are held in the connection circuit PCC, respectively.
[0021]
Next, the scan test operation will be described. During the scan test, the test pattern is shifted in, executed, and the test result is shifted out in order.
[0022]
1. Test pattern shift-in
As a preparation for inputting a test pattern to the data circuit 1, the test pattern is shifted into the connection circuit PCC on the input side. When the shift mode control signal SM is “1”, the test pattern input to the data circuit 1 can be shifted in from the scan-in terminal SI. Since the conventional data circuit 1 has 4 bits, a 4-bit test pattern is shifted in. The test pattern is shifted in the order of the input side connection circuits PCC [0] → PCC [1] → PCC [2] → PCC [3], and the test patterns are input to the input side connection circuits PCC [0] to [3]. Entered.
[0023]
2. Execution
The shift mode control signal SM is set to “0”. At this time, if the holding control signal HLD0 is “1”, the data after the shift-in of the test pattern, that is, the test pattern is held in the connection circuit PCC on the input side. In the output side connection circuit PCC, the data after the completion of the test pattern shift-in is held. If the hold control signal HLD0 is “0” when the shift mode control signal SM is set to “0”, the input data IN is taken into the input terminal DI, and the output data DO which is the test result of the data circuit 1 is output as data. Output to the terminal OUT. Thereafter, when the holding control signal HLD0 is changed from “0” to “1”, the input data IN is held in the input side connection circuit PCC, and the output data DO which is the test result is held in the output side connection circuit PCC. Is done.
[0024]
3. Shift out test results
The shift mode control signal SM is set to “1”. At this time, the test results are sequentially shifted out from the scan-out terminal SO.
[0025]
The above is the circuit operation of the circuit shown in FIG.
[0026]
[Problems to be solved by the invention]
As shown in FIG. 32, the conventional scan path circuit includes two selectors 102 and 103 between the data input terminal IN for normal operation and the input terminal DI of the data circuit 1. Similarly, two selectors 102 and 103 are included between the output terminal DO of the data circuit 1 and the data output terminal OUT for normal operation. Therefore, there is a problem in that the setup becomes large and the circuit speed during normal operation decreases.
[0027]
SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a scan path configuration circuit for an operation test of a logic circuit, which can obtain a high speed operation during a normal operation.
[0028]
[Means for Solving the Problems]
  The scan path configuration circuit according to claim 1 includes first and second switching circuits and a memory circuit, and includes a connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are provided with the first and second control terminals, respectively. The first switching circuit includes a first switching circuit, one input terminal for the first switching circuit, the other input terminal for the first switching circuit, an output terminal for the first switching circuit, and a second switching logic. 1 switching circuit control terminal, the second switching circuit has a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal and a second switching circuit control terminal. And the memory circuit is an input terminal for the memory circuit. And the output terminal for the memory circuit, the control terminal for the first switching circuit constitutes the first control terminal for the connection circuit, the one input terminal for the first switching circuit constitutes the input terminal for the connection circuit, and When the first control signal takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit, and when the first control signal for the connecting circuit takes the second logic, the first switching is made. The other input terminal for the circuit is connected to the output terminal for the first switching circuit, the control terminal for the second switching circuit constitutes the second control terminal for the connection circuit, and the one input terminal for the second switching circuit is the test input for the connection circuit When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit, and the second control signal for the connection circuit is the second When taking logic, the other input terminal for the second switching circuit is connected to the output for the second switching circuit. The second switching circuit output terminal is connected to the first switching circuit other input terminal, the first switching circuit output terminal is connected to the memory circuit input terminal, and the memory circuit output terminal is the connection circuit. And a control circuit first and second control input terminal, and a control circuit first and second control output. Control circuit test terminal, control circuit first and second control input terminals and control circuit test terminals are input with control circuit first and second control input signals and control circuit test signals, respectively. The first and second control output signals for the control circuit are output from the first and second control output terminals for the control circuit, respectively, and the first and second control input signals for the control circuit and the first and second control circuit signals are output. 2 Control output signal And the control circuit test signal each take binary logic, and when the control circuit test signal takes either binary logic, the logic of the control circuit first and second control output signals is for the control circuit. When the control circuit test signal takes the other of the binary logic and is equal to the logic of the second control input signal,2The logic of the control output signal is equal to the inverted logic of the first control input signal for the control circuit.1The logic of the control output signal is equal to the logic of the first control input signal for the control circuit, the first control output terminal for the control circuit is connected to the first control terminal for the connection circuit, and the second control output terminal for the control circuit is the connection circuit. And a control circuit that controls the connection circuit by being connected to the second control terminal.
[0029]
  The scan path configuration circuit according to claim 2 includes first and second switching circuits and a memory circuit, and includes a connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are provided with the first and second control terminals, respectively. The first switching circuit includes a first switching circuit, one input terminal for the first switching circuit, the other input terminal for the first switching circuit, an output terminal for the first switching circuit, and a second switching logic. 1 switching circuit control terminal, the second switching circuit has a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal and a second switching circuit control terminal. And the memory circuit is an input terminal for the memory circuit. And the output terminal for the memory circuit, the control terminal for the first switching circuit constitutes the first control terminal for the connection circuit, the one input terminal for the first switching circuit constitutes the input terminal for the connection circuit, and When the first control signal takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit, and when the first control signal for the connecting circuit takes the second logic, the first switching is made. The other input terminal for the circuit is connected to the output terminal for the first switching circuit, the control terminal for the second switching circuit constitutes the second control terminal for the connection circuit, and the one input terminal for the second switching circuit is the test input for the connection circuit When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit, and the second control signal for the connection circuit is the second When taking logic, the other input terminal for the second switching circuit is connected to the output for the second switching circuit. The second switching circuit output terminal is connected to the first switching circuit other input terminal, the first switching circuit output terminal is connected to the memory circuit input terminal, and the memory circuit output terminal is the connection circuit. A connection circuit comprising an output terminal for the second switching circuit and connected to the other input terminal for the second switching circuit, the first and second control input terminals for the control circuit, and the first and second control outputs for the control circuit The first and second control input terminals for the control circuit are respectively input with the first and second control input signals for the control circuit, and the first and second control output terminals for the control circuit are respectively for the control circuit. First and second control output signals are output, and the first and second control input signals for the control circuit and the first and second control output signals for the control circuit each take binary logic, and the first control for the control circuit Input signal is first logic The logic of the first and second control output signals for the control circuit is equal to the logic of the second control input signal for the control circuit, and when the first control input signal for the control circuit takes the second logic,2The logic of the control output signal is equal to the inverted logic of the first control input signal for the control circuit.1The logic of the control output signal is equal to the logic of the control circuit first control input signal, the control circuit first control output terminal is connected to the connection circuit first control terminal, and the control circuit second control output terminal is connected to the connection circuit. And a control circuit that controls the connection circuit by being connected to the second control terminal.
[0030]
The scan path configuration circuit according to claim 3 includes first and second switching circuits and a memory circuit, and includes a connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit use. The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are provided with the first and second control terminals, respectively. The first switching circuit includes a first switching circuit, one input terminal for the first switching circuit, the other input terminal for the first switching circuit, an output terminal for the first switching circuit, and a second switching logic. 1 switching circuit control terminal, the second switching circuit has a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal and a second switching circuit control terminal. And the memory circuit is an input terminal for the memory circuit. And the output terminal for the memory circuit, the control terminal for the first switching circuit constitutes the first control terminal for the connection circuit, the one input terminal for the first switching circuit constitutes the input terminal for the connection circuit, and When the first control signal takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit, and when the first control signal for the connecting circuit takes the second logic, the first switching is made. The other input terminal for the circuit is connected to the output terminal for the first switching circuit, the control terminal for the second switching circuit constitutes the second control terminal for the connection circuit, and the one input terminal for the second switching circuit is the test input for the connection circuit When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit, and the second control signal for the connection circuit is the second When taking logic, the other input terminal for the second switching circuit is connected to the output for the second switching circuit. The second switching circuit output terminal is connected to the first switching circuit other input terminal, the first switching circuit output terminal is connected to the memory circuit input terminal, and the memory circuit output terminal is the connection circuit. And a control circuit first to third control input terminals, first and second control outputs for the control circuit, and an output terminal for the control circuit and connected to the other input terminal for the second switching circuit And control circuit test terminals. The control circuit first to third control input signals and the control circuit test signals are input to the control circuit first to third control input terminals and the control circuit test terminal, respectively. The control circuit first and second control output signals are output from the control circuit first and second control output terminals, respectively, and the control circuit first to third control input signals and the control circuit first and second control output signals are output. 2 Control output signal And the control circuit test signal each take binary logic, and when the control circuit test signal takes either binary logic, the logic of the control circuit first and second control output signals is for the control circuit. When the control circuit test signal takes the other of the binary logic, the logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit and is equal to the logic of the second control input signal. The logic of the second control output signal for circuit is equal to the logic of the third control input signal for control circuit, the first control output terminal for control circuit is connected to the first control terminal for connection circuit, and the second control output for control circuit The terminal includes a control circuit for controlling the connection circuit by being connected to the second control terminal for connection circuit.
[0031]
  The scan path configuration circuit according to claim 4 includes first and second switching circuits and a memory circuit, and includes a connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit use. The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are provided with the first and second control terminals, respectively. The first switching circuit includes a first switching circuit, one input terminal for the first switching circuit, the other input terminal for the first switching circuit, an output terminal for the first switching circuit, and a second switching logic. 1 switching circuit control terminal, the second switching circuit has a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal and a second switching circuit control terminal. And the memory circuit is an input terminal for the memory circuit. And the output terminal for the memory circuit, the control terminal for the first switching circuit constitutes the first control terminal for the connection circuit, the one input terminal for the first switching circuit constitutes the input terminal for the connection circuit, and When the first control signal takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit, and when the first control signal for the connecting circuit takes the second logic, the first switching is made. The other input terminal for the circuit is connected to the output terminal for the first switching circuit, the control terminal for the second switching circuit constitutes the second control terminal for the connection circuit, and the one input terminal for the second switching circuit is the test input for the connection circuit When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit, and the second control signal for the connection circuit is the second When taking logic, the other input terminal for the second switching circuit is connected to the output for the second switching circuit. The second switching circuit output terminal is connected to the first switching circuit other input terminal, the first switching circuit output terminal is connected to the memory circuit input terminal, and the memory circuit output terminal is the connection circuit. And a control circuit first to third control input terminals, first and second control outputs for the control circuit, and an output terminal for the control circuit and connected to the other input terminal for the second switching circuit And control circuit test terminals. The control circuit first to third control input signals and the control circuit test signals are input to the control circuit first to third control input terminals and the control circuit test terminal, respectively. The control circuit first and second control output signals are output from the control circuit first and second control output terminals, respectively, and the control circuit first to third control input signals and the control circuit first and second control output signals are output. 2 Control output signal And the control circuit test signal each take binary logic, the control circuit test signal takes either binary logic, and the control circuit first and third control input signals each take first logic. The logic of the first and second control output signals for the control circuit is equal to the logic of the second control input signal for the control circuit, and when the test signal for the control circuit takes the other of the binary logic,When the third control input signal for the control circuit takes the second logic, the first control input signal for the control circuit also takes the second logic,The logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit, the logic of the second control output signal for the control circuit is equal to the logic of the third control input signal for the control circuit, and the control circuit A first control output terminal for connection is connected to the first control terminal for connection circuit, and a second control output terminal for control circuit is connected to the second control terminal for connection circuit, thereby controlling the connection circuit. It is characterized by the following.
[0032]
The scan path configuration circuit according to claim 5 includes first and second switching circuits and a memory circuit, and includes a connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are provided with the first and second control terminals, respectively. The first switching circuit includes a first switching circuit, one input terminal for the first switching circuit, the other input terminal for the first switching circuit, an output terminal for the first switching circuit, and a second switching logic. 1 switching circuit control terminal, the second switching circuit has a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal and a second switching circuit control terminal. And the memory circuit is an input terminal for the memory circuit. And the output terminal for the memory circuit, the control terminal for the first switching circuit constitutes the first control terminal for the connection circuit, the one input terminal for the first switching circuit constitutes the input terminal for the connection circuit, and When the first control signal takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit, and when the first control signal for the connecting circuit takes the second logic, the first switching is made. The other input terminal for the circuit is connected to the output terminal for the first switching circuit, the control terminal for the second switching circuit constitutes the second control terminal for the connection circuit, and the one input terminal for the second switching circuit is the test input for the connection circuit When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit, and the second control signal for the connection circuit is the second When taking logic, the other input terminal for the second switching circuit is connected to the output for the second switching circuit. The second switching circuit output terminal is connected to the first switching circuit other input terminal, the first switching circuit output terminal is connected to the memory circuit input terminal, and the memory circuit output terminal is the connection circuit. And a control circuit first to third control input terminal and control circuit first and second control outputs, wherein the connection circuit is configured to be connected to the other input terminal for the second switching circuit. Control circuit first to third control input terminals are input to control circuit first to third control input signals, respectively, and control circuit first and second control output terminals are respectively used to control circuit First and second control output signals are output, and the first to third control input signals for the control circuit and the first and second control output signals for the control circuit each take binary logic, and the first control input for the control circuit The signal has the first logic The logic of the first and second control output signals for the control circuit is equal to the logic of the second control input signal for the control circuit, and when the first control input signal for the control circuit takes the second logic, The logic of one control output signal is equal to the logic of the first control input signal for the control circuit, the logic of the second control output signal for the control circuit is equal to the logic of the third control input signal for the control circuit, and the first control for the control circuit. The output terminal is connected to the connection circuit first control terminal, and the control circuit second control output terminal is connected to the connection circuit second control terminal to control the connection circuit. Features.
[0033]
The scan path configuration circuit according to claim 6 includes first and second switching circuits and a memory circuit, and includes a connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit use. The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are provided with the first and second control terminals, respectively. The first switching circuit includes a first switching circuit, one input terminal for the first switching circuit, the other input terminal for the first switching circuit, an output terminal for the first switching circuit, and a second switching logic. 1 switching circuit control terminal, the second switching circuit has a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal and a second switching circuit control terminal. And the memory circuit is an input terminal for the memory circuit. And the output terminal for the memory circuit, the control terminal for the first switching circuit constitutes the first control terminal for the connection circuit, the one input terminal for the first switching circuit constitutes the input terminal for the connection circuit, and When the first control signal takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit, and when the first control signal for the connecting circuit takes the second logic, the first switching is made. The other input terminal for the circuit is connected to the output terminal for the first switching circuit, the control terminal for the second switching circuit constitutes the second control terminal for the connection circuit, and the one input terminal for the second switching circuit is the test input for the connection circuit When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit, and the second control signal for the connection circuit is the second When taking logic, the other input terminal for the second switching circuit is connected to the output for the second switching circuit. The second switching circuit output terminal is connected to the first switching circuit other input terminal, the first switching circuit output terminal is connected to the memory circuit input terminal, and the memory circuit output terminal is the connection circuit. And a control circuit first to third control input terminal and control circuit first and second control outputs, wherein the connection circuit is configured to be connected to the other input terminal for the second switching circuit. Control circuit first to third control input terminals are input to control circuit first to third control input signals, respectively, and control circuit first and second control output terminals are respectively used to control circuit First and second control output signals are output, and the first to third control input signals for the control circuit and the first and second control output signals for the control circuit each take binary logic, and the first control input for the control circuit The signal has the first logic And third control for the control circuitinputWhen the signal takes the first logic, the logic of the first and second control output signals for the control circuit is equal to the logic of the second control input signal for the control circuit, and the first control input signal for the control circuit takes the second logic. The logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit, the logic of the second control output signal for the control circuit is equal to the logic of the third control input signal for the control circuit, A control circuit for controlling the connection circuit by connecting the first control output terminal for the control circuit to the first control terminal for the connection circuit, and connecting the second control output terminal for the control circuit to the second control terminal for the connection circuit; It is characterized by comprising.
[0034]
  8. The scan path configuration circuit according to claim 7, comprising a connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, a connection circuit first and second control terminal, and an expectation terminal, and a connection circuit. The first control signal for connection circuit input to the first control terminal for connection and the second control signal for connection circuit input to the second control terminal for connection circuit are composed of different first logic and second logic, respectively. When the first control signal for the connection circuit takes the first logic, the signal input to the input terminal for the connection circuit is output from the output terminal for the connection circuit, and the first control signal for the connection circuit is When the second control signal for the connection circuit takes the first logic, the signal input to the test input terminal for the connection circuit is output from the output terminal for the connection circuit, and the first and second connection circuit signals are output. Each control signal takes second logic If the logic of the signal input to the expected terminal matches the logic of the signal input to the connection circuit input terminal, the signal output from the connection circuit output terminal is output to the connection circuit output terminal. The first and third control input terminals for the control circuit, the first and third control input terminals for the control circuit, and the first and third control input terminals for the control circuit. A second control output terminal, and control circuit first to third control input signals are respectively input to the control circuit first to third control input terminals; First and second control output signals for the control circuit are output, respectively, and the first to third control input signals for the control circuit and the first and second control output signals for the control circuit take binary logic, respectively. The first control input signal is When the control circuit third control input signal takes the first logic, the control circuit first and second control output signals have the same logic as the control circuit second control input signal. When the circuit first control input signal takes the second logic, the logic of the control circuit first control output signal is equal to the logic of the control circuit first control input signal, and the logic of the control circuit second control output signal is The first control output terminal for the control circuit is connected to the first control terminal for the connection circuit, and the second control output terminal for the control circuit is connected to the second control terminal for the connection circuit. And a control circuit that controls the connection circuit by being connected.
The scan path configuration circuit according to claim 8, comprising a connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, a connection circuit first and second control terminal, and an expectation terminal, and the connection A first control signal for connection circuit input to the first control terminal for circuit and a second control signal for connection circuit input to the second control terminal for connection circuit are different from each other in first logic and second logic, respectively. When the first control signal for connection circuit takes the first logic, the signal input to the input terminal for connection circuit is output from the output terminal for connection circuit, and the connection circuit When the first control signal for the circuit takes the second logic and the second control signal for the connection circuit takes the first logic, the signal input to the test input terminal for the connection circuit is the output terminal for the connection circuit Output from When the circuit first and second control signals each take the second logic, the logic of the signal input to the expected terminal matches the logic of the signal input to the connection circuit input terminal. The signal output from the connection circuit output terminal is continuously output from the connection circuit output terminal, and when the signals do not match, the first logic is continuously output from the connection circuit output terminal. A control circuit first to third control input terminal, a control circuit first and second control output terminal, and a control circuit test terminal, the control circuit first to third control input terminal and the control circuit The control circuit test terminals are supplied with first to third control input signals for the control circuit and a test signal for the control circuit, respectively, and the first and second control output terminals for the control circuit respectively receive the first control circuit test signal. And a second control output signal, the control circuit first to third control input signals, the control circuit first and second control output signals, and the control circuit test signal each have the binary logic. When the control circuit test signal takes one of the binary logic, the logic of the control circuit first and second control output signals is equal to the logic of the control circuit second control input signal, When the control circuit test signal takes the other of the binary logic, the logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit, and the second control for the control circuit The logic of the output signal is equal to the logic of the third control input signal for the control circuit, the first control output terminal for the control circuit is connected to the first control terminal for the connection circuit, and the second control output terminal for the control circuit Is for the connection circuit And a control circuit for controlling the connection circuit by being connected to two control terminals.
[0035]
  Claim9In the scan path configuration circuit described in (1), the connection circuit further includes a comparison terminal and an expectation terminal, and includes an exclusive OR element, a NOT AND element, and a comparison signal input to the comparison terminal. Takes binary logic, the exclusive OR element has an exclusive OR element output terminal and two exclusive OR element input terminals, and the negative AND element has a negative AND element output terminal and two negation elements An AND element input terminal is provided. The AND element includes an AND element output terminal and two AND element input terminals. The connection between the memory circuit output terminal and the second input terminal for the second switching circuit is logical. One of the input terminals for the exclusive OR element constitutes an expected terminal, and the other input terminal for the exclusive OR element and the one input terminal for the first switching circuit are shared. Connected and exclusive OR element The output terminal is connected to one of the input terminals for the negative AND element, the other input terminal for the negative AND element constitutes a comparison terminal, and the output terminal for the negative AND element is one of the input terminals for the AND element The memory circuit output terminal is connected to the other one of the AND element input terminals.
[0036]
  Claim10In the scan path configuration circuit described in (1), the connection circuit further includes a comparison terminal and an expectation terminal, and includes an exclusive OR element and a negative AND element, and the storage circuit further includes a storage circuit initialization terminal, The comparison signal input to the comparison terminal takes binary logic, the exclusive OR element has an exclusive OR element output terminal and two exclusive OR element input terminals, and the negative AND element has negative logic. An output terminal for the product element and two input terminals for the negative logical product element, and either one of the input terminals for the exclusive OR element constitutes an expected terminal, and the other one of the input terminals for the exclusive OR element One input terminal for the switching circuit is connected in common, the output terminal for the exclusive OR element is connected to one of the input terminals for the negative AND element, and the other input terminal for the negative AND element is the comparison terminal Construct and disjunctive Use output terminal and being connected to the initialization terminal storage circuit.
[0037]
  Claim11The scan path configuration circuit described in 1 is a scan path configuration circuit provided in a RAM having a write terminal and a read terminal, and a connection circuit is prepared for each write terminal and for each read terminal. The connection circuit output terminal of the connection circuit prepared is connected to the write terminal, and the connection circuit input terminal of the connection circuit prepared to the read terminal is connected to the read terminal, respectively. The write control circuit for controlling the connection circuit prepared for each is a control circuit, and the read control circuit for controlling the connection circuit prepared for each read terminal is a control circuit. The control and the control by the reading control circuit are independent of each other.
[0038]
  Claim12The scan path configuration circuit described in 1 includes a write terminal and a read terminal, the read / write terminal includes a write address terminal and a write input terminal, and the read terminal is a read address terminal and a read output terminal. A scan path configuration circuit provided in a RAM comprising: a connection circuit prepared for each write address terminal; for each write input terminal; for each read address terminal; and for each read output terminal; A write address terminal is connected to each of the connection circuit output terminals of the connection circuit prepared for the address terminal for writing, and a write input terminal is respectively connected to the output terminal for the connection circuit of the connection circuit prepared for the input terminal for writing. The connection circuit input terminal of the connection circuit that is connected and prepared for the read address terminal Each read address terminal is connected, and a read output terminal is connected to each connection circuit input terminal of the connection circuit prepared for the read output terminal, and the connection circuit prepared for each write address terminal is controlled. The write address control circuit is a control circuit, and the write input control circuit for controlling the connection circuit prepared for each write input terminal is a control circuit, and the connection circuit prepared for each read address terminal. The read address control circuit that controls the read address control circuit is a control circuit, and the read output control circuit that controls the connection circuit prepared for each read output terminal is a control circuit. Control by write input control circuit, control by read address control circuit, and read output control circuit Characterized in that that control and are each independently.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a circuit diagram of a logic circuit provided with a control circuit and a test circuit according to the present embodiment. Components having the same configuration, function, etc. as those of the circuits shown in the prior art are given the same reference numerals.
[0040]
As shown in the figure, the data circuit 1 that is a logic circuit is controlled in input / output by a test circuit TC that is a test circuit.
[0041]
First, the data circuit 1 will be described. The data circuit 1 includes input terminals DI [0] to [3] and output terminals DO [0] to [3]. The data circuit 1 outputs unique output data DO [0] to [3] to the output terminals DO [0] to [3] with respect to the input data DI [0] to [3] given to the input terminals DI [0] to [3]. This is a circuit that outputs from [3]. Examples of the data circuit 1 include a combinational circuit or a storage circuit such as a RAM.
[0042]
Although the data circuit 1 shown in the present embodiment is 4 bits, the application of the test circuit according to the present invention is not limited to a 4-bit logic circuit, and can be applied to a logic circuit having any number of bits. It is possible to apply the test circuit of the present invention. [Number] added to data or a terminal represents a bit number of the data. As described above, the data input to the terminal or the data output from the terminal is associated with the bit number. Therefore, when data or terminals are collectively referred to, or when it is not necessary to consider the difference due to the bit number, the bit number is omitted below. Even when the bit number is omitted, each data corresponds to a bit number terminal. In particular, when it is desired to clarify the correspondence for each bit, it is described as DI [N]. Unless otherwise stated, N represents any number among 0, 1, 2, and 3.
[0043]
Next, a circuit related to data input / output will be described. Test circuits TC are inserted between the input terminal DI and the data input terminal IN of the data circuit 1 and between the output terminal DO and the data output terminal OUT, respectively. The test circuit TC is a circuit including input terminals d [0] to [3], output terminals q [0] to [3], a scan-in terminal si, a test holding terminal thld, a shift mode terminal sm, and a scan-out terminal so. .
[0044]
An operation of the test circuit TC by the test holding control signal thld and the shift mode control signal sm input to the test holding terminal thld and the shift mode terminal sm, respectively, will be described. When the shift mode control signal sm is “0”, the test circuit TC takes in the data input to the input terminal d and outputs it directly from the output terminal q. When the shift mode control signal sm is “1” and the test holding control signal thld is “0”, the test circuit TC takes in the data input to the scan-in terminal si and outputs it from the scan-out terminal so. When the shift mode control signal sm is “1” and the test holding control signal thld is “1”, data is held in a connection circuit CC described later provided in the test circuit TC.
[0045]
The test circuit TC performing the circuit operation as described above can be obtained by using the connection circuit CC shown in FIG. The connection circuit CC will be described. The connection circuit CC is configured by the selectors 2 and 3 and the flip-flop 4. The selectors 2 and 3 are selectors each having a data input 0 terminal, a data input 1 terminal, an output terminal, and a control terminal. A control signal for switching the selector is input to the control terminal of the selector. The data input 0 terminal is selected and connected to the output terminal when the control signal is “0”. On the other hand, the data input 1 terminal is selected and connected to the output terminal when the control signal is “1”. Therefore, it is possible to select data output from the selector by switching between “1” and “0” of the control signal input to the selector. The selector 2 is controlled by a test holding control signal thld, and the selector 3 is controlled by a shift mode control signal sm. The data input 0 terminal of the selector 2 is connected to the scan-in terminal si, and the data input 1 terminal is connected to the output terminal of the flip-flop 4. The output terminal of the selector 2 is connected to the data input 1 terminal of the selector 3. An input terminal d is connected to the data input 0 terminal of the selector 3. The output terminal of the selector 3 is connected to the input terminal of the flip-flop 4. The output data of the flip-flop 4 is input to the data input 1 terminal of the selector 2 as described above, and further output as scan-out data so or serial input data q of the connection circuit CC. Serial input data is data output during normal operation. The flip-flop 4 is a D flip-flop or a flip-flop having the same function as the D flip-flop.
[0046]
The circuit operation of the connection circuit CC will be described. The connection circuit CC is a circuit that outputs a signal input to the input terminal d when the shift mode control signal sm is “0”. When the shift mode control signal sm is “1” and the test holding control signal thld is “0”, the connection circuit CC outputs data input to the scan-in terminal si. When the shift mode control signal sm is “1” and the test holding control signal thld is “1”, the connection circuit CC holds the data of the scan flip-flop 4. The connection circuits CC [0] to [3] are inserted and connected between the data input terminals d [0] to [3] and the output terminals q [0] to [3], respectively, and the 4-bit test circuit TC is connected. Composed.
[0047]
FIG. 3 is a circuit diagram showing a configuration of the test circuit TC. The connection circuit CC is connected in order to configure the test circuit TC. The connection between the connection circuits CC will be described. The data input 0 terminal of the selector 2 [0] of the connection circuit CC [0] is connected to the scan-in terminal si of the test circuit TC. For N = 1 to 3, the scan-out data so [N−1] of the connection circuit CC [N−1] is input to the data input 0 terminal of the selector 2 [N] of the connection circuit CC [N]. The output terminal of the flip-flop 4 [3] of the connection circuit CC [3] is connected to the scan-out terminal so of the test circuit TC. In addition to being connected as described above, each scan-out terminal so [N] of the connection circuit CC [N] also constitutes an output terminal q [N] of the test circuit TC.
[0048]
Next, the data circuit 1 and the circuit including the scan path according to the present embodiment will be described with reference to FIG.
[0049]
First, the data input terminal IN, the data output terminal OUT, and the connection between the data circuit 1 and the test circuit TC, which are necessary for normal operation, will be described. On the input side of the data circuit 1, the input terminal d [N] and the output terminal q [N] of the test circuit TC are connected to the data input terminal IN [N] and the input terminal DI [N] of the data circuit 1, respectively. . Similarly, on the output side, the input terminal d [N] and the output terminal q [N] of the test circuit TC are connected to the output terminal DO [N] and the data output terminal OUT [N] of the data circuit 1.
[0050]
Next, the scan-in terminals SI and si and the scan-out terminals SO and so used when performing a scan test will be described. The scan-in terminal SI is connected to the scan-in terminal si of the input side test circuit TC. The scan-out terminal so of the input-side test circuit TC is connected to the scan-in terminal si of the output-side test circuit TC. The scan-out terminal so of the output-side test circuit TC is connected to the scan-out terminal SO which is the final output terminal of the scan path.
[0051]
Next, the control circuit CTL1 according to the present embodiment that gives the test holding control signal thld and the shift mode control signal sm to the test circuit TC will be described. The control circuit CTL1 is a circuit that receives the test control signal TEST, the shift mode control signal SM, and the hold control signal HLD0, and outputs the test hold control signal thld and the shift mode control signal sm to the test circuit TC.
[0052]
When the test control signal TEST is “0”, the control circuit CTL1 outputs the holding control signal HLD0 as the test holding control signal thld and the shift mode control signal sm. When the test control signal TEST is “1”, the control circuit CTL outputs the logically inverted signal of the shift mode control signal SM as the test holding control signal thld and the shift mode control signal SM as the shift mode control signal sm. Here, the logic inversion signal will be described. When the input signal is “0”, the logic inversion signal is “1”, and when the input signal is “1”, the logic inversion signal is “0”.
[0053]
The connection of the control circuit CTL1 will be described. The control circuit CTL1 is configured by the selectors 5 and 6 and the inverter 10. Selectors 5 and 6 have data input 0 terminal, data input 1 terminal, output terminal and control terminal.EndIt is a selector having each child. A test control signal TEST for simultaneously switching the selectors 5 and 6 is input to the control terminals of the selectors 5 and 6. The data input 0 terminal is selected and connected to the output terminal when the test control signal TEST is “0”. On the other hand, the data input 1 terminal is selected and connected to the output terminal when the test control signal TEST is “1”. Therefore, by switching between “1” and “0” of the test control signal TEST input to the selectors 5 and 6, data output from the selectors 5 and 6 can be selected. A holding terminal HLD0 is commonly connected to the data input 0 terminals of the selectors 5 and 6, respectively. The shift mode terminal SM is connected to the data input 1 terminal of the selector 5 via the inverter 10, and the shift mode terminal SM is connected to the data input 1 terminal of the selector 6 without going through anything. The output terminal of the selector 5 is connected to the test holding terminal thld of the test circuit TC. The output terminal of the selector 6 is connected to the shift mode terminal sm of the test circuit TC.
[0054]
The circuit operation of the circuit shown in FIG. 1 is summarized below. As the circuit operation, there are a normal operation and a scan test operation. Table 1 shows the optimum setting values of the respective signals and data in the normal operation and the scan test. In the table, “DC” means “Don't Care” and indicates that no signal or data is involved in the operation.
[0055]
[Table 1]

[0056]
First, normal operation will be described. During normal operation, the test control signal TEST is set to “0”. When the test control signal TEST is “0”, the selectors 5 and 6 output the data input to the data input 0 terminal. Therefore, the holding control signal HLD0 is input as the test holding control signal thld and the shift mode control signal sm. This is given to the test circuit TC on the output side. At this time, if the holding control signal HLD0 is “0”, on the input side, the input data IN is taken into the input terminal DI of the data circuit 1 via the connection circuit CC on the input side. On the output side, the output data DO is output to the data output terminal OUT via the output side connection circuit CC. If the holding control signal HLD0 is “1”, the input data IN and the output data DO are held in the connection circuit CC, respectively.
[0057]
Next, the scan test operation will be described. During the scan test, the test pattern is shifted in, executed, and the test result is shifted out in order. At the time of the scan test, the test control signal TEST is set to “1”. When the test control signal TEST is “1”, the inverted logic of the shift mode control signal SM and the shift mode control signal SM are supplied to the test circuit TC on the input side and the output side as the test holding control signal thld and the shift mode control signal sm, respectively. Given.
[0058]
1. Test pattern shift-in
In preparation for inputting a test pattern to the data circuit 1, the test pattern is shifted into the connection circuit CC on the input side. When the shift mode control signal SM is “1”, the test pattern input to the data circuit 1 can be shifted in from the scan-in terminal SI. Since the data circuit 1 of this embodiment has 4 bits, a 4-bit test pattern is shifted in. The test pattern is shifted in the order of the input side connection circuits CC [0] → CC [1] → CC [2] → CC [3], and the test patterns are input to the input side connection circuits CC [0] to [3]. Entered. Since the input-side and output-side test circuits TC are simultaneously controlled by the shift mode control signal SM, data shift also occurs in the output-side connection circuits CC [0] to CC [3].
[0059]
2. Execution
The shift mode control signal SM is set to “0”. At this time, the input data IN is taken into the input terminal DI via the connection circuits CC on the input side or the output side, and the output data DO which is the test result of the data circuit 1 is output to the data output terminal OUT.
[0060]
3. Shift out test results
The shift mode control signal SM is set to “1”. At this time, the test results are sequentially shifted out from the scan-out terminal SO.
[0061]
The above is the circuit operation of the circuit shown in FIG. The data input 0 terminal and the data input 1 terminal of the selectors 2 and 3 shown in FIG. 2 are interchanged, and the test holding control signal thld and the shift mode control signal sm input to the control terminals of the selectors 2 and 3 are “ Even if each of “0” and “1” is replaced, the circuit operation of the test circuit of the present invention does not change.
[0062]
Use of the control circuit CTL1 shown in FIG. 1 has the following advantages.
[0063]
FIG. 4 is a circuit diagram showing a circuit in which a test path TC is provided on each of the input side and output side of the data circuits 1, 1a and 1b to form a scan path. The data circuits 1a and 1b are logic circuits, and the data circuit 1 is controlled by a control circuit CTL1 (not shown). The holding control signal HLD0 input to the TC on the input side and the output side of the data circuit 1 is output from the data circuit 1a..
The data circuits 1a, 1 and 1b are arranged in order, and the scan path is composed of the scan-in terminal SI → the test circuit TC on the input side of the data circuit 1a → the test circuit TC on the output side of the data circuit 1a → the input side of the data circuit 1 Test circuit TC → Test circuit TC on the output side of data circuit 1 → Test circuit TC on the input side of data circuit 1b → Test circuit TC on the output side of data circuit 1b → Scan-out terminal SO
[0064]
As described above, in the circuit shown in FIG. 4, the holding control signal HLD0 is supplied from the data circuit 1a to the test circuit TC on the input side and output side of the data circuit 1, respectively. In the control circuit CTL1, which of the holding terminal HLD0 and the shift mode terminal SM is selected is controlled by the test control signal TEST. Therefore, by controlling the test circuit TC on the input side and the output side of the data circuit 1 by the control circuit CTL1, the scan test of the data circuit 1 can be performed independently of the holding control signal HLD0 given from the data circuit 1a. Test pattern generation is simplified.
[0065]
As shown in FIG. 5, it is also possible to connect the scan-in terminal SI to the scan-in terminal si of the test circuit TC on the input side via the scan flip-flop HSFF.
[0066]
FIG. 6 is a circuit diagram showing the scan flip-flop HSFF. The scan flip-flop HSFF is a circuit including a selector 14 and a flip-flop 15. A scan flip-flop HFSS is provided to confirm the holding control signal HLD input to the control circuit that controls the test circuit TC. The holding control signal HLD is a signal including the holding control signal HLD0. The selector 14 has a data input 0 terminal, a data input 1 terminal, an output terminal, and a control terminal. A shift mode control signal SM for switching the selector 14 is input to the control terminal. The data input 0 terminal is selected and connected to the output terminal when the shift mode control signal SM is “0”. On the other hand, the data input 1 terminal is selected and connected to the output terminal when the shift mode control signal SM is “1”. Therefore, the data output from the selector 14 can be selected by switching between “1” and “0” of the shift mode control signal SM input to the selector 14. The data input 1 terminal of the selector 14 is connected to the scan-in terminal SI, and the data input 0 terminal is connected to the holding terminal HLD. The output terminal of the selector 14 is connected to the input terminal of the flip-flop 15. The output terminal of the flip-flop 15 becomes the scan-out terminal SO of the scan flip-flop HSFF. The flip-flop 15 is a D flip-flop or a flip-flop having the same function as the D flip-flop.
[0067]
The holding control signal HLD is a signal input to the control circuit. The holding control signal HLD input to the control circuit is a signal for controlling the test circuit TC. Specifically, the holding control signal HLD is a signal for switching the connection of the selector 2 included in the test circuit TC. It is not output as data from the data circuit 1 or from the scan path. Therefore, it is difficult to directly observe the holding control signal HLD when the scan flip-flop HSFF is not provided. If the holding control signal HLD does not take a desired logic, the test circuit TC controlled by the holding control signal HLD does not perform a desired operation, and it becomes impossible to trust the operation test of the logic circuit. Therefore, it is necessary to directly observe the holding control signal HLD. By using the scan flip-flop HSFF, the holding control signal HLD can be directly observed.
[0068]
By inputting the holding control signal HLD to the data input 0 terminal of the scan flip-flop HSFF and setting the shift mode control signal SM to “0”, the value of the holding control signal HLD can be stored in the flip-flop 15. . As described above, the selector 14 is controlled by the shift mode control signal SM. However, it is also possible to newly provide a control terminal not related to the control of the test circuit TC, and to control the selector 14 by a control signal output from this control terminal.
[0069]
A method for observing the value stored in the flip-flop 15 of the scan flip-flop HSFF will be described. In FIG. 5, the holding control signal HLD input to the data input 0 terminal of the selector 14 of the scan flip-flop HSFF is the holding control signal HLD0. In the configuration shown in FIG. 5, since the data held in the scan flip-flop HFSS is inputted to the scan-in terminal si of the input-side test circuit TC, the hold control signal HLD0 is taken out as scan-out data SO from the scan path. It will be possible to observe later.
[0070]
In FIG. 5, the scan flip-flop HSFF is inserted between the scan-in terminal SI and the scan-in terminal si of the input-side test circuit TC, but the scan-out terminal so of the input-side test circuit TC and the output-side test circuit. Even if it is inserted between the TC scan-in terminals si, the same effect is obtained, and the holding control signal HLD can be observed. Further, the same effect can be obtained even if it is inserted between the scan-out terminal so and the scan-out terminal SO of the test circuit TC on the output side.
[0071]
As apparent from the above description, the scan flip-flop HFSS is not directly required for the operation test of the data circuit 1. Hereinafter, in this embodiment and other embodiments, the scan flip-flop HSFF is not shown and described unless it is particularly required.
[0072]
Next, another control circuit according to the present embodiment will be described. Figure 71FIG. 6 is a circuit diagram showing a control circuit CTL2 used in place of the control circuit CTL1 shown in FIG.
[0073]
The control circuit CTL2 will be described. The control circuit CTL2 is a circuit that receives the shift mode control signal SM and the holding control signal HLD0 and outputs the test holding control signal thld and the shift mode control signal sm to the test circuit TC.
[0074]
When the shift mode control signal SM is “0”, the control circuit CTL2 outputs the holding control signal HLD0 as the test holding control signal thld and the shift mode control signal sm. When the shift mode control signal SM is “1”, the control circuit CTL2 outputs “0” as the test holding control signal thld and “1” as the shift mode control signal sm.
[0075]
The configuration of the control circuit CTL2 will be described with reference to FIG. The control circuit CTL2 can be configured using two gates. Each gate has two input terminals and one output terminal. One gate is a gate 20 and the other gate is an OR gate 21. The gate 20 is a gate that takes the logical product of the inverted logic of the input signal re input to the inverting input terminal re and the input signal ge input to the input terminal ge. The OR gate 21 is a gate that takes a logical sum of two input signals input to the OR gate 21.
[0076]
The connection state of the control circuit CTL2 will be described. The holding terminal HLD0 is commonly connected to the input terminal ge of the gate 20 and one input terminal of the OR gate 21. The shift mode terminal SM is commonly connected to the inverting input terminal re of the gate 20 and the other input terminal of the OR gate 21. The output terminal of the gate 20 outputs the test holding control signal thld to the test circuit TC, and the output terminal of the OR gate 21 outputs the shift mode control signal sm to the test circuit TC. The difference from the control circuit CTL1 is that the control circuit CTL2 is not provided with the test terminal TEST.
[0077]
The circuit operation of the control circuit shown in FIG. 7 is summarized below. The circuit operation includes normal operation control and scan test operation control. Control circuit CTL in normal operation and scan test2Table 2 shows the optimum setting values of each signal and data.
[0078]
[Table 2]

[0079]
First, normal operation will be described. During normal operation, the shift mode control signal SM is set to “0”. When the shift mode control signal SM is “0”, the gate 20 and the OR gate 21 supply the logic of the holding control signal HLD0 to the test circuit TC on the input side and the output side as the test holding control signal thld and the shift mode control signal sm. . At this time, if the holding control signal HLD0 is “0”, on the input side, the input data IN is taken into the input terminal DI of the data circuit 1 via the connection circuit CC on the input side. On the output side, the output data DO is output to the data output terminal OUT via the output side connection circuit CC. If the holding control signal HLD0 is “1”, the input data IN and the output data DO are held in the connection circuit CC, respectively.
[0080]
Next, the scan test operation will be described. During the scan test, the test pattern is shifted in, executed, and the test result is shifted out in order.
[0081]
1. Test pattern shift-in
When the shift mode control signal SM is “1”, the test pattern input to the data circuit 1 can be shifted in from the scan-in terminal SI.
[0082]
2. Execution
The shift mode control signal SM is set to “0”. Since the shift mode control signal SM is “0”, the circuit operation is equal to the normal operation. At this time, the input data IN is taken into the input terminal DI via the connection circuits CC on the input side or the output side, and the output data DO which is the test result of the data circuit 1 is output to the data output terminal OUT.
[0083]
3. Shift out test results
The shift mode control signal SM is set to “1”. At this time, the test results are sequentially shifted out from the scan-out terminal SO.
[0084]
The above is the circuit operation of the circuit shown in FIG.
[0085]
Even if the control circuit CTL2 shown in FIG. 7 is replaced with the CTL2a shown in FIG. 9, the same circuit operation can be obtained. The control circuit CTL2a will be described. Similar to the control circuit CTL2, the control circuit CTL2a is a circuit that receives the shift mode control signal SM and the hold control signal HLD0 and outputs the test hold control signal thld and the shift mode control signal sm to the test circuit TC.
[0086]
When the shift mode control signal SM is “0”, the control circuit CTL2a outputs the holding control signal HLD0 as the test holding control signal thld and the shift mode control signal sm. When the shift mode control signal SM is “1”, “0” is set as the test holding control signal thld, and “1” is set as the shift mode control signal sm.2aWill output.
[0087]
The configuration of the control circuit CTL2a will be described with reference to FIG. The control circuit CTL2a can be configured using two gates. Each gate has two input terminals and one output terminal. One gate is the gate 20a, and the other gate is the OR gate 21a. Gate 20a andORGate 21aAre gates having the same configuration and function as the gate 20 and the OR gate 21, respectively.
[0088]
The connection state of the control circuit CTL2a will be described. The holding terminal HLD0 is an input terminal ge of the gate 20a.Close toContinued. The shift mode terminal SM is commonly connected to the inverting input terminal re of the gate 20a and one input terminal of the OR gate 21a. The output terminal of the gate 20a is commonly connected to the test holding terminal thld of the test circuit TC and the other input terminal of the gate 21a. The output terminal of the OR gate 21a is connected to the shift mode terminal sm of the test circuit TC.
[0089]
When the control circuits CTL2 and 2a that do not receive the test control signal TEST are used, the scan test of the data circuit 1 cannot be performed independently of the holding control signal HLD0 supplied from the data circuit 1a in the circuit shown in FIG. It becomes. However, in the control circuit CTL1, two selectors 5 and 6 are used. The two-input selector is composed of three gates as shown in FIG. Of the three gates, one is an AND gate G1, one is an OR gate G2, and the other is a gate G3 having an inverting input terminal re and an input terminal ge. Therefore, the circuit area is reduced by exchanging the selectors 5 and 6 with two gates of the gate 20 and the OR gate 21.
[0090]
Embodiment 2. FIG.
In the present embodiment, a test circuit of a logic circuit to which a function of holding and compressing a test result is added is shown. In this embodiment mode, a control circuit capable of holding data during an operation test of a logic circuit is shown. Further, in the present embodiment, a test circuit for independently controlling an input side test circuit and an output side test circuit is shown.
[0091]
FIG. 10 is a circuit diagram showing a logic circuit and a test circuit according to the present embodiment. Components having the same configuration, function, and the like as those of the circuit shown in Embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.
[0092]
As shown in the figure, the input of the data circuit 1 is controlled by the test circuit TC, and the output of the data circuit 1 is controlled by the test circuit CTC.
[0093]
The test circuit CTC will be described. The test circuit CTC is inserted between the data output terminal OUT and the output terminal DO of the data circuit 1. Similarly to the test circuit TC, the test circuit CTC includes input terminals d [0] to [3], output terminals q [0] to [3], a scan-in terminal si, a test holding terminal thld, a shift mode terminal sm, and a scan The circuit includes an out terminal so, and further includes an expected data terminal exp and a comparison terminal cmpen. The test circuit CTC has a function of comparing the data DO actually output from the data circuit 1 with respect to the test pattern, the expected data, and EXP, and also has a function of holding the comparison result and compressing the test result. Here, the expected data EXP is an output data pattern that is output uniquely by the data circuit 1 operating normally to the test pattern input to the data circuit 1. Expected data EXP is input to expected data terminal exp.
[0094]
Here, compression of test results will be described. Before starting the test, the test circuit CTC is set so that “0” is not held. If the data to be compared do not match, the test circuit CTC will not hold “0” unless it is determined once. If it is once determined that the data compared in the test circuit CTC does not match, “0” is held in the test circuit CTC. Once “0” is held, “0” is subsequently held. This is the compression of the test results.
[0095]
The compression test represents a test that uses compression of a test result. If it is confirmed that “0” is not held in the test circuit CTC after the test is completed, it is observed that the data circuit 1 outputs the same data as all expected output data. Is confirmed to work properly. If it is confirmed that “0” is held in the test circuit CTC, it is observed that the data circuit 1 outputs data different from the expected output data at least once, and the data circuit 1 is normal. It was confirmed that it did not work. Therefore, it is not necessary to observe the test result every time a test pattern is input to the data circuit 1. The operation test of the data circuit 1 can be performed only by inputting a plurality of test patterns in order to the data circuit 1 and simultaneously compressing the test result by the test circuit CTC and observing the compressed test result after the completion of the compression test. It becomes possible.
[0096]
Test holding terminal thld, shift mode terminal sm, ratioComparisonThe operation of the test circuit CTC using the test holding control signal thld, the shift mode control signal sm, the comparison enable signal CMPEN, and the expected data EXP input to the child cmpen and the expected data terminal exp will be described.
[0097]
The test circuit CTC is a circuit having a function of comparing the expected data EXP and the input data d. When the shift mode control signal sm is “0”, the test circuit CTC takes in the data input to the input terminal d and outputs it directly from the output terminal q. When the shift mode control signal sm is “1” and the test holding control signal thld is “0”, the test circuit CTC takes in data from the scan-in terminal si and outputs data from the scan-out terminal so. When the shift mode control signal sm is “1”, the test holding control signal thld is “1”, and the comparison enable signal CMPEN is “0”, the test circuit CTC holds the compressed test result. When the shift mode control signal sm is “1”, the test holding control signal thld is “1”, and the comparison enable signal CMPEN is “1”, the test circuit CTC outputs the expected data EXP and the input data d. The comparison result is compressed and held.
[0098]
The test circuit CTC performing the above operation is obtained by using the connection circuit CCC shown in FIG. The connection circuit CCC will be described. The connection circuit CCC is a circuit including an input terminal cd, a scan-in terminal csi, a test holding terminal cthld, a shift mode terminal csm, a scan-out terminal cso, an expected data terminal cexp, and a comparison terminal cmppen. The selectors 2 and 3, the flip-flop 4, the Ex-OR gate 30, the NAND gate 31, and the AND gate 32 constitute a connection circuit CCC.
[0099]
The selectors 2 and 3 have a data input 0 terminal, a data input 1 terminal, an output terminal, and a control terminal.EndIt is a selector having each child. The selector 2 is switched by the test holding control signal cthld, and the selector 3 is switched by the shift mode control signal csm. The input terminal cd is commonly connected to one input terminal of the Ex-OR gate 30 and the data input 0 terminal of the selector 3. The expected data terminal cexp is connected to the other input terminal of the Ex-OR gate 30. The output terminal of the Ex-OR gate 30 is connected to one input terminal of the NAND gate 31, and the comparison terminal cmppen is connected to the other input terminal of the NAND gate 31. The output terminal of the NAND gate 31 is connected to one input terminal of the AND gate 32, and the output terminal of the flip-flop 4 is connected to the other input terminal of the AND gate 32. The output terminal of the AND gate 32 is connected to the data input 1 terminal of the selector 2, and the scan-in terminal csi is connected to the data input 0 terminal of the selector 2. The output terminal of the selector 2 is connected to the data input 1 terminal of the selector 3, and the input terminal cd is connected to the data input 0 terminal of the selector 3 as described above. The output terminal of the selector 3 is connected to the input terminal of the flip-flop 4. The output data of the flip-flop 4 is input to the other input terminal of the AND gate 32 as described above, and is connected to the scan-out terminal cso of the connection circuit CCC.
[0100]
The circuit operation of the connection circuit CCC will be described.
[0101]
1. The connection circuit CCC outputs a signal input to the input terminal cd via the selector 3 and the flip-flop 4 when the shift mode control signal csm is “0”.
[0102]
2. When the shift mode control signal csm is “1” and the test holding control signal cthld is “0”, the connection circuit CCC passes the data input to the scan-in terminal csi via the selectors 2 and 3 and the flip-flop 4. Output from the scan-out terminal cso.
[0103]
3. The circuit operation when the shift mode control signal csm is “1” and the test holding control signal cthld is “1” will be described below.
[0104]
When the comparison enable signal ccmpen input from the comparison terminal ccmpen is “0”, the NAND gate 31 outputs “1” to the AND gate 32 regardless of the output data from the Ex-OR gate 30. At this time, the gate 32 outputs the output data of the flip-flop 4 to the flip-flop 4 via the selectors 2 and 3. Accordingly, the connection circuit CCC continues to hold the data of the flip-flop 4.
[0105]
When the comparison enable signal ccmpen input from the comparison terminal ccmpen is “1”, the NAND gate 31 outputs the inverted logic of the output data of the Ex-OR gate 30. The Ex-OR gate 30 outputs “0” when the expected data exp and the input data cd match, and outputs “1” when they do not match. Accordingly, the NAND gate 31 outputs “1” to the AND gate 32 when the expected data exp matches the input data cd in the Ex-OR gate 30. At this time, the gate 32 outputs the output data of the flip-flop 4 to the flip-flop 4 via the selectors 2 and 3. Accordingly, the connection circuit CCC continues to hold the data of the flip-flop 4. When the expected data exp does not match the input data cd in the Ex-OR gate 30, the NAND gate 31 outputs “0” to the AND gate 32. At this time, the AND gate 32 outputs “0” to the flip-flop 4 via the selectors 2 and 3, and the flip-flop 4 outputs “0” to the AND gate 32. As a result, “0” is held in the AND gate 32, the selectors 2 and 3, and the flip-flop 4.
[0106]
By using the connection circuit CCC, the circuit operation of the test circuit CTC described above can be obtained.
[0107]
The connection circuits CCC [0] to [3] are inserted and connected between the data input terminals d [0] to [3] and the output terminals q [0] to [3], respectively, so that a 4-bit test circuit CTC is formed. Composed. A test circuit CTC is shown in FIG.
[0108]
The configuration of the test circuit CTC will be described in detail as follows. An input terminal cd [N], a test holding terminal cthld [N], a shift mode terminal csm [N], a scan-out terminal cso [N], an expected data terminal cexp [N], and a comparison terminal cmppen [N] of the connection circuit CCC [N]. N] are connected to the input terminal d [N], test holding terminal thld, shift mode terminal sm, output terminal q [N], expected data terminal exp and comparison terminal cmpen, respectively, of the test circuit CTC. Further, the scan-out terminal cso [N] of the connection circuit CCC [N] is connected to the scan-in terminal csi [N + 1] of the connection circuit CCC [N + 1]. However, when N = 3, the scan-out terminal csi [3] of the connection circuit CCC [3] is connected to the scan-out terminal so of the test circuit CTC. Further, the scan-in terminal csi [0] of the connection circuit CCC [0] is connected to the scan-in terminal si of the test circuit CTC.
[0109]
A circuit including a logic circuit and a test circuit according to this embodiment will be described with reference to FIG.
[0110]
First, data input terminal IN, data output terminal OUT, and connection between data circuit 1 and test circuits TC and CTC, which are necessary for normal operation, will be described. On the input side of the data circuit 1, the input terminal d [N] and the output terminal q [N] of the test circuit TC are connected to the data input terminal IN [N] and the input terminal DI [N] of the data circuit 1, respectively. . Similarly, on the output side, the input terminal d [N] and the output terminal q [N] of the test circuit CTC are connected to the output terminal DO [N] and the data output terminal OUT [N] of the data circuit 1.
[0111]
Next, connection of the scan-in terminal SI and the scan-in terminals si of the test circuits TC and CTC and the scan-out terminal SO and the scan-out terminals so of the test circuits TC and CTC, which are used when performing a scan test, will be described. I do. The scan-in terminal SI is connected to the scan-in terminal si of the test circuit TC. The scan-out terminal so of the test circuit TC is connected to the scan-in terminal si of the test circuit CTC. The scan-out terminal so of the test circuit CTC is connected to the scan-out terminal SO that is the final output terminal of the scan path.
[0112]
In the present embodiment, as shown in FIG. 10, one of the holding control signal HLD0 and the shift mode control signal SM is applied to the shift mode terminal sm of the test circuit TC. One of the holding control signal HLD1 and the shift mode control signal SM is supplied to the shift mode terminal sm of the test circuit CTC. One of the holding control signal HLD0 and the test holding control signal THLD0 is supplied to the test holding terminal thld of the test circuit TC. One of the holding control signal HLD1 and the test holding control signal THLD1 is supplied to the test holding terminal thld of the test circuit CTC. The expected data terminal exp and the comparison terminal cmpen of the test circuit CTC are expected data respectively.TAControl is performed by giving XP and a comparison enable signal CMPEN.
[0113]
FIG. 14 shows a control circuit for supplying the control signal as described above. FIG. 14 is a circuit diagram showing a circuit provided with a control circuit CTL3 for controlling the test circuit TC and a control circuit CCTL3 for controlling the test circuit CTC.
[0114]
The control circuit CTL3 receives the holding control signal HLD0, the test holding control signal THLD0, the shift mode control signal SM and the test control signal TEST, and supplies the test holding control signal thld and the shift mode control signal sm to the test circuit TC. Similar to the control circuit CTL3, the control circuit CCTL3 receives the holding control signal HLD1, the test holding control signal THLD1, the shift mode control signal SM and the test control signal TEST, and tests the test holding control signal thld and the shift mode control signal sm. Is applied to the circuit CTC. Shift mode control signal SM and test control signal TEST are controlled in commoncircuitGiven to CTL3 and CCTL3. In addition, independently of the control circuit CCTL3, the expected data EXP and the comparison enable signal CMPEN are supplied to the test circuit.CTCGiven to.
[0115]
First, the circuit operation of the control circuit CTL3 will be described. When the test control signal TEST is “0”, the control circuit CTL3 outputs the holding control signal HLD0 as the test holding control signal thld and the shift mode control signal sm. When the test control signal TEST is “1”, the control circuit CTL3 outputs the test holding control signal THLD0 as the test holding control signal thld and the shift mode control signal SM as the shift mode control signal sm.
[0116]
Next, the circuit operation of the control circuit CCTL3 will be described. The circuit operation of the control circuit CCTL3 is the same as the circuit operation of the control circuit CTL3. When the test control signal TEST is “0”, the control circuit CCTL3 outputs the holding control signal HLD1 as the test holding control signal thld and the shift mode control signal sm. When the test control signal TEST is “1”, the control circuit CCTL3 outputs the test holding control signal THLD1 as the test holding control signal thld and the shift mode control signal SM as the shift mode control signal sm.
[0117]
The configuration of the control circuit CTL3 will be described with reference to FIG. The control circuit CTL3 is configured by the selectors 5 and 6. Selectors 5 and 6 have data input 0 terminal, data input 1 terminal, output terminal and control terminal.EndIt is a selector having each child. A test control signal TEST for simultaneously switching the selectors 5 and 6 is input to the control terminals of the selectors 5 and 6. The data input 0 terminal is selected and connected to the output terminal when the test control signal TEST is “0”. On the other hand, the data input 1 terminal is selected and connected to the output terminal when the test control signal TEST is “1”. Therefore, by switching between “1” and “0” of the test control signal TEST input to the selectors 5 and 6, data output from the selectors 5 and 6 can be selected. A holding terminal HLD0 is commonly connected to the data input 0 terminals of the selectors 5 and 6, respectively. The test holding terminal THLD0 is connected to the data input 1 terminal of the selector 5, and the shift mode terminal SM is connected to the data input 1 terminal of the selector 6. The output terminal of the selector 5 is connected to the test holding terminal thld of the test circuit TC. The output terminal of the selector 6 is connected to the shift mode terminal sm of the test circuit TC.
[0118]
The configuration of the control circuit CCTL3 will be described with reference to FIG. The connection of the control circuit CCTL3 is the same as the connection of the control circuit CTL3. Control circuit CTL3
Selector 5, 6 → Selector 7, 8
Holding terminal HLD0 → Holding terminal HLD1
Test holding terminal THLD0 → Test holding terminal THLD1
The control circuit CCTL3 is configured by converting as described above.
[0119]
The circuit operation of the control circuit shown in FIG. 14 is summarized below. The circuit operation includes a normal operation, a normal scan test operation, and a scan test operation using a test result compression function. The normal scan test operation is a scan test operation shown in the first embodiment. The scan test operation that uses the test result compression function is the comparison between the actual logic circuit output data and the expected logic circuit output data on the output side of the logic circuit, and the test result is stored by holding the comparison result. This is an operation of compressing and scanning out data after compression. Table 3 shows optimum setting values of the respective signals and data in the normal operation, the normal scan test, and the scan test using the test result compression function.
[0120]
[Table 3]

[0121]
First, normal operation will be described. During normal operation, the test control signal TEST is set to “0”, and the comparison enable signal CMPEN is set to “0”.FirstFor this purpose, the input side will be described. Since the selectors 5 and 6 output data input to the data input 0 terminal when the test control signal TEST is “0”, the holding control signal HLD0 is used as the test holding control signal thld and the shift mode control signal sm as the test circuit TC. Given to. At this time, if the holding control signal HLD0 is “0”, the input data IN is taken into the input terminal DI of the data circuit 1 through the connection circuit CC constituting the test circuit TC. If the holding control signal HLD0 is “1”, the input data IN is held in the connection circuit CC. On the output side, since the selectors 7 and 8 output the data input to the data input 0 terminal, the holding control signal HLD1 is given to the test circuit CTC as the test holding control signal thld and the shift mode control signal sm. At this time, if the holding control signal HLD1 is “0”, the output data DO is output to the data output terminal OUT via the connection circuit CCC constituting the test circuit CTC. If the holding control signal HLD1 is “1”, the output data DO is held in the connection circuit CCC because the comparison enable signal CMPEN is “0”.
[0122]
In the normal operation, the normal scan test, and the scan test using the test result compression function, the test control signal TEST is set to “1”. When the test control signal TEST is “1”, the selectors 5 and 6 constituting the control circuit CTL3 and the selectors 7 and 8 constituting the control circuit CCTL3 respectively output data input to the data input 1 terminal. At this time, on the input side, the test holding control signal THLD0 and the shift mode control signal SM are output to the test circuit TC as the test holding control signal thld and the shift mode control signal sm, respectively. On the output side, the test holding control signal THLD1 and the shift mode control signal SM are output to the test circuit CTC as the test holding control signal thld and the shift mode control signal sm, respectively.
[0123]
Next, a normal scan test operation will be described. In the normal scan test, the comparison enable signal CMPEN is set to “0”. During a normal scan test, test pattern shift-in, execution, and test result shift-out are performed in order. Further, it is possible to hold data in the connection circuits CC and CCC.
[0124]
1. Test pattern shift-in
In preparation for inputting a test pattern to the data circuit 1, the test pattern is shifted into the connection circuit CC on the input side. When the test holding control signal THLD0 is “0” and the shift mode control signal SM is “1”, the test pattern input to the data circuit 1 can be shifted in from the scan-in terminal SI. Since the data circuit 1 of this embodiment has 4 bits, a 4-bit test pattern is shifted in. The test pattern is shifted in the order of the input side connection circuits CC [0] → CC [1] → CC [2] → CC [3], and the test patterns are input to the input side connection circuits CC [0] to [3]. Entered.
[0125]
2. Execution
The shift mode control signal SM is set to “0”. At this time, on the input side, the input data IN is taken into the input terminal DI via the connection circuit CC, and on the output side, the output data DO which is the test result of the data circuit 1 is output to the data output terminal OUT via the connection circuit CCC. Is done.
[0126]
3. Shift out test results
The test holding control signal THLD1 is set to “0”, and the shift mode control signal SM is set to “1”. At this time, the test results are sequentially shifted out from the scan-out terminal SO.
[0127]
When it is desired to hold data during the scan test, the shift mode control signal SM is set to “1”. If the holding control signal THLD0 is “1”, the connection circuit CC holds data on the input side. If the holding control signal THLD1 is “1”, the connection circuit CCC holds data on the output side.
[0128]
Of course, even if the output-side test circuit CTC is replaced with the test circuit TC, the above-described normal operation and normal scan test can be performed. In addition, since the data holding during the normal operation and the data holding during the normal scan test are shared by the connection circuit CC or CCC, the circuit overhead can be reduced and the circuit area can be reduced. .
[0129]
By holding the input data IN fetched into the input terminal DI during execution in the scan test operation, it becomes possible to perform a scan test of a plurality of logic circuits in one scan path. A description will be given below.
[0130]
FIG. 15 shows the input side of the data circuit 1in, the output side of the data circuit 1in and the input side of the data circuit 1, the output side of the data circuit 1 and the input side of the data circuit 1out, and the output side of the data circuit 1out. 2 is a circuit diagram illustrating a circuit in which test circuits TCa, TC, TCb, and TCc are provided and a scan path is configured. Each of the data circuits 1in and 1out is a logic circuit. The data circuit 1in gives input data IN to the data circuit 1. Data circuit 1 is a data circuit1Output data OUT is given to out. The test circuits TCa, TC, TCb, and TCc are controlled by control circuits CTLTCa, CTL3, CTLTCb, and CTLTCc (not shown), respectively. The test circuit TCa is a test circuit having the same function as the test circuit TC. The test circuits TCb and TCc are test circuits having the same configuration and function as the test circuit TC or CTC.
[0131]
The data circuits 1in, 1 and 1out are arranged in order, and the scan path is configured as scan-in terminal SI → test circuit TCa → test circuit TC → test circuit TCb → test circuit TCc → scan-out terminal SO.
[0132]
The input data IN from the data circuit 1in captured at the time of execution at the input terminal DI of the data circuit 1 is held by the test circuit TC and then shifted out and taken out from the scan-out terminal SO. A similar operation can be performed in the test circuit TCb or TCc.
[0133]
If the above operation is performed, a scan test of a plurality of logic circuits can be performed in one scan path.
[0134]
In a normal scan test, the operations described in 1 to 3 must be repeated for the number of test patterns. Next, a scan test in which only one shift-out is required for all patterns, that is, a scan test operation using a test result compression function will be described.
[0135]
The scan test operation using the test result compression function will be described with reference to FIG. In the scan test using the test result compression function, the test pattern shift-in, comparison, and compression are alternately performed after the initial setting. After all the desired test patterns have been compared and compressed, the compressed test results are shifted out.
[0136]
In a scan test using the test result compression function, the comparison enable signal CMPEN takes both values of “0” and “1”.
[0137]
1. Initial setting
As an initial setting, “1” is set to all the flip-flops 4 included in the connection circuit CCC constituting the test circuit CTC. When the shift mode control signal SM is set to "1", the test holding control signals THLD0 and THLD1 are set to "0", and "1" is shifted in from the scan-in terminal SI, "1" is set to the flip-flop 4. . The comparison enable signal CMPEN is set to “0”.
[0138]
2. Test pattern shift-in and comparison and compression
In preparation for inputting a test pattern to the data circuit 1, the test pattern is shifted into the connection circuit CC on the input side. At this time, the test holding control signal THLD1 is set to “1” in order to hold “1” set in the flip-flop 4 of the connection circuit CCC in the initial setting. The values of the test holding control signal THLD0 and the shift mode control signal SM are equal to the values at the initial setting. That is, when the test holding control signal THLD0 is “0”, the test holding control signal THLD1 is “1”, and the shift mode control signal SM is “1”, the test pattern input to the data circuit 1 is scanned in. Shift in from SI.
[0139]
Since the data circuit 1 of this embodiment has 4 bits, a 4-bit test pattern is shifted in. The test pattern is shifted in the order of the input side connection circuits CC [0] → CC [1] → CC [2] → CC [3], and the test patterns are input to the input side connection circuits CC [0] to [3]. Entered. For example, a quaternary full cycle sequence is given as a test pattern. Here, the all period series is obtained by adding data in which all bits are “0” to the M series. Therefore, the entire periodic sequence generates all combinations of data. Therefore, by giving a whole cycle sequence as a test pattern, it becomes possible to efficiently set all combinations of test patterns in the connection circuit CC. Further, the test pattern is shifted in when the test holding control signal THLD0 is “0” so that “0” and “1” are sequentially repeated in the marching pattern, and then the test holding control signal THLD0 is set to “1”. By inputting the test pattern to the data circuit 1 while repeatedly holding the test pattern in the connection circuit CC, the test pattern can be efficiently input to the data circuit 1.
[0140]
Comparison enable signal only for the test pattern to be tested in the state where the expected data EXP is inputCMPENBy setting “1” to “1”, the output data of the data circuit 1 and the expected data EXP are compared. The comparison result is compressed by the above-described circuit operation of the test circuit CTC.
[0141]
3. Shift out test results
The test holding control signal THLD1 is set to “0”, and the shift mode control signal SM is set to “1”. At this time, the test results compressed by the connection circuit CCC are sequentially shifted out from the scan-out terminal SO.
[0142]
The above is the circuit operation of the circuit shown in FIG. Similar circuit operation can be obtained by using the connection circuit CCCr shown in FIG. 12 instead of the connection circuit CCC shown in FIG. The connection circuit CCCr is characterized in that a reset terminal normally provided in a flip-flop is effectively used. The connection circuit CCCr will be described based on the difference from the connection circuit CCC.
[0143]
The connection circuit CCCr includes a terminal having the same function as the terminal included in the connection circuit CCC, and further includes a clock terminal t. That is, the input terminal cdr, the scan-in terminal csir, the test holding terminal cthldr, the shift mode terminal csmr, the scan-out terminal csor, the expected data terminal cexpr, and the comparison terminal ccmprenr provided in the connection circuit CCCr are respectively input terminals cd provided in the connection circuit CCC. The scan-in terminal csi, the test holding terminal cthld, the shift mode terminal csm, the scan-out terminal cso, the expected data terminal cexp, and the comparison terminal cmppen have the same functions.
[0144]
The connection circuit CCCr includes selectors 2 and 3, a flip-flop 4r, an Ex-OR gate 30r, and a gate 31r. The Ex-OR gate 30r has the same configuration and function as the Ex-OR gate 30, and the gate 31r includes a signal input to each of two input terminals and an inverted signal of a signal input to one inverting input terminal. Is a circuit that takes the negative logical product of and outputs from the output terminal.
[0145]
Although the flip-flop 4 has a reset terminal and a clock terminal, it has not been necessary to perform a special function in the previous embodiments. Therefore, those explanations and illustrations have been omitted. In the connection circuit CCCr, the reset terminal is used effectively, and further, the signal input to the clock terminal is used to synchronize and compress the test result. Therefore, the reset terminal and the clock terminal of the flip-flop 4r are particularly illustrated only in the connection circuit CCCr. Accordingly, it is necessary to add the clock terminal T to the test circuit CTC and connect it to the clock terminal t of the connection circuit CCCr. However, the illustration of the clock terminal T placed in the test circuit CTC is omitted.
[0146]
The main difference between the connection circuit CCCr and the connection circuit CCC is:
1. The difference between the gate 31r and the NAND gate 31 and the AND gate 32;
2. Difference between connection between flip-flop 4 and selector 2 and connection between flip-flop 4r and selector 2
3. Differences arising from the presence and connection of clock terminal t
It is. Since other connections are the same, description thereof is omitted.
[0147]
The output terminal of the Ex-OR gate 30r is connected to one input terminal of the gate 31r, and the comparison terminal ccmpenr is connected to the other input terminal of the gate 31r. The clock terminal t is connected to the inverting input terminal of the gate 31r, and at the same time, the clock terminal t is connected in common to the clock terminal of the flip-flop 4r. The output terminal of the gate 31r is connected to the reset terminal of the flip-flop 4r. When the reset terminal of the flip-flop 4r receives "0", it resets the data stored in itself. The output terminal of the flip-flop 4r is connected to the data input 1 terminal of the selector 2, and is also connected to the scan-out terminal csor of the connection circuit CCCr.
[0148]
The circuit operation of the connection circuit CCCr will be described. Even if the connection circuit CCCr is used, the same circuit operation as the circuit operations 1 and 2 of the connection circuit CCC is obtained, and the same circuit operation as the circuit operation 3 of the connection circuit CCC is obtained. Therefore, the circuit operation 3 when the connection circuit CCCr is used will be described below.
[0149]
When the comparison enable signal ccmpenr is “0”, the gate 31r outputs “1” to the reset terminal of the flip-flop 4r regardless of the output data from the Ex-OR gate 30r and the clock signal t input to the clock terminal t. To do. Accordingly, the data is not reset in the flip-flop 4r, and the connection circuit CCCr continues to hold the data in the flip-flop 4r.
[0150]
When the comparison enable signal ccmpenr is “1” and the clock signal t input from the clock terminal t is “0”, the gate 31r outputs the inverted logic of the output data of the Ex-OR gate 30r. Therefore, the expected data exp in the Ex-OR gate 30rrAnd input data cdrIf the two match, the gate 31r outputs “1” to the reset terminal of the flip-flop 4r. Therefore, the connection circuit CCCrKeeps the data of the flip-flop 4r.
[0151]
At this time, if the expected data expr does not match the input data cdr in the Ex-OR gate 30r, the gate 31r outputs “0” to the reset terminal of the flip-flop 4r. Accordingly, since the data is reset in the flip-flop 4r, “0” is held in the selectors 2 and 3 and the flip-flop 4r.
[0152]
That is, the connection circuit CCCr has a circuit function of holding the data of the flip-flop 4r when the expected data expr and the input data cdr match, and holding “0” at the flip-flop 4r when they do not match. This circuit function is the same as the circuit function of the connection circuit CCC. However, the following advantages can be obtained particularly by using the connection circuit CCCr.
[0153]
In the connection circuit CCC, data is held by a loop formed by the selectors 2 and 3, the flip-flop 4 and the AND gate 32. However, in the connection circuit CCCr, data is held by a loop formed only by the selectors 2 and 3 and the flip-flop 4r, so that the possibility that the data is affected by extra noise or the like is reduced.
[0154]
The connection circuit CCCr is synchronized with the clock signal t. However, by removing the inverting input terminal from the gate 31r, the gate 31r may be a NAND gate so as not to be synchronized with the clock signal.
[0155]
As is clear from the above description, the test circuit CTC can be configured using the connection circuit CCCr, as in the case of using the connection circuit CCC.
[0156]
By providing the test circuit CTC on the output side of the data circuit 1 and performing the scan test using the test result compression function, there is an advantage that the test result is shifted out only once for a plurality of test patterns. Accordingly, the time required for performing the scan test using the test result compression function for the plurality of test patterns is shorter than the time required for performing the normal scan test for the plurality of test patterns a plurality of times. . That is, the test time can be shortened.
[0157]
When the control circuit CTL3 shown in FIG. 14 is used, the same effect as that described in the first embodiment is produced. In the control circuit CTL3, the test control signal TEST controls which one of the holding terminal HLD0, the test holding terminal THLD0, and the shift mode terminal SM is selected. Therefore, by using the control circuit CTL3, the scan test of the data circuit 1 in the circuit shown in FIG. 4 can be performed independently of the holding control signal HLD0 supplied from the data circuit 1a.
[0158]
The difference in configuration between the control circuit CTL3 and the control circuit CCTL3 is only a difference depending on the input control signal and is controlled simultaneously by the test control signal TEST. Therefore, the operations of the selectors 5 and 6 and the operations of the selectors 7 and 8 are performed. Are the same. That is, regarding the invention relating to the configuration of the control circuit, it is possible to describe the control circuit that controls the test circuit TC, and to replace this description with the description of the control circuit that controls the test circuit CTC. Therefore, the circuit on the output side of the data circuit 1 can be omitted, and the circuit shown in FIG. 14 can be illustrated as shown in FIG. In the future, illustration and description of the circuit on the output side of the data circuit 1 will be omitted except when particularly required.
[0159]
In the present embodiment, the holding control signal HLD0 input to the input side control circuit is different from the holding control signal HLD1 input to the output side control circuit. Therefore, it is necessary to use a plurality of scan flip-flops for confirming the holding control signal. A scan flip-flop used for confirming a plurality of holding control signals will be described below with reference to FIG. FIG. 16 is a diagram showing a connection state of scan flip-flops used for confirming a plurality of holding control signals, and illustration of a test holding terminal, an expected data terminal, a comparison terminal, and the like is omitted in the figure. .
[0160]
Consider a case where the holding control signals HLD0 and HLD1 are confirmed. Scan flip-flops HSFF and HSFFa are inserted between the scan-in terminal SI and the scan-in terminal si of the test circuit TC. The scan flip-flop HSFF is a circuit including a selector 14 and a flip-flop 15. Similarly, the scan flip-flop HSFFa is a circuit including a selector 14a and a flip-flop 15a. A scan flip-flop HFSS is provided to confirm the holding control signal HLD0 input to the control circuit that controls the test circuit TC. Similarly, a scan flip-flop HFSSa is provided to confirm the holding control signal HLD1 input to the control circuit that controls the test circuit CTC. The selectors 14 and 14a have a data input 0 terminal, a data input 1 terminal, an output terminal and a control terminal.EndEach has a child. A shift mode control signal SM for switching the selectors 14 and 14a is input to each control terminal. The data input 0 terminal is selected and connected to the output terminal when the shift mode control signal SM is “0”. On the other hand, the data input 1 terminal is selected and connected to the output terminal when the shift mode control signal SM is “1”. Therefore, it is possible to select data output from the selectors 14 and 14a by switching between “1” and “0” of the shift mode control signal SM input to the selectors 14 and 14a. A scan-in terminal SI is connected to the data input 1 terminal of the selector 14. A holding terminal HLD0 is connected to the data input 0 terminal of the selector. The output terminal of the selector 14 is connected to the input terminal of the flip-flop 15. The output terminal of the flip-flop 15 is connected to the data input 1 terminal of the selector 14a. The holding terminal HLD1 is connected to the data input 0 terminal of the selector 14a. Flip-flop 15aAre connected to the scan-in terminal si of the test circuit TC. The flip-flops 15 and 15a are D flip-flops or flip-flops having the same function as the D flip-flop.
[0161]
By setting the shift mode control signal SM to “0” in the scan flip-flops HSFF and HSFFa as described above, the values of the holding control signals HLD0 and HLD1 can be stored in the flip-flops 15 and 15a, respectively. In the configuration shown in FIG. 16, the output terminals of the scan flip-flops HSFF and HSFFa are connected to the scan-in terminal si of the test circuit TC. Accordingly, the shift control signal SM is set to “1”, the test holding control signals THLD0 and THLD1 are set to “0”, and the holding control stored in the scan flip-flops HSFF and HSFFa when the shift mode control signal SM is “0”. Observation may be performed after the logic of the signals HLD0 and HLD1 is taken out as scan-out data SO from the scan path. For example, observation of other control signals such as the test holding control signals THLD0 and THLD1 is also possible by using a similar configuration.
[0162]
As described above, the selectors 14 and 14a are controlled by the shift mode control signal SM, but a control terminal not newly related to the control of the test circuits TC and CTC is newly provided, and the selectors 14 and 14a are controlled by the control signal output from the control terminal. It is also possible to control 14a. However, as described above, by using the shift mode control signal SM and also controlling the selectors 14 and 14a, the following advantages arise.
[0163]
In the test circuits TC and CTC of this embodiment, when the test control signal TEST is “1”, the shift mode control signal SM is set to “0”, so that the input data IN is input via the connection circuit CC on the input side. Is taken into the input terminal DI. At this time, on the output side, output data DO, which is a test result of the data circuit 1, is output to the data output terminal OUT via the connection circuit CCC. When shift mode control signal SM is “0”, control signals HLD0 and HLD1 are stored in scan flip-flops HSFF and HSFFa in selectors 14 and 14a, but are not shifted into test circuit TC. In the scan test, when the test pattern is shifted in or the test result is shifted out, the shift mode control signal SM is set to “1”. Therefore, since the test pattern shifted in from the scan-in terminal SI is conducted in the selectors 14 and 14a, the scan flip-flops HSFF and HSFFa do not hinder the test pattern shift-in or the test result shift-out. Even if the selectors 14 and 14a are controlled by the shift mode control signal SM, the scan test operation is not adversely affected. Therefore, by using the shift mode control signal SM, a control signal is given to the scan flip-flops HSFF and HSFFa. It is possible to reduce the number of control terminals.
[0164]
In FIG. 16, the scan flip-flops HSFF and HSFFa are inserted between the scan-in terminal SI and the scan-in terminal si of the test circuit TC, but the scan-out terminal so of the test circuit TC and the scan-in terminal of the test circuit CTC. Even if it is inserted between si, the same effect can be obtained, and the holding control signals HLD0 and HLD1 can be observed. Further, the same effect can be obtained even if it is inserted between the scan-out terminal so and the scan-out terminal SO of the test circuit CTC.
[0165]
In the above description, the number of control signals to be observed is two, but the number of control signals that can be observed is not limited to two. Obviously, when there are a plurality of control signals to be observed, the plurality of scan flip-flops may be connected in series.
[0166]
Since the holding functions of the test circuits TC and CTC according to the present embodiment can also be used during normal operation and scan test operation, the circuit area can be reduced by eliminating overhead.
[0167]
Next, another control circuit according to the present embodiment will be described. FIG. 18 is a circuit diagram showing a control circuit CTL3a having the same function as that of the control circuit CTL3 shown in FIG.
[0168]
The difference between the control circuit CTL3a and the control circuit CTL3 is only the difference in configuration. The difference in configuration is a difference in terminals connected to the data input 0 terminal of the selector 6, and the output terminal of the selector 5 is connected to the data input 0 terminal of the selector 6.
[0169]
The circuit operation of the control circuit CTL3a will be described. In view of the difference in configuration described above, it is only necessary to consider when the test control signal TEST is “0”. When the test control signal TEST is “0”, the selector 6 outputs the output of the selector 5, so that the holding control signal HLD 0 is output from the output terminal of the selector 6.
[0170]
Therefore, the circuit operation of the control circuit CTL3a is the same as the circuit operation of the control circuit CTL3.
[0171]
In FIG. 17, the control circuit CTL3 is directly connected to the holding terminal HLD0, the test holding terminal THLD0, and the shift mode control signal SM. By setting the shift mode control signal SM input to the control terminal of the selector 14 to “0” during normal operation, the holding terminal HLD0 is connected to the control circuit CTL3 via the scan flip-flop HSFF as in the circuit shown in FIG. It is also possible to connect.
[0172]
Next, a test circuit according to the present embodiment that can be obtained by changing the configuration of the scan flip-flop will be described. Components having the same configuration and function as those of the above-described circuits and the like are denoted by the same reference numerals, and description thereof is omitted.
[0173]
FIG. 20 is a circuit diagram showing a logic circuit and a test circuit according to the present embodiment. Test circuit TCS according to the present embodiment is a circuit that can be used in place of test circuit TC. Similarly to the test circuit TC, the test circuit TCS according to the present embodiment is composed of a flip-flop 4, a holding function switching selector 2, and a scan mode switching selector 3. The selector 2 is controlled by the test holding control signal thld, and the selector 3 is controlled by the shift mode control signal sm.
[0174]
The difference between the test circuit TC and the test circuit TCS is that the order of the selector 2 for switching the holding function and the selector 3 for switching the scan mode are switched.
[0175]
The test circuit TCS will be described. The test circuit TCS can be used on either the input side or the output side of the data circuit 1. The operation of the test circuit TCS used on the output side is the same as the operation of the test circuit TCS used on the input side. Accordingly, only the input side is shown in the figure, and only the input side is performed except when the explanation is required.
[0176]
The input of the data circuit 1 is controlled by the test circuit TCS. The test circuit TCS is inserted between the data input terminal IN and the input terminal DI of the data circuit 1. The test circuit TCS has input terminals d [0] to [3] for inputting the input data IN [0] to [3] and output terminals q [0] to [3] for outputting to the input terminal DI of the data circuit 1. 3], and a circuit including a scan-in terminal si, a test holding terminal thld, a shift mode terminal sm and a scan-out terminal so.
[0177]
An operation of the test circuit TCS by the test holding control signal thld and the shift mode control signal sm input to the test holding terminal thld and the shift mode terminal sm, respectively, will be described. When the shift mode control signal sm is “0” and the test holding control signal thld is “0”, the test circuit TCS captures the data input to the input terminal d and outputs it directly from the output terminal q. When the shift mode control signal sm is “1” and the test holding control signal thld is “0”, the test circuit TCS takes in the data input to the scan-in terminal si and outputs it from the scan-out terminal so. When the test holding control signal thld is “1”, data is held in the test circuit TCS.
[0178]
The test circuit TCS performing the above operation is configured as follows. The output terminal [N−1] of the flip-flop 4 is connected to the data input 1 terminal of the selector 3 [N]. However, particularly when N = 0, the scan-in terminal si is connected to the data input 1 terminal of the selector 3 [0]. The data input terminal IN is connected to the data input 0 terminal of the selector 3 [N]. The output terminal of the selector 3 [N] is connected to the data input 0 terminal of the selector 2 [N]. The output terminal of the flip-flop 4 [N] is connected to the data input 1 terminal of the selector 2 [N]. The output terminal of the selector 2 [N] is connected to the input terminal of the flip-flop 4 [N]. As described above, the output terminal of the flip-flop 4 [N] is connected to the data input 1 terminal of the selector 2 [N].ConnectionFurther, the input terminal DI [N] and the selector 3 [N + 1] of the data circuit 1 are connected in common. However, particularly when N = 3, the output terminal of the flip-flop 4 [3] is connected in common to the data input 1 terminal of the selector 2 [3], the input terminal DI [3], and the scan-out terminal so of the test circuit TCS. The
[0179]
When the test circuit TCS is provided on the output side of the data circuit 1, in the above description,
Data input terminal IN → Output terminal DO
Input terminal DI → Data output terminal OUT
You can think by converting like this.
[0180]
The normal operation and the scan test operation can be performed also by the above-described test circuit TCS.
[0181]
Next, the control circuit CTL4 according to the present embodiment that gives the test holding control signal thld and the shift mode control signal sm to the test circuit TCS will be described. The control circuit CTL4 has a test control signal TEST and a shift mode control signal SM., Test holding control signal THLD0The holding control signal HLD0 is input, and the test holding control signal thld and the shift mode control signal sm are output to the test circuit TCS.
[0182]
The control circuit CTL4 always outputs the shift mode control signal SM as the shift mode control signal sm. When the test control signal TEST is “0”, the control circuit CTL4 outputs the holding control signal HLD0 as the test holding control signal thld. When the test control signal TEST is “1”, the test holding control signal THLD0 is output as the test holding control signal thld.
[0183]
The connection of the control circuit CTL4 will be described with reference to FIG. The control circuit CTL4 includes a selector called selector 5. A test control signal TEST is input to the control terminal of the selector 5.
[0184]
A holding terminal HLD 0 is connected to the data input 0 terminal of the selector 5. Test holding control at the data input 1 terminal of the selector 5TerminalTHLD0 is connected. The output terminal of the selector 5 is connected to the test holding terminal thld of the test circuit TCS. The shift mode control signal SM is directly connected to the shift mode terminal sm of the test circuit TCS.
[0185]
Regarding the control circuit CTL4 used on the output side of the data circuit 1, in the above description,
Holding terminal HLD0 → Holding terminal HLD1
Test holding terminal THLD0 → Test holding terminal THLD1
You can think by converting like this.
[0186]
The normal operation and the scan test operation can be performed also by the above-described test circuit TCS.
[0187]
The circuit operation of the circuit shown in FIG. 20 is summarized below. The case where the test circuit TCS is provided on the input side and the output side of the data circuit 1 will be described. As the circuit operation, there are a normal operation and a scan test operation.
[0188]
The circuit operation during the normal operation is the same as the circuit operation of the circuit composed of the control circuit CTL1, CTL2 or CTL3 and the test circuit TC.
[0189]
Next, the scan test operation will be described. Only at the time of execution and at the time of holding data, the operation of the circuit comprising the control circuit CTL4 and the test circuit TCS is different from the operation of the circuit comprising the control circuit CTL3 and the test circuit TC. Therefore, only the execution time and the data holding time will be described.
[0190]
1. runtime
By setting the shift mode control signal SM to “0” and the test holding control signal THLD1 to “0”, the same circuit operation as the circuit composed of the control circuit CTL3 and the test circuit TC can be obtained.
[0191]
2. When holding
When it is desired to hold data on the input side during the scan test, the test holding control signal THLD0 may be set to “1”. When it is desired to hold data on the output side, the test holding control signal THLD1 is set to “1”.
[0192]
The above is the circuit operation of the control circuit shown in FIG. When the test circuits TCS are provided on the input side and the output side of the data circuit 1, the input side and output side test circuits TCS can be simultaneously controlled by the shift mode control signal SM.
[0193]
A scan path configured by the test circuit TCS will be described. When the test circuit TCS is provided on the input side of the data circuit 1, two selectors 2 and 3 are included between the data input terminal IN and the input terminal DI of the logic circuit. Similarly, when the test circuit TCS is provided on the output side of the data circuit 1, two selectors 2 and 3 are included between the output terminal DO and the data output terminal OUT. Accordingly, during normal operation, only the operation speed similar to that of the test circuit according to the prior art can be obtained.
[0194]
However, since the control circuit CTL4 that controls the test circuit TCS includes only one selector, the selector 5, it is possible to reduce the circuit area. The test circuit TCS can also be used during the normal operation and the scan test operation by using the hold function of the test circuit TCS. Therefore, the circuit area can be reduced by eliminating overhead.
[0195]
Embodiment 3 FIG.
The invention according to the present embodiment relates to a control circuit for controlling a test circuit.
[0196]
The control circuit according to the present embodiment is a control circuit that controls the test circuit TC or CTC, and has a simpler configuration than the control circuit shown in the first and second embodiments. The control circuit that controls the test circuit TC or CTC is a circuit that provides the test holding control signal thld and the shift mode control signal sm to the test circuit TC or CTC. Hereinafter, since the configuration and operation of the control circuit are not changed in the test circuit TC and the test circuit CTC, only the test circuit TC will be described as a controlled circuit. The following description will be given regarding the input side of the data circuit 1, but the same applies to the output side.
[0197]
FIG. 21 is a circuit diagram showing a control circuit CTL5 according to the present embodiment. The control circuit CTL5 receives the holding control signal HLD0, the test holding control signal THLD0, the shift mode control signal SM and the test control signal TEST, and supplies the test holding control signal thld and the shift mode control signal sm to the test circuit TC. By setting the test holding control signal THLD0 to “0” during normal operation, the control circuit CTL5 has a smaller circuit area than the control circuit shown in the second embodiment. When providing the control circuit CTL5 in the test circuit TC on the output side,
Holding control signal HLD0 → Holding control signal HLD1
Test holding control signal THLD0 → Test holding control signal THLD1
You can convert as follows.
[0198]
The configuration of the control circuit CTL5 will be described with reference to FIG. The control circuit CTL5 can be configured using three gates. Each gate has two input terminals and one output terminal. One gate is a gate 41 and the remaining two are OR gates 42 and 43.
[0199]
The gate 41 has an input terminal ge and an inverting input terminal re. Gate 41Is a gate that takes the logical product of the inverted logic of the input signal re input to the inverting input terminal re and the input signal ge input to the input terminal ge. Each of the OR gates 42 and 43 is a gate that takes a logical sum of two input signals that are input.
[0200]
The connection state of the control circuit CTL5 will be described. A test terminal TEST is connected to the inverting input terminal of the gate 41. The holding terminal HLD0 is connected to the input terminal ge of the gate 41. The output terminal of the gate 41 is commonly connected to one input terminal of each of the OR gates 42 and 43. The test holding terminal THLD0 is connected to the other input terminal of the OR gate. The shift mode terminal SM is connected to the other input terminal of the OR gate 43. The output terminal of the OR gate 42 outputs the test holding control signal thld to the test circuit TC, and the output terminal of the OR gate 43 outputs the shift mode control signal sm to the test circuit TC.
[0201]
The circuit operation of the control circuit shown in FIG. 21 is summarized below. The circuit operation includes normal operation control and scan test operation control. Table 4 shows the optimum setting values of the respective signals and data related to the control circuit CTL5 in the normal operation and the scan test.
[0202]
[Table 4]

[0203]
The difference between the circuit operation of the control circuit CTL5 and the circuit operation of the control circuit CTL3 in normal operation will be described. In the normal operation, the test control signal TEST is set to “0” similarly to the setting in the control circuit CTL3. In particular, in the control circuit CTL5, the shift mode control signal SM and the test holding control signal THLD0 are set to “0”. With the above settings, the circuit operation of the control circuit CTL5 during normal operation is the same as the circuit operation of the control circuit CTL3.
[0204]
Since the circuit operation of the control circuit CTL5 in the scan test operation is the same as the circuit operation of the control circuit CTL3, description thereof is omitted.
[0205]
Even when the control of the test circuit TC is performed using the control circuit CTL5, the control of the normal operation and the control of the scan test operation shown in the second embodiment can be obtained.
[0206]
Since the control circuit CTL5 is composed of three gates, the circuit area of the semiconductor device can be reduced by performing control using the control circuit CTL5 with the test holding control signal set to “0”.
[0207]
FIG. 22 shows a control circuit CTL5a configured similarly to the control circuit CTL5 and having the same function.
[0208]
The configuration and connection of the control circuit CTL5a will be described based on the difference from the configuration of the control circuit CTL5. Similar to the control circuit CTL5, the control circuit CTL5a can be configured by using three gates of a gate 41a and OR gates 42a and 43a. The gate 41a and the OR gates 42a and 43a have the same configuration and function as the gate 41 and the OR gates 42 and 43, respectively.
[0209]
In the control circuit CTL5, the output terminal of the gate 41 is connected to one input terminal of the OR gate 43. In the control circuit CTL5a, the output terminal of the OR gate 42a is connected to one input terminal of the OR gate 43a. Is done.
[0210]
Since there is no difference between the circuit operation of the control circuit CTL5 and the circuit operation of the control circuit CTL5a due to the difference in connection as described above, the description regarding the circuit operation is omitted.
[0211]
The control circuit CTL5a is configured similarly to the control circuit CTL5, and the circuit operation of the control circuit CTL5a is the same as the circuit operation of the control circuit CTL5. Therefore, the same effect as that of the control circuit CTL5 can be obtained by using the control circuit CTL5a.
[0212]
Next, similarly to the control circuit CTL2 shown in the first embodiment, the control circuit CTL6 that can control the test circuits TC and CTC without receiving the test control signal TEST will be described.
[0213]
FIG. 23 is a circuit diagram showing a control circuit CTL6 according to the present embodiment. Although the shift mode control signal SM is set to “0” in the control circuit CTL5, the test terminal TEST is omitted in the control circuit CTL6 by further setting the holding control signal HLD0 to “0” during the scan test operation. .
[0214]
When providing the control circuit CTL6 in the test circuit TC on the output side,
Holding control signal HLD0 → Holding control signal HLD1
Test holding control signal THLD0 → Test holding control signal THLD1
You can convert as follows.
[0215]
The configuration of the control circuit CTL6 will be described with reference to FIG. The control circuit CTL6 includes a selector 5 and an OR gate 45.
[0216]
The connection state of the control circuit CTL6 will be described. The selector 5 has a data input 0 terminal, a data input 1 terminal, an output terminal, and a control terminal.EndA selector with children. The holding terminal HLD0 is commonly connected to the data input 0 terminal of the selector 5 and one input terminal of the OR gate 45. A test holding terminal THLD0 is connected to the data input 1 terminal of the selector 5. The shift mode terminal SM is commonly connected to the control terminal of the selector 5 and the other input terminal of the OR gate 45. The output terminal of the selector 5 outputs the test holding control signal thld to the test circuit TC, and the output terminal of the OR gate 45 outputs the shift mode control signal sm to the test circuit TC.
[0217]
The circuit operation of the control circuit shown in FIG. 23 is summarized below. The circuit operation includes normal operation control and scan test operation control. Table 5 shows optimum setting values of the respective signals and data related to the control circuit CTL6 in the normal operation and the scan test.
[0218]
[Table 5]

[0219]
In the normal operation, by setting the shift mode control signal SM to “0”, it is possible to obtain the same circuit operation as that of the control circuits CTL3 and CTL5.
[0220]
Next, the circuit operation of the control circuit CTL6 in the scan test operation will be described. In the scan test operation, the shift mode control signal SM is set to “1” when the test pattern is shifted in, the test result is shifted out, and the data is held. The circuit operation of the control circuit CTL6 at this time is the same as that of the control circuits CTL3 and CTL5. When executing the scan test operation, the shift mode control signal SM is set to “0” and the holding control signal HLD0 is set to “0”, whereby the circuit operation of the control circuit CTL6 is the same as the circuit operation of the control circuits CTL3 and CTL5. It will be the same.
[0221]
Therefore, even when the control of the test circuit TC is performed using the control circuit CTL6, it is possible to obtain the control of the normal operation and the control of the scan test operation shown in the second embodiment.
[0222]
By setting the holding control signal HLD0 to “0” during the scan test operation, the control circuit CTL6 can control the test circuit TC without using the test terminal TEST. Since the test terminal TEST can be omitted, when the control circuit according to the present embodiment is used, the circuit area of the semiconductor device is reduced.
[0223]
A control circuit CTL6a having the same function as that of the control circuit CTL6 is shown in FIG.4Shown in
[0224]
The configuration of the control circuit CTL6a will be described with reference to FIG. The control circuit CTL6a is configured by the selector 5a and the OR gate 45a having the same configuration and function as the selector 5 and the OR gate 45 constituting the control circuit CTL6.
[0225]
In the control circuit CTL6, the holding terminal HLD0 is connected to one input terminal of the OR circuit 45. In the control circuit CTL6a, the output terminal of the selector 5a is connected to one input terminal of the selector 45a. The circuit operation does not differ depending on the connection state, the circuit operation of the control circuit CTL6a is the same as the circuit operation of the control circuit CTL6, and the same operation as the control circuit CTL6 is performed even if the control circuit CTL6a is used. Is possible.
[0226]
Therefore, even when the control of the test circuit TC is performed using the control circuit CTL6a, it is possible to obtain the normal operation control and the scan test operation control described in the second embodiment. Further, the same effect as that obtained by the control circuit CTL6 can be obtained by using the control circuit CTL6a.
[0227]
Next, a control circuit obtained by further simplifying the configuration of the control circuit shown in this embodiment will be described.
[0228]
FIG. 25 is a circuit diagram showing a control circuit CTL7 according to the present embodiment. The terminals provided in the control circuit CTL7 are the same as the terminals provided in the control circuit CTL6. The circuit configuration of the control circuit CTL7 is very similar to the circuit configuration of the control circuit CTL5. Table 6 shows optimum setting values of the respective signals and data regarding the control circuit CTL7 in the normal operation and the scan test.
[0229]
[Table 6]

[0230]
In the control circuit CTL7, the shift mode control signal SM and the test holding control signal THLD0 are set to “0” during normal operation, and the holding control signal HLD0 is set to “0” during the scan test operation, thereby controlling even a small circuit configuration. The same circuit operation as the circuits CTL5 and CTL6 is obtained.
[0231]
The configuration and connection state of the control circuit CTL7 will be described with reference to FIG. Similar to the control circuit CTL5, the control circuit CTL7 can be configured using three gates of the gate 50 and the OR gates 51 and 52. The gate 50 is a gate constituting the control circuit CTL541Has the same structure and function.
[0232]
The connection state of the control circuit CTL7 will be described based on the difference from the control circuit CTL5. In the control circuit CTL5, the test terminal TEST is connected to the inverting input terminal re of the gate 41, and the holding terminal HLD0 is connected to one input terminal of the OR gate 43. A shift mode terminal SM is connected to the inverting input terminal of the gate 50, and a holding terminal HLD 0 is connected to one input terminal of the OR gate 52. The connection of the other terminals is the same in the control circuit CTL5 and the control circuit CTL7.
[0233]
In order to understand the circuit operation of the control circuit CTL7, shift mode control is used instead of the test holding terminal TEST.TerminalSMButThe operation of the gate 50 connected to the inverting input terminal re and the holding terminal HLD0 as one input terminalButIt is sufficient to understand the operation of the connected OR gate 52.
[0234]
First, the operation of the gate 50 will be described. In the control operation using the control circuit CTL5, the values of the test control signal TEST and the shift mode control signal SM in the normal operation and the scan test operation differ only when the scan test is executed. Therefore, the gate 50 in which the shift mode terminal SM is connected to the inverting input terminal re need only be considered when the scan test is performed. However, when the scan test is executed, the OR gate 52 whose output terminal is connected to the control terminal of the selector 3 only needs to output “0”. In the control circuit CTL7, the holding control signal HLD0 is “ When the scan test is executed, the shift mode control signal SM is set to “0”, so this condition is satisfied. Therefore, the operation of the gate 50 does not affect the execution of the scan test.
[0235]
Next, the operation of the OR gate 52 will be described. If the shift mode control signal SM is “1”, the OR gate 52 always outputs “1”, which is the same as the operation of the OR gate 43. Therefore, it is only necessary to understand the normal operation time when the shift mode control signal SM is “0” and the scan test execution time. The explanation regarding the execution time of the scan test has already been made when the operation of the gate 50 is explained. The OR gate 52 only needs to output “0” during normal operation, and the holding control signal HLD0 is set to “0” during normal operation, so this condition is satisfied.
[0236]
From the above description, it can be seen that the circuit operation of the control circuit CTL7 and the circuit operation of the control circuit CTL5 are the same.
[0237]
Therefore, even when the control of the test circuit TC is performed using the control circuit CTL7, it is possible to obtain the normal operation control and the scan test operation control shown in the second embodiment.
[0238]
Since the control circuit CTL7 is composed of three gates, the test holding control signal THLD0 is set to “0” and control is performed using the control circuit CTL7, so that the circuit of the semiconductor device is more than the case where control is performed using the control circuit CTL6. It is possible to reduce the area.
[0239]
Also, by setting the holding control signal HLD0 to “0” during the scan test operation, the control circuit CTL7 can control the test circuit TC without using the test terminal TEST. Since the test terminal TEST can be omitted, the use of the control circuit according to the present embodiment further reduces the circuit area of the semiconductor device.
[0240]
FIG. 26 shows a control circuit CTL7a having the same configuration and the same function as the control circuit CTL7, and FIG. 27 shows a control circuit CTL7b. FIG. 26 is a circuit diagram showing a control circuit CTL7a according to the present embodiment, and FIG. 27 is a circuit diagram showing a control circuit CTL7b according to the present embodiment.
[0241]
The difference between the configuration of the control circuits CTL7a and CTL7b and the configuration of the control circuit CTL7 is shown in FIGS.7Based on the explanation. The control circuit CTL7a is configured by the gate 50a and the OR gates 51a and 52a, and the control circuit CTL7b is configured by the gate 50b and the OR gates 51b and 52b. The gates 50a and 50b, the OR gates 51a and 51b, and the OR gates 52a and 52b have the same functions and configurations as the gate 50, the OR gate 51, and the OR gate 52, respectively.
[0242]
The connection state of the control circuits CTL7a and CTL7b will be described based on the difference from the control circuit CTL7. In the control circuit CTL7, the holding terminal HLD0 is connected to one input terminal of the OR circuit 52. In the control circuit CTL7a, the output terminal of the gate 50a is connected to one input terminal of the OR gate 52a. In the control circuit CTL7b, the output terminal of the OR gate 51b is connected to one input terminal of the OR gate 52b.
[0243]
The circuit operation of the control circuits CTL7, CTL7a, and CTL7b does not differ due to the difference in connection described above, and it is possible to control the test circuit TC using the control circuits CTL7a and CTL7b instead of the control circuit CTL7. .
[0244]
By using various control circuits shown in this embodiment, the test circuit TC can be controlled.
[0245]
Embodiment 4 FIG.
In the present embodiment, a scan path is configured using the test circuit TC and the test circuit CTC shown in the second embodiment, and is used for an operation test of the RAM.
[0246]
FIG. 28 is a circuit diagram showing a RAM provided with a test circuit. Components having the same configuration and function as the circuits and the like shown in the first to third embodiments are denoted by the same reference numerals.
[0247]
As shown in the figure, the RAM 11 which is a logic circuit is controlled by the test circuits TCA0, TCDI, TCA1 and CTC which are test circuits.
[0248]
First, the RAM 11 will be described. For writing to the RAM 11, the RAM 11 includes address input terminals A0 [0] to [2] for address writing and input terminals DI0 [0] to [2] for data input. Further, the RAM 11 includes address input terminals A1 [0] to [2] for address writing and input terminals DO1 [0] to [2] for data output for reading from the RAM 11.
[0249]
The RAM 11 receives the input data DI0 [0] given to the input terminals DI0 [0] to [2] at a unique address corresponding to the input data A0 [0] to [2] given to the address input terminals A0 [0] to [2]. This is a circuit for writing to [2]. In addition, the RAM 11 outputs data input to a specific address corresponding to the input data A1 [0] to [2] given to the address input terminals A1 [0] to [2] as output terminals DO1 [0] to [2]. Is output from the circuit. Although the RAM 11 shown in this embodiment has 3 bits, the test circuit according to this embodiment can be applied to any number of bits of RAM.
[0250]
The terminals for inputting data to the address input terminals A0 [0] to [2] are the data input terminals INA0 [0] to [2], and for inputting data to the input terminals DI0 [0] to [2]. These terminals are data input terminals INDI [0] to [2]. The terminals for inputting data to the address input terminals A1 [0] to [2] are the data input terminals INA1 [0] to [2]. Terminals for outputting data output from the output terminals DO1 [0] to [2] are data output terminals OUT [0] to [2].
[0251]
Next, the test circuits TCA0, TCDI, TCA1, and CTC will be described. The test circuits TCA0, TCDI, and TCA are test circuits having the same configuration as the test circuit TC and performing the same operation. A test circuit TCA0 is inserted between the address input terminals A0 [0] to [2] and INA0 [0] to [2]. A test circuit TCDI is inserted between the input terminals DI0 [0] to [2] and INDI [0] to [2]. A test circuit TCA1 is inserted between the address input terminals A1 [0] to [2] and INA1 [0] to [2]. A test circuit CTC is inserted between the output terminals DO1 [0] to [2] and OUT [0] to [2].
[0252]
Next, the connection between the scan-in terminal SI and the scan-out terminal SO and the test circuits TCA0, TCDI, TCA1, and CTC used when performing the scan test will be described.
[0253]
In FIG. 28, scan-in terminal SI → scan flip-flops 70 and 71 → scan-in terminal si of test circuit TCA0 → scan-out terminal so of test circuit TCA0 → scan-in terminal si of test circuit TCDI → scan-out of test circuit TCDI The scan path is configured as follows: terminal so → scan-in terminal si of test circuit TCA1 → scan-out terminal so of test circuit TCA1 → scan-in terminal si of test circuit CTC → scan-out terminal so of test circuit CTC → scan-out terminal SO Has been. The scan flip-flops 70 and 71 are provided between the test circuit TCDI and the test circuit TCDI, between the test circuit TCDI and the test circuit TCA1, between the test circuit TCA1 and the test circuit CTC, and between the test circuit CTC and the scan-out terminal SO. It may be provided at any of the intervals.
[0254]
The scan flip-flops 70 and 71 will be described. The scan flip-flops 70 and 71 are scan flip-flops used for observing the holding control signals HLD0 and HLD1, respectively. Similarly to the scan flip-flop HSFF shown in FIG. 6, the scan flip-flops 70 and 71 are composed of one selector and one flip-flop. The data input terminal 0 terminal, data input 1 terminal and control terminal of the selector 14 constituting the scan flip-flop HSFF can be regarded as the data input terminal 0 terminal, data input 1 terminal and control terminal of the scan flip-flop HSFF itself. . Similarly, the scan flip-flops 70 and 71 have a data input 0 terminal, a data input 1 terminal, an output terminal, and a control terminal.EndProvide each child. In response to a signal input to the control terminal, each of the scan flip-flops 70 and 71 outputs one of a signal input to the data input 0 terminal and a signal input to the data input 1 terminal.
[0255]
Test circuits TCA0, TCDI, TCA1, and CTC are provided with a test holding terminal thld and a shift mode terminal sm, respectively, and are supplied with a test holding control signal thld and a shift mode control signal sm, respectively. The test circuit CTC further includes a comparison terminal cmpen and expected terminals exp [0] to [2], and is supplied with a comparison enable signal CMPEN and expected data EXP [0] to [2], respectively.
[0256]
A description will be given of circuits that provide the test holding control signal thld and the shift mode control signal sm to the test circuits TCA0, TCDI, TCA1, and CTC, respectively. A circuit that provides the test holding control signal thld and the shift mode control signal sm is configured using the selectors 60 to 65.
[0257]
Each of the selectors 60 to 65 is a selector having a data input 0 terminal, a data input 1 terminal, an output terminal, and a control terminal. A test terminal TEST is commonly connected to the control terminals of the selectors 60 to 65.
[0258]
The output terminals of the selectors 60 and 61 are connected to the test holding terminals thld of the test circuits TCA0 and TCDI, respectively, and provide the test holding control signal thld independently of each other. The output terminal of the selector 62 is connected in common to the respective shift mode terminals sm of the test circuits TCA0 and TCDI, and supplies the shift mode control signal sm in common. Similarly, the output terminals of the selectors 63 and 64 are connected to the test holding terminals thld of the test circuits TCA1 and CTC, respectively, and give the test holding control signal thld independently of each other. The output terminal of the selector 65 is connected in common to the shift mode terminals sm of the test circuits TCA1 and CTC, and applies the shift mode control signal sm in common.
[0259]
Next, the holding terminal will be described. The holding terminal HLD0 is connected in common to the data input 0 terminals of the scan flip-flop 70 and the selectors 60-62. Similarly, the holding terminal HLD1 is commonly connected to the data input 0 terminals of the scan flip-flop 71 and the selectors 63 to 65. The shift mode terminal SM is connected in common to the respective data input 1 terminals of the selectors 62 and 65 and the control terminals of the scan flip-flops 70 and 71. Test holding terminals THLDA0 and THLDDI0 are connected to the data input 1 terminals of the selectors 60 and 61, respectively. Test holding terminals THLDA1 and THLDDO1 are connected to the data input 1 terminals of the selectors 63 and 64, respectively.
[0260]
The circuit operation of the circuit shown in FIG. 28 will be described. The circuit operation includes a normal operation and a test operation. The test operation is an operation including a normal scan test operation and a scan test operation using a test result compression function.
[0261]
First, normal operation will be described. During normal operation, the test control signal TEST is set to “0”, and the comparison enable signal CMPEN is set to “0”. When the test control signal TEST is “0”, the selectors 60 to 65 respectively output data input to the data input 0 terminal. Accordingly, the holding control signal HLD0 is supplied to the test circuits TCA0 and TCDI as the test holding control signal thld and the shift mode control signal sm. The holding control signal HLD1 is supplied to the test circuits TCA1 and CTC as the test holding control signal thld and the shift mode control signal sm. At this time, if the holding control signal HLD0 is “0”, the input data INA0 and INDI are taken into the address input terminal A0 and the input terminal DI of the RAM 11 via the test circuits TCA0 and TCDI, respectively. If the holding control signal HLD0 is “1”, the input data INA0 and INDI are held in the test circuits TCA0 and TCDI. Similarly, if the holding control signal HLD1 is “0”, the input data INA1 is taken into the address input terminal A1 of the RAM 11 via the test circuit TCA1. The output data DO1 is output to the data output terminal OUT via the test circuit CTC. If the holding control signal HLD1 is “1”, the input data INA1 and the output data DO1 are held in the test circuits TCA1 and CTC.
[0262]
That is, in the normal operation, the holding of the data in the test circuits TCA0 and TCDI is simultaneously controlled by the holding control signal HLD0. Further, data holding in the test circuits TCA1 and CTC is simultaneously controlled by the holding control signal HLD1. Accordingly, data holding at the address input terminal A0 for writing and the input terminal DI0 and data holding at the address input terminal A1 for reading and the output terminal DO1 are controlled independently.
[0263]
Next, the test operation will be described. During the test operation, the test control signal TEST is set to “1”, and the comparison enable signal CMPEN is set to “0”. When the test control signal TEST is “1”, the selectors 60 to 65 respectively output data input to the data input 1 terminal. At this time, the test holding control signal THLDA0 and the shift mode control signal SM are input to the test circuit TCA0 as the test holding control signal thld and the shift mode control signal sm, respectively. The test holding control signal THLDDI0 and the shift mode control signal SM are input to the test circuit TCDI as the test holding control signal thld and the shift mode control signal sm, respectively. The test holding control signal THLDA1 and the shift mode control signal SM are input to the test circuit TCA1 as the test holding control signal thld and the shift mode control signal sm, respectively. The test holding control signal THLDDO1 and the shift mode control signal SM are used as the test holding control signal thld and the shift mode control signal sm, respectively.CTCIs input.
[0264]
Summarize the control in the test operation. The shift mode control signal SM is input as a shift mode control signal sm in common to the test circuits TCA0, TCDI, TCA1, and CTC, and selection of data input in the test circuits TCA0, TCDI, TCA1, and CTC is controlled. Data holding in the test circuits TCA0, TCDI, TCA1, and CTC is independently performed by test holding control signals THLDA0, THLDDI0, THLDA1, and THLDDO1.
[0265]
By holding data in each test circuit independently, the following advantages are obtained.
[0266]
The path from the address input terminals A0, A1 and the input terminal DI to the output terminal DO of the RAM 11 includes a total of two flip-flops, each consisting of one flip-flop on the input terminal side and one flip-flop on the output terminal side. I think. Here, consider the case where there is a logic circuit 12 that must synchronize the RAM 11. Assume that the path between the input terminal and the output terminal of the logic circuit 12 includes, for example, three flip-flops. In order to synchronize the RAM 11 and the logic circuit 12, it is preferable to hold the data in the RAM 11 for the time required for the data to pass through one flip-flop. That is, synchronization can be achieved by holding data by the number of flip-flops included in the path.
[0267]
In the circuit shown in FIG. 28, the data holding at the address input terminal A0 for writing and the input terminal DI and the data holding at the address input terminal A1 for reading and the output terminal DO are independently controlled during normal operation. Is done. Therefore, it is possible to synchronize the output of the RAM 11 in a flexible manner corresponding to the number of flip-flops included in the logic circuit 12 that must be synchronized to form a path.
[0268]
During the test operation, data holding at the address input terminal A0, data holding at the input terminal DI, data holding at the address input terminal A1, and data holding at the output terminal DO are controlled independently. Therefore, the operation test of the RAM 11 can be performed efficiently.
[0269]
Next, even during normal operation, data holding at the address input terminal A0, data holding at the input terminal DI, data holding at the address input terminal A1, and data holding at the output terminal DO are independent of each other. FIG. 29 shows a circuit that can be controlled.
[0270]
FIG. 29 is a circuit diagram showing a RAM provided with a test circuit. As in the circuit shown in FIG. 28, in this figure, the RAM 11 which is a logic circuit is controlled in input / output by the test circuits TCA0, TCDI, TCA1 and CTC which are test circuits.
[0271]
In order to control data retention independently during normal operation, the holding terminal shown in FIG.
Holding terminal HLD0 → Holding terminals HLDA0, HLDDI0
Holding terminal HLD1 → Holding terminals HLDA1, HLDDO1
It is converted like this. Along with the conversion of the holding terminal, regarding the selector and scan flip-flop,
Selector 62 → selectors 62a, 62b
Selector 65 → selectors 65a, 65b
Scan flip-flop 70 → scan flip-flops 70a and 70b
Scan flip-flop 71 → scan flip-flops 71a and 71b
The conversion like this is given. The selectors 62a, 62b, 65a, 65b are selectors having the same configuration and function as the selectors 62, 65, respectively. Similarly, the scan flip-flops 70a, 70b, 71a, 71b are scan flip-flops having the same configuration and function as the scan flip-flops 70, 71, respectively. Only the parts different from the circuit shown in FIG. 28 will be described below with respect to the circuit shown in FIG.
[0272]
The scan flip-flops 70a, 70b, 71a, 71b will be described. The scan flip-flops 70a, 70b, 71a, 71b are scan flip-flops used for observing the holding control signals HLDA0, HLDDI0, HLDA1, and HLDO1, respectively. Each of the scan flip-flops 70a, 70b, 71a, 71b includes a data input 0 terminal, a data input 1 terminal, an output terminal, and a control terminal. Depending on the signal input to the control terminal, each of the scan flip-flops 70a, 70b, 71a, 71b is either a signal input to the data input 0 terminal or a signal input to the data input 1 terminal. Is output.
[0273]
A description will be given of circuits that provide the test holding control signal thld and the shift mode control signal sm to the test circuits TCA0, TCDI, TCA1, and CTC, respectively. Using the selectors 60, 61, 62a, 62b, 63, 64, 65a, and 65b, a circuit that provides the test holding control signal thld and the shift mode control signal sm is configured.
[0274]
The selectors 60, 61, 62a, 62b, 63, 64, 65a, and 65b are selectors each having a data input 0 terminal, a data input 1 terminal, an output terminal, and a control terminal. A test terminal TEST is commonly connected to the control terminals of these selectors.
[0275]
The output terminals of the selectors 60 and 62a are connected to the test holding terminal thld and the shift mode terminal sm of the test circuit TCA0, and give the test holding control signal thld and the shift mode control signal sm. By the same connection, the selectors 61 and 62b supply the test holding control signal thld and the shift mode control signal sm to the test circuit TCDI. The selectors 63 and 65a supply the test holding control signal thld and the shift mode control signal sm to the test circuit TCA1. The selectors 64 and 65b supply the test holding control signal thld and the shift mode control signal sm to the test circuit CTC.
[0276]
Next, the holding terminal will be described. The holding terminal HLDA0 is commonly connected to the data input 0 terminals of the scan flip-flop 70a and the selectors 60 and 62a. The holding terminal HLDDI0 is commonly connected to the data input 0 terminals of the scan flip-flop 70b and the selectors 61 and 62b. Similarly, the holding terminal HLDA1 is commonly connected to the data input 0 terminals of the scan flip-flop 71a and the selectors 63 and 65a. The holding terminal HLDDO1 is commonly connected to the data input 0 terminals of the scan flip-flop 71b and the selectors 63 and 65b. The shift mode terminal SM is connected in common to the data input 1 terminal of each of the selectors 62a, 62b, 65a, 65b and the control terminals of the scan flip-flops 70a, 70b, 71a, 71b. Test holding terminals THLDA0 and THLDDI0 are connected to the data input 1 terminals of the selectors 60 and 61, respectively. Test holding terminals THLDA1 and THLDDO1 are connected to the data input 1 terminals of the selectors 63 and 64, respectively.
[0277]
The circuit operation of the circuit shown in FIG. 29 will be described. Similar to the circuit shown in FIG. 28, there are a normal operation and a test operation as circuit operations.
[0278]
First, normal operation will be described. During normal operation, the test control signal TEST is set to “0”, and the comparison enable signal CMPEN is set to “0”. When the test control signal TEST is “0”, the selectors 60, 61, 62 a, 62 b, 63, 64, 65 a, 65 b output data input to the data input 0 terminal, respectively. Accordingly, the holding control signal HLDA0 is supplied to the test circuit TCA0 as the test holding control signal thld and the shift mode control signal sm. The holding control signal HLDDI0 is supplied to the test circuit TCDI as the test holding control signal thld and the shift mode control signal sm. Similarly, the holding control signal HLDA1 is supplied to the test circuit TCA1 as the test holding control signal thld and the shift mode control signal sm. The holding control signal HLDDO1 is supplied to the test circuit CTC as the test holding control signal thld and the shift mode control signal sm.
[0279]
Accordingly, by switching between “0” and “1” of the holding control signals HLDA0, HLDDI0, HLDA1, and HLDO1, respectively, the input data INA0, INDI, INA1 and the output of OUT in the test circuits TCA0, TCDI, TCA1, CTC It is possible to control switching of data retention independently of each other.
[0280]
Next, the test operation will be described. During the test operation, the test control signal TEST is set to “1”, and the comparison enable signal CMPEN is set to “0”. When the test control signal TEST is “1”, the selectors 60, 61, 62 a, 62 b, 63, 64, 65 a, 65 b output data input to the data input 1 terminal, respectively. As described above, the shift mode terminal SM is commonly connected to the data input 1 terminals of the selectors 62a, 62b, 65a, and 65b. Similarly to the circuit shown in FIG. 28, the test holding terminals THLDA0 and THLDDI0 are connected to the data input 1 terminals of the selectors 60 and 61, respectively, and the data input 1 terminals of the selectors 63 and 64 are tested. Holding terminals THLDA1 and THLDDO1 are connected to each other. Therefore, the circuit operation during the test operation is the same as the circuit operation of the circuit shown in FIG.
[0281]
That is, in the circuit shown in FIG. 29, the same circuit operation as that of the circuit shown in FIG. 28 can be obtained during the test operation. During normal operation, it is possible to independently control data holding at the address input terminal A0, data holding at the input terminal DI, data holding at the address input terminal A1, and data holding at the output terminal DO. There are even more excellent effects.
[0282]
【The invention's effect】
According to the structure of Claims 1-6, the switching circuit contained between the connection circuit input terminal and the connection circuit output terminal is one. Therefore, the setup is reduced by connecting the terminal for normal operation to the input terminal for connection circuit, and the circuit speed during normal operation is improved.
[0283]
According to the configuration of claim 1, the first control input signal for the control circuit and the second control for the control circuitinputA control circuit is used that ignores one of the logic of the signals in the control of the connection circuit by receiving the control circuit test signal. Therefore, ignored controlinputThe connection circuit can be controlled independently of the signal logic.
[0284]
According to the configuration of the second aspect, the first control input signal for the control circuit and the second control for the control circuitinputA control circuit that controls the connection circuit by receiving the signal is used. Therefore, it is possible to control the connection circuit with a control signal smaller than the control signal described in claim 1.
[0285]
According to the configuration of the third aspect, the control circuit first and third control input signals and the control circuit second control are provided.inputA control circuit that ignores one of the signals in the control of the connection circuit by receiving the control circuit test signal is used. Therefore, ignored controlinputThe connection circuit can be controlled independently of the signal logic.
[0286]
According to a fourth aspect of the present invention, when the control circuit test signal takes the first logic, the first and third control input signals for the control circuit also take the first logic. First and third control input signals and second control for control circuitinputA control circuit that ignores one of the signals in the control of the connection circuit by receiving the control circuit test signal is used. Therefore, ignored controlinputThe connection circuit can be controlled independently of the signal logic.
[0287]
According to the configuration of the fifth aspect, the first and third control input signals for the control circuit and the control circuit are set under the setting that the first control input signal for the control circuit takes the first logic during normal operation. Second controlinputA control circuit that ignores one of the signals in the control of the connection circuit by receiving the control circuit first control input signal is used. Therefore, ignored controlinputThe connection circuit can be controlled independently of the signal logic.
[0288]
According to the configuration of the sixth aspect, the first and third control input signals for the control circuit are set under the setting that the first and third control input signals for the control circuit each take the first logic during normal operation. And second control for control circuitinputA control circuit that ignores one of the signals in the control of the connection circuit by receiving the control circuit first control input signal is used. Therefore, ignored controlinputThe connection circuit can be controlled independently of the signal logic.
[0289]
  Claim 7And 8According to the configuration described above, when the first and second control input signals for the connection circuit take the second logic, the connection circuit holds the signal and compresses the test result. Therefore, the number of observations of the test result can be reduced by compressing the test result.
[0290]
  Claim9as well as10According to the configuration described above, when the first and second control input signals for the connection circuit take the second logic, the data stored in the memory circuit is held and the test result is compressed by switching the logic of the comparison signal. I do. Therefore, the number of observations of the test result can be reduced by compressing the test result.
[0291]
  Claim11According to the configuration described above, the control by the write control circuit and the control by the read control circuit are independent. Therefore, it is possible to independently control the synchronization operation at the write terminal and the synchronization operation at the read terminal.
[0292]
  Claim12According to the configuration described above, the control by the write address control circuit, the control by the write input control circuit, the control by the read address control circuit, and the control by the read output control circuit are independent. Accordingly, the synchronization operation at the write address terminal, the synchronization operation at the write input terminal, the synchronization operation at the read address terminal, and the synchronization operation at the read output terminal can be controlled independently.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a logic circuit provided with a test circuit comprising a test circuit TC and a control circuit CTL1 according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a connection circuit CC.
FIG. 3 is a circuit diagram showing a test circuit TC according to the present invention.
FIG. 4 is a circuit diagram showing a plurality of logic circuits provided with a scan path including a test circuit TC.
FIG. 5 is a circuit diagram showing a circuit provided with a scan flip-flop HSFF;
FIG. 6 is a circuit diagram showing a scan flip-flop HSFF according to the present invention.
FIG. 7 is a circuit diagram showing a control circuit CTL2.
FIG. 8 is a circuit diagram showing a configuration of a two-input selector.
FIG. 9 is a circuit diagram showing a control circuit CTL2a.
FIG. 10 is a circuit diagram showing a logic circuit provided with a test circuit including a test circuit CTC according to the second embodiment.
FIG. 11 is a circuit diagram showing a connection circuit CCC.
FIG. 12 is a circuit diagram showing a connection circuit CCCr.
FIG. 13 is a circuit diagram showing a test circuit CTC configured by a connection circuit CCC.
FIG. 14 is a circuit diagram showing control circuits CTL3 and CCTL3 for controlling test circuits TC and CTC, respectively.
FIG. 15 is a circuit diagram showing a circuit having a configuration in which a scan path is provided in a plurality of logic circuits.
FIG. 16 is a circuit diagram showing a circuit provided with scan flip-flops HSFF and HSFFa;
17 is a circuit diagram showing only the circuit shown in FIG. 14 on the input side.
FIG. 18 is a circuit diagram showing a control circuit CTL3a having the same function as that of the control circuit CTL3.
FIG. 19 is a circuit diagram showing a circuit having a configuration in which a holding terminal HLD0 is connected to a control circuit CTL3 via a scan flip-flop HSFF;
20 is a circuit diagram showing a test circuit TCS according to the second embodiment. FIG.
FIG. 21 is a circuit diagram showing a control circuit CTL5 according to the third embodiment.
FIG. 22 is a circuit diagram showing a control circuit CTL5a.
FIG. 23 is a circuit diagram showing a control circuit CTL6.
FIG. 24 is a circuit diagram showing a control circuit CTL6a.
FIG. 25 is a circuit diagram showing a control circuit CTL7.
FIG. 26 is a circuit diagram showing a control circuit CTL7a.
FIG. 27 is a circuit diagram showing a control circuit CTL7b.
FIG. 28 is a circuit diagram showing a RAM provided with a scan path according to the fourth embodiment.
FIG. 29 is a circuit diagram showing a circuit configured by further improving the circuit shown in FIG. 28;
FIG. 30 is a circuit diagram showing a logic circuit with a holding function.
FIG. 31 is a circuit diagram showing how the flip-flop 4 is scan-converted.
32 is a circuit diagram showing a circuit configured by scan-converting the flip-flop shown in FIG. 30;
FIG. 33 is a circuit diagram showing a connection circuit PCC.
[Explanation of symbols]
2, 3, 60 to 65 selector, 4, 4r flip-flop, 11 RAM, 30, 30r Ex-OR gate, 31 NAND gate, 31r gate, 32 AND gate, A0, 1 address input terminal, CC, CCC, CCCr connection Circuit, CMPEN, cmppen, cmppenr comparison terminal, comparison enable signal, CTL1-7 control circuit, DI, d, cd, cdr input terminal, input data, DO output terminal, output data, EXP, exp, cexp, cexpr expectation terminal, Expected data, HLD0, HLD1 holding terminal, holding control signal, q output terminal, serial input data, SI, si, csi, csir scan-in terminal, SM, sm, csm, csmr shift mode terminal, shift mode control signal, SO, so, cso, csor Scanout terminal, T, t clock terminal, TC, TCA0, TCA1, TCDI, CTC test circuit, TEST test terminal, test control signal, THLD0, THLD1, thld, cthld, cthldr Test holding terminal, test holding control signal.

Claims (12)

Comprising first and second switching circuits and a memory circuit;
A connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit first and second control terminal;
The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are different from each other in first logic and second Take binary logic consisting of logic,
The first switching circuit has a first switching circuit one input terminal, a first switching circuit other input terminal, a first switching circuit output terminal, and a first switching circuit control terminal,
The second switching circuit includes a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal, and a second switching circuit control terminal,
The memory circuit has a memory circuit input terminal and a memory circuit output terminal,
The first switching circuit control terminal constitutes the connection circuit first control terminal;
The one input terminal for the first switching circuit constitutes the input terminal for the connection circuit,
When the first control signal for the connection circuit takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
When the first control signal for connection circuit takes the second logic, the other input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
The second switching circuit control terminal constitutes the connection circuit second control terminal;
The one input terminal for the second switching circuit constitutes the test input terminal for the connection circuit,
When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
When the second control signal for the connection circuit takes the second logic, the other input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
The output terminal for the second switching circuit is connected to the other input terminal for the first switching circuit,
The first switching circuit output terminal is connected to the storage circuit input terminal;
The storage circuit output terminal constitutes the connection circuit output terminal and is connected to the other input terminal for the second switching circuit; and
First and second control input terminals for control circuit, first and second control output terminals for control circuit, and test terminal for control circuit,
The control circuit first and second control input signals and the control circuit test signal are input to the control circuit first and second control input terminals and the control circuit test terminal, respectively. Control circuit first and second control output signals are output from the second control output terminal,
The control circuit first and second control input signals, the control circuit first and second control output signals, and the control circuit test signal each take the binary logic,
When the control circuit test signal takes one of the binary logic, the logic of the control circuit first and second control output signals is equal to the logic of the control circuit second control input signal;
When the control circuit test signal takes the other of the binary logic, the logic of the control circuit second control output signal is equal to the inverted logic of the control circuit first control input signal, and the control circuit first The logic of the control output signal is equal to the logic of the first control input signal for the control circuit,
The control circuit first control output terminal is connected to the connection circuit first control terminal,
The control path second circuit output terminal includes a control circuit that controls the connection circuit by being connected to the connection circuit second control terminal. Comprising first and second switching circuits and a memory circuit;
A connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit first and second control terminal;
The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are different from each other in first logic and second Take binary logic consisting of logic,
The first switching circuit has a first switching circuit one input terminal, a first switching circuit other input terminal, a first switching circuit output terminal, and a first switching circuit control terminal,
The second switching circuit includes a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal, and a second switching circuit control terminal,
The memory circuit has a memory circuit input terminal and a memory circuit output terminal,
The first switching circuit control terminal constitutes the connection circuit first control terminal;
The one input terminal for the first switching circuit constitutes the input terminal for the connection circuit,
When the first control signal for the connection circuit takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
When the first control signal for connection circuit takes the second logic, the other input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
The second switching circuit control terminal constitutes the connection circuit second control terminal;
The one input terminal for the second switching circuit constitutes the test input terminal for the connection circuit,
When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
When the second control signal for the connection circuit takes the second logic, the other input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
The output terminal for the second switching circuit is connected to the other input terminal for the first switching circuit,
The first switching circuit output terminal is connected to the storage circuit input terminal;
The storage circuit output terminal constitutes the connection circuit output terminal and is connected to the other input terminal for the second switching circuit; and
First and second control input terminals for the control circuit and first and second control output terminals for the control circuit,
Control circuit first and second control input signals are input to the control circuit first and second control input terminals, respectively, and control circuit first and second control output terminals respectively receive control circuit first and second control input signals. And a second control output signal is output,
The control circuit first and second control input signals and the control circuit first and second control output signals each take the binary logic,
When the first control input signal for the control circuit takes the first logic, the logic of the first and second control output signals for the control circuit is equal to the logic of the second control input signal for the control circuit,
When the first control input signal for the control circuit takes the second logic, the logic of the second control output signal for the control circuit is equal to the inverted logic of the first control input signal for the control circuit, and The logic of one control output signal is equal to the logic of the first control input signal for the control circuit,
The first control output terminal for the control circuit is connected to the first control terminal for the connection circuit;
And a control circuit that controls the connection circuit by connecting the second control output terminal for the control circuit to the second control terminal for the connection circuit. Comprising first and second switching circuits and a memory circuit;
A connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit first and second control terminal;
The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are different from each other in first logic and second Take binary logic consisting of logic,
The first switching circuit has a first switching circuit one input terminal, a first switching circuit other input terminal, a first switching circuit output terminal, and a first switching circuit control terminal,
The second switching circuit includes a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal, and a second switching circuit control terminal,
The memory circuit has a memory circuit input terminal and a memory circuit output terminal,
The first switching circuit control terminal constitutes the connection circuit first control terminal;
The one input terminal for the first switching circuit constitutes the input terminal for the connection circuit,
When the first control signal for the connection circuit takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
When the first control signal for connection circuit takes the second logic, the other input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
The second switching circuit control terminal constitutes the connection circuit second control terminal;
The one input terminal for the second switching circuit constitutes the test input terminal for the connection circuit,
When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
When the second control signal for the connection circuit takes the second logic, the other input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
The output terminal for the second switching circuit is connected to the other input terminal for the first switching circuit,
The first switching circuit output terminal is connected to the storage circuit input terminal;
The storage circuit output terminal constitutes the connection circuit output terminal and is connected to the other input terminal for the second switching circuit; and
First to third control input terminals for control circuit, first and second control output terminals for control circuit, and test terminal for control circuit,
Control circuit first to third control input signals and control circuit test signals are input to the control circuit first to third control input terminals and the control circuit test terminals, respectively. Control circuit first and second control output signals are output from the second control output terminal,
The control circuit first to third control input signals, the control circuit first and second control output signals, and the control circuit test signal each take the binary logic,
When the control circuit test signal takes one of the binary logics, the logic of the control circuit first and second control output signals is equal to the logic of the control circuit second control input signal;
When the control circuit test signal takes the other of the binary logic, the logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit, and the second control for the control circuit The logic of the output signal is equal to the logic of the third control input signal for the control circuit,
The control circuit first control output terminal is connected to the connection circuit first control terminal,
The scan path configuration circuit, wherein the control circuit second control output terminal includes a control circuit that controls the connection circuit by being connected to the connection circuit second control terminal. Comprising first and second switching circuits and a memory circuit;
A connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit first and second control terminal;
The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are different from each other in first logic and second Take binary logic consisting of logic,
The first switching circuit has a first switching circuit one input terminal, a first switching circuit other input terminal, a first switching circuit output terminal, and a first switching circuit control terminal,
The second switching circuit includes a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal, and a second switching circuit control terminal,
The memory circuit has a memory circuit input terminal and a memory circuit output terminal,
The first switching circuit control terminal constitutes the connection circuit first control terminal;
The one input terminal for the first switching circuit constitutes the input terminal for the connection circuit,
When the first control signal for the connection circuit takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
When the first control signal for connection circuit takes the second logic, the other input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
The second switching circuit control terminal constitutes the connection circuit second control terminal;
The one input terminal for the second switching circuit constitutes the test input terminal for the connection circuit,
When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
When the second control signal for the connection circuit takes the second logic, the other input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
The output terminal for the second switching circuit is connected to the other input terminal for the first switching circuit,
The first switching circuit output terminal is connected to the storage circuit input terminal;
The storage circuit output terminal constitutes the connection circuit output terminal and is connected to the other input terminal for the second switching circuit; and
First to third control input terminals for control circuit, first and second control output terminals for control circuit, and test terminal for control circuit,
Control circuit first to third control input signals and control circuit test signals are input to the control circuit first to third control input terminals and the control circuit test terminals, respectively. Control circuit first and second control output signals are output from the second control output terminal,
The control circuit first to third control input signals, the control circuit first and second control output signals, and the control circuit test signal each take the binary logic,
When the control circuit test signal takes one of the binary logic and the control circuit first and third control input signals take the first logic, respectively, the control circuit first and second The logic of the control output signal is equal to the logic of the second control input signal for the control circuit,
When the control circuit test signal takes the other of the binary logic and the third control input signal for the control circuit takes the second logic, the first control input signal for the control circuit also takes the second logic. taken, the logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit, the logic of the second control output signal for the control circuit the third control input signals for the control circuit Is equal to the logic of
The control circuit first control output terminal is connected to the connection circuit first control terminal,
The scan path configuration circuit, wherein the control circuit second control output terminal includes a control circuit that controls the connection circuit by being connected to the connection circuit second control terminal. Comprising first and second switching circuits and a memory circuit;
A connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit first and second control terminal;
The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are different from each other in first logic and second Take binary logic consisting of logic,
The first switching circuit has a first switching circuit one input terminal, a first switching circuit other input terminal, a first switching circuit output terminal, and a first switching circuit control terminal,
The second switching circuit includes a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal, and a second switching circuit control terminal,
The memory circuit has a memory circuit input terminal and a memory circuit output terminal,
The first switching circuit control terminal constitutes the connection circuit first control terminal;
The one input terminal for the first switching circuit constitutes the input terminal for the connection circuit,
When the first control signal for the connection circuit takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
When the first control signal for connection circuit takes the second logic, the other input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
The second switching circuit control terminal constitutes the connection circuit second control terminal;
The one input terminal for the second switching circuit constitutes the test input terminal for the connection circuit,
When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
When the second control signal for the connection circuit takes the second logic, the other input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
The output terminal for the second switching circuit is connected to the other input terminal for the first switching circuit,
The first switching circuit output terminal is connected to the storage circuit input terminal;
The storage circuit output terminal constitutes the connection circuit output terminal and is connected to the other input terminal for the second switching circuit; and
Comprising first to third control input terminals for the control circuit and first and second control output terminals for the control circuit;
The control circuit first to third control input signals are respectively input to the control circuit first to third control input terminals, and the control circuit first and second control output terminals respectively receive the control circuit first. And a second control output signal is output,
The first to third control input signals for the control circuit and the first and second control output signals for the control circuit each take the binary logic,
When the first control input signal for the control circuit takes the first logic, the logic of the first and second control output signals for the control circuit is equal to the logic of the second control input signal for the control circuit,
When the first control input signal for the control circuit takes the second logic, the logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit, and the second for the control circuit. The logic of the control output signal is equal to the logic of the third control input signal for the control circuit,
The control circuit first control output terminal is connected to the connection circuit first control terminal,
The scan path configuration circuit, wherein the control circuit second control output terminal includes a control circuit that controls the connection circuit by being connected to the connection circuit second control terminal. Comprising first and second switching circuits and a memory circuit;
A connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, and a connection circuit first and second control terminal;
The first control signal for connection circuit input to the first control terminal for connection circuit and the second control signal for connection circuit input to the second control terminal for connection circuit are different from each other in first logic and second Take binary logic consisting of logic,
The first switching circuit has a first switching circuit one input terminal, a first switching circuit other input terminal, a first switching circuit output terminal, and a first switching circuit control terminal,
The second switching circuit includes a second switching circuit one input terminal, a second switching circuit other input terminal, a second switching circuit output terminal, and a second switching circuit control terminal,
The memory circuit has a memory circuit input terminal and a memory circuit output terminal,
The first switching circuit control terminal constitutes the connection circuit first control terminal;
The one input terminal for the first switching circuit constitutes the input terminal for the connection circuit,
When the first control signal for the connection circuit takes the first logic, the one input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
When the first control signal for connection circuit takes the second logic, the other input terminal for the first switching circuit is connected to the output terminal for the first switching circuit,
The second switching circuit control terminal constitutes the connection circuit second control terminal;
The one input terminal for the second switching circuit constitutes the test input terminal for the connection circuit,
When the second control signal for the connection circuit takes the first logic, the one input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
When the second control signal for the connection circuit takes the second logic, the other input terminal for the second switching circuit is connected to the output terminal for the second switching circuit,
The output terminal for the second switching circuit is connected to the other input terminal for the first switching circuit,
The first switching circuit output terminal is connected to the storage circuit input terminal;
The storage circuit output terminal constitutes the connection circuit output terminal and is connected to the other input terminal for the second switching circuit; and
Comprising first to third control input terminals for the control circuit and first and second control output terminals for the control circuit;
The control circuit first to third control input signals are respectively input to the control circuit first to third control input terminals, and the control circuit first and second control output terminals respectively receive the control circuit first. And a second control output signal is output,
The first to third control input signals for the control circuit and the first and second control output signals for the control circuit each take the binary logic,
When the first control input signal for the control circuit takes the first logic and the third control input signal for the control circuit takes the first logic, the logic of the first and second control output signals for the control circuit Is equal to the logic of the second control input signal for the control circuit;
When the first control input signal for the control circuit takes the second logic, the logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit, and the second for the control circuit. The logic of the control output signal is equal to the logic of the third control input signal for the control circuit,
The control circuit first control output terminal is connected to the connection circuit first control terminal,
The scan path configuration circuit, wherein the control circuit second control output terminal includes a control circuit that controls the connection circuit by being connected to the connection circuit second control terminal. A connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, a connection circuit first and second control terminal, and an expectation terminal,
The connection circuit first control signal input to the connection circuit first control terminal and the connection circuit second control signal input to the connection circuit second control terminal are different from each other in the first logic and the first logic. Take binary logic consisting of two logics,
When the connection circuit first control signal takes the first logic, a signal input to the connection circuit input terminal is output from the connection circuit output terminal;
When the first control signal for connection circuit takes the second logic and the second control signal for connection circuit takes the first logic, a signal input to the test input terminal for connection circuit is sent to the connection circuit Output from the output terminal for
When the connection circuit first and second control signals each take the second logic, the logic of the signal input to the expected terminal matches the logic of the signal input to the connection circuit input terminal In this case, the signal output from the connection circuit output terminal is continuously output from the connection circuit output terminal, and if they do not match, the first logic is continuously output from the connection circuit output terminal. A connection circuit to
Comprising first to third control input terminals for the control circuit and first and second control output terminals for the control circuit;
The control circuit first to third control input signals are respectively input to the control circuit first to third control input terminals, and the control circuit first and second control output terminals respectively receive the control circuit first. And a second control output signal is output,
The first to third control input signals for the control circuit and the first and second control output signals for the control circuit each take the binary logic,
When the first control input signal for the control circuit takes the first logic and the third control input signal for the control circuit takes the first logic, the logic of the first and second control output signals for the control circuit Is equal to the logic of the second control input signal for the control circuit;
When the first control input signal for the control circuit takes the second logic, the logic of the first control output signal for the control circuit is equal to the logic of the first control input signal for the control circuit, and the second for the control circuit. The logic of the control output signal is equal to the logic of the third control input signal for the control circuit,
The control circuit first control output terminal is connected to the connection circuit first control terminal,
The scan path configuration circuit, wherein the control circuit second control output terminal includes a control circuit that controls the connection circuit by being connected to the connection circuit second control terminal.   A connection circuit input terminal, a connection circuit test input terminal, a connection circuit output terminal, a connection circuit first and second control terminal, and an expectation terminal,
  The connection circuit first control signal input to the connection circuit first control terminal and the connection circuit second control signal input to the connection circuit second control terminal are different from each other in the first logic and the first logic. Take binary logic consisting of two logics,
  When the connection circuit first control signal takes the first logic, a signal input to the connection circuit input terminal is output from the connection circuit output terminal;
  When the first control signal for connection circuit takes the second logic and the second control signal for connection circuit takes the first logic, a signal input to the test input terminal for connection circuit is sent to the connection circuit Output from the output terminal for
  When the connection circuit first and second control signals each take the second logic, the logic of the signal input to the expected terminal matches the logic of the signal input to the connection circuit input terminal Continuously outputs the signal output from the connection circuit output terminal from the connection circuit output terminal, and continues to output the first logic from the connection circuit output terminal if they do not match.
A connection circuit characterized by:
  First to third control input terminals for control circuit, first and second control output terminals for control circuit, and test terminal for control circuit,
  The first to third control input signals for the control circuit and the test signal for the control circuit are input to the first to third control input terminals for the control circuit and the test terminal for the control circuit, respectively. Control circuit first and second control output signals are output from the second control output terminal,
  The control circuit first to third control input signals, the control circuit first and second control output signals, and the control circuit test signal each take the binary logic,
  When the control circuit test signal takes one of the binary logic, the logic of the control circuit first and second control output signals is equal to the logic of the control circuit second control input signal;
  When the control circuit test signal takes the other of the binary logic, the logic of the control circuit first control output signal is equal to the logic of the control circuit first control input signal, and the control circuit second control The logic of the output signal is equal to the logic of the third control input signal for the control circuit,
  The control circuit first control output terminal is connected to the connection circuit first control terminal;
  The control circuit second control output terminal is connected to the connection circuit second control terminal.
A control circuit for controlling the connection circuit
A scan path constituting circuit comprising: The connection circuit further includes a comparison terminal and an expectation terminal, and includes an exclusive OR element, a NOT AND element, and an AND element.
The comparison signal input to the comparison terminal takes the above binary logic,
The exclusive OR element comprises an exclusive OR element output terminal and two exclusive OR element input terminals,
The negative AND element includes a negative AND element output terminal and two negative AND element input terminals,
The AND element includes an AND element output terminal and two AND element input terminals,
The connection between the output terminal for the memory circuit and the other input terminal for the second switching circuit is a connection through the AND element,
Any one of the input terminals for the exclusive OR element constitutes the expected terminal,
The other input terminal for the exclusive OR element and the one input terminal for the first switching circuit are connected in common,
The exclusive OR element output terminal is connected to either one of the negative AND element input terminals;
The other of the input terminals for the negative AND element constitutes the comparison terminal,
The negative AND element output terminal is connected to one of the AND element input terminals,
7. The scan path configuration circuit according to claim 3, wherein the storage circuit output terminal is connected to the other one of the AND element input terminals. The connection circuit further includes a comparison terminal and an expectation terminal, and includes an exclusive OR element and a negative AND element,
The memory circuit further includes a memory circuit initialization terminal,
The comparison signal input to the comparison terminal takes the above binary logic,
The exclusive OR element comprises an exclusive OR element output terminal and two exclusive OR element input terminals,
The negative AND element includes a negative AND element output terminal and two negative AND element input terminals,
Any one of the input terminals for the exclusive OR element constitutes the expected terminal,
The other input terminal for the exclusive OR element and the one input terminal for the first switching circuit are connected in common,
The exclusive OR element output terminal is connected to either one of the negative AND element input terminals;
The other of the input terminals for the negative AND element constitutes the comparison terminal,
7. The scan path configuration circuit according to claim 3, wherein the output terminal for the negative AND element is connected to the initialization terminal for the memory circuit. A scan path configuration circuit provided in a RAM having a write terminal and a read terminal;
The connection circuit is prepared for each of the write terminals and for each of the read terminals,
The write terminal is connected to the connection circuit output terminal of the connection circuit prepared for the write terminal,
The readout terminal is connected to the connection circuit input terminal of the connection circuit prepared for the readout terminal,
The write control circuit for controlling the connection circuit prepared for each write terminal is the control circuit,
The readout control circuit that controls the connection circuit prepared for each readout terminal is the control circuit,
Scan path forming circuit according to any one of claims 3 to 10, wherein the the control by the write control circuit and the control by the read control circuit are each independently. It has a writing terminal and a reading terminal,
The read / write terminal comprises a write address terminal and a write input terminal.
The read terminal is a scan path configuration circuit provided in a RAM including a read address terminal and a read output terminal.
The connection circuit is prepared for each of the write address terminals, for each of the write input terminals, for each of the read address terminals, and for each of the read output terminals,
The write address terminal is connected to the connection circuit output terminal of the connection circuit prepared for the write address terminal, respectively.
The input terminal for writing is connected to the output terminal for the connection circuit of the connection circuit prepared for the input terminal for writing, respectively.
The read address terminal is connected to the connection circuit input terminal of the connection circuit prepared for the read address terminal,
The output terminal for readout is connected to the input terminal for connection circuit of the connection circuit prepared for the output terminal for readout, respectively.
The write address control circuit for controlling the connection circuit prepared for each write address terminal is the control circuit,
The write input control circuit for controlling the connection circuit prepared for each of the write input terminals is the control circuit,
The read address control circuit for controlling the connection circuit prepared for each read address terminal is the control circuit,
A readout output control circuit that controls the connection circuit prepared for each readout output terminal is the control circuit,
The control by the write address control circuit, the control by the write input control circuit, the control by the read address control circuit, and the control by the read output control circuit are independent of each other. Item 11. The scan path configuration circuit according to any one of Items 3 to 10 .

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