JP3681860B2 - Electronic clock - Google Patents

Electronic clock Download PDF

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Publication number
JP3681860B2
JP3681860B2 JP14761397A JP14761397A JP3681860B2 JP 3681860 B2 JP3681860 B2 JP 3681860B2 JP 14761397 A JP14761397 A JP 14761397A JP 14761397 A JP14761397 A JP 14761397A JP 3681860 B2 JP3681860 B2 JP 3681860B2
Authority
JP
Japan
Prior art keywords
memory
circuit
timing
electronic timepiece
motor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP14761397A
Other languages
Japanese (ja)
Other versions
JPH10332852A (en
Inventor
村上  哲功
樋口  晴彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP14761397A priority Critical patent/JP3681860B2/en
Publication of JPH10332852A publication Critical patent/JPH10332852A/en
Application granted granted Critical
Publication of JP3681860B2 publication Critical patent/JP3681860B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【0001】
【発明の属する技術】
本発明は電子時計におけるメモリ書き換えに関するものである。
【0002】
【従来の技術】
まず従来のメモリ書き換えを行う電子時計の構成を、メモリによって歩度が制御される例を用いて図を用いて説明する。
は従来のメモリ書き換えを行う電子時計の回路ブロック図であり、1は基準信号を発振する発振回路であり、2は発振回路1の信号を分周する分周回路であり、3は分周回路2を論理的に操作して歩度を調整する歩度調整回路であり、4は歩度調整回路3の動作タイミングを決定するタイミング作成回路である。
5は分周回路2の信号を用いてモータ駆動用信号を作成する波形整形回路であり、6は波形整形回路5の信号を用いてモータを駆動するためのモータ駆動回路であり、7はモータ駆動回路6により駆動するモータであり、7aはモータを構成するコイルであり、8はモータ7により動作する指針である。
9は歩度調整回路3の歩度調整量を決定するメモリであり、10は時計外部で磁界を発生させたときのコイル7aの誘起電圧を利用して時計外部からのデータを受信し、メモリ9の内容をその受信したデータに書き換えるためのメモリ書き換え回路である。
【0003】
次にメモリ書き換えを行うための装置の構成を図を用いて説明する。
12は書き換え装置発振回路であり、13はモータ7が動作するときに生じる磁界の変化を検出する受信コイルであり、14は受信コイル13がモータ7による磁界の変化を検出してから一定時間を数える送信タイミング作成回路である。15は歩度の調整量を入力する入力回路であり、16は入力回路15のデータを2進数に変換する送信データ作成回路であり、17は送信タイミング作成回路14のタイミングにあわせて送信データ作成回路16のデータを送信する送信制御回路であり、18は送信制御回路17の信号を磁界の変化として送信するための送信コイルである。
【0004】
次に従来のメモリ書き換えを行う電子時計の動作を、図2と図3を用いて説明する。
まず歩度の調整を行っている回路の説明をする。タイミング作成回路4が作成するタイミングを例えば1分とすると、1分に1回歩度調整回路3が動作し、メモリ9の内容に基づいて分周回路2の各分周段にリセットやセットをかけ、歩度の調整を行う。
次にメモリ書き換えを行っている回路の説明をする。モータ駆動回路6の信号によってモータ7が駆動すると磁界を発生する。その磁界の変化をメモリ書き換え装置の受信コイル13が検出し、送信タイミング作成回路14がスタートする。送信データ作成回路16はあらかじめ入力回路15に入力されている歩度調整データを2進数データに変換しており、送信制御回路17は送信タイミング作成回路14のタイミングに同期させて送信コイル18によって磁界を発生させ送信する。時計側は送信コイル18で発生した磁界をコイル7aで検知することにより、データの受信を行う。コイル7aで受信したデータをメモリ書き換え回路10によってメモリ9に書き、メモリの書き換えが終了する。
【0005】
【発明が解決しようとする課題】
しかしながら歩度調整回路3が新しいメモリの内容に基づいて歩度調整を行うのは、タイミング作成回路4が動作してからであって、それ以前に歩度を測定してもメモリ書き換え以前とは変わりがない。生産時にこの方法で歩度調整を行った場合、少なくともタイミング作成回路4のタイミングまでは歩度測定を行うことができなかった。
本発明の目的は上記課題を解決しようとするもので、メモリ9を書き換えた直後に歩度調整回路3を強制動作させ、すぐに歩度測定ができる電子時計を提供することである。
【0006】
【課題を解決するための手段】
上記目的を達成するための本発明の電子時計は、メモリ9を書き換えた直後に歩度調整回路3にそのデータを反映させるために、歩度調整回路3を強制的に動作させる強制動作回路を設けたことを特徴とする。
【発明の実施の形態】
【0007】
以下に本発明の実施例の構成を図1を用いて説明する。
図1は、本発明に係わる電子時計の回路図ブロック図であり、図と同じ要素には同じ番号を付して説明は省略する。
11は歩度調整回路3を強制的に動作させるための強制動作回路である。
次に本発明の実施例の動作を図1を用いて説明する。
メモリ書き換え回路10がメモリ9を書き換えたとき、強制動作回路11はメモリ書き換え回路10の書き換え終了信号を受けて、歩度調整回路3をタイミング作成回路4のタイミングに関わらず強制的に動作させる。これによりメモリ書き込み直後に新しいメモリ内容に基づいた歩度調整が行われ、すぐに歩度測定をすることができる。
メモリによって制御されるものは歩度である必要はなく、アラームの周波数やセンサの合わせ込み値でもよい。
【0008】
【発明の効果】
上記のごとく本発明によれば、メモリを書き換えた直後に新しいメモリ内容に基づいた歩度によって運針を行うので、すぐに調整後の歩度測定ができ、生産時に有効である。
【図面の簡単な説明】
【図1】本発明の一実施例を示す電子時計の回路ブロック図である。
【図2】従来の一実施例を示すメモリ書き換え装置の回路ブロック図である。
【図3】従来の一実施例を示す電子時計の回路ブロック図である。
【符号の説明】
3 歩度調整回路
4 タイミング作成回路
9 メモリ
10 メモリ書き換え回路
11 強制動作回路
[0001]
[Technology to which the invention belongs]
The present invention relates to memory rewriting in an electronic timepiece.
[0002]
[Prior art]
First, the configuration of a conventional electronic timepiece that performs memory rewriting will be described with reference to FIG. 2 using an example in which the rate is controlled by a memory.
FIG. 2 is a circuit block diagram of a conventional electronic timepiece that performs memory rewriting. 1 is an oscillation circuit that oscillates a reference signal, 2 is a frequency divider circuit that divides the signal of the oscillation circuit 1, and 3 is a frequency divider. A rate adjustment circuit that logically operates the peripheral circuit 2 to adjust the rate, and 4 is a timing generation circuit that determines the operation timing of the rate adjustment circuit 3.
Reference numeral 5 denotes a waveform shaping circuit that creates a motor driving signal using the signal of the frequency dividing circuit 2, 6 denotes a motor driving circuit for driving the motor using the signal of the waveform shaping circuit 5, and 7 denotes a motor. A motor driven by the drive circuit 6, 7 a is a coil constituting the motor, and 8 is a pointer operated by the motor 7.
Reference numeral 9 denotes a memory for determining a rate adjustment amount of the rate adjustment circuit 3. Reference numeral 10 denotes data received from the outside of the watch using an induced voltage of the coil 7 a when a magnetic field is generated outside the watch. It is a memory rewriting circuit for rewriting the contents to the received data.
[0003]
It will now be described with reference to FIG. 3 the configuration of an apparatus for performing memory rewrite.
Reference numeral 12 denotes a rewriting device oscillation circuit, reference numeral 13 denotes a receiving coil that detects a change in magnetic field generated when the motor 7 operates, and reference numeral 14 denotes a certain time after the receiving coil 13 detects a change in magnetic field by the motor 7. This is a counting timing generation circuit. Reference numeral 15 denotes an input circuit for inputting a rate adjustment amount, reference numeral 16 denotes a transmission data generation circuit for converting the data of the input circuit 15 into a binary number, and reference numeral 17 denotes a transmission data generation circuit in accordance with the timing of the transmission timing generation circuit 14. Reference numeral 18 denotes a transmission control circuit for transmitting 16 data. Reference numeral 18 denotes a transmission coil for transmitting a signal from the transmission control circuit 17 as a change in magnetic field.
[0004]
Next, the operation of a conventional electronic timepiece for rewriting memory will be described with reference to FIGS.
First, a circuit that adjusts the rate will be described. If the timing created by the timing creating circuit 4 is, for example, 1 minute, the rate adjusting circuit 3 operates once per minute, and resets or sets the frequency dividing stages of the frequency dividing circuit 2 based on the contents of the memory 9. , Adjust the rate.
Next, a circuit that performs memory rewriting will be described. When the motor 7 is driven by a signal from the motor drive circuit 6, a magnetic field is generated. The change in the magnetic field is detected by the reception coil 13 of the memory rewriting device, and the transmission timing generation circuit 14 is started. The transmission data creation circuit 16 converts the rate adjustment data inputted in advance to the input circuit 15 into binary data, and the transmission control circuit 17 generates a magnetic field by the transmission coil 18 in synchronization with the timing of the transmission timing creation circuit 14. Generate and send. The watch side receives data by detecting the magnetic field generated by the transmission coil 18 with the coil 7a. Data received by the coil 7a is written to the memory 9 by the memory rewriting circuit 10, and the rewriting of the memory is completed.
[0005]
[Problems to be solved by the invention]
However, the rate adjustment circuit 3 performs the rate adjustment based on the contents of the new memory after the timing generation circuit 4 operates, and even if the rate is measured before that, there is no change from before the memory rewrite. . When the rate adjustment is performed by this method at the time of production, the rate cannot be measured at least until the timing of the timing generation circuit 4.
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide an electronic timepiece in which a rate adjustment circuit 3 is forcibly operated immediately after rewriting a memory 9 and a rate can be measured immediately.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the electronic timepiece of the present invention is provided with a forcible operation circuit for forcibly operating the rate adjustment circuit 3 in order to reflect the data in the rate adjustment circuit 3 immediately after the memory 9 is rewritten. It is characterized by that.
DETAILED DESCRIPTION OF THE INVENTION
[0007]
The configuration of the embodiment of the present invention will be described below with reference to FIG.
Figure 1 is a circuit diagram block diagram of an electronic timepiece according to the present invention, it will be assigned the same numerals to the same elements as in FIG. 2 will be omitted.
Reference numeral 11 denotes a forcible operation circuit for forcibly operating the rate adjusting circuit 3.
Next, the operation of the embodiment of the present invention will be described with reference to FIG.
When the memory rewrite circuit 10 rewrites the memory 9, the forcible operation circuit 11 receives the rewrite completion signal from the memory rewrite circuit 10 and forcibly operates the rate adjustment circuit 3 regardless of the timing of the timing generation circuit 4. As a result, the rate adjustment based on the new memory contents is performed immediately after the memory is written, and the rate can be measured immediately.
What is controlled by the memory does not need to be a rate, but may be an alarm frequency or a sensor fitting value.
[0008]
【The invention's effect】
As described above, according to the present invention, the hands are moved at the rate based on the new memory contents immediately after the memory is rewritten, so that the adjusted rate can be measured immediately, which is effective during production.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram of an electronic timepiece showing an embodiment of the present invention.
FIG. 2 is a circuit block diagram of a memory rewriting apparatus showing a conventional example.
FIG. 3 is a circuit block diagram of an electronic timepiece showing a conventional example.
[Explanation of symbols]
3 Rate adjustment circuit 4 Timing creation circuit 9 Memory 10 Memory rewrite circuit 11 Forced operation circuit

Claims (2)

書き換え可能なメモリと、時計外部からのデータを受信しメモリを書き換えるメモリ書き換え手段と、書き込まれているメモリによって制御する量が変化する制御手段と、制御手段を定期的に動作させるためのタイミング作成手段を有する電子時計において、メモリ書き換え手段によってメモリが書き換えられた後、タイミング作成手段のタイミングと無関係にすぐにその結果を制御手段に反映させるための強制動作手段を設けたことを特徴とする電子時計。Rewritable memory, memory rewrite means that receives data from outside the watch and rewrites the memory, control means that changes the amount controlled by the written memory, and timing generation for operating the control means periodically An electronic timepiece having means for providing an electronic operation characterized in that after the memory is rewritten by the memory rewriting means, forcible operation means is provided for immediately reflecting the result on the control means irrespective of the timing of the timing creating means. clock. 指針を駆動するモータを有し、メモリ書き換え手段は時計外部の磁界によりモータを構成するコイルに発生した誘起電圧を利用して時計外部からのデータを受信し、メモリの内容をその受信したデータに書き換えることを特徴とする請求項1記載の電子時計。It has a motor that drives the pointer, and the memory rewrite means receives data from outside the watch using the induced voltage generated in the coil constituting the motor by a magnetic field outside the watch, and converts the contents of the memory into the received data 2. The electronic timepiece according to claim 1, wherein the electronic timepiece is rewritten.
JP14761397A 1997-06-05 1997-06-05 Electronic clock Expired - Fee Related JP3681860B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14761397A JP3681860B2 (en) 1997-06-05 1997-06-05 Electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14761397A JP3681860B2 (en) 1997-06-05 1997-06-05 Electronic clock

Publications (2)

Publication Number Publication Date
JPH10332852A JPH10332852A (en) 1998-12-18
JP3681860B2 true JP3681860B2 (en) 2005-08-10

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Family Applications (1)

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JP14761397A Expired - Fee Related JP3681860B2 (en) 1997-06-05 1997-06-05 Electronic clock

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JP (1) JP3681860B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6536446B2 (en) 2016-03-23 2019-07-03 セイコーエプソン株式会社 Electronic clock

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