JPH10332852A - Electronic time piece - Google Patents

Electronic time piece

Info

Publication number
JPH10332852A
JPH10332852A JP14761397A JP14761397A JPH10332852A JP H10332852 A JPH10332852 A JP H10332852A JP 14761397 A JP14761397 A JP 14761397A JP 14761397 A JP14761397 A JP 14761397A JP H10332852 A JPH10332852 A JP H10332852A
Authority
JP
Japan
Prior art keywords
circuit
memory
rewriting
rate
rate adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14761397A
Other languages
Japanese (ja)
Other versions
JP3681860B2 (en
Inventor
Akinari Murakami
村上  哲功
Haruhiko Higuchi
樋口  晴彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP14761397A priority Critical patent/JP3681860B2/en
Publication of JPH10332852A publication Critical patent/JPH10332852A/en
Application granted granted Critical
Publication of JP3681860B2 publication Critical patent/JP3681860B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To compulsorily operate a stepping rate adjustment circuit immediately after rewriting a memory and enable quickly rate measurement by providing a forced operation circuit compulsorily operating the rate adjustment circuit. SOLUTION: An oscillation circuit 1 oscillates a reference signal, a frequency division circuit 2 divides frequency of the signal of the oscillation circuit 1 and a rate adjustment circuit 3 adjusts the rate by logically operating the frequency division circuit 2. A timing forming circuit 4 determines the operation timing of the rate adjustment circuit 3 and a waveform shaping circuit 5 forms a signal for motor driving using the signal of the frequency division circuit 2. When a memory rewriting circuit 10 rewrites a memory 9, a forced operation circuit 11 receives a rewriting completion signal of a memory rewriting circuit 10 and compulsorily operates the rate adjustment circuit 3 regardless of the timing forming circuit 4. By this, a rate adjustment based on the contents of the new memory 9 is done immediately after writing in the memory 9 and rate measurement can be quickly performed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術】本発明は電子時計におけるメモリ
書き換えに関するものである。
The present invention relates to rewriting of memory in an electronic timepiece.

【0002】[0002]

【従来の技術】まず従来のメモリ書き換えを行う電子時
計の構成を、メモリによって歩度が制御される例を用い
て図3を用いて説明する。図3は従来のメモリ書き換え
を行う電子時計の回路ブロック図であり、1は基準信号
を発振する発振回路であり、2は発振回路1の信号を分
周する分周回路であり、3は分周回路2を論理的に操作
して歩度を調整する歩度調整回路であり、4は歩度調整
回路3の動作タイミングを決定するタイミング作成回路
である。5は分周回路2の信号を用いてモータ駆動用信
号を作成する波形整形回路であり、6は波形整形回路5
の信号を用いてモータを駆動するためのモータ駆動回路
であり、7はモータ駆動回路6により駆動するモータで
あり、7aはモータを構成するコイルであり、8はモー
タ7により動作する指針である。9は歩度調整回路3の
歩度調整量を決定するメモリであり、10は時計外部で
磁界を発生させたときのコイル7aの誘起電圧を利用し
て時計外部からのデータを受信し、メモリ9の内容をそ
の受信したデータに書き換えるためのメモリ書き換え回
路である。
2. Description of the Related Art First, a configuration of a conventional electronic timepiece that rewrites a memory will be described with reference to FIG. 3 using an example in which a rate is controlled by a memory. FIG. 3 is a circuit block diagram of a conventional electronic timepiece that rewrites memory, wherein 1 is an oscillation circuit that oscillates a reference signal, 2 is a frequency divider that divides the signal of the oscillation circuit 1, and 3 is a divider. A rate adjusting circuit for logically operating the peripheral circuit 2 to adjust the rate, and 4 is a timing creating circuit for determining the operation timing of the rate adjusting circuit 3. Reference numeral 5 denotes a waveform shaping circuit for generating a motor driving signal using the signal of the frequency dividing circuit 2;
, A motor driven by the motor drive circuit 6, 7a a coil constituting the motor, and 8 a pointer operated by the motor 7. . Reference numeral 9 denotes a memory for determining a rate adjustment amount of the rate adjusting circuit 3. Reference numeral 10 denotes a memory for receiving data from outside the watch using an induced voltage of the coil 7a when a magnetic field is generated outside the watch. This is a memory rewriting circuit for rewriting the contents to the received data.

【0003】次にメモリ書き換えを行うための装置の構
成を図2を用いて説明する。12は書き換え装置発振回
路であり、13はモータ7が動作するときに生じる磁界
の変化を検出する受信コイルであり、14は受信コイル
13がモータ7による磁界の変化を検出してから一定時
間を数える送信タイミング作成回路である。15は歩度
の調整量を入力する入力回路であり、16は入力回路1
5のデータを2進数に変換する送信データ作成回路であ
り、17は送信タイミング作成回路14のタイミングに
あわせて送信データ作成回路16のデータを送信する送
信制御回路であり、18は送信制御回路17の信号を磁
界の変化として送信するための送信コイルである。
Next, the configuration of an apparatus for rewriting memory will be described with reference to FIG. 12 is a rewriting device oscillation circuit, 13 is a receiving coil for detecting a change in the magnetic field generated when the motor 7 operates, and 14 is a fixed time after the receiving coil 13 detects the change in the magnetic field by the motor 7. This is a transmission timing creation circuit that counts. 15 is an input circuit for inputting a rate adjustment amount, and 16 is an input circuit 1
5 is a transmission data generation circuit for converting data of No. 5 into a binary number, 17 is a transmission control circuit for transmitting data of the transmission data generation circuit 16 in accordance with the timing of the transmission timing generation circuit 14, and 18 is a transmission control circuit 17 Is a transmission coil for transmitting the signal of the above as a change in the magnetic field.

【0004】次に従来のメモリ書き換えを行う電子時計
の動作を、図2と図3を用いて説明する。まず歩度の調
整を行っている回路の説明をする。タイミング作成回路
4が作成するタイミングを例えば1分とすると、1分に
1回歩度調整回路3が動作し、メモリ9の内容に基づい
て分周回路2の各分周段にリセットやセットをかけ、歩
度の調整を行う。次にメモリ書き換えを行っている回路
の説明をする。モータ駆動回路6の信号によってモータ
7が駆動すると磁界を発生する。その磁界の変化をメモ
リ書き換え装置の受信コイル13が検出し、送信タイミ
ング作成回路14がスタートする。送信データ作成回路
16はあらかじめ入力回路15に入力されている歩度調
整データを2進数データに変換しており、送信制御回路
17は送信タイミング作成回路14のタイミングに同期
させて送信コイル18によって磁界を発生させ送信す
る。時計側は送信コイル18で発生した磁界をコイル7
aで検知することにより、データの受信を行う。コイル
7aで受信したデータをメモリ書き換え回路10によっ
てメモリ9に書き、メモリの書き換えが終了する。
Next, the operation of a conventional electronic timepiece which performs memory rewriting will be described with reference to FIGS. 2 and 3. FIG. First, a circuit for adjusting the rate will be described. Assuming that the timing created by the timing creation circuit 4 is one minute, for example, the rate adjustment circuit 3 operates once a minute, and resets or sets each of the frequency dividing stages of the frequency dividing circuit 2 based on the contents of the memory 9. , Adjust the rate. Next, a circuit for rewriting the memory will be described. When the motor 7 is driven by a signal from the motor drive circuit 6, a magnetic field is generated. The change in the magnetic field is detected by the reception coil 13 of the memory rewriting device, and the transmission timing creation circuit 14 starts. The transmission data generation circuit 16 converts the rate adjustment data input to the input circuit 15 in advance into binary data, and the transmission control circuit 17 generates a magnetic field by the transmission coil 18 in synchronization with the timing of the transmission timing generation circuit 14. Generate and send. On the clock side, the magnetic field generated by the transmission coil 18 is
The data is received by detecting at a. The data received by the coil 7a is written into the memory 9 by the memory rewriting circuit 10, and the rewriting of the memory is completed.

【0005】[0005]

【発明が解決しようとする課題】しかしながら歩度調整
回路3が新しいメモリの内容に基づいて歩度調整を行う
のは、タイミング作成回路4が動作してからであって、
それ以前に歩度を測定してもメモリ書き換え以前とは変
わりがない。生産時にこの方法で歩度調整を行った場
合、少なくともタイミング作成回路4のタイミングまで
は歩度測定を行うことができなかった。本発明の目的は
上記課題を解決しようとするもので、メモリ9を書き換
えた直後に歩度調整回路3を強制動作させ、すぐに歩度
測定ができる電子時計を提供することである。
However, the rate adjustment circuit 3 adjusts the rate based on the contents of the new memory only after the timing creation circuit 4 operates.
Even if the rate is measured before that, there is no difference from before the memory rewriting. When the rate was adjusted by this method during production, the rate could not be measured at least until the timing of the timing creation circuit 4. An object of the present invention is to solve the above-mentioned problem, and to provide an electronic timepiece in which the rate adjusting circuit 3 is forcibly operated immediately after rewriting the memory 9 and the rate can be measured immediately.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
の本発明の電子時計は、メモリ9を書き換えた直後に歩
度調整回路3にそのデータを反映させるために、歩度調
整回路3を強制的に動作させる強制動作回路を設けたこ
とを特徴とする。
According to the electronic timepiece of the present invention for achieving the above object, the rate adjusting circuit 3 is forced to reflect the data to the rate adjusting circuit 3 immediately after rewriting the memory 9. And a forcible operation circuit for causing the operation is performed.

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

【0007】以下に本発明の実施例の構成を図1を用い
て説明する。図1は、本発明に係わる電子時計の回路図
ブロック図であり、図3と同じ要素には同じ番号を付し
て説明は省略する。11は歩度調整回路3を強制的に動
作させるための強制動作回路である。次に本発明の実施
例の動作を図1を用いて説明する。メモリ書き換え回路
10がメモリ9を書き換えたとき、強制動作回路11は
メモリ書き換え回路10の書き換え終了信号を受けて、
歩度調整回路3をタイミング作成回路4のタイミングに
関わらず強制的に動作させる。これによりメモリ書き込
み直後に新しいメモリ内容に基づいた歩度調整が行わ
れ、すぐに歩度測定をすることができる。メモリによっ
て制御されるものは歩度である必要はなく、アラームの
周波数やセンサの合わせ込み値でもよい。
The configuration of an embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a circuit diagram block diagram of an electronic timepiece according to the present invention, and the same elements as those in FIG. Reference numeral 11 denotes a forced operation circuit for forcibly operating the rate adjustment circuit 3. Next, the operation of the embodiment of the present invention will be described with reference to FIG. When the memory rewriting circuit 10 rewrites the memory 9, the forced operation circuit 11 receives the rewriting end signal of the memory rewriting circuit 10,
The rate adjusting circuit 3 is forcibly operated regardless of the timing of the timing generating circuit 4. As a result, the rate adjustment based on the new memory content is performed immediately after writing to the memory, and the rate can be measured immediately. What is controlled by the memory need not be the rate, but may be the alarm frequency or the fitted value of the sensor.

【0008】[0008]

【発明の効果】上記のごとく本発明によれば、メモリを
書き換えた直後に新しいメモリ内容に基づいた歩度によ
って運針を行うので、すぐに調整後の歩度測定ができ、
生産時に有効である。
As described above, according to the present invention, the hands are moved by the rate based on the new memory contents immediately after rewriting the memory, so that the adjusted rate can be measured immediately.
Effective during production.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す電子時計の回路ブロッ
ク図である。
FIG. 1 is a circuit block diagram of an electronic timepiece showing one embodiment of the present invention.

【図2】従来の一実施例を示すメモリ書き換え装置の回
路ブロック図である。
FIG. 2 is a circuit block diagram of a memory rewriting device showing one embodiment of the related art.

【図3】従来の一実施例を示す電子時計の回路ブロック
図である。
FIG. 3 is a circuit block diagram of an electronic timepiece showing a conventional example.

【符号の説明】[Explanation of symbols]

3 歩度調整回路 4 タイミング作成回路 9 メモリ 10 メモリ書き換え回路 11 強制動作回路 3 rate adjustment circuit 4 timing creation circuit 9 memory 10 memory rewrite circuit 11 forced operation circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 書き換え可能なメモリと、端子設定する
ことなくメモリを書き換えるメモリ書き換え手段と、書
き込まれているメモリによって制御する量が変化する制
御手段と、制御手段を定期的に動作させるためのタイミ
ング作成手段を有する電子時計において、メモリ書き換
え手段によってメモリが書き換えられた後、タイミング
作成手段のタイミングと無関係にすぐにその結果を制御
手段に反映させるための強制動作手段を設けたことを特
徴とする電子時計。
1. A rewritable memory, a memory rewriting means for rewriting a memory without setting a terminal, a control means for changing an amount controlled by the written memory, and a means for periodically operating the control means An electronic timepiece having a timing creating means, wherein after the memory is rewritten by the memory rewriting means, a forced operation means for immediately reflecting the result on the control means irrespective of the timing of the timing creating means is provided. Electronic clock.
JP14761397A 1997-06-05 1997-06-05 Electronic clock Expired - Fee Related JP3681860B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14761397A JP3681860B2 (en) 1997-06-05 1997-06-05 Electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14761397A JP3681860B2 (en) 1997-06-05 1997-06-05 Electronic clock

Publications (2)

Publication Number Publication Date
JPH10332852A true JPH10332852A (en) 1998-12-18
JP3681860B2 JP3681860B2 (en) 2005-08-10

Family

ID=15434292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14761397A Expired - Fee Related JP3681860B2 (en) 1997-06-05 1997-06-05 Electronic clock

Country Status (1)

Country Link
JP (1) JP3681860B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10317847B2 (en) 2016-03-23 2019-06-11 Seiko Epson Corporation Electronic timepiece

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10317847B2 (en) 2016-03-23 2019-06-11 Seiko Epson Corporation Electronic timepiece

Also Published As

Publication number Publication date
JP3681860B2 (en) 2005-08-10

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