JP3679937B2 - Amorphous silicon solar cell and manufacturing method thereof - Google Patents

Amorphous silicon solar cell and manufacturing method thereof Download PDF

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Publication number
JP3679937B2
JP3679937B2 JP33970298A JP33970298A JP3679937B2 JP 3679937 B2 JP3679937 B2 JP 3679937B2 JP 33970298 A JP33970298 A JP 33970298A JP 33970298 A JP33970298 A JP 33970298A JP 3679937 B2 JP3679937 B2 JP 3679937B2
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layer
film
late
solar cell
amorphous silicon
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JP2000164908A (en
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章二 森田
正義 村田
良昭 竹内
立淳 西宮
暁己 高野
一晃 大嶋
辰史 青井
竜治 堀岡
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Mitsubishi Heavy Industries Ltd
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Mitsubishi Heavy Industries Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells

Description

【0001】
【発明の属する技術分野】
本発明は、特に太陽電池発電システムで使用される非晶質シリコン太陽電池及びその製造方法に関する。
【0002】
【従来の技術】
従来、pin型a−Si太陽電池としては、図3に示す構成のものが知られている(特公平5−10835号)。
図中の符番1はガラス基板(又は透明フィルム)である。このガラス基板1上には、SnO2 からなる透明電極2が形成されている。ここで、透明電極2の表面Sは、光閉じ込め効果を向上させる目的でヘイズ率10%程度の凹凸を有している。この透明電極2上には、p層3,i層4及びn層5からなる非晶質シリコン層6がプラズマCVD法により形成されている。この非晶質シリコン層6上には、真空蒸着などの手段により金属電極7が形成されている。
【0003】
こうした構成の太陽電池において、光はガラス基板1側から入射された後、透明電極2,p層3を通過してi層4に達し、このi層4で光エネルギーが電気エネルギーに変換される。
【0004】
ところで、上記太陽電池において、生産性向上による低コスト化を図るためには、最も膜厚の厚いi層4の高速成膜化が必須である。そして、非晶質シリコン成膜方法であるプラズマCVD法において成膜速度を増大させるには高周波電力を増大させ、プラズマ密度を高める方法が最も一般的かつ直接的である。
【0005】
【発明が解決しようとする課題】
しかしながら、従来の太陽電池によれば、下記の問題点を有していた。
(1) 高速成膜のためにプラズマを発生させる高周波電力を増大させると、プラズマ中のイオンエネルギーも増大する。i層4成膜初期に高エネルギーイオンがp層3/i層4界面に衝突すると、欠陥準位を生じ、キャリア再結合損失が増大するため、短絡電流が増大する。
【0006】
(2) 高速成膜したi層4は表面の凹凸が大きいため、i層4とn層5の密着性が低下し、隙間を生じ、電池としての有効面積が減少する。
【0007】
(3) 凹凸を有する透明電極2上に高速でa−Si太陽電池を構成すると、透明電極2を構成する結晶粒間の谷からi層5の膜厚方向に微細な亀裂が生じ、キャリアの再結合中心となるため短絡電流が低下する。
【0008】
本発明はこうした事情を考慮してなされたもので、透明電極上のp層上に低欠陥密度のi層初期膜及びi層バルク膜からなるi層を設けることにより、p層/i層界面付近の欠陥準位を低減させ、短波長感度を改善して短絡電流を増大しえる非晶質シリコン太陽電池及びその製造方法を提供することを目的とする。
【0009】
また、本発明は、透明電極上のp層上にi層バルク膜及び低欠陥で表面被覆性に優れたi層後期膜を有するi層を設けることにより、i層/n層界面の密着性を向上し、長波長感度を改善して短絡電流を増大しえるとともに、n層も膜厚分布を改善しi層内の内部電界の均一性を向上して開放電圧を増大しえる非晶質シリコン太陽電池及びその製造方法を提供することを目的とする。
【0010】
更に、本発明は、透明電極上のp層上に低欠陥密度のi層初期膜及び低欠陥で表面被覆性に優れたi層後期膜を設けることにより、i層の膜厚方向の亀裂発生を抑制し、i層内でのキャリア再結合を低減し、短絡電流を増大しえる非晶質シリコン太陽電池及びその製造方法を提供することを目的とする。
【0011】
【課題を解決するための手段】
本願第1の発明は、透明基板と、この透明基板上に形成された透明電極と、この透明電極上に形成されたp層と、このp層上に順次形成された、i層初期膜、高速成膜されたi層バルク膜、及びi層後期膜を有したi層と、このi層上に形成されたn層と、このn層上に形成された金属電極とを具備し、該i層初期膜は、成膜速度0.1〜0.4nm/sで形成され、その膜厚が5〜50nmの範囲であり、その欠陥密度が8×10 14 個/cc以下であり、前記i層後期膜は、成膜速度0.1〜0.4nm/sで形成され、前記i層バルク膜の膜厚方向の亀裂発生を抑制するように設けられており、その欠陥密度が8×10 14 個/cc以下であり、その表面粗さが200〜300nmの範囲であることを特徴とする非晶質シリコン太陽電池である。
【0015】
本願第2の発明は、透明基板上に透明電極を形成する工程と、この透明電極上にp層を形成する工程と、このp層上に成膜速度0.1〜0.4nm/sで形成されるi層初期膜、高速成膜されるi層バルク膜、及び該i層バルク膜の膜厚方向の亀裂発生を抑制するように設け、成膜速度0.1〜0.4nm/sで形成されるi層後期膜を有したi層を形成する工程と、このi層上にn層を形成する工程と、このn層上に金属電極を形成する工程とを具備し、前記i層初期膜の膜厚が5〜50nmの範囲であり、その欠陥密度が8×10 14 個/cc以下であり、前記i層後期膜の欠陥密度が8×10 14 個/cc以下であり、その表面粗さが200〜300nmの範囲であることを特徴とする非晶質シリコン太陽電池の製造方法である。
【0016】
【発明の実施の形態】
以下、本発明の一実施例に係る非晶質シリコン太陽電池について図1を参照して説明する。
図中の符号11は、透明基板としてのガラス基板を示す。このガラス基板11上には、酸化スズからなる表面粗さ400〜500nmの透明電極12が形成されている。この透明電極12上には、p層13と、バッファ層14と、膜厚5〜50nmのi層初期膜15と、i層バルク膜16と、膜厚10〜50nmのi層後期膜17と、n層18からなる非晶質シリコン層19が形成されている。
【0017】
なお、i層初期膜15の膜厚が5nm未満の場合、p層/i層界面特性を改善する効果が小さい。一方、i層初期膜15の膜厚が50nmを超えると、p層/i層界面特性を改善する効果は飽和する。また、i層後期膜17の膜厚が5nm未満の場合、i層/n層界面特性を改善する効果が小さい。一方、i層後期膜17の膜厚が50nmを超えると、i層/n層界面特性を改善する効果は飽和する。
【0018】
前記i層初期膜15の欠陥密度は、8×1014個/cc以下である。ここで、i層初期膜15の欠陥密度が8×1014個/ccを超えると、i層初期膜としてのp層/i層界面特性を改善する効果が低減する。前記i層後期膜17の欠陥密度は、8×1014個/cc以下である。ここで、i層後期膜17の欠陥密度が8×1014個/ccを超えると、i層後期膜としてのi層/n層界面特性を改善する効果が低減する。前記非晶質シリコン層19上には、Alからなる金属電極20が形成されている。
【0019】
上記した構成の非晶質シリコン太陽電池は、図2に示す製造装置を用いて形成される。図中の符番21は反応容器であり、内部に基板加熱用ヒータ22,アース線23に接続された放電用電極24が対向して配置されている。前記放電用電極24には、高周波電源25がインピーダンス整合器26を介して接続されている。前記基板加熱用ヒータ22には、基板27が支持されている。この基板27と前記放電用電極24間には、製膜表面ヒータ用電源28に接続されたメッシュ状の製膜表面ヒータ29が配置されている。前記反応容器21には、放電用電極24周辺に反応ガスを導入する反応ガス導入管30が接続されている。また、前記反応容器21には、排気管31を介して真空ポンプ32が接続されている。
【0020】
次に、図2の製造装置を用いて図1の非晶質シリコン太陽電池を製造する方法について説明する。
まず、ガラス基板11上に透明電極12を形成した。つづいて、この透明電極12上に、p層13と,バッファ層14と,膜厚5〜50nmのi層初期膜15と,i層バルク膜16と,膜厚10〜50nmのi層後期膜17と,n層18からなる非晶質シリコン層19を形成した。前記i層初期膜15の形成に際しては、成膜速度0.1〜0.4nm/s,製膜表面ヒータ電力150〜200W,放電周波数27〜100MHzの少なくともいずれかの条件を満たしながら、欠陥密度8×1014個/cc以下とした。また、i層バルク膜16は、i層初期膜15を形成後、放電を維持したまま形成した。さらに、i層後期膜17はi層バルク膜16を形成後、放電を維持したまま形成した。
【0021】
i層初期膜15の成膜速度を上記のように設定したのは、0.1nm/s未満では、放電が不安定となって品質の安定した太陽電池の製造が困難になるからであり、0.4nm/sを超えると、欠陥密度の小さい高品質膜が得られないため、i層初期膜としてのp層/i層界面特性の改善効果が小さいからである。
【0022】
製膜表面ヒータ電力を上記のように設定したのは、次の理由による。即ち、電力が150W未満の場合、ラジカルに与えるエネルギーが小さいため、ラジカルの表面拡散が不十分となり、低欠陥密度膜が得られず、i層初期膜としてのp層/i層界面特性の改善効果が小さい。一方、電力が200Wを超えると、基板が高温となるため、透明電極12からp層13、p層13からi層初期膜15への不純物拡散が顕著になり、p層13及びi層初期膜15の膜質が低下するからである。
【0023】
放電周波数を上記のように設定したのは、次の理由による。即ち、放電周波数が27MHz未満の場合、プラズマの高周波数化に伴う電子温度低下の効果が小さいため、低欠陥密度膜が得られず、i層初期膜としてのp層/i層初期膜としてのp層/i層界面特性の改善効果が小さい。一方、放電周波数が100MHzを超えると、放電が局所的となり、均一なプラズマが得られないため、太陽電池特性がばらつく。
【0024】
前記i層後期膜17の形成に際しては、i層バルク膜16の形成後、成膜速度0.1〜0.4nm/s,製膜表面ヒータ電力150〜200W,放電周波数27〜100MHzの少なくともいずれかの条件を満たしながら、欠陥密度8×1014個/cc以下とした。また、i層後期膜17の表面粗さは200〜300nmとした。
【0025】
i層後期膜17の成膜速度を上記の設定したのは、0.1nm/s未満では、放電が不安定となって品質の安定した太陽電池の製造が困難になるからであり、0.4nm/sを超えると、欠陥密度の小さい高品質膜が得られないため、i層後期膜としてのi層/n層界面特性の改善効果が小さいからである。
【0026】
i層後期膜17を形成する際の製膜表面ヒータ電力を上記のように設定したのは、次の理由による。即ち、電力が150W未満の場合、ラジカルに与えるエネルギーが小さいため、ラジカルの表面拡散が不十分となり、低欠陥密度膜が得られず、i層後期膜としてのi層/n層界面特性の改善効果が小さい。一方、電力が200Wを超えると、基板が高温となるため、既に積層した層間の不純物拡散が顕著になるとともに最表面層であるi層16の熱的変質が生じるからである。
【0027】
i層後期膜17を形成する際の放電周波数を上記のように設定したのは、次の理由による。即ち、放電周波数が27MHz未満の場合、プラズマの高周波数化に伴う電子温度低下の効果が小さいため、低欠陥密度膜が得られず、i層後期膜17としてのi層/n層界面特性の改善効果が小さい。一方、放電周波数が100MHzを超えると、放電が局所的となり、均一なプラズマが得られないため、太陽電池特性がばらつくからである。
【0028】
i層後期膜17の表面粗さを上記のように設定したのは、次の理由による。400から500nmの表面粗さを有する透明電極12上にi層を積層するが、i層高速成膜条件であること及びi層の表面粗さが透明電極12の影響を受けるため、その上に積層するi層後期膜17の表面粗さは基本的には200nm以下未満に制御することは困難である。一方、i層後期膜17の表面粗さが300nmを超えた場合、n層18との密着性が低下し、隙間が多くなるため発電有効面積が減少する。
【0029】
図4は、i層初期膜〜i層後期膜における成膜速度と時間の関係を示す特性図を示す。図4において、T1 はi層初期膜15形成時間を、T2 及びT4 は移行膜形成時間を、T3 はi層バルク膜16形成時間を、T5 はi層後期膜17形成時間を示す。
【0030】
図5は、i層初期膜〜i層後期膜における製膜表面ヒータ電力と時間の関係を示す特性図を示す。図5において、T1 はi層初期膜15形成時間を、T2 はi層バルク膜16形成時間を、T3 はi層後期膜17形成時間を示す。
【0031】
図6は、i層初期膜〜i層後期膜における放電周波数と時間の関係を示す特性図を示す。図6において、T1 はi層初期膜15形成時間を、T2 はi層バルク膜16形成時間を、T3 はi層後期膜17形成時間を示す。
【0032】
このようにして製造される非晶質シリコン太陽電池によれば、以下に述べる効果を有する。
1)低欠陥密度のi層初期膜15をp層13上にバッファ層14を介して設けることにより、p層13/i層バルク膜16界面付近の欠陥準位が低減し、短波長感度を改善でき、短絡電流を増大できる。
【0033】
2)低欠陥で表面被覆性に優れたi層後期膜17をi層バルク膜16上に設けることにより、i層バルク膜16/n層18界面の密着性を向上できる。その結果、長波長が改善され、短絡電流を増大できる。また、n層18の膜厚分布が改善され、i層バルク膜16内の内部電界の均一性が向上するため、開放電圧が増大する。
【0034】
3)低欠陥密度のi層初期膜15及び低欠陥で表面被覆性に優れたi層後期膜17を設けることにより、i層バルク膜16の亀裂発生が抑制されるため、i層バルク膜16内でのキャリア再結合が向上低減し、短絡電流が増大する。
【0035】
事実、i層初期膜及びi層後期膜のいずれも設けない場合(比較例)の効率を100とした場合、既述したような条件下でi層初期膜を設けた場合、i層後期膜を設けた場合、i層初期膜及びi層後期膜の両者を設けた場合の夫々の効率は、115、120、120であることが判明した。これにより、本発明に寄る効果が確認できた。
【0036】
【発明の効果】
以上詳述したように本発明によれば、透明基板と、この透明基板上に形成された透明電極と、この透明電極上に形成されたp層と、このp層上に順次形成された、i層初期膜、高速成膜されたi層バルク膜、及びi層後期膜を有したi層と、このi層上に形成されたn層と、このn層上に形成された金属電極とを具備し、該i層初期膜は、成膜速度0.1〜0.4nm/sで形成され、その膜厚が5〜50nmの範囲であり、その欠陥密度が8×10 14 個/cc以下であり、前記i層後期膜は、成膜速度0.1〜0.4nm/sで形成され、前記i層バルク膜の膜厚方向の亀裂発生を抑制するように設けられており、その欠陥密度が8×10 14 個/cc以下であり、その表面粗さが200〜300nmの範囲であることにより、p層/i層界面付近の欠陥準位を低減させて短波長感度を改善し、i層/n層界面の密着性を向上させて長波長感度を改善し、i層の膜厚方向の亀裂発生を抑制して i 層内でのキャリア再結合を低減し、短絡電流を増大しえる非晶質シリコン太陽電池及びその製造方法を提供できる。
【図面の簡単な説明】
【図1】本発明の一実施例に係る非晶質シリコン太陽電池の断面図。
【図2】図1の非晶質シリコン太陽電池の製造に用いた製造装置の説明図。
【図3】従来の非晶質シリコン太陽電池の断面図。
【図4】図1の非晶質シリコン太陽電池において、i層初期膜〜i層後期膜の成膜における成膜速度の特性図。
【図5】図1の非晶質シリコン太陽電池において、i層初期膜〜i層後期膜の成膜におけるラジカルヒータ電力の特性図。
【図6】図1の非晶質シリコン太陽電池において、i層初期膜〜i層後期膜の成膜に
おける放電周波数の特性図。
【符号の説明】
11…ガラス基板、
12…透明電極、
13…p層、
14…バッファ層、
15…i層初期膜、
16…i層バルク膜、
17…i層後期膜、
18…n層、
19…非晶質シリコン層、
20…金属電極、
21…真空容器、
22…基板加熱用ヒータ、
23…アース線、
24…放電用電極、
25…高周波電源、
26…インピーダンス整合器、
27…基板、
28…製膜表面ヒータ用電源、
29…製膜表面ヒータ、
30…ガス導入管、
31…排気管、
32…真空ポンプ。
[0001]
BACKGROUND OF THE INVENTION
The present invention particularly relates to an amorphous silicon solar cell used in a solar cell power generation system and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, as a pin-type a-Si solar cell, the structure shown in FIG. 3 is known (Japanese Patent Publication No. 5-10835).
Reference numeral 1 in the figure is a glass substrate (or transparent film). On this glass substrate 1, transparent electrodes 2 made of SnO 2 is formed. Here, the surface S of the transparent electrode 2 has irregularities with a haze ratio of about 10% for the purpose of improving the light confinement effect. On the transparent electrode 2, an amorphous silicon layer 6 composed of a p layer 3, an i layer 4 and an n layer 5 is formed by a plasma CVD method. A metal electrode 7 is formed on the amorphous silicon layer 6 by means such as vacuum deposition.
[0003]
In the solar cell having such a configuration, light is incident from the glass substrate 1 side, then passes through the transparent electrode 2 and the p layer 3 to reach the i layer 4, and light energy is converted into electric energy in the i layer 4. .
[0004]
By the way, in the solar cell, in order to reduce the cost by improving the productivity, it is essential to form the i layer 4 having the thickest film at a high speed. In order to increase the deposition rate in the plasma CVD method, which is an amorphous silicon deposition method, the most common and direct method is to increase the high-frequency power and increase the plasma density.
[0005]
[Problems to be solved by the invention]
However, the conventional solar cell has the following problems.
(1) Increasing the high-frequency power that generates plasma for high-speed film formation increases the ion energy in the plasma. When high energy ions collide with the interface between the p layer 3 and the i layer 4 at the initial stage of the formation of the i layer 4, a defect level is generated and a carrier recombination loss increases, so that a short circuit current increases.
[0006]
(2) Since the i-layer 4 formed at high speed has large surface irregularities, the adhesion between the i-layer 4 and the n-layer 5 is reduced, a gap is formed, and the effective area as a battery is reduced.
[0007]
(3) When an a-Si solar cell is constructed on the transparent electrode 2 having irregularities at a high speed, fine cracks are generated in the film thickness direction of the i layer 5 from the valleys between the crystal grains constituting the transparent electrode 2, and the carrier Since it becomes a recombination center, a short circuit current falls.
[0008]
The present invention has been made in view of such circumstances, and by providing an i layer comprising a low defect density i layer initial film and an i layer bulk film on the p layer on the transparent electrode, the p layer / i layer interface is provided. An object of the present invention is to provide an amorphous silicon solar cell capable of reducing the defect level in the vicinity, improving the short wavelength sensitivity and increasing the short-circuit current, and a method for manufacturing the same.
[0009]
In addition, the present invention provides an i layer / n layer interface adhesion by providing an i layer bulk film and an i layer late film having low defects and excellent surface coverage on the p layer on the transparent electrode. Can improve the long wavelength sensitivity and increase the short-circuit current, and the n layer can also improve the film thickness distribution and improve the uniformity of the internal electric field in the i layer to increase the open circuit voltage. It aims at providing a silicon solar cell and its manufacturing method.
[0010]
Furthermore, the present invention provides an i-layer initial film having a low defect density and an i-layer late film having a low defect and excellent surface coverage on the p-layer on the transparent electrode, thereby generating cracks in the thickness direction of the i-layer. It is an object to provide an amorphous silicon solar cell and a method for manufacturing the same, which can suppress short circuit current, reduce carrier recombination in the i layer, and increase the short-circuit current.
[0011]
[Means for Solving the Problems]
The first invention of the present application includes a transparent substrate, a transparent electrode formed on the transparent substrate, a p layer formed on the transparent electrode , an i-layer initial film sequentially formed on the p layer , comprising the i layer having a high-speed film formation has been i layer bulk layer, and the i-layer late film, and the i layer n layer formed on, and a metal electrode formed on the n layer, the The i-layer initial film is formed at a deposition rate of 0.1 to 0.4 nm / s, the film thickness is in the range of 5 to 50 nm, the defect density is 8 × 10 14 pieces / cc or less, The i-layer late film is formed at a deposition rate of 0.1 to 0.4 nm / s, and is provided so as to suppress the occurrence of cracks in the film thickness direction of the i-layer bulk film. 10 14 / cc or less, an amorphous silicon solar, characterized in that the surface roughness is in the range of 200~300nm It is.
[0015]
The second invention of the present application includes a step of forming a transparent electrode on a transparent substrate, a step of forming a p layer on the transparent electrode, and a film formation rate of 0.1 to 0.4 nm / s on the p layer. An i-layer initial film to be formed, an i-layer bulk film to be formed at a high speed, and a film formation rate of 0.1 to 0.4 nm / s are provided so as to suppress the occurrence of cracks in the film thickness direction of the i-layer bulk film. A step of forming an i layer having an i layer late film formed in step i, a step of forming an n layer on the i layer, and a step of forming a metal electrode on the n layer. The film thickness of the initial layer film is in the range of 5 to 50 nm, the defect density thereof is 8 × 10 14 pieces / cc or less, the defect density of the i-layer late film is 8 × 10 14 pieces / cc or less, The surface roughness is in a range of 200 to 300 nm .
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an amorphous silicon solar cell according to an embodiment of the present invention will be described with reference to FIG.
The code | symbol 11 in a figure shows the glass substrate as a transparent substrate. On the glass substrate 11, a transparent electrode 12 made of tin oxide and having a surface roughness of 400 to 500 nm is formed. On this transparent electrode 12, a p-layer 13, a buffer layer 14, an i-layer initial film 15 having a thickness of 5 to 50 nm, an i-layer bulk film 16, and an i-layer late film 17 having a thickness of 10 to 50 nm, , An amorphous silicon layer 19 made of the n layer 18 is formed.
[0017]
When the film thickness of the i-layer initial film 15 is less than 5 nm, the effect of improving the p-layer / i-layer interface characteristics is small. On the other hand, when the film thickness of the i-layer initial film 15 exceeds 50 nm, the effect of improving the p-layer / i-layer interface characteristics is saturated. Further, when the film thickness of the i-layer late film 17 is less than 5 nm, the effect of improving the i-layer / n-layer interface characteristics is small. On the other hand, when the film thickness of the i-layer late film 17 exceeds 50 nm, the effect of improving the i-layer / n-layer interface characteristics is saturated.
[0018]
The defect density of the i-layer initial film 15 is 8 × 10 14 pieces / cc or less. Here, when the defect density of the i-layer initial film 15 exceeds 8 × 10 14 / cc, the effect of improving the p-layer / i-layer interface characteristics as the i-layer initial film is reduced. The defect density of the i-layer late film 17 is 8 × 10 14 pieces / cc or less. Here, when the defect density of the i-layer late film 17 exceeds 8 × 10 14 pieces / cc, the effect of improving the i-layer / n-layer interface characteristics as the i-layer late film is reduced. A metal electrode 20 made of Al is formed on the amorphous silicon layer 19.
[0019]
The amorphous silicon solar cell having the above-described configuration is formed using the manufacturing apparatus shown in FIG. Reference numeral 21 in the figure denotes a reaction vessel, in which a substrate heating heater 22 and a discharge electrode 24 connected to a ground wire 23 are arranged facing each other. A high frequency power source 25 is connected to the discharge electrode 24 via an impedance matching unit 26. A substrate 27 is supported on the substrate heating heater 22. Between the substrate 27 and the discharge electrode 24, a mesh-shaped film-forming surface heater 29 connected to a film-forming surface heater power source 28 is disposed. Connected to the reaction vessel 21 is a reaction gas introduction tube 30 for introducing a reaction gas around the discharge electrode 24. A vacuum pump 32 is connected to the reaction vessel 21 through an exhaust pipe 31.
[0020]
Next, a method for manufacturing the amorphous silicon solar cell of FIG. 1 using the manufacturing apparatus of FIG. 2 will be described.
First, the transparent electrode 12 was formed on the glass substrate 11. Subsequently, on this transparent electrode 12, a p layer 13, a buffer layer 14, an i layer initial film 15 having a thickness of 5 to 50 nm, an i layer bulk film 16, and an i layer late film having a thickness of 10 to 50 nm. 17 and an amorphous silicon layer 19 composed of an n layer 18 were formed. In forming the i-layer initial film 15, the defect density is satisfied while satisfying at least one of the conditions of a film formation speed of 0.1 to 0.4 nm / s, a film-forming surface heater power of 150 to 200 W, and a discharge frequency of 27 to 100 MHz. 8 × 10 14 pieces / cc or less. The i-layer bulk film 16 was formed while maintaining the discharge after the i-layer initial film 15 was formed. Further, the i-layer late film 17 was formed while maintaining the discharge after the i-layer bulk film 16 was formed.
[0021]
The reason why the film formation rate of the i-layer initial film 15 is set as described above is that when it is less than 0.1 nm / s, the discharge becomes unstable and it becomes difficult to manufacture a solar cell with stable quality. This is because if the thickness exceeds 0.4 nm / s, a high-quality film having a low defect density cannot be obtained, so that the effect of improving the p-layer / i-layer interface characteristics as the i-layer initial film is small.
[0022]
The reason why the film forming surface heater power is set as described above is as follows. That is, when the electric power is less than 150 W, the energy imparted to the radical is small, so that the surface diffusion of the radical becomes insufficient, a low defect density film cannot be obtained, and the p layer / i layer interface characteristics as the i layer initial film are improved. Small effect. On the other hand, when the power exceeds 200 W, the temperature of the substrate becomes high, so that impurity diffusion from the transparent electrode 12 to the p layer 13 and from the p layer 13 to the i layer initial film 15 becomes significant. It is because the film quality of 15 falls.
[0023]
The reason for setting the discharge frequency as described above is as follows. That is, when the discharge frequency is less than 27 MHz, the effect of lowering the electron temperature due to the higher frequency of plasma is small, so a low defect density film cannot be obtained, and the p layer / i layer initial film as the i layer initial film is not obtained. The effect of improving the p-layer / i-layer interface characteristics is small. On the other hand, when the discharge frequency exceeds 100 MHz, the discharge becomes local and uniform plasma cannot be obtained, so that the solar cell characteristics vary.
[0024]
When forming the i-layer late film 17, after forming the i-layer bulk film 16, at least one of a film formation speed of 0.1 to 0.4 nm / s, a film-forming surface heater power of 150 to 200 W, and a discharge frequency of 27 to 100 MHz. While satisfying these conditions, the defect density was set to 8 × 10 14 pieces / cc or less. The surface roughness of the i-layer late film 17 was 200 to 300 nm.
[0025]
The reason why the film formation rate of the i-layer late film 17 is set as described above is that if it is less than 0.1 nm / s, the discharge becomes unstable and it becomes difficult to manufacture a solar cell with stable quality. This is because if the thickness exceeds 4 nm / s, a high-quality film having a low defect density cannot be obtained, so that the effect of improving the i-layer / n-layer interface characteristics as the i-layer late film is small.
[0026]
The reason for setting the film-forming surface heater power when forming the i-layer late film 17 as described above is as follows. That is, when the electric power is less than 150 W, the energy given to the radical is small, so that the surface diffusion of the radical becomes insufficient, a low defect density film cannot be obtained, and the i layer / n layer interface characteristics as an i layer late film are improved. Small effect. On the other hand, when the electric power exceeds 200 W, the substrate becomes high temperature, so that impurity diffusion between the already laminated layers becomes remarkable and thermal alteration of the i-layer 16 which is the outermost surface layer occurs.
[0027]
The reason why the discharge frequency when forming the i-layer late film 17 is set as described above is as follows. That is, when the discharge frequency is less than 27 MHz, the effect of lowering the electron temperature due to the higher frequency of the plasma is small, so a low defect density film cannot be obtained, and the i layer / n layer interface characteristic as the i layer late film 17 is not obtained. The improvement effect is small. On the other hand, if the discharge frequency exceeds 100 MHz, the discharge becomes local and uniform plasma cannot be obtained, so that the solar cell characteristics vary.
[0028]
The reason why the surface roughness of the i-layer late film 17 is set as described above is as follows. The i layer is laminated on the transparent electrode 12 having a surface roughness of 400 to 500 nm. However, since the i layer has a high-speed film forming condition and the surface roughness of the i layer is affected by the transparent electrode 12, the i layer is formed thereon. It is difficult to basically control the surface roughness of the laminated i-layer late film 17 to be less than 200 nm or less. On the other hand, when the surface roughness of the i-layer late film 17 exceeds 300 nm, the adhesion with the n-layer 18 is lowered and the gap is increased, so that the power generation effective area is reduced.
[0029]
FIG. 4 is a characteristic diagram showing the relationship between the deposition rate and time in the i-layer initial film to the i-layer late film. In FIG. 4, T 1 is the formation time of the i-layer initial film 15, T 2 and T 4 are the transition film formation time, T 3 is the formation time of the i-layer bulk film 16, and T 5 is the formation time of the i-layer late film 17. Indicates.
[0030]
FIG. 5 is a characteristic diagram showing the relationship between the deposition surface heater power and time in the i-layer initial film to the i-layer late film. In FIG. 5, T 1 represents the formation time of the i-layer initial film 15, T 2 represents the formation time of the i-layer bulk film 16, and T 3 represents the formation time of the i-layer late film 17.
[0031]
FIG. 6 is a characteristic diagram showing the relationship between the discharge frequency and time in the i-layer initial film to the i-layer late film. In FIG. 6, T 1 indicates the formation time of the i-layer initial film 15, T 2 indicates the formation time of the i-layer bulk film 16, and T 3 indicates the formation time of the i-layer late film 17.
[0032]
The amorphous silicon solar cell thus manufactured has the following effects.
1) By providing the low defect density i-layer initial film 15 on the p-layer 13 via the buffer layer 14, the defect level near the interface of the p-layer 13 / i-layer bulk film 16 is reduced, and the short wavelength sensitivity is improved. It can be improved and the short circuit current can be increased.
[0033]
2) By providing the i-layer late film 17 with low defects and excellent surface coverage on the i-layer bulk film 16, the adhesion at the interface between the i-layer bulk film 16 and the n-layer 18 can be improved. As a result, the long wavelength is improved and the short circuit current can be increased. In addition, since the film thickness distribution of the n layer 18 is improved and the uniformity of the internal electric field in the i layer bulk film 16 is improved, the open circuit voltage increases.
[0034]
3) Since the i-layer initial film 15 having a low defect density and the i-layer late film 17 having a low defect and excellent surface coverage are provided, the generation of cracks in the i-layer bulk film 16 is suppressed. The carrier recombination is improved and reduced, and the short circuit current is increased.
[0035]
In fact, when neither the i-layer initial film nor the i-layer late film is provided (comparative example), the efficiency is 100. When the i-layer initial film is provided under the conditions described above, the i-layer late film It was found that the respective efficiencies when both the i-layer initial film and the i-layer late film were provided were 115, 120, and 120. Thereby, the effect close to the present invention was confirmed.
[0036]
【The invention's effect】
As described above in detail, according to the present invention, the transparent substrate, the transparent electrode formed on the transparent substrate, the p layer formed on the transparent electrode, and the p layer are sequentially formed. an i-layer having an i-layer initial film, an i-layer bulk film formed at a high speed, an i-layer late film, an n-layer formed on the i-layer, and a metal electrode formed on the n-layer The i-layer initial film is formed at a deposition rate of 0.1 to 0.4 nm / s, the film thickness is in the range of 5 to 50 nm, and the defect density is 8 × 10 14 / cc. The i-layer late film is formed at a deposition rate of 0.1 to 0.4 nm / s, and is provided so as to suppress the occurrence of cracks in the film thickness direction of the i-layer bulk film. When the defect density is 8 × 10 14 pieces / cc or less and the surface roughness is in the range of 200 to 300 nm, p layer / i By reducing the defect level in the vicinity of the layer interface improves short wavelength sensitivity, i layer / n layer to improve the adhesion at the interface to improve the long wavelength sensitivity, suppressing the thickness direction of the crack generation of the i layer Thus, it is possible to provide an amorphous silicon solar cell that can reduce carrier recombination in the i layer and increase a short-circuit current, and a method for manufacturing the same.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an amorphous silicon solar cell according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing apparatus used for manufacturing the amorphous silicon solar cell of FIG.
FIG. 3 is a cross-sectional view of a conventional amorphous silicon solar cell.
4 is a characteristic diagram of film formation speed in the formation of an i-layer initial film to an i-layer late film in the amorphous silicon solar cell of FIG. 1. FIG.
FIG. 5 is a characteristic diagram of radical heater power in the formation of an i-layer initial film to an i-layer late film in the amorphous silicon solar cell of FIG.
6 is a characteristic diagram of discharge frequency in the formation of an i-layer initial film to an i-layer late film in the amorphous silicon solar cell of FIG. 1. FIG.
[Explanation of symbols]
11 ... Glass substrate,
12 ... Transparent electrode,
13 ... p layer,
14 ... buffer layer,
15 ... i layer initial film,
16 ... i layer bulk film,
17 ... I layer late membrane,
18 ... n layer,
19 ... amorphous silicon layer,
20: Metal electrode,
21 ... Vacuum container,
22 ... Substrate heating heater,
23 ... Earth wire,
24 ... Electrode for discharge,
25 ... High frequency power supply,
26: Impedance matching device,
27 ... substrate
28 ... Power source for film-forming surface heater,
29 ... Film-forming surface heater,
30: Gas introduction pipe,
31 ... exhaust pipe,
32 ... Vacuum pump.

Claims (2)

透明基板と、この透明基板上に形成された透明電極と、この透明電極上に形成されたp層と、このp層上に順次形成された、i層初期膜、高速成膜されたi層バルク膜、及びi層後期膜を有したi層と、このi層上に形成されたn層と、このn層上に形成された金属電極とを具備し、該i層初期膜は、成膜速度0.1〜0.4nm/sで形成され、その膜厚が5〜50nmの範囲であり、その欠陥密度が8×10 14 個/cc以下であり、前記i層後期膜は、成膜速度0.1〜0.4nm/sで形成され、前記i層バルク膜の膜厚方向の亀裂発生を抑制するように設けられており、その欠陥密度が8×10 14 個/cc以下であり、その表面粗さが200〜300nmの範囲であることを特徴とする非晶質シリコン太陽電池。Transparent substrate, transparent electrode formed on this transparent substrate, p layer formed on this transparent electrode , i layer initial film formed on this p layer in sequence, i layer formed at high speed The i-layer having a bulk film and an i-layer late film , an n-layer formed on the i-layer, and a metal electrode formed on the n-layer , The film is formed at a film speed of 0.1 to 0.4 nm / s, the film thickness is in the range of 5 to 50 nm, the defect density is 8 × 10 14 pieces / cc or less, and the i-layer late film is composed of It is formed at a film speed of 0.1 to 0.4 nm / s, and is provided so as to suppress the occurrence of cracks in the film thickness direction of the i-layer bulk film, and its defect density is 8 × 10 14 pieces / cc or less. An amorphous silicon solar cell having a surface roughness in the range of 200 to 300 nm . 透明基板上に透明電極を形成する工程と、この透明電極上にp層を形成する工程と、このp層上に成膜速度0.1〜0.4nm/sで形成されるi層初期膜、高速成膜されるi層バルク膜、及び該i層バルク膜の膜厚方向の亀裂発生を抑制するように設け、成膜速度0.1〜0.4nm/sで形成されるi層後期膜を有したi層を形成する工程と、このi層上にn層を形成する工程と、このn層上に金属電極を形成する工程とを具備し、前記i層初期膜の膜厚が5〜50nmの範囲であり、その欠陥密度が8×10 14 個/cc以下であり、前記i層後期膜の欠陥密度が8×10 14 個/cc以下であり、その表面粗さが200〜300nmの範囲であることを特徴とする非晶質シリコン太陽電池の製造方法。 A step of forming a transparent electrode on a transparent substrate, a step of forming a p layer on the transparent electrode, and an i-layer initial film formed on the p layer at a film formation rate of 0.1 to 0.4 nm / s I layer bulk film formed at high speed, and i layer late film formed at a film formation rate of 0.1 to 0.4 nm / s, so as to suppress the occurrence of cracks in the film thickness direction of the i layer bulk film A step of forming an i layer having a film; a step of forming an n layer on the i layer; and a step of forming a metal electrode on the n layer. The defect density is in the range of 5 to 50 nm, the defect density is 8 × 10 14 pieces / cc or less, the defect density of the i-layer late film is 8 × 10 14 pieces / cc or less, and the surface roughness is 200 to A method for producing an amorphous silicon solar cell, characterized by being in a range of 300 nm .
JP33970298A 1998-11-30 1998-11-30 Amorphous silicon solar cell and manufacturing method thereof Expired - Fee Related JP3679937B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210040677A (en) * 2019-10-04 2021-04-14 한국재료연구원 Semitransparent thin film solar cell and manufacturing method of the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210040677A (en) * 2019-10-04 2021-04-14 한국재료연구원 Semitransparent thin film solar cell and manufacturing method of the same
KR102297241B1 (en) * 2019-10-04 2021-09-03 한국재료연구원 Semitransparent thin film solar cell and manufacturing method of the same

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