JP3677996B2 - Liquid crystal device and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix liquid crystal device and a driving method thereof.
[0002]
[Prior art]
The configuration of a conventional active matrix liquid crystal device will be briefly described with reference to FIG.
[0003]
The active matrix liquid crystal device includes a liquid crystal pixel LC (including a pixel electrode and a liquid crystal layer) arranged in a matrix, a thin film transistor T (hereinafter referred to as a pixel transistor T) for driving each liquid crystal pixel LC, It consists of row-like gate lines Y and column-like source lines X. One end of each liquid crystal pixel LC is connected to each pixel transistor T, and the other end is all connected to the same electrode (hereinafter referred to as a counter electrode), and is supplied with a specific counter electrode potential VC. One end of each source line X is provided with thin film transistors TS1, TS2,..., TSn (hereinafter referred to as sample hold transistors TS) for sampling the image signal VSIG, and is supplied with the image signal VSIG. At the other end of each source line X, thin film transistors TP1, TP2,..., TPn (hereinafter referred to as preliminary write transistors TP) for performing preliminary writing are provided and supplied with preliminary writing voltage VP. A shift register 6 is connected to each gate line Y, and each gate line is line-sequentially scanned to select one row of liquid crystal pixels LC for each horizontal scanning period. The shift register 7 is connected to the sample hold transistor TS, and the image signal VSIG is written in a dot sequential manner to the selected one row of liquid crystal pixels LC within one horizontal scanning period.
[0004]
Next, a driving method of the active matrix liquid crystal device shown in FIG. 5 will be briefly described with reference to FIG.
[0005]
The writing of the image signal VSIG to each liquid crystal pixel LC is generally performed by alternately writing positive and negative polarities with respect to the counter electrode potential VC every one vertical scanning period. In FIG. On the other hand, the state written on the positive electrode side is shown. The shift register 6 sequentially transfers a row start signal DY in synchronization with the row clock signal CLY, outputs a row selection signal to each gate line Y, and controls opening / closing of the pixel transistors T for one row every horizontal scanning period. Do. FIG. 6 shows a state where Yi−1, Yi, Yi + 1, which are arbitrary rows, are sequentially selected. Within one horizontal scanning period when the row line is selected, the shift register 7 sequentially transfers the column start signal DX in synchronization with the column clock signal CLX, and sequentially outputs the column selection signal to each sample and hold transistor TS. The open / close control of the sample hold transistor TS is performed, and the image signal VSIG is sequentially written in the liquid crystal pixels LC of the selected row line. Specifically, the sample hold transistor TS that has received the column selection signal transmits the image signal VSIG to the source line X, and is connected to the intersection of the source line X and the selected gate line Y. Through T, the image signal VSIG is written into the liquid crystal pixel LC. FIG. 6 shows a state where the liquid crystal pixels LCi1, LCi2, and LCi3 are sequentially selected by the row selection signals S1, S2, and S3. At this time, in order to make up for the insufficient writing of the image signal VSIG to the liquid crystal pixel LC, preliminary writing for writing a predetermined potential to the liquid crystal pixels LC for one row prior to the writing of the image signal VSIG at the beginning of one horizontal scanning period. It is operating. Specifically, as shown in FIG. 6, the preliminary write signal SP becomes high level at the beginning of one horizontal scanning period and all the preliminary write transistors TP are turned on, and the preliminary write voltage VP is supplied to the source line X through the transistor TP. The preliminary write voltage VP is written to the liquid crystal pixels LC for one row selected at this time. FIG. 6 shows a state in which the preliminary write voltage VP is given the same level as the counter electrode potential VC.
[0006]
[Problems to be solved by the invention]
As the definition of the active matrix device has been increased, the writing time to each pixel has not been sufficient, and there has been a problem that insufficient writing occurs in the preliminary writing operation performed within the conventional horizontal blanking period.
[0007]
Further, when the writing of the image signal to a certain arbitrary liquid crystal pixel LCij is finished, the sample hold transistor is not turned off instantaneously but gradually turned off with time. At this time, since a new image signal is written to the next liquid crystal pixel LCij + 1, the potential of the next source line Xj + 1 may vary greatly. For example, as shown in FIG. 6, immediately after the start of the selected period P2 of the sample and hold transistor TSi2, the potential VLCi2 of the liquid crystal pixel LCi2 and the potential Vx2 of the source line X2 are suddenly changed from the pre-write voltage to the voltage of the image signal. It will change. This potential variation is transmitted to the liquid crystal pixel LCi1 due to capacitive coupling between the source line X2 and the liquid crystal pixel LCi1, and affects the potential VLCi1 of the liquid crystal pixel LCi1. Similarly, the potential fluctuation of the source line X3 affects the potential VLCi2 of the liquid crystal pixel LCi2. As described above, since the potential of the adjacent source line may fluctuate greatly in a state where it is not sufficiently turned off, this potential fluctuation affects the potential of the liquid crystal pixel which should have been written. There was a problem that display unevenness occurred.
[0008]
[Means for Solving the Problems]
The liquid crystal device according to the invention, a plurality of row lines and a plurality of column lines intersecting with each other, provided in correspondence with intersections between the row lines and said column lines, the active matrix including a plurality of pixels having a switching element Type liquid crystal display device, row selection means for sequentially selecting the row lines, delay means for delaying an image signal for a predetermined time and generating a delayed image signal, and the image signal and the delayed image signal according to a column clock signal and a column control means for have a switching means for supplying sequentially to said column line is switched bets, said delay means includes a capacitor for holding the image signal, first supplying the image signal to said capacitor A transistor, and a second transistor that outputs the image signal held in the capacitor as the delayed image signal. The period during which each of the first and second transistors is on is one clock of the column clock signal, and the period during which the first transistor is on and the second transistor are on. The period is shifted by one clock of the column clock signal .
[0009]
According to the above configuration, it is possible to take a sufficient writing time for each pixel, and to avoid an insufficient writing. Further, there is almost no potential fluctuation of the adjacent line at the end of writing, and therefore, there is an effect that a good image quality can be obtained without affecting the writing voltage. Furthermore, since a sufficient writing time can be taken, there is an effect that the preliminary writing operation which has been conventionally performed can be eliminated.
[0010]
The liquid crystal device according to the present invention is characterized in that the delay means delays the image signal by one clock of the column clock signal.
[0011]
According to the above configuration, in addition to the effect of avoiding insufficient writing, the effect of obtaining good image quality, the effect of eliminating the preliminary writing operation, the effect can be realized by a simple circuit configuration. .
[0012]
A driving method of a liquid crystal device according to the present invention includes a plurality of pixels having a plurality of row lines and a plurality of column lines intersecting with each other , provided corresponding to the intersection of the row lines and the column lines, and having switching elements. a driving method of an active matrix type liquid crystal display device comprising the sequentially selects a row line, an image signal a predetermined time is delayed by holding capacitor to generate a delayed image signal, the row line is selected comprises sequentially supplies steps in accordance with the image signal and the column clock signal to the delayed video signal to one end of the liquid crystal of the pixels are connected to row lines selected for each one horizontal scanning period in which the, the delayed video signal When generating, the period of supplying the image signal to the capacitor and the image signal held in the second capacitor are used as the delayed image signal. Each of the input periods is one clock of the column clock signal, and a period during which the image signal is supplied to the capacitor and a period during which the image signal held in the first capacitor is output as the delayed image signal. The column clock signal is shifted by one clock .
[0013]
According to the above driving method, it is possible to take a sufficient writing time for each pixel and to avoid an insufficient writing. Further, there is almost no potential fluctuation of the adjacent line at the end of writing, and therefore, there is an effect that a good image quality can be obtained without affecting the writing voltage. Furthermore, since a sufficient writing time can be taken, there is an effect that the preliminary writing operation which has been conventionally performed can be eliminated.
[0014]
The driving method of the liquid crystal device according to the present invention is characterized in that the delayed image signal delays the image signal by one clock of the column clock signal.
[0015]
According to the above driving method, in addition to the effect of avoiding insufficient writing, the effect of obtaining good image quality, the effect of eliminating the preliminary writing operation, the effect of realizing the above effect by a simple circuit configuration. Have.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
(Example 1)
FIG. 1 is a diagram showing an embodiment of an active matrix liquid crystal device according to the present invention. This active matrix display device includes matrix-like liquid crystal pixels LC11, LC12 arranged at intersections between row-like gate lines Y1, Y2,..., Ym and column-like source lines X1, X2,. ..., LCmn is provided. In this embodiment, a pixel using liquid crystal is provided as an electro-optical material, but the present invention is not limited to this, and other electro-optical material may be used. Drive thin film transistors T11, T12,..., Tmn (hereinafter referred to as pixel transistors T) are provided corresponding to the individual liquid crystal pixels LC. The gate electrode of the pixel transistor T is connected to the corresponding gate line Y, the source electrode is connected to the corresponding source line X, and the drain electrode is connected to the corresponding liquid crystal pixel LC.
[0018]
A row control unit 1 is provided, and the gate lines Y are sequentially scanned to select one row of liquid crystal pixels LC for each horizontal scanning period. Specifically, the row control unit 1 has a shift register function, sequentially transfers the row start signal DY in synchronization with the row clock signal CLY, and outputs a row selection signal to each gate line Y. As a result, the pixel transistor T is controlled to open and close. In this embodiment, line-sequential scanning for each line is shown as a representative example, but scanning may be performed simultaneously in blocks for each of a plurality of scanning lines, such as every 6 lines (12 lines or 24 lines). Further, a delay means 4 is provided, and the input image signal VSIGO is delayed for a predetermined time to generate a delayed image signal VSIGD. Here, an example of a specific configuration of the delay means 4 is shown in FIG.
[0019]
This delay means is provided with transistors T1 and T2 for writing control, the control signal SG1 and control signal SG2 are input to the gate electrode of the transistor, the source electrode is connected to the image signal VSIGO, and the drain electrode Are connected to capacitors C1 and C2 for temporarily storing image signals, and the other ends of the capacitors C1 and C2 are connected to the ground level. Also, output control transistors T3 and T4 are provided, the source lines of the transistors are connected to capacitors C1 and C2, the gate electrode of the transistor T3 is connected to the control signal SG2, and the gate electrode of the transistor T4 is controlled. The drain electrode is connected to the output terminal VSIGD, connected to the signal SG1.
[0020]
Next, the operation of the delay means shown in FIG. 3 will be described with reference to FIG.
[0021]
The control signal SG1 is a signal in which a high level and a low level are alternately repeated for each clock of the column clock signal CLX. The control signal SG2 is a signal obtained by inverting the high level and the low level of the control signal SG1. The transistors T1, T2, T3, and T4 are turned on when a control signal input to each gate electrode is in a high level state, and transmit the potential input to the source electrode to the drain electrode.
[0022]
Here, as shown in FIG. 4, a period PD1, a period PD2, and a period PD3 are assumed for each clock of the column clock signal CLX. In the period PD1, since the control signal SG1 is at a high level, the transistor T1 is turned on, and the image signal VSIGO at that time is transmitted to the capacitor C1, and the capacitor C1 is charged or discharged to the potential level of the image signal VSIGO. In the period PD2, since the control signal SG1 is at a low level, the transistor T1 is turned off. At this time, the transistor T3 is turned on by the control signal SG2, and the potential level of the image signal in the PD1 period stored in the capacitor C1 is output as the delayed image signal VSIGD through the transistor T3. Further, in the period PD2, the transistor T2 is turned on by the control signal SG2, and the capacitor C2 is charged or discharged to the potential level of the image signal VSIGO. In the period PD3, since the control signal SG2 is at a low level, the transistor T2 is turned off. At this time, the transistor T4 is turned on by the control signal SG1, and the potential level of the image signal in the PD2 period stored in the capacitor C2 is output as the delayed image signal VSIGD through the transistor T4. Further, in the period PD3, the transistor T1 is turned on by the control signal SG1, and the capacitor C1 is charged or discharged to the potential level of the image signal VSIGO.
[0023]
As described above, the delayed image signal VSIGD outputs the image signal VSIGO of the period PD1 in the period PD2, and outputs the image signal VSIGO of the period PD2 in the period PD3. That is, the delay unit 4 outputs the delayed image signal VSIGD that is delayed by one clock of the column clock signal CLX of the image signal VSIGO. In the delay means of this embodiment, the image signal VSIGO is delayed by one clock of the column clock signal CLX, but the present invention is not limited to this, and an arbitrary delay time can be set.
[0024]
Further, a column control means 2 comprising a shift register 3 and a switching means 5 is provided, and the image signal VSIGO and the delayed image signal VSIGD are appropriately switched within one horizontal scanning period and sequentially sampled and selected on each source line X. In addition, image signals are written dot-sequentially to the liquid crystal pixels LC for one row. Specifically, at one end of each source line X, thin film transistors TSO1, TSO2,..., TSOn (hereinafter referred to as sample hold transistors TSO) for sampling image signals and thin film transistors TSD1, TSD2,. , A sample hold transistor TSD), and is supplied with an image signal. The source electrodes of the sample and hold transistors TSO1, TSO2, ..., TSOn are connected to the image signal VSIGO, and the source electrodes of the sample and hold transistors TSD1, TSD2, ..., TSDn are connected to the delayed image signal VSIGD. The shift register 3 sequentially transfers the column start signal DX in synchronization with a predetermined column clock signal CLX, and outputs column selection signals S1, S2,..., Sn, Sn + 1. The column selection signals S1, S2,..., Sn control the opening and closing of the sample and hold transistors TSO1, TSO2,..., TSOn, respectively, and the column selection signals S2, S3, ..., Sn, Sn + 1 are the sample hold transistors TSD1, TSD2, respectively. ,..., TSDn−1, TSDn are controlled to open and close, and image signals are sampled and held on the individual source lines X.
[0025]
Next, a driving method of the active matrix display device shown in FIG. 1 will be described in detail with reference to FIG.
[0026]
When the row start signal DY is input, the row control unit 1 sequentially outputs row selection signals having a pulse width of 1H in synchronization with the row clock signal CLY. FIG. 2 shows a state in which Yi-1, Yi, Yi + 1, which are arbitrary rows, are sequentially output. When the row selection signal is output and each pixel transistor T in the row direction is turned on, the column control means 2 sequentially writes the image signal VSIGO and the delayed image signal VSIGD into the liquid crystal pixel LC through the pixel transistor T. When the column start signal DX is input, the shift register 3 of the column controller 2 sequentially outputs column selection signals S1, S2,..., Sn, Sn + 1 in synchronization with the column clock signal CLX. When the column selection signal S is at a high level, the corresponding sample hold transistor is turned on, the image signal is supplied to the corresponding source line X, and further written into the liquid crystal pixel LC through the pixel transistor T. FIG. 2 shows a state where Xj−1 and Xj, which are arbitrary columns, are sequentially selected by the column selection signals Sj−1, Sj, and Sj + 1. Here, the periods in which the column selection signals Sj−1, Sj, and Sj + 1 are output are defined as a period Pj−1, a period Pj, and a period Pj + 1, respectively. FIG. 2 shows the potential fluctuations of the liquid crystal pixel LCij-1 and the liquid crystal pixel LCij (VLCIj-1, VLCij) and the potential fluctuations of the image signal VSIGO and the delayed image signal VSIGD from the period Pj-1 to the period Pj + 1. . In the period Pj-1, the sample hold transistor TSOj-1 is selected by the column selection signal Sj-1, and the image signal VSIGO is written into the liquid crystal pixel LCij-1. In the period Pj, the sample hold transistor TSOj is selected by the column selection signal Sj, the image signal VSIGO is written to the liquid crystal pixel LCij, the sample hold transistor TSDj-1 is selected by the column selection signal Sj, and the delayed image signal VSIGD is the liquid crystal. It is written in the pixel LCij-1. In the period Pj + 1, the sample hold transistor TSDj is selected by the column selection signal Sj + 1, and the delayed image signal VSIGD is written into the liquid crystal pixel LCij. In other words, the image signal VSIGO is written to the liquid crystal pixel LCij through the sample and hold transistor TSOj in the period Pj, and the delayed image signal VSIGD is written through the sample and hold transistor TSDj in the period Pj + 1. Further, immediately after the start of the period Pj, the potential fluctuation of the source line Xj is transmitted to the liquid crystal pixel LCij-1 by capacitive coupling between the source line Xj and the liquid crystal pixel LCij-1, but at this time, the liquid crystal pixel LCij− Since 1 is in the middle of writing of the image signal VSIGD, it does not affect the voltage finally written. Further, since the image signal to the adjacent source line Xj and the liquid crystal pixel LCij is almost finished at the end of the writing of the liquid crystal pixel LCij-1, there is no large potential fluctuation at this time, and the liquid crystal pixel LCij is capacitively coupled. There is no effect on the write voltage of -1.
[Brief description of the drawings]
1 is a configuration diagram of the present invention shown in Embodiment 1. FIG.
2 is a diagram for explaining the overall operation of the configuration shown in FIG. 1; FIG.
FIG. 3 is a specific configuration diagram of a delay unit 4;
4 is a diagram for explaining the overall operation of the configuration shown in FIG. 3; FIG.
FIG. 5 is a configuration diagram of a conventional apparatus.
6 is a diagram for explaining the overall operation of the configuration shown in FIG. 5;
[Explanation of symbols]
1. 1. Row control means 2. Column control means 3. Shift register 4. Delay means 5. Switching means 6. Shift register Shift register

Claims (2)

A plurality of row lines and a plurality of column lines intersecting with each other, provided in correspondence with intersections between the row lines and said column lines, the active matrix liquid crystal display device and a plurality of pixels having a switching element,
Row selection means for sequentially selecting the row lines;
Delay means for delaying an image signal for a predetermined time and generating a delayed image signal;
In accordance with a column clock signal, and a column control means for chromatic switching means for supplying the image signal and sequentially the column line switching between the delayed image signal,
Equipped with a,
The delay means is
A capacitor for holding the image signal;
A first transistor for supplying the image signal to the capacitor;
A second transistor that outputs the image signal held in the capacitor as the delayed image signal;
Comprising
The period during which each of the first and second transistors is turned on is one clock of the column clock signal,
The liquid crystal device , wherein a period in which the first transistor is on and a period in which the second transistor is on are shifted by one clock of the column clock signal . An active matrix type liquid crystal display device having a plurality of row lines and a plurality of column lines intersecting each other, and provided corresponding to the intersection of the row lines and the column lines, and comprising a plurality of pixels having switching elements A driving method comprising :
The row lines are sequentially selected, and a delayed image signal is generated by delaying a predetermined time by holding the image signal with a capacitor, and connected to the selected row line every horizontal scanning period in which the row line is selected. said image signal and said delayed video signal to the liquid crystal of one of the pixels to be include sequentially supplying step in accordance with a column clock signal,
When generating the delayed image signal,
The period for supplying the image signal to the capacitor and the period for outputting the image signal held in the second capacitor as the delayed image signal are each one clock of the column clock signal,
A liquid crystal device characterized in that a period during which the image signal is supplied to the capacitor and a period during which the image signal held in the first capacitor is output as the delayed image signal are shifted by one clock of the column clock signal Driving method.

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