JP3663848B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device suitable for application to, for example, an active matrix display device.
[0002]
[Prior art]
Conventionally, in a polysilicon TFT liquid crystal panel in which a high-speed video signal is supplied to a liquid crystal display unit with a low-speed multi-channel on each signal line by a horizontal driver using an analog demultiplexer, there is an output deviation between the channels by the horizontal driver. In some cases, light and dark streaks occur on the display screen in the liquid crystal display unit, resulting in a reduction in display quality. Therefore, in order to correct the deviation, a method has been used in which each output is compared with a reference voltage to form a feedback loop to cancel the deviation. As a conventional example described above, Japanese Patent Laid-Open No. 5-265405 discloses a correction signal by measuring a difference between an output from a multiplexer unit that multiplexes a video output from a data driver and a reference voltage by an offset amount measuring unit. A first liquid crystal display device that feeds back to a data driver in response to a vertical synchronization signal is disclosed.
[0003]
It is also known to precharge the pixel capacitors in the currently selected row to a predetermined voltage level before the video signal is supplied to the signal line. In this way, the pixel capacitor can be further charged and discharged to the level of the subsequent video signal in a time shorter than the time required when the pixel capacitor was charged only with the video signal. In Japanese Patent Laid-Open No. 8-76083, in order to prevent insufficient voltage charging in a circuit for driving a liquid crystal display unit, a driving voltage for the liquid crystal display unit is allowed to reach a target level during a precharge period. However, there is no means for canceling the offset of the data driver. Japanese Patent Laid-Open No. 7-104703 discloses a third liquid crystal display device in which the precharge timing is set to the head portion of the video signal. Similarly, there is a means for canceling the offset of the data driver. There wasn't.
[0004]
[Problems to be solved by the invention]
However, in the conventional first liquid crystal display device, it is necessary to provide a means for making a timing for comparing each output of the data driver and the reference voltage outside the driver, so that it is optimal for each of various input signals. There is an inconvenience that it is necessary to set the timing for canceling the offset. Also, since one vertical synchronization period is short, the output offset voltage for all data drivers cannot be calculated in one vertical synchronization period, and only one driver data collection is performed in one vertical synchronization period. Since the timing for canceling is controlled, there is a disadvantage that the video signal changes when it interferes with an effective pixel.
[0005]
In view of the above, the present invention has an object to provide a liquid crystal display device in which offset cancellation is performed at a timing at which an input video signal does not change with a simple configuration.
[0006]
[Means for Solving the Problems]
The display device according to the present invention performs vertical scanning by scanning each gate line sequentially and selecting one row of pixels every horizontal period, and sequentially sampling the video signal to each signal line within one horizontal period. The horizontal scanning is performed by writing the video signal in a dot sequential manner to the pixels for one row selected in advance, and prior to the sequential sampling of the video signal for each signal line other than the video signal period based on the horizontal synchronization signal. In a display device having precharge means for supplying a predetermined precharge signal to each signal line, the offset of the potential of the video signal between the signal lines generated when the video signal is written to each signal line in the horizontal scanning is corrected. the timing of comprising an offset correction signal generating means for a period of occurrence of the pre-charge signal, the offset correction signal Serial is to occur based on the pre-charge signal.
[0007]
Such a liquid crystal display device operates as follows.
Since the precharge signal and the horizontal clock signal are supplied to the offset cancel signal generating means, the offset cancel signal is output in the offset cancel signal generating means. The offset cancel signal has a signal waveform in which the rising point is delayed by a predetermined delay amount from the precharge signal and the falling point is preceded by a predetermined delay amount from the precharge signal. As a result, it is possible to generate an offset cancel signal that is synchronized with the horizontal clock signal that is active during the period in which the precharge signal is active.
[0008]
By supplying this offset cancel signal to the offset cancel means, the offset cancel means compares the output of each signal line Y with the reference voltage within the active period of the offset cancel signal within the precharge period, Each channel of the input video signal supplied to each signal line is detected by detecting the difference between the output of the signal line Y and the reference voltage and supplying correction data having a sampling width corresponding to this difference to the horizontal scanning driver. Cancel the offset that is the potential deviation between.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The liquid crystal display device according to the present embodiment automatically generates an offset cancel signal for controlling the timing for correcting the output deviation within the precharge period in the driver of the multi-channel output liquid crystal display device. .
[0010]
The configuration of the liquid crystal display device of the present embodiment will be described with reference to FIG. The liquid crystal display device according to the present embodiment includes, as liquid crystal display units, row-like gate lines X, column-like signal lines Y, matrix-like liquid crystal pixels LC arranged at respective intersections thereof, and individual liquid crystals. A driving thin film transistor Tr is provided corresponding to the pixel LC. In this embodiment, the pixel LC using liquid crystal is used. However, the present invention is not limited to this, and another electro-optical material may be used. The source electrode of the thin film transistor Tr is connected to the corresponding signal line Y, and the drain electrode is connected to the corresponding liquid crystal pixel LC.
[0011]
Further, the liquid crystal display device of the present embodiment is provided with a V driver 1, and the V driver 1 scans each gate line X line-sequentially to select a row of liquid crystal pixels LC every horizontal period. A scanning circuit is configured. Specifically, the V driver 1 sequentially transfers the vertical start signal VST in synchronization with the vertical clock signal VCK and outputs selection pulses φV1, φV2,..., ΦVM to each gate line X. As a result, the thin film transistor Tr is controlled to open and close.
[0012]
Further, the liquid crystal display device according to the present embodiment is provided with an H driver 2, and the H driver 2 sequentially samples the input video signal VSIG on each signal line Y within one horizontal period and is selected for one row. A horizontal scanning circuit for writing the input video signal VSIG in a dot sequential manner to the liquid crystal pixels LC is configured. Specifically, horizontal switching elements HSW1, HSW2, HSW3, HSW4,..., HSWN are provided at one end of each signal line Y, and each switching element is connected to the video line 3, and the input video signal VSIG. Is supplied. On the other hand, the H driver 2 sequentially transfers the horizontal start signal HST in synchronization with a predetermined horizontal clock signal HCK, and outputs sampling pulses φH1, φH2, φH3, φH4,. These sampling pulses control the opening and closing of the corresponding horizontal switching elements, and sample and hold the input video signal VSIG on each signal line Y.
[0013]
Further, the liquid crystal display device according to the present embodiment is provided with the precharge means 4, and the precharge means 4 is synchronized with the horizontal synchronization signal prior to the sequential sampling of the input video signal VSIG for each signal line Y. A predetermined precharge signal VPS is sequentially supplied to each signal line Y to suppress charging / discharging of each signal line Y due to sampling. Thereby, the potential fluctuation of the video line 3 is reduced. Specifically, the precharge unit 4 includes switching elements PSW1, PSW2, PSW3, PSW4,..., PSWN connected to the end portions of the individual signal lines Y, and a P driver 5, and is switched. Control means for supplying the precharge signal VPS to each signal line Y by sequentially controlling the opening and closing of the elements PSW is configured.
[0014]
Specifically, in the precharge means 4, the P driver 5 has the same configuration as the H driver 2, and sequentially transfers the horizontal start signal PST in synchronization with the horizontal clock PCK which is the same as the horizontal clock signal HCK. Sampling pulses φP1, φP2, φP3, φP4,..., ΦPN are output. The horizontal switching elements are sequentially controlled to open and close by these precharge sampling pulses. In the present embodiment, the configuration in which the sampling of the precharge signal VPS is controlled by the P driver 5 provided separately from the H driver 2 is shown. However, the H driver 2 and the P driver 5 are configured integrally. Also good. In this case, the horizontal switches HSW and PSW are both provided on one end side of the signal line Y.
[0015]
The horizontal scanning circuits such as the H driver 2 and the P driver 5 have a shift register as a basic configuration, and are formed by integrating thin film transistors or single crystal silicon transistors. The switching element PSW for sampling the input video signal VSIG is composed of NMOS, PMOS, CMOS, or the like.
[0016]
In addition, the liquid crystal display device according to the present embodiment supplies a feedback signal to the H driver 2 so as to cancel the offset, which is a potential deviation between the channels of the input video signal VSIG supplied to each signal line, thereby sampling pulses. An offset cancel circuit 9 that cancels the offset by correcting the sampling width of φH1, φH2, φH3, φH4,. Specifically, the offset cancel circuit 9 compares the output of each signal line Y with the reference voltage, detects the difference between the output of each signal line Y and the reference voltage, and the sampling width corresponding to this difference. The correction data is supplied to the H driver 2.
[0017]
In addition, the liquid crystal display device according to the present embodiment particularly includes an offset cancel signal generating circuit 6 that generates an offset cancel signal OCS for setting timing for performing an offset cancel operation in the offset cancel circuit 9. . Specifically, the offset cancel signal generation circuit 6 uses the precharge signal VPS synchronized with the horizontal synchronization signal and the horizontal clock signal PCK to perform an offset cancel operation within a period during which the precharge signal VPS is generated. An offset cancel signal OCS for setting is automatically generated. In the present embodiment, the offset cancel signal generation circuit 6 calculates a logical sum of a delay circuit 7 that delays the precharge signal VPS by a horizontal clock signal PCK for a predetermined period, and an output of the delay circuit 7 and the precharge signal VPS. And an AND circuit 8. By doing so, the offset cancel signal OCS for setting the timing for performing the offset cancel operation in the offset cancel circuit 9 within the precharge period in which the precharge signal VPS is active (high level in this embodiment) is generated. Can be generated. Note that the offset cancel signal generation circuit 6 is not limited to this, and may be realized by other configurations.
[0018]
The operation of the liquid crystal display device of the present embodiment configured as described above will be described below. As described above, the P driver 5 sequentially transfers the start signal PST in synchronization with the horizontal clock signal PCK, and outputs precharge sampling pulses φP1, φP2, φP3, φP4,. Similarly, the H driver 2 sequentially transfers the horizontal start signal HST in synchronization with the horizontal clock signal HCK, and outputs sampling pulses φH1, φH2, φH3, φH4,..., ΦHN. In the present embodiment, the horizontal clock signal PCK and the horizontal clock signal HCK use the same horizontal clock signal. On the other hand, the horizontal start signal is output during the non-video signal period in synchronism with the horizontal synchronization signal for PST, and HST is output at the head of the video signal. As described above, the precharge sampling pulse is output in a non-video signal period in which no effective pixel of the input video signal VSIG exists.
[0019]
An input video signal VSIG is supplied to the H driver 2 side, and a precharge signal VPS synchronized with the horizontal synchronizing signal is supplied to the P driver 5 side. As shown in FIG. 2A, the input video signal VSIG has a waveform that repeats a non-video signal period and a video signal period and changes between a white level and a black level in the video signal period. On the other hand, as shown in FIG. 2B, the precharge signal VPS is active (high level in the present embodiment) in the non-video signal period in synchronization with the horizontal synchronization signal and has a constant gray level between the white level and the black level. The waveform becomes a potential and becomes negative during the video signal period. Alternatively, the precharge signal VPS may be a waveform having the same polarity and the same waveform as the input video signal VSIG. When the same waveform is used for the input video signal VSIG and the precharge signal VPS, the charge / discharge amount of the signal line during sampling is extremely reduced, and the potential fluctuation of the video line 3 can be suppressed very effectively.
[0020]
Here, in particular, since the precharge signal VPS and the horizontal clock signal PCK are supplied to the offset cancel signal generating circuit 6, the precharge signal VPS is supplied by the delay circuit 7 by a predetermined delay amount in the offset cancel signal generating circuit 6. After being delayed, the delay signal and the precharge signal VPS are supplied to the AND circuit 8 and ORed to output an offset cancel signal OCS. As shown in FIG. 2C, the offset cancel signal OCS has a signal waveform whose rising time is delayed by a predetermined delay amount from the precharge signal VPS and whose falling time precedes the precharge signal VPS by a predetermined delay amount.
[0021]
Thereby, it is possible to generate the offset cancel signal OCS synchronized with the horizontal clock signal PCK that becomes active within the period in which the precharge signal VPS is active (high level in the present embodiment). In this way, an offset that automatically controls the offset cancellation timing with a simple configuration using the existing precharge signal VPS and the horizontal clock signal PCK without providing a signal generation circuit outside the driver. A cancel signal OCS can be generated. As described above, since a precharge operation is necessary in a liquid crystal display device, a precharge period is set in advance in a non-video signal period before a video signal display period. Since the offset cancel signal OCS is generated using the precharge period, it is not necessary to set a new timing for the operation of generating the offset cancel signal OCS.
[0022]
By supplying the offset cancel signal OCS to the offset cancel circuit 9, the offset cancel circuit 9 compares the output of each signal line Y with the reference voltage within the active period of the offset cancel signal OCS within the precharge period. Then, the difference between the output of each signal line Y and the reference voltage is detected, and the correction data of the sampling width corresponding to this difference is supplied to the H driver 2, whereby the input video signal supplied to each signal line. The offset which is a potential deviation between each channel of VSIG is canceled.
[0023]
In this way, the cancel operation of the offset of the potential of the input video signal VSIG due to the variation in the sampling width of the H driver 2 is performed only within the precharge period which is the non-video signal period. Since the offset cancel operation can be performed during the period, the input video signal VSIG can be prevented from changing.
[0024]
【The invention's effect】
The liquid crystal display device according to the present invention performs vertical scanning by scanning each gate line sequentially and selecting one row of pixels every horizontal period, and sequentially sampling video signals to each signal line within one horizontal period. Then, horizontal scanning is performed by writing video signals to the selected pixels for one row in a dot-sequential manner, and a predetermined precharge signal is applied to each signal line prior to sequential sampling of the video signals for each signal line. In the liquid crystal display device having the precharge means for supplying, the timing for correcting the offset of the potential of the video signal between the signal lines generated when the video signal is written to each signal line in the horizontal scanning is generated. Since the offset correction signal generating means is provided within the period to be used, the liquid crystal display device requires a precharge operation. The precharge period is set in advance in the non-video signal period before the video signal display period, and the offset cancel signal is generated using the precharge period. There is no need to set a new timing for the operation to generate the offset, and the offset can be canceled with a simple configuration. In addition, since the operation of canceling the offset of the potential of the input video signal due to the variation in the sampling width of the driver that performs horizontal scanning only during the precharge period, which is the non-video signal period, is performed, the non-video signal period in which no effective pixel exists. Since the offset cancel operation can be executed, there is an effect that the input video signal can be prevented from changing.
[0025]
In the liquid crystal display device of the present invention, since the offset correction signal is generated based on the precharge signal in the above description, the signal generating circuit is not provided outside the driver for performing horizontal scanning. The offset can be canceled by generating an offset cancel signal for controlling the offset cancel timing automatically with a simple configuration using the precharge signal and the horizontal clock signal.
[0026]
In the liquid crystal display device of the present invention, since the precharge signal is generated outside the video signal period based on the horizontal synchronization signal, the offset cancel timing is controlled without interfering with the effective pixels. An offset cancel signal is generated to cancel the offset.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention.
2A and 2B are signal waveform diagrams of the liquid crystal display device according to the embodiment of the present invention, in which FIG. 2A is an input video signal VSIG, FIG. 2B is a precharge signal VPS, and FIG. 2C is an offset cancel signal OCS; .
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... V driver, 2 ... H driver, 3 ... Bide line, 4 ... Precharge means, 5 ... P driver, 6 ... Offset cancellation signal generation circuit, 7 ... Delay circuit, 8 ... AND circuit, 9 ... Offset cancellation circuit, VSIG ... input video signal, VPS ... precharge signal, OCS ... offset cancel signal,

Claims (3)

Each gate line is scanned sequentially to select one row of pixels for each horizontal period, and vertical scanning is performed, and a video signal is sequentially sampled to each signal line within one horizontal period to select one row. In addition to performing horizontal scanning by writing video signals to the pixels dot-sequentially, a predetermined precharge signal is applied to each signal line prior to sequential sampling of the video signals other than the video signal period based on the horizontal synchronization signal. In a display device having precharge means for supplying a signal line,
Offset correction signal generating means for correcting the timing of correcting the offset of the potential of the video signal between the signal lines generated when writing the video signal to each signal line in the horizontal scanning is within the period during which the precharge signal is generated. the offset correction signal display apparatus characterized by generating on the basis of the precharge signal. The display device according to claim 1,
The offset correction signal generating means includes a delay circuit that delays the precharge signal by the horizontal synchronization signal, and a circuit that calculates a logical product of the output of the delay circuit and the precharge signal. A display device. The display device according to claim 1,
The display apparatus, wherein the offset correction signal has a signal waveform whose rising edge is delayed from the precharge signal and whose falling edge precedes the precharge signal.

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