JP3663351B2 - Interface device between self-synchronous system and clock synchronous system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interface device and relates to an interface device used for data transfer between a self-synchronizing system and a clock synchronizing system.
[0002]
[Prior art]
In recent years, various approaches to research and practical use of self-synchronous systems have been made. For example, “Self-synchronous transfer control circuit (Japanese Patent Laid-Open No. 6-83731)” (Reference 1) describes an example of a data transmission apparatus employing an asynchronous handshake method. The data transmission apparatus described in Document 1 will be described with reference to FIG.
[0003]
The data transmission device 900 shown in FIG. 16 includes self-synchronous transfer control circuits 1a to 1c, pipeline registers 2a to 2c as data holding circuits, and a logic circuit 3a that performs an operation on the output of the data holding circuit. 3b.
[0004]
The self-synchronous transfer control circuits 1a to 1c receive an input terminal CI that receives a transfer request signal from the previous stage, an output terminal CO that outputs a transfer request signal to the subsequent stage, and a transfer permission signal that indicates transfer permission or transfer prohibition in the subsequent stage. It has an input terminal RI, an output terminal RO that outputs a transfer permission signal to the previous stage, and a control signal output terminal CP that controls the pipeline registers 2a to 2c.
[0005]
The operation of the data transmission apparatus 900 will be described with reference to FIG. In FIG. 17, when the transfer request signal at the input terminal CI is “0”, the data transfer request is received from the previous stage (the previous stage is performing data transfer), and the transfer request signal at the output terminal CO is “0” indicates a state in which a data transfer request is made in the subsequent stage.
[0006]
Conversely, when the transfer request signal at the terminal CI is “1”, the data transfer request has not been received from the previous stage (the previous stage has not made a data transfer request), and the transfer request signal at the terminal CO is “1”. "Indicates a state where no data transfer request is made in the subsequent stage.
[0007]
When the transfer permission signal at the input terminal RI is “0”, the subsequent stage is in a transfer prohibited state, and when the transfer permission signal at the output terminal RO is “0”, the data transfer from the previous stage is prohibited. It is shown that.
[0008]
Conversely, when the transfer permission signal at the terminal RI is “1”, the subsequent stage is in a transfer permission state, and when the transfer permission signal at the terminal RO is “1”, the data transfer from the previous stage is permitted. It shows that there is.
[0009]
When the transfer request signal input to the input terminal CI of a certain self-synchronous transfer control circuit changes from “1” to “0”, that is, when data transfer is requested and data is transferred from the previous stage, the output terminal RO Is changed from “1” to “0”, and further data transfer from the previous stage is prohibited.
[0010]
When the transfer is completed, the transfer request signal input to the input terminal CI changes from “0” to “1”, no data transfer request is made from the previous stage, and data is transferred from the previous stage to the self-synchronous transfer control circuit. You will be informed that your set has ended.
[0011]
Along with this, the transfer permission signal output from the output terminal RO changes from “0” to “1” to notify the previous stage that the next transfer permission state is set. Then, after the transfer request signal input to the input terminal CI becomes “1” and the data transfer request from the previous stage is not performed, the corresponding pipeline register according to the control signal output from the output terminal CP. The data is output from, and the operation is performed by the corresponding logic circuit.
[0012]
Next, the transfer request signal output from the output terminal CO changes from “1” to “0”, and a data transfer request is made in the subsequent stage. When data is transferred to the subsequent stage, the transfer permission signal input to the input terminal RI changes from “1” to “0”, and it is notified that the subsequent stage is in a transfer prohibited state. In response to this, the control signal output to the output terminal CP is set to “0”, the control of the pipeline register is stopped, and then the transfer request signal output from the output terminal CO is changed from “0” to “1”. It changes, and it will be in the state which does not perform a data transfer request | requirement with respect to a subsequent stage. When the data is stored in the pipeline register at the subsequent stage and further output to the next logic circuit, the transfer permission signal input to the input terminal RI changes from “0” to “1”, and the transfer permission is performed at the subsequent stage. It becomes a state. By repeating this cycle, the next data is transferred and processing such as calculation is performed, and data transfer is performed by the self-synchronous system.
[0013]
The system realized by using the above self-synchronous data transmission device 900 is suitable for the development of a large scale integrated circuit (LSI) because there is no problem with clock distribution unlike the clock synchronous system. . In addition, since the circuit operates only in a portion where data exists, there is an advantage that unnecessary power consumption does not occur.
[0014]
However, at present, the clock synchronous system is dominant, and in a system that realizes any application, a design that ignores the clock synchronous system is unrealistic.
[0015]
Therefore, the presence of an interface device between the self-synchronization system and the clock synchronization system is indispensable for using the self-synchronization system having several advantages.
[0016]
One example of a conventional interface device between a self-synchronizing system and a clock synchronizing system is disclosed in Japanese Patent Laid-Open No. 7-249001 (Reference 2). An interface device 901 described in Document 2 will be described with reference to FIGS.
[0017]
The interface device 901 shown in FIG. 18 is arranged between the clock synchronization system side 902 and the self-synchronization system side 903. The interface device 901 includes a circuit 904 for transferring data from the clock synchronization system side 902 to the self synchronization system side 903, and a circuit 905 for transferring data from the self synchronization system side 903 to the clock synchronization system side 902. .
[0018]
The interface device 901 is provided with terminals DSO, CLOCK, and DSI that exchange signals with the data output unit DSO, the clock output unit CLOCK, and the data input unit DSI on the clock synchronization system side 902.
[0019]
The interface device 901 further includes a data input unit DASI, a transfer request signal input unit CI, a transfer permission signal output unit RO, a data output unit DASO, a transfer request signal output unit CO, and a transfer permission signal input in the self-synchronous system side 903. Terminals DASI, CI, RO, DASO, CO, RI for exchanging signals with the unit RI are provided.
[0020]
When the clock signal changes, the transfer request signal input to the transfer request signal input unit CI on the self-synchronization system side 903 changes, and the data from the data output unit DSO on the clock synchronization system side 902 becomes the data on the self-synchronization system side 903. Input to the input unit DASI.
[0021]
When the clock signal changes after the transfer permission signal of the transfer permission signal output unit RO on the self-synchronous system side 903 changes, the transfer request signal input to the transfer request signal input unit CI on the self-synchronous system side 903 changes. Return to the initial state. Data from the data output unit DSO on the clock synchronization system side 902 is input to the data input unit DASI on the self-synchronization system side 903, and the transfer permission signal output from the transfer permission signal output unit RO on the self-synchronization system side 903 is in the initial state. Return to.
[0022]
On the other hand, when the transfer request signal output from the transfer request signal output unit CO on the self-synchronous system side 903 changes, the data output from the data output unit DASO on the self-synchronous system side 903 becomes the data input on the clock synchronous system side 902. To the part DSI. When the clock signal changes, the transfer permission signal output to the transfer permission signal input unit RI on the self-synchronous system side 903 changes. When the transfer request signal output to the transfer request signal output unit CO on the self-synchronous system side 903 changes, the data output from the data output unit DASO on the self-synchronous system side 903 changes to the data input unit DSI on the clock synchronous system side 902. Entered. When the clock signal changes, the transfer permission signal input to the transfer permission signal input unit RI changes, data input from the self-synchronization system side 903 to the clock synchronization system side 902, and from the clock synchronization system side 902 to the self-synchronization system side 903. The cycle of data input to is repeated.
[0023]
19 shows an example of a circuit 904 that realizes data transfer from the clock synchronization system side 902 to the self-synchronization system side 903, and FIG. 20 realizes data transfer from the self-synchronization system side 903 to the clock synchronization system side 902. An example of the circuit 905 is shown.
[0024]
19 to 20, DETFF (Double-Edge-Triggered Flip-Flop) operates on both rising and falling of the clock signal, and SETFF (Single-Edge-Triggered Flip-Flop) is on the clock synchronization system side 902. Operates at the rising or falling edge of the clock signal.
[0025]
In FIG. 19, if both the transfer permission signal RI and the transfer request signal CO are “0”, the DETFF 81 holds the data so far. When the clock signal CLOCK on the clock synchronization system side 902 becomes “1”, the SETFF 82 sets the transfer request output unit CO to “1”, thereby causing the DETFF 81 to set the data input unit DASI to the “1” level. If the clock signal CLOCK becomes “1” while the transfer permission signal RI is “1”, the SETFF 82 sets the transfer request signal to “0”. As a result, the DETFF 81 sets the data input unit DASI to “0”, and the DETFF 81 again inputs data to the self-synchronous system side 903.
[0026]
In FIG. 20, when both the transfer permission signal and the transfer request signal are “0”, the DETFF 83 holds the data so far. In this state, when the transfer request signal on the self-synchronous system side 903 becomes "1", the DETFF 83 inputs data to the clock synchronization system side 902, and when the clock signal CLOCK becomes "1", the SETFF 84 sets the transfer permission signal as " 1 ”. When the clock signal CLOCK becomes “1” in a state where the transfer permission signal becomes “1”, the SETFF 84 sets the transfer permission signal to “1”, and the DETFF 83 inputs data to the clock synchronization system side 902 again. In this way, by using the circuits 904 and 905 of FIGS. 19 to 20, an interface device between the self-synchronizing system side and the clock synchronizing system side having a relatively small circuit scale can be realized.
[0027]
[Problems to be solved by the invention]
However, the conventional example shown in FIGS. 18 to 20 has the following problems in data transfer from the clock synchronization system side to the self-synchronization system side. That is, valid data is not necessarily output on the clock synchronization system side because the clock is operating. This is because valid data is output from the clock synchronization system side after some delay after the input data to the clock synchronization system side is input. Before valid data is output, the output on the clock synchronization system side is usually in an initial state or fixed to a desired value by a system designer on the clock synchronization system side.
[0028]
However, it is necessary to operate the clock in order to operate the clock synchronization system itself even during a period before valid data is output. Therefore, the interface device between the self-synchronous system side and the clock synchronous system side of the conventional example clearly lacks a function for setting a valid period for transferring data from the clock synchronous system side to the self-synchronous system side.
[0029]
On the other hand, there are the following problems in data transfer from the self-synchronous system side to the clock synchronous system side. That is, the data output from the self-synchronous system side is not necessarily output at regular intervals in time as in the clock synchronous system side. Because of the self-synchronization, it is natural that the timing of the output pulse varies. When the output interval fluctuates in time, data transfer is performed in synchronization with the clock in the interface device between the self-synchronization system and the clock synchronization system of the conventional example. There is a high possibility of end.
[0030]
The following problems can also be considered. For example, assuming another case where a Y / C separation LSI is constructed while processing a video signal in a self-synchronous system, another problem will be described. In this case, a composite signal of TV is input from the clock synchronization system side to the self-synchronization system side, and the composite signal is processed by the self-synchronization system side and separated into a Y signal (luminance signal) and a C signal (color signal) and clocked. Output to the synchronization system. The Y signal and C signal must be output at the same timing for the same pixel.
[0031]
This is because if one pixel is shifted, the Y signal and C signal of different pixels are carried. Since the Y signal and the C signal are finally calculated independently of each other, when processed in the self-synchronous system, the Y signal and the C signal are output to the same pixel at the same timing. It cannot be guaranteed at all.
[0032]
Therefore, the present invention has been made to solve such a problem, and the main object of the present invention is to provide an interface device that can reliably realize optimum data transfer between the clock synchronization system and the self-synchronization system. It is to provide.
[0033]
[Means for Solving the Problems]
An interface device according to an aspect of the present invention includes a data input unit to which data is provided at least from the clock synchronization system side, and a synchronization system clock signal input unit to which a clock signal is provided from the clock synchronization system side, and a self-synchronization system A clock synchronization system having a transfer request signal output unit for outputting a transfer request signal to the side and a data output unit for outputting data to the self-synchronous system side, and an interface device between the self-synchronous system and requesting transfer of the clock signal Outputs data as a signal and outputs the data input to the data input section from the data output section in synchronization with the clock signal The clock signal is output to the transfer request signal output unit by controlling the signal indicating the valid period of the data output received from the clock synchronization system. It is characterized by doing.
[0034]
An interface device according to a further aspect of the present invention includes at least a data output unit for outputting data to the clock synchronization system side, and a synchronization system clock signal input unit to which a clock signal is applied from the clock synchronization system side, Transfer request signal input unit that receives a transfer request signal from the synchronous system side, transfer permission signal output unit that outputs a transfer permission signal to the self-synchronous system side, and data input that receives data from the self-synchronous system side An interface device between a clock synchronization system and a self-synchronization system, which generates a transfer permission signal based on a transfer request signal and absorbs a time output interval of data input to the data input unit Output from the data output section In addition, the storage memory for storing the data input to the data input unit in the input order, the number set in the data storage capacity of the storage memory is counted, the predetermined number is counted, and the flag is set. Counting means, and when the counting means counts a predetermined number, the input clock signal is output as a transfer permission signal It is characterized by doing.
[0037]
More preferably, the interface device is provided with a plurality of data output units, a transfer request signal input unit, a transfer permission signal output unit, and a data input unit for the self-synchronization system. Each of the input units counts the number set in the storage capacity of the storage memory and sets the flag.
[0038]
An interface device according to a further aspect of the present invention is an interface device that outputs data of a self-synchronous system in synchronization with a clock signal of the clock synchronous system, and absorbs an output time interval of data received from the self-synchronous system to obtain data. An absorption circuit for outputting, and detecting that a predetermined amount of data is held in the absorption circuit and permitting data transfer to the clock synchronization system; if the predetermined amount of data is not held, the clock synchronization system And a transfer control circuit that prohibits data transfer to the self-synchronous system and requests data transfer.
[0039]
Preferably, the transfer control circuit outputs a signal for identifying whether the output data is valid or invalid simultaneously with the data output.
[0040]
Preferably, the absorption circuit outputs the data generation number together with the data output. Preferably, the absorption circuit includes a first self-synchronous transfer control circuit connected in series and having a function of performing a transfer operation at any desired timing, and a plurality of second self-synchronous transfer control circuits, including. Each of the first self-synchronous transfer control circuit and the plurality of second self-synchronous transfer control circuits includes a transfer permission output terminal and a transfer permission input terminal. The first self-synchronous transfer control circuit operates in synchronization with a clock signal in a predetermined mode, and the transfer control circuit observes signals at transfer permission output terminals in the plurality of second self-synchronous transfer control circuits. Then, the output is controlled by determining.
[0041]
Preferably, the transfer control circuit includes a circuit that switches between data transfer in synchronization with a clock signal of the clock synchronization system and data transfer by handshaking with the self-synchronization system.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
An interface device according to an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same symbols or symbols, and the description thereof is omitted. In the following, “0” represents the L level and “1” represents the H level.
[0043]
[First Embodiment]
FIG. 1 is a block diagram showing an overall configuration of an interface device 10 connected between a self-synchronizing system and a clock synchronizing system according to the first embodiment.
[0044]
1, the interface device 10 has a data transfer unit 11 having a function of transferring data from the clock synchronization system side 1000 to the self-synchronization system side 2000, and a function of transferring data from the self-synchronization system side 2000 to the clock synchronization system side 1000. And a data transfer unit 12.
[0045]
The data transfer unit 11 is provided with a data input terminal DSO, a start signal input terminal GO, setting terminals IMOD, PCK, ICKE, PCE, a data output terminal DASI, and a transfer request output terminal CI.
[0046]
The data input terminal DSO, the start signal input terminal GO, and the setting terminals IMOD, PCK, ICKE, and PCE receive signals output from the clock synchronization system side 1000, and the signals at the data output terminal DASI and the transfer request output terminal CI are self-synchronized. The data is output to the system side 2000.
[0047]
The data transfer unit 12 is provided with a data output terminal DSI, a transfer request output terminal CO ′, a setting terminal OSS, a data input terminal DASO, a transfer request input terminal CO, and a transfer permission output terminal RI. .
[0048]
The data output terminal DSI and the transfer request output terminal CO ′ are output to the clock synchronization system side 1000. The signal OSS output from the clock synchronization system side 1000 is given to the setting terminal OSS.
[0049]
The data input terminal DASO and the transfer request input terminal CO receive a signal output from the self-synchronous system side 2000, and a signal at the transfer permission output terminal RI is output to the self-synchronous system side 2000.
[0050]
The data transfer units 11 and 12 are further provided with a clock input terminal CLOCK and a reset input terminal MRB.
[0051]
A specific configuration of the data transfer unit 11 illustrated in FIG. 1 will be described with reference to FIG. As shown in FIG. 2, the data transfer unit 11 includes inverters 21 and 28, an AND gate 22, D-type flip-flops 25 to 27, EXOR gates 23 and 24, and a NAND gate 29.
[0052]
In FIG. 2, a data output start signal GO from the clock synchronization system side 1000 is input to the terminal GO. The start signal GO is given to one input terminal of the AND gate 22.
[0053]
The terminal IMOD receives a signal IMOD that enables the data input function when it is at the “L” level. Signal IMOD is inverted by inverter 21 and applied to the other input terminal of AND gate 22. The output of the AND gate 22 is input to the data input terminal D of the D type flip-flop 25. The output Q from the data output terminal Q of the D type flip-flop 25 is given to one input terminal of the NAND gate 29.
[0054]
A clock signal CLOCK is given to the terminal CLOCK from the clock synchronization system side 1000. The terminal PCK is supplied with a setting signal PCK for setting whether the D-type flip-flops 25, 26 and 27 are operated at the rising edge or falling edge of the clock signal.
[0055]
The EXOR gate 23 is supplied with a clock signal CLOCK and a setting signal PCK. The output of the EXOR gate 23 is supplied to the clock input terminal CK of the D type flip-flops 25, 26 and 27 and the inverter 28. The output of the inverter 28 is given to one input terminal of the NAND gate 29.
[0056]
A reset signal MRB is input to the terminal MRB. Reset signal MRB is applied to reset input terminal R of D-type flip-flops 25, 26 and 27. A control signal ICKE for controlling whether to enable or disable the clock input is input to the terminal ICKE. The terminal PCE is supplied with a signal PCE for setting the positive / negative of the control signal ICKE.
[0057]
The EXOR gate 24 is supplied with a control signal ICKE and a signal PCE. The output of the EXOR gate 24 is given to the data input terminal D of the D type flip-flop 26. The output Q from the data output terminal Q of the D type flip-flop 26 is given to one input terminal of the NAND gate 29.
[0058]
A signal DSO is given to the terminal DSO from the clock synchronization system side 1000. Signal DSO is applied to data input terminal D of D-type flip-flop 27. The output Q from the data output terminal Q of the D type flip-flop 27 is given to the terminal DSAI.
[0059]
The operation of the data transfer unit 11 shown in FIG. 2 will be described with reference to FIG. Referring to FIG. 3, it is assumed that signal IMOD input to terminal IMOD is set to “0” and setting signal PCK input to terminal PCK is set to “0”.
[0060]
Since the setting signal PCK is “0”, the EXOR gate 23 outputs the same signal as the clock signal CLOCK. Therefore, D-type flip-flops 25, 26 and 27 are set at the rising edge of clock signal CLOCK and output signal Q from data output terminal Q.
[0061]
Further, it is assumed that the control signal ICKE input to the terminal ICKE is fixed to “1” and the signal PCE input to the terminal PCE is fixed to “0”.
[0062]
The reset signal MRB input to the terminal MRB once becomes “0” at the start of operation, and after the D-type flip-flops 25, 26 and 27 are reset, changes to “1” and a sufficient time has elapsed. Suppose you are.
[0063]
Since the control signal ICKE of the terminal ICKE is fixed to “1” and the signal PCE of the terminal PCE is fixed to “0”, the output of the D-type flip-flop 26 is fixed to “1” by the rise of the clock signal CLOCK. .
[0064]
Further, since the setting signal PCK is fixed to “0”, a signal obtained by inverting the clock signal CLOCK is output from the inverter 28. Further, since the signal IMOD at the terminal IMOD is fixed to “0”, the AND gate 22 outputs a signal in phase with the start signal GO.
[0065]
It is assumed that the start signal GO rises from “0” to “1” at time t1. After the start signal GO rises from “0” to “1”, the D type flip-flop 25 latches the output of the AND gate 22 in synchronization with the rise of the input clock signal, and from the data output terminal Q Output.
[0066]
Therefore, the NAND gate 29 outputs the same signal waveform as that of the clock signal CLOCK after the rise of the first clock signal after the start signal GO rises to “1”. The output CI of the NAND gate 29 is input to the self-synchronous system side 2000 as the transfer request signal CI.
[0067]
The D-type flip-flop 27 takes in the signal DSO from the data output unit DSO on the clock synchronization system side 1000 in synchronization with the rise of the clock signal CLOCK and transfers it to the data input unit DASI on the self-synchronization system side 2000.
[0068]
In the interface apparatus shown in FIG. 2, a transfer request signal to the self-synchronous system side 2000 is generated based on the clock signal CLOCK on the clock synchronous system side 1000. For this reason, the self-synchronous system side 2000 is requested to transfer data at regular intervals regardless of the transfer permission signal of the self-synchronous system side 2000. At this time, as long as the data input rate on the clock synchronization system side 1000 does not exceed the data transfer rate on the self-synchronization system side 2000, data is transferred from the clock synchronization system side 1000 to the self-synchronization system side 2000 without any problem.
[0069]
Next, a specific configuration of the data transfer unit 12 illustrated in FIG. 1 will be described with reference to FIG. As shown in FIG. 4, the data transfer unit 12 includes an inverter 41, an OR gate 45, an AND gate 46, a functional circuit block 42, a D-type flip-flop 44, and a FIFO memory 43.
[0070]
In FIG. 4, the data transfer unit 12 includes a terminal OSS, a terminal MRB, a terminal CLOCK, a terminal CO, a terminal RI, a terminal DASO, a terminal CO ′, and a terminal DSI.
[0071]
A setting signal OSS output from the clock synchronization system side 1000 is applied to the terminal OSS. The setting signal OSS is inverted by the inverter 41.
[0072]
A clock signal CLOCK output from the clock synchronization system side 1000 is supplied to the terminal CLOCK.
[0073]
A transfer request signal output from the self-synchronous system side 2000 is applied to the terminal CO.
[0074]
A transfer request signal received at the terminal CO is input to the terminal CI of the functional circuit block 42. When the falling edge of the transfer request signal is input four times, the functional circuit block 42 raises the output QOE from “0” to “1”.
[0075]
The output QOE of the functional circuit block 42 is input to the data input terminal D of the D type flip-flop 44. The clock signal CLOCK is supplied to the clock input terminal CK of the D type flip-flop 44.
[0076]
The OR gate 45 receives the output of the inverter 41 and the output Q of the D-type flip-flop 44, and outputs a signal RIE.
[0077]
The AND gate 46 receives the signal RIE and the clock signal CLOCK and outputs a signal RI ′.
[0078]
The reset signal MRB is applied to the reset input terminal MRB of the functional circuit block 42 and the reset input terminal R of the D-type flip-flop 44.
[0079]
The FIFO memory 43 has a capacity for storing eight data, and includes a write clock input terminal WCK, an input ready signal output terminal IR, an output ready signal output terminal OR, and a read clock input terminal RCK. , A data input terminal DI and a data output terminal DO.
[0080]
A transfer request signal received at terminal CO is applied to write clock input terminal WCK, and data received at terminal DASO is input to data input terminal DI. A transfer permission signal is output from the input ready signal output terminal IR to the terminal RI, a transfer request signal is output from the output ready signal output terminal OR to the terminal CO ′, and the output RI of the AND gate 46 is supplied to the read clock input terminal RCK. 'Is provided, and data is output from the data output terminal DO to the terminal DSI.
[0081]
The FIFO memory 43 includes a write pointer and a read pointer. The write pointer increases at the rise of the transfer request signal received at the terminal WCK, and the read pointer increases at the rise of the signal RI ′ received at the terminal RCK.
[0082]
If the input ready signal output terminal IR is “1”, writing to the FIFO memory 43 is possible, and if the output ready signal output terminal OR is “1”, the data output terminal DO It shows that effective data reading is possible.
[0083]
Data at the data input terminal DI is taken into the FIFO memory 43 at the fall of the transfer request signal. When the data is taken in, the input ready signal output terminal IR changes to “0”.
[0084]
Next, when the transfer request signal rises, the value of the write pointer is increased by “1” to indicate the next word position. Then, the input ready signal output terminal IR returns to “1” to indicate that new data can be written.
[0085]
When data is stored in the entire storage area of the FIFO memory 43 and no more data can be written, the input ready signal output terminal IR remains in the “0” state even if the transfer request signal rises. . That is, the transfer request signal is ignored.
[0086]
At this time, the next data cannot be written until the data is read and the input ready signal output terminal IR returns to “1”.
[0087]
The data in the FIFO memory 43 is output from the data output terminal DO at the falling edge of the signal RI ′. When data is read, the value of the read pointer is increased by “1” to indicate the next word position. Then, the output ready signal output terminal OR changes to “1”.
[0088]
When there is no data in the FIFO memory 43 and data cannot be output from the data output terminal DO, the output ready signal output terminal OR holds “0” and the data in the FIFO memory 43 is not stored. Indicates that does not exist. That is, the input to the terminal RCK is ignored. In this case, the valid data read last is still output from the data output terminal DO.
[0089]
When data exists in the FIFO memory 43, the output ready signal output terminal rises to “1” at the rise of the signal RI ′. The output from the data output terminal DO is the data in the previous state until the signal RI ′ falls.
[0090]
As described above, the FIFO memory 43 has a depth of 8 data, and the functional circuit block 42 counts the fall of four pulses and raises the output to “1”. Here, it is meaningful that the functional circuit block 42 counts the number of pulses that are half the data depth (capacity) of the FIFO memory 43, but the numbers 8 and 4 are provisionally determined here, Can be set to an appropriate value according to the overall system design of the synchronous system and the asynchronous system.
[0091]
A specific operation of the data transfer unit 12 shown in FIG. 4 will be described with reference to FIG. Referring to FIG. 5, setting signal OSS received at terminal OSS is fixed to “1”, and output Q of D-type flip-flop 44 is derived as output RIE of OR gate 45, and is synchronized with clock synchronization system side 1000. It is assumed that data is ready to be transferred.
[0092]
When the setting signal OSS becomes “0”, the RIE of the output of the OR gate 45 is always “1”, so that the output RI ′ of the AND gate 46 is always equal to the clock signal CLOCK. Therefore, if data exists in the FIFO memory 43, the FIFO memory 43 can be used in a state where data is read.
[0093]
FIG. 5 shows a state in which the reset signal is once reset to “0” and then returned to “1”.
[0094]
The functional circuit block 42 raises the output QOE to “1” in response to the transfer request signal received at the terminal CO falling four times. At this time, four data are already written in the FIFO memory 43.
[0095]
When the output QOE of the functional circuit block 42 becomes “1”, the output Q of the D-type flip-flop 44 becomes “1” at the next rise of the clock signal. Therefore, the output signal RIE of the OR gate 45 rises from “0” to “1” (time t1). The AND gate 46 outputs a signal RI ′ that is the result of the logical product of the signal RIE and the clock signal CLOCK.
[0096]
Data is output from the terminal DO of the FIFO memory 43 to the DSI terminal at the falling edge of the signal RI ′. Then, after half of the data depth that can be stored in the FIFO memory 43 is written, the FIFO memory 43 starts a read operation. As a result, data is present in the FIFO memory 43 and the data is not full.
[0097]
Reading of data from the FIFO memory 43, that is, output from the terminal DSI to the clock synchronous system side 1000 satisfies the following relationship. That is, after the signal RIE rises, new data is output to the terminal DSI every time the signal RI ′ falls (time t2, t3, t4,...). Output data is held between the falling edges of the signal RI ′.
[0098]
Further, the read pointer of the FIFO memory 43 is incremented by one by the fall of the signal RI ′. Thereafter, the signal CO ′ is raised to “1”. The signal CO ′ is a signal for informing the clock synchronization system 1000 that the next data can be read.
[0099]
As long as data exists in the FIFO memory 43, that is, data transferred asynchronously from the self-synchronous system side 2000 is absorbed by the FIFO memory 43, the clock synchronization system side 1000 is synchronized with the clock signal CLOCK as described later. Thus, valid data can be transferred continuously.
[0100]
Therefore, the terminal DSI for transferring data to the clock synchronization system side 1000 always outputs data at the falling edge of the signal RI ′.
[0101]
As shown in FIG. 5, since the signal RI ′ is generated from the clock signal CLOCK on the clock synchronization system side 1000, data output from the self-synchronization system side 2000 asynchronously with the clock synchronization system side 1000 (at the terminal DASO). Data) is transferred in synchronization with the fall of the clock signal CLOCK on the clock synchronization system side 1000.
[0102]
In FIG. 5, each of the signals at the terminals CO and DASO is shown to be synchronized with the clock signal CLOCK, but this is only shown for ease of explanation, and is actually synchronized. Not done.
[0103]
Data input to the terminal DASO from the self-synchronous system side 2000 is transferred along with a transfer request signal input to the terminal CO.
[0104]
The FIFO memory 43 is surely written with the data at the terminal DASO at the time when the transfer request signal received at the terminal CO falls. Meanwhile, “0” is output to the terminal RI, and the next writing is prohibited. Thereafter, with the rise of the transfer request signal, the write pointer of the FIFO memory 43 is incremented by one, the terminal RI becomes “1”, and the next writing is enabled. According to these operations, since the FIFO memory 43 is not full, data is always written to the FIFO memory 43 reliably.
[0105]
A further configuration example of the data transfer unit that transfers data from the self-synchronous system side 2000 to the clock synchronous system side 1000 will be described with reference to FIG. The data transfer unit illustrated in FIG. 6 is referred to as a data transfer unit 13.
[0106]
The data transfer unit 13 illustrated in FIG. 6 is configured in the same manner as the data transfer unit 12 illustrated in FIG. 4 except for the following points. That is, the data transfer unit 12 shown in FIG. 4 has one system of data output from the self-synchronous system side 2000 to the clock synchronization system side 1000, whereas the data transfer unit 13 shown in FIG. It is that.
[0107]
Further, in the data transfer unit 13 shown in FIG. 6, two functional circuit blocks related to data transfer from the self-synchronous system side 2000 to the clock synchronous system side 1000 are provided in order to correspond to two systems of outputs. The same method can be used to extend the data transfer unit so that it can easily handle a plurality of outputs.
[0108]
As shown in FIG. 6, the data transfer unit 13 includes an inverter 41, OR gates 45 and 47, an AND gate 46, functional circuit blocks 42 and 48, a D type flip-flop 44, and FIFO memories 43 and 49.
[0109]
A functional circuit block 48 similar to the functional circuit block 42 shown in FIG. 4 is newly provided.
[0110]
A reset signal MRB is input to the reset input terminals MRB of the functional circuit blocks 42 and 48.
[0111]
The first transfer request signal COA is input from the terminal COA to the terminal CI of the functional circuit block 42, and the second transfer request signal COB is input from the terminal COB to the terminal CI of the functional circuit block 48.
[0112]
The output QOE of each of the functional circuit blocks 42 and 48 is supplied to the OR gate 47. The output of the OR gate 47 is given to the data input terminal D of the D type flip-flop 44.
[0113]
A FIFO memory 49 similar to the FIFO memory 43 shown in FIG. 4 is provided. The output signal RI ′ of the AND gate 46 is supplied to each terminal RCK of the FOFO memories 43 and 49.
[0114]
A first transfer request signal is supplied from the terminal COA to the write clock input terminal WCK of the FIFO memory 43, and a second transfer request signal is supplied from the terminal COB to the write clock input terminal WCK of the FIFO memory 49.
[0115]
A first transfer permission signal RIA is output from the input ready signal output terminal IR of the FIFO memory 43, and a second transfer permission signal RIB is output from the input ready signal output terminal IR of the FIFO memory 49.
[0116]
The first data DASOA is inputted from the terminal DASOA to the data input terminal DI of the FIFO memory 43, and the second data DASOB is inputted from the terminal DASOB to the data input terminal DI of the FIFO memory 49.
[0117]
A signal is output from the output ready signal output terminal OR of the FIFO memory 43 to the terminal COA ′, and a signal is output from the output ready signal output terminal OR of the FIFO memory 49 to the terminal COB ′.
[0118]
The first data is output from the data output terminal DO of the FIFO memory 43 to the terminal DSIA, and the second data is output from the data output terminal DO of the FIFO memory 49 to the terminal DSIB.
[0119]
The terminals DSIA, DSIB, COA ′, and COB ′ are connected to the clock synchronization system side, and the terminals DASOA, DASOB, COA, COB, RIA, and RIB are connected to the self-synchronization system side.
[0120]
The operation of each unit of the data transfer unit 13 illustrated in FIG. 6 will be described with reference to FIG. The functional circuit block 42 raises the output QOE to “1” when the first transfer request signal COA falls four times, and the functional circuit block 48 outputs the output QOE when the second transfer request signal COB falls four times. Is raised to "1".
[0121]
The output QOE of the functional circuit blocks 42 and 48 is given to the data input terminal D of the D type flip-flop 44 through the OR gate 47. Therefore, when the output QOE of any one of the functional circuit blocks 42 and 48 becomes “1”, the output Q of the D-type flip-flop 44 rises from “0” to “1” at the next rise of the clock signal CLOCK. In response to this, the output signal RIE of the OR gate 45 changes from “0” to “1” (time t1). The AND gate 46 outputs a signal RI ′ that is the result of the logical product of the signal RIE and the clock signal CLOCK.
[0122]
Data is output from the terminals DO of the FIFO memories 43 and 49 at the falling edge of the signal RI ′ in the same manner as the operation of the FIFO memory 43 described with reference to FIG. After one half of the data depth (capacity) is written in one of the FIFO memories 43 and 49, the read operation is started. At that time, data is written to the other half of the FIFO memories 43 and 49 to nearly half the data depth. Therefore, data is output for each clock in synchronization with the clock signal CLOCK. The phase between the two data outputs in the FIFO memories 43 and 49 is also synchronized.
[0123]
As described above, after half of the data depth is written in either FIFO memory 43 or 49, signal RIE becomes "1", and FIFO memories 43 and 49 start the read operation. .
[0124]
As a result, the FIFO memories 43 and 49 are in a state where data exists and the data is not full.
[0125]
Data reading from the FIFO memories 43 and 49, that is, data output from the terminals DSIA and DSIB to the clock synchronous system side satisfies the following relationship. That is, after the signal RIE rises, new data is output to the terminals DSIA and DSIB every time the signal RI ′ falls (time t2, t3, t4,...). Output data is held between the falling edges of the signal RI ′.
[0126]
Further, the read pointers of the FIFO memories 43 and 49 are each incremented by one at the fall of the signal RI ′. Thereafter, the signal COA ′ and the signal COB ′ are raised to “1”. The signals COA ′ and COB ′ are signals that inform the clock synchronization system that the next data can be read out.
[0127]
As long as data exists in the FIFO memories 43 and 49, that is, data transferred asynchronously from the self-synchronous system side is absorbed by the FIFO memories 43 and 49, the clock signal CLOCK is transmitted to the clock synchronous system side as described later. It is possible to transfer valid data continuously in synchronization with.
[0128]
Therefore, data is always output at the falling edge of the RI ′ signal to terminals DSIA and DSIB for outputting data to the clock synchronization system side.
[0129]
As shown in FIG. 7, since the signal RI ′ is generated from the clock signal CLOCK of the clock synchronous system, data output from the self-synchronous system side asynchronously with the clock synchronous system side (input to the terminals DASOA and DASOB) Data) is transferred in synchronization with the falling of the clock signal CLOCK on the clock synchronization system side.
[0130]
In FIG. 7, the signals at the terminals COA, COB, DASOA, and DASOB are shown to be synchronized with the clock signal CLOCK. However, this is shown for ease of explanation, and actually Are not synchronized.
[0131]
Data input to the terminal DASOA from the self-synchronous system side is accompanied by a transfer request signal input to the terminal COA, and data input from the self-synchronous system side to the terminal DASOB is accompanied by a transfer request signal input to the terminal COB. Each will be forwarded.
[0132]
Note that the data in the terminals DASOA and DASOB is reliably written into the FIFO memories 43 and 49 at the time when the transfer request signal falls. Meanwhile, “0” is output to the terminals RIA and RIB, and the next writing is prohibited. Thereafter, with the rise of the transfer request signal, the write pointer of the FIFO memory 43 is incremented by 1, and the terminals RIA and RIB are set to “1” to enable the next writing.
[0133]
According to these operations, since the FIFO memories 43 and 49 are not full, data is always written to the FIFO memories 43 and 49 reliably. As a result, the data from the two self-synchronous systems having different phases are transferred into the clock synchronous system in synchronization with the fall of the clock signal on the clock synchronous system side.
[0134]
As described above, according to the data transfer unit 13, two data are transferred in a state where the phases are aligned such as 1a and 1b, 2a and 2b,... In DSIA and DSIB of FIG.
[0135]
Since the self-synchronizing system transfers data when predetermined data or data pairs are ready, it is not synchronized with the clock signal. Therefore, in the self-synchronizing system, the phases of data of 1a and 1b, 2a and 2b,... Are naturally different.
[0136]
However, by using the data transfer unit 13, it is possible to transfer the two data with the same phase within a range in which the temporal fluctuations of the FIFO memories 43 and 49 can be absorbed.
[0137]
Therefore, this embodiment can be used effectively in Y / C separation processing and the like.
[0138]
[Second Embodiment]
The overall configuration of the interface device 100 according to the second embodiment will be described with reference to FIG. The interface device 100 is provided for transferring data from the self-synchronization system 3000 to the clock synchronization system 4000.
[0139]
Data transfer is performed between the self-synchronous system 3000 and the interface apparatus 100 by adopting an asynchronous handshake method as in the data transmission apparatus 900 shown in FIG. On the other hand, since the interface device 100 and the clock synchronization system 4000 are exchanged asynchronously and synchronously, the data transfer timing becomes difficult. For example, since interface device 100 is asynchronous, there is data to be captured even if clock synchronization system 4000 attempts to input data from data input terminal D at regular intervals at the rising edge of clock signal CLK of clock synchronization system 4000. Is not limited. Therefore, the clock synchronization system 4000 is provided with a valid / invalid flag DVF for identifying whether data in the interface device 100 is valid or invalid.
[0140]
As shown in FIG. 8, the interface apparatus 100 includes a transfer control unit 111 that controls data transfer from the self-synchronization system 3000 to the clock synchronization system 4000 and a FIFO memory 112 that stores data.
[0141]
The interface apparatus 100 further includes a packet format selection signal input terminal PFSL that receives a packet format selection signal PFSL, a transfer request input terminal CI, a transfer permission output terminal RO, a packet data input terminal PI, and a master data that receives a master reset signal MR. It has a set input terminal MR, a transfer request output terminal CO, a transfer permission input terminal RI, and a packet data output terminal PO.
[0142]
Transfer request input terminal CI, transfer permission output terminal RO, and packet data input terminal PI are connected to transfer request output terminal CO, transfer permission input terminal RI, and data output terminal Q of self-synchronization system 3000, respectively.
[0143]
Transfer request output terminal CO, transfer permission input terminal RI, and packet data output terminal PO are connected to valid / invalid flag DVF, clock output terminal CLK, and data input terminal D of clock synchronization system 4000, respectively.
[0144]
The transfer control unit 111 includes a packet format selection signal input terminal PFSL that receives the packet format selection signal PFSL, a transfer request input terminal CI, a transfer permission output terminal RO, and an observation terminal STAT for knowing the state of the FIFO memory 112. A clock output terminal FCK that outputs a clock signal FCK to the FIFO memory 112, a master reset input terminal MR that receives a master reset signal MR, a transfer request output terminal CO, and a transfer permission input terminal RI are provided.
[0145]
The FIFO memory 112 includes a packet format selection signal input terminal PFSL that receives a packet format selection signal PFSL, a transfer request input terminal CI, a transfer permission output terminal RO, a packet data input terminal DI, and a master memory that receives a master reset signal MR. A set input terminal MR, a transfer request output terminal CO, a transfer permission input terminal RI, a status output terminal STAT, a clock input terminal FCK that receives a clock signal FCK, and a packet data output terminal DO are provided.
[0146]
The transfer request output terminal CO and the transfer permission input terminal RI of the transfer control unit 111 are connected to the transfer request output terminal CO and the transfer permission input terminal RI of the interface apparatus 100, respectively.
[0147]
The transfer request input terminal CI, the transfer permission output terminal RO, the observation terminal STAT, and the clock output terminal FCK in the transfer control unit 111 are respectively a transfer request output terminal CO, a transfer permission input terminal RI, a status output terminal STAT, and a FIFO memory 112. Connect to clock input terminal FCK.
[0148]
Transfer request input terminal CI, transfer permission output terminal RO and packet data input terminal DI in FIFO memory 112 are connected to transfer request input terminal CI, transfer permission output terminal RO and packet data input terminal PI of interface device 100, respectively. The packet data output terminal DO in the FIFO memory 112 is connected to the packet data output terminal PO in the interface device 100.
[0149]
A specific configuration of the FIFO memory 112 will be described with reference to FIG. The FIFO memory 112 is a memory that stores data in order to absorb temporal fluctuations in the output interval of the self-synchronous system 3000. Here, it is assumed that the output of the self-synchronization system 3000 is accumulated in the FIFO memory 112 and then the output to the clock synchronization system 4000 is started.
[0150]
In this case, as shown in FIG. 9, the FIFO memory 112 is configured to include five self-synchronous transfer control circuits, five pipeline registers, and a status output terminal STAT including signal output terminals RO1 to RO4. To do.
[0151]
More specifically, the FIFO memory 112 includes self-synchronous transfer control circuits 401 to 405 and pipeline registers 406 to 410 connected in series. Pipeline registers 406 to 410 accumulate five data. Each of the self-synchronous transfer control circuits 401 to 405 controls the data holding operation of the pipeline registers 406 to 410.
[0152]
Each of the signal output terminals RO1, RO2, RO3, and RO4 is connected to a transfer permission output terminal RO in the self-synchronous transfer control circuits 405, 404, 403, and 402 (or in the self-synchronous transfer control circuits 404, 403, 402, and 401). The signal of the transfer permission input terminal RI) is output.
[0153]
A handshake operation is performed between the self-synchronous transfer control circuits 401 to 405. As a result, data is transferred from the pipeline registers 406 to 407, from 407 to 408, from 408 to 409, and from 409 to 410.
[0154]
The self-synchronous transfer control circuit 401 (CSYNC) includes a terminal SYNC, a clock input terminal CLK, a transfer request input terminal CI, a transfer permission output terminal RO, a master reset input terminal MR, a control signal output terminal CP, It includes a transfer permission input terminal RI and a transfer request output terminal CO.
[0155]
The terminal SYNC is supplied with a packet format selection signal PFSL. The clock input terminal CLK, transfer request input terminal CI, and transfer permission output terminal RO in the self-synchronous transfer control circuit 401 are connected to the clock input terminal FCK, transfer request input terminal CI, and transfer permission output terminal RO in the FIFO memory 112, respectively. Is done.
[0156]
Self-synchronous transfer control circuits 402 to 405 include a transfer request input terminal CI, a transfer permission output terminal RO, a master reset input terminal MR, a control signal output terminal CP, a transfer permission input terminal RI, and a transfer request output terminal. Including CO.
[0157]
Each of the transfer request input terminal CI and the transfer permission output terminal RO in the self-synchronous transfer control circuit 40k (k = 2 to 5) is transferred by the self-synchronous transfer control circuit 40j (j = k-1) located in the preceding stage. Connected to the request output terminal CO and the transfer permission input terminal RI. The transfer permission input terminal RI and the transfer request output terminal CO in the self-synchronous transfer control circuit 405 are connected to the transfer permission input terminal RI and the transfer request output terminal CO in the FIFO memory 112, respectively.
[0158]
The control signal output terminals CP in the self-synchronous transfer control circuits 401 to 405 are connected to the control signal input terminals CP of the pipeline registers 406 to 410, respectively.
[0159]
An example of the configuration of the self-synchronous transfer control circuits 402 to 405 will be described with reference to FIG. As shown in FIG. 10, self-synchronous transfer control circuits 402 to 405 include RS flip-flops 1111 and 1112, NAND gate 1140, inverters 1130, 1170, 1175 and 1180, and delay element 1190.
[0160]
RS flip-flop 1111 includes NAND gates 1110 and 1120. When the “L” pulse is applied to the node / S of the RA flip-flop 1111, the RS flip-flop 1111 is set. As a result, the RS flip-flop 1111 stores the pulse of “L” and outputs “H” to the node Q. Further, when an “L” pulse is given to the node / R, the RS flip-flop 1111 is reset. As a result, the RS flip-flop 1111 outputs “L” to the node Q.
[0161]
Note that the node / S in the RS flip-flop 1111 is connected to the terminal CI, and the node / R is connected to the output node G of the NAND gate 1140. The node Q in the RS flip-flop 1111 is connected to the terminal RO through the inverter 1130.
[0162]
RS flip-flop 1112 includes NADN gates 1150 and 1160. The operation of the RS flip-flop 1112 is the same as that of the RS flip-flop 1111. Note that the node / S in the RS flip-flop 1112 is connected to the terminal RI, and the node / R is connected to the output terminal of the NAND gate 1140.
[0163]
A reset signal input from terminal MR is inverted by inverter 1175 and then supplied to RS flip-flops 1111 and 1112.
[0164]
Regarding the 4-input NAND gate 1140, the first input terminal is the terminal CI, the second input terminal is the node Q of the RS flip-flop 1111, the third input terminal is the terminal RI, and the fourth input terminal is the output of the inverter 1180. Connected with the node.
[0165]
Inverter 1170 inverts the output of RS flip-flop 1112 and outputs control signal CP. Inverter 1180 inverts the output of inverter 1170. Delay element 1190 delays the output signal of inverter 1180 and applies the delayed signal to terminal CO.
[0166]
The self-synchronous transfer control circuit 401 that exchanges signals with the self-synchronous system 3000 has a function that can control the transfer operation at any desired timing. More specifically, the self-synchronous transfer control circuit 401 changes the operation mode according to the level of the packet format selection signal PFSL.
[0167]
An example of the configuration of the self-synchronous transfer control circuit 401 (CSYNC) will be described with reference to FIG. As shown in FIG. 11, the self-synchronous transfer control circuit CSYNC includes a NAND gate 1141 instead of the NAND gate 1140 of the self-synchronous transfer control circuits 402 to 405, and further includes a transfer request control unit 1200.
[0168]
In the 5-input NAND gate 1141, the first input terminal is the terminal CI, the second input terminal is the node Q of the RS flip-flop 1111, the third input terminal is the terminal RI, and the fourth input terminal is the output of the inverter 1180. The output INHB of the transfer request control unit 1200 is given to the fifth input terminal.
[0169]
Transfer request control unit 1200 includes D-type flip-flops 1011 and 1021, inverter 1031, EXOR gate 1041, and NAND gate 1051.
[0170]
The clock input terminal CK of the D-type flip-flop 1021 is connected to the terminal CI via the inverter 1031, the data input terminal D is connected to the data output terminal / Q of the D-type flip-flop 1011, and the data output terminal Q is Connected to the data input terminal D of the D-type flip-flop 1011. The clock input terminal CK of the D type flip-flop 1011 is connected to the terminal CLK.
[0171]
EXOR gate 1041 receives a signal at data output terminal Q of D-type flip-flop 1011 and a signal at data output terminal Q of D-type flip-flop 1021. The NAND gate 1051 receives the signal of the terminal SYNC and the signal of the EXOR gate 1041, and outputs a signal INHB.
[0172]
When the terminal SYNC is “L”, the signal INHB is fixed to “H”. In this case, the self-synchronous transfer control circuit CSYNC operates as a self-synchronous transfer control circuit similar to the conventional one. When the terminal SYNC is “H”, transfer to the subsequent stage of the transfer request signal applied to the terminal CI can be controlled in accordance with the signal level of the terminal CLK.
[0173]
A case where the packet format selection signal PFSL is “1” will be described. In this case, the self-synchronous transfer control circuit 401 is controlled by the clock signal FCK input from the transfer control unit 111 to the clock input terminal CLK.
[0174]
That is, since the self-synchronous transfer control circuit 401 outputs the transfer request output CO and the control signal CP for controlling the pipeline register 406 at the rising edge of the clock signal FCK, the self-synchronous transfer control circuit 401 performs an output operation in synchronization with the clock signal FCK. In this case, the handshake operation in the self-synchronous transfer control circuits 402 to 405 connected to the self-synchronous transfer control circuit 401 is synchronized with the clock signal FCK. Accordingly, when the transfer control unit 111 latches and observes the status signal STAT, the metastaple state can be avoided.
On the other hand, when the packet format selection signal PFSL is “0”, a self-synchronous handshake operation is performed. In this case, the same operation as that of the conventional data transmission apparatus as shown in FIG. 17 is realized.
[0175]
Master reset signal MR is applied to master reset input terminal MR in self-synchronous transfer control circuits 401-405. The self-synchronous transfer control circuits 401 to 405 are initialized by the master reset signal MR.
[0176]
Next, the pipeline registers 406 to 410 will be described. Each of the pipeline registers 406 to 410 includes a data input terminal D, a control signal input terminal CP, and a data output terminal Q.
[0177]
The data input terminal D in the pipeline register 406 is connected to the packet data input terminal DI in the FIFO memory 112, and the data output terminal Q in the pipeline register 410 is connected to the packet data output terminal DO in the FIFO memory 112. The data input terminal D in each of the pipeline registers 407 to 410 is connected to the data output terminal Q of the pipeline registers 406 to 409.
[0178]
The format of packet data input from the packet data input terminal DI and output from the packet data output terminal DO will be described with reference to FIG. As shown in FIG. 12, the packet data includes a generation number (symbol GN # in the figure) and data (symbol DATA in the figure). Here, the generation number represents a number for distinguishing data groups to be processed in parallel.
[0179]
In this way, by outputting the data DATA and the generation number GN # at the same time, the clock synchronization system can output the R signal, the G signal, and the B signal according to the generation number even when three signals such as RGB are output. Each signal can be identified.
[0180]
The operation of the FIFO memory 112 shown in FIG. 9 will be described with reference to FIG. In FIG. 13, CSYNC is a self-synchronous transfer control circuit 401, transfer request input CIs, transfer permission output ROs, and control signal CPs are a transfer request input terminal CI and transfer permission output terminal RO in self-synchronous transfer control circuit 401. And a signal at the control signal output terminal CP.
[0181]
C1, C2, C3, and C4 are self-synchronous transfer control circuits 405, 404, 403, and 402, transfer request input CIk, transfer permission output ROk, and control signal CPk (k = 1 to 4) are self-synchronized. The signals of the transfer request input terminal CI, the transfer permission output terminal RO, and the control signal output terminal CP in the type transfer control circuit Ck are respectively shown. The transfer request output CO1 and the transfer permission input RI1 represent signals of the transfer request output terminal CO and the transfer permission input terminal RI in the self-synchronous transfer control circuit 405, respectively.
[0182]
Assume that the packet format selection signal input terminal PFSL is fixed at “1” and the self-synchronous transfer control circuit 401 is controlled by the clock signal FCK. Further, the master reset input terminal MR once becomes “0” at the start of the operation (after the self-synchronous transfer control circuits 401 to 405 are reset), and then sufficient time has elapsed since the master reset input terminal MR changed to “1”. Suppose you are.
[0183]
The number assigned to the signal waveform at the packet data input terminal DI and the symbol attached to the signal waveform at the packet data output terminal DO are in a correspondence relationship.
[0184]
In the self-synchronous transfer control circuit 401, the control signal CPs and the transfer request output COs (that is, the transfer request input CI4 of the self-synchronous transfer control circuit 402) are output in synchronization with the rise of the clock signal FCK.
[0185]
The transfer permission input RI1 in the self-synchronous transfer control circuit 405, that is, the transfer permission output of the transfer control unit 111 holds “0” (transfer prohibited state) until the FIFO memory 112 stores four pieces of data.
[0186]
As shown in FIG. 13, a case is considered in which after four data are input from the self-synchronizing system 3000 to the FIFO memory 112, the data is continuously input after a while.
[0187]
First, by handshaking between the self-synchronous transfer control circuits, four pieces of data input at appropriate timing are sequentially transferred from the pipeline registers 406 to 407, 408, 409, and 410.
[0188]
Since the transfer permission input RI1 of the self-synchronous transfer control circuit 405 is “0”, data is sequentially accumulated from the pipeline registers 410 to 409, 408, 407, and 406.
[0189]
At the time t1 when four data are accumulated, the transfer permission output received from the transfer control unit 111, that is, the transfer permission input RI1 to the self-synchronous transfer control circuit 405 is changed from “0” to “1”.
[0190]
In response to this, the control signal CP1 and the transfer permission output RO1 in the self-synchronous transfer control circuit 405 change from “0” to “1”. In response, the control output CP2 and the transfer permission output RO2 in the self-synchronous transfer control circuit 404 change from “0” to “1”. In response, the control output CP3 and the transfer permission output RO3 in the self-synchronous transfer control circuit 403 change from “0” to “1”. In response, the control output CP4 and the transfer permission output RO4 in the self-synchronous transfer control circuit 402 change from “0” to “1”. As a result, the four data stored in the FIFO memory 112 are sequentially output.
[0191]
When the data output from the self-synchronous system 3000 is interrupted for a while, the transfer permission input RI1 of the self-synchronous transfer control circuit 405 becomes “0” again, and the FIFO memory 112 enters a state of storing data.
[0192]
After time t2, when data is continuously input from the self-synchronization system 3000, four pieces of data are accumulated in the FIFO memory 112. After the four pieces of data are accumulated (t3), the data are sequentially output to the clock synchronization system 4000 side. The FIFO memory 112 repeats such an operation.
[0193]
Next, a specific configuration example of the transfer control unit 111 that controls data transfer from the self-synchronization system 3000 to the clock synchronization system 4000 will be described with reference to FIG. In the above description, the FIFO memory 112 is set to start the output of four pieces of data. For this reason, the signal input terminals RI1, RI2, RI3, and RI4 are arranged in the transfer control unit 111 as terminals STAT for observing the state of the FIFO memory 112.
[0194]
The signal input terminals RI1, RI2, RI3, and RI4 are respectively connected to the signal output terminals RO1, RO2, RO3, and RO4 in the FIFO memory 112 described above.
[0195]
The packet format selection signal input terminal PFSL in the transfer control unit 111 receives a signal for selecting whether to output data to the clock synchronization system 4000 in synchronization with the clock or to perform a normal handshake operation with the self-synchronization system 3000.
[0196]
When the packet format selection signal PFSL received at the packet format selection signal input terminal PFSL is “0”, the normal handshake operation mode is set. When the packet format selection signal PFSL is “1”, the clock synchronization mode is set.
[0197]
A clock signal CLK output from the clock synchronization system 4000 is supplied to the transfer permission input terminal RI in the transfer control unit 111. A clock signal received at the transfer permission input terminal RI is referred to as a clock signal RI.
[0198]
Transfer control unit 111 includes inverters 201, 207 and 210, NOR gate 202, OR gate 206, D-type flip-flops 204, 205 and 209, AND gates 203 and 208, EXOR gate 211, and multiplexer (MUX) 212.
[0199]
Each of the D type flip-flops 204, 205 and 209 has a clock input terminal, a data input terminal D for receiving data, a data output terminal Q for outputting data, and a reset for receiving a master reset signal MR from the master reset input terminal MR. Input terminal R. The D-type flip-flops 204, 205 and 209 are initialized by the master reset signal MR.
[0200]
The multiplexer 212 outputs the signal received at the input terminal b from the output terminal Y when the signal received at the select signal input terminal S is “1”, and the signal received at the input terminal a when it is “0”. The output terminal Y is connected to the transfer request output terminal CO of the transfer control unit 111. The input terminal a of the multiplexer 212 is connected to the transfer request input terminal CI, and the input terminal b receives the output of the inverter 210 that inverts the output Q of the D-type flip-flop 209.
[0201]
The packet format selection signal PFSL input from the packet format selection signal input terminal PFSL is applied to the select signal input terminal S of the multiplexer 212 and the first input terminal of the EXOR gate 211. The packet format selection signal PFSL is further inverted by the inverter 207 and then applied to the first input terminal of the OR gate 206.
[0202]
The clock signal RI received at the transfer permission input terminal RI is supplied to the D type flip-flops 204 and 205. The D-type flip-flops 204 and 205 are operated at the rising edge of the clock signal RI.
[0203]
The EXOR gate 211 calculates an exclusive OR of the packet format selection signal PFSL and the clock signal RI.
[0204]
Here, if the packet format selection signal PFSL is “1” (clock synchronous mode), a signal obtained by inverting the clock signal RI is output from the EXOR gate 211 (the output of the EXOR gate 211 is denoted as RIx). The clock signal RIx is supplied to the clock input terminal of the D type flip-flop 209, the clock output terminal FCK connected to the FIFO memory 112, and the first input terminal of the AND gate 208.
[0205]
Signals are supplied to the NOR gate 202 from the signal input terminals RI1 to RI4 constituting the observation terminal STAT. Only when four pieces of data are stored in the FIFO memory 112, that is, when the signals of the transfer permission input terminals RI1 to RI4 in the self-synchronous transfer control circuits 401 to 404 of the FIFO memory 112 are all "0", the NOR gate 202 Becomes “1”.
[0206]
The output of the NOR gate 202 is given to the input terminal D of the D type flip-flop 204. An input terminal D of the D type flip-flop 205 is connected to an output node of the AND gate 203. AND gate 203 receives as input the output RIE of OR gate 206 and the output of inverter 201 that receives the signal at signal input terminal RI1 at terminal STAT.
[0207]
The OR gate 206 receives the outputs of the D type flip-flops 204 and 205 and the inverter 207, and outputs a signal RIE.
[0208]
At the rising edge of the clock signal RI, “1” is output from the output terminal Q of the D-type flip-flop 204 and applied to the second input terminal of the OR gate 206. Therefore, when the signals RI1 to RI4 are “0”, the output RIE of the OR gate 206 is “1”, and transfer is possible.
[0209]
The output RIE is supplied to the input terminal D of the D-type flip-flop 209, the first input terminal of the AND gate 203, and the second input terminal of the AND gate 208.
[0210]
When the output RIE of the OR gate 206 is “1”, the output of the EXOR gate 211 is output as it is from the AND gate 208. That is, an inverted signal of the clock signal CLK (RI) is supplied from the transfer permission output terminal RO to the FIFO memory 112. As a result, data output to the clock synchronization system 4000 is started in clock synchronization.
[0211]
When transfer is possible, the signal RIE is latched at the rising edge of the inverted signal of the clock signal CLK (RI), that is, at the falling edge of the clock signal, and the D-type flip-flop 209 always outputs “1”. The output Q of the D type flip-flop 209 is inverted by the inverter 210 and supplied to the multiplexer 212.
[0212]
As a result, when transfer is possible, “0” indicating that the data currently output from the transfer request output terminal CO is valid is continuously output via the multiplexer 212.
[0213]
Data output to the clock synchronization system 4000 is performed when there is no data in the self-synchronous transfer control circuit 405 that is coupled to the clock synchronization system 4000, that is, when all the data once stored in the FIFO memory 112 is output. Is stopped when data is not continuous (data lost).
[0214]
At this time, since the transfer permission input RI1 (output from the self-synchronous transfer control circuit 405 positioned immediately before) received at the signal input terminal RI1 is “1”, the output of the inverter 201 is “0”. Therefore, the output of the AND gate 203 becomes “0”. In the D-type flip-flop 205, the output “0” of the AND gate 203 is latched at the rising edge of the clock signal.
[0215]
At this time, since the NOR gate 202 outputs “0”, all the inputs of the OR gate 206 are “0”. Accordingly, the output RIE of the OR gate 206 is “0”, and the transfer is prohibited. “0” is output again from the transfer permission output terminal RO. Further, since the data latched by the D-type flip-flop 209 is inverted by the inverter 210 and applied to the input terminal b of the multiplexer 212, “1” indicating that the data is invalid is output from the transfer request output terminal CO. .
[0216]
Next, the operation of the transfer control unit 111 shown in FIG. 14 will be described with reference to FIG. Here, it is assumed that the packet format selection signal input terminal PFSL is fixed to “1” and the clock synchronous mode is set. It is assumed that the clock signal CLK from the clock synchronization system 4000 is input to the transfer permission input terminal RI.
[0217]
Furthermore, it is assumed that the master reset input terminal MR once becomes “0” at the start of operation (reset of the D-type flip-flops 204, 205, and 209) and then changes to “1” and a sufficient time has passed.
[0218]
Since the packet format selection signal PFSL is fixed at “1”, a signal obtained by inverting the clock signal CLK received at the transfer permission input terminal RI is output from the clock output terminal FCK. In the multiplexer 212, the signal at the input terminal b is selected regardless of the transfer request input CI input to the input terminal a.
[0219]
The transfer permission output terminal RO maintains the state of “0”. That is, the system is in a transfer prohibited state. Therefore, the FIFO memory 112 cannot output data, and the data is accumulated in the FIFO memory 112.
[0220]
The data accumulation state is observed by inputting the transfer permission outputs RO1 to RO4 of the self-synchronous transfer control circuit in the FIFO memory 112 to the observation terminals STAT (RI1, RI2, RI3 and RI4) of the transfer control unit 111. can do.
[0221]
Currently, the FIFO memory 112 is set to start outputting when four pieces of data are accumulated. When the fourth data reaches the FIFO memory 112 and the transfer permission output RO4 (ie, RI4) of the self-synchronous transfer control circuit 402 changes to “0” (t1), the output of the NOR gate 202 is “ 1 ".
[0222]
Then, at the rising edge (t2) of the clock signal RI, the output RIE of the OR gate 206 changes from “0” to “1” (transferable state).
[0223]
As the output RIE becomes “1”, the clock signal FCK that is an inverted signal of the clock signal RI is output to the transfer permission output terminal RO through the AND gate 208 (t3-t4).
[0224]
Further, “0” indicating that the data is valid is output from the transfer request output terminal CO at the rising edge of the clock signal FCK, that is, the falling edge of the clock signal RI (t3−t5).
[0225]
When the transfer permission output terminal RO becomes “1”, the data stored in the FIFO memory 112 is output in order. When all the data stored in the FIFO memory 112 is output, the signal RIE changes from “1” to “0” at the rising edge (t4) of the clock signal RI. Subsequently, the transfer permission output terminal RO becomes “0” indicating the transfer prohibited state. The transfer request output terminal CO also outputs “1” indicating that the data is invalid at the rising edge of the clock signal FCK (t5).
[0226]
In the interface apparatus according to the first embodiment, even if the interval of data output from the self-synchronous system side fluctuates in time, some data is output so that the data output to the clock synchronous system side does not become intermittent. Is stored in synchronization with the clock signal. However, once the output from the self-synchronous system is interrupted, when the output resumes, the data is not stored in the FIFO memory. It is also conceivable that data is not continuously output (intermittent state). On the other hand, according to the interface device in the second embodiment, even if the data output of the self-synchronization system 3000 is interrupted, if a predetermined number of data is accumulated in the FIFO memory 112, the clock synchronization system 4000 is transferred. Can start to output.
[0227]
In addition, according to the interface device in the second embodiment, since only one FIFO memory is required, an increase in circuit scale can be suppressed.
[0228]
Furthermore, in the second embodiment, a flag (output CO of the transfer control unit 111) indicating whether the data output at the time of data output is valid or invalid is also output at the same time. Therefore, when using a scanner, invalid data is added to both terminals of the data captured by the line sensor, so only valid data is processed using the signal CO when using scanner data. Can be adopted.
[0229]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0230]
【The invention's effect】
As described above, according to the interface device of the present invention, the clock signal given from the clock synchronization system side is output as a transfer request signal to the self-synchronization system side, and the data given from the clock synchronization system side is synchronized with the clock signal. Output to the self-synchronous system side. Therefore, an interface between the clock synchronization system side and the self-synchronization system side can be easily taken.
[0231]
In addition, the interface device according to the present invention absorbs the temporal output interval even if the data output from the self-synchronous system side fluctuates in time, and synchronizes with the clock signal to synchronize with the clock signal. The data can be transferred from the side to the clock synchronous system side.
[0232]
In addition, the interface device according to the present invention accumulates data inputted from the clock synchronization system side in the accumulation memory in the order of input, sets the flag by counting the number set in the data storage capacity of the accumulation memory, A clock signal is output as a transfer permission signal in response to the flag being set. Thereby, the temporal fluctuation of the data output from the self-synchronizing system can be absorbed. By setting the data depth of the storage memory separately, it is possible to set according to the characteristics of the system.
[0233]
Furthermore, when there are a plurality of data outputs from the self-synchronization system to the clock synchronization system, the interface device according to the present invention aligns the phases of the data outputs of the respective systems and synchronizes with each other and outputs the self-synchronization system. Even if the output interval of data fluctuates with time, the output interval can be absorbed and data can be transferred from the self-synchronous system to the synchronous system in synchronization with the clock signal.
[0234]
Further, according to the interface device of the present invention, the time output interval of data from the self-synchronous system is absorbed, and even if the data output from the self-synchronous system is once interrupted and the output is resumed, the self-synchronous system again Can be output in synchronization with the clock signal of the clock synchronization system.
[0235]
Further, the interface device according to the present invention can simultaneously output a flag for identifying whether the output data is valid or invalid at the same time as the clock synchronization data output from the self-synchronization system to the clock synchronization system. It is possible to easily determine whether the received data is valid or invalid.
[0236]
In addition, since the interface device according to the present invention can simultaneously output the generation number of the data simultaneously with the clock synchronization data output from the self-synchronization system to the clock synchronization system, the clock synchronization system receives only one system output. It becomes possible to identify the type of data. Accordingly, it is not necessary to provide a new identification circuit, and the circuit scale can be reduced.
[0237]
Furthermore, the interface device according to the present invention includes a FIFO memory in which a plurality of self-synchronous transfer control circuits are arranged in parallel. Then, a self-synchronous transfer control circuit having a function capable of controlling the transfer operation at any desired timing is arranged in the first stage, and is operated in synchronization with the clock signal. As a result, the self-synchronous transfer control circuit in the FIFO memory can be handshaked in synchronization with the clock signal. In addition, by observing the transfer permission output signal in the plurality of self-synchronous transfer control circuits, it becomes possible to easily control the output of data in the FIFO memory.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of an interface device 10 that connects a self-synchronizing system and a clock synchronizing system according to a first embodiment;
FIG. 2 is a diagram showing a specific configuration of a data transfer unit 11 shown in FIG.
3 is a timing chart for explaining the operation of the data transfer unit 11 shown in FIG. 2;
4 is a diagram showing a specific configuration of a data transfer unit 12 shown in FIG.
5 is a timing chart for explaining the operation of the data transfer unit 12 shown in FIG. 4;
FIG. 6 is a diagram illustrating another configuration example of a data transfer unit that performs data transfer from the self-synchronous system side to the clock synchronous system side.
7 is a timing chart for explaining the operation of the data transfer unit 13 shown in FIG. 6;
FIG. 8 is a block diagram showing an outline of a configuration of an interface apparatus 100 arranged between a self-synchronizing system and a clock synchronizing system according to a second embodiment.
9 is a block diagram showing an example of the configuration of a FIFO memory 112. FIG.
10 is a diagram illustrating an example of the configuration of self-synchronous transfer control circuits 402 to 405 (C4 to C1) illustrated in FIG. 9;
11 is a diagram illustrating an example of a configuration of a self-synchronous transfer control circuit 401 (CSYNC) illustrated in FIG. 9;
FIG. 12 is a diagram for explaining input / output data of the FIFO memory 112;
13 is a timing chart for explaining the operation of the FIFO memory 112 shown in FIG. 9;
14 is a circuit diagram showing a specific configuration example of a transfer control unit 111 shown in FIG. 8. FIG.
15 is a timing chart for explaining the operation of the transfer control unit 111 shown in FIG. 14;
FIG. 16 is a block diagram illustrating an example of a data transmission apparatus 900 employing a conventional asynchronous handshake method in Literature 1.
17 is a timing chart for explaining the operation of the data transmission apparatus 900 shown in FIG.
18 is a diagram showing a configuration of a conventional interface device 901 in Document 2. FIG.
19 is a diagram showing a configuration of a circuit 904 included in the interface device 901 shown in FIG.
20 is a diagram showing a configuration of a circuit 905 included in the interface device 901 shown in FIG.
[Explanation of symbols]
10, 100 interface device, 11, 12, 13 data transfer unit, 21, 28, 41 inverter, 22, 46 AND gate, 23, 24 EXOR gate, 25, 26, 27, 44 D type flip-flop, 29 NAND gate, 42, 48 functional circuit block, 45, 47 OR gate, 43, 49, 112 FIFO memory, 111 transfer control unit, 211 EXOR gate, 212 multiplexer, 401-405 self-synchronous transfer control circuit, 406-410 pipeline register, 3000 self-synchronization system, 4000 clock synchronization system.

Claims (8)

At least a data input unit (DSO) to which data is supplied from the clock synchronous system side and a synchronous system clock signal input unit (CLOCK) to which a clock signal is supplied from the clock synchronous system side, and transferred to the self-synchronous system side A clock synchronization system having a transfer request signal output unit (CI) for outputting a request signal and a data output unit (DASI) for outputting data to the self-synchronous system side, and an interface device between the self-synchronous system,
The clock signal is output as the transfer request signal , and the data input to the data input unit is output from the data output unit in synchronization with the clock signal ,
An interface device between a self-synchronous system and a clock synchronous system , wherein the clock signal is output to the transfer request signal output unit by controlling a signal indicating a valid period of data output received from the clock synchronous system . A self-synchronous system side having at least a data output part (DSI) for outputting data to the clock synchronous system side and a synchronous system clock signal input part (CLOCK) to which a clock signal is given from the clock synchronous system side A transfer request signal input unit (CO) to which a transfer request signal is input, a transfer permission signal output unit (RI) that outputs a transfer permission signal to the self-synchronous system side, and data from the self-synchronous system side An interface device between a clock synchronization system having a data input unit (DASO) and a self-synchronization system,
The transfer permission signal is generated based on the transfer request signal, and the data input to the data input unit is absorbed from the time output interval and output from the data output unit ,
Furthermore, an accumulation memory for accumulating the data input to the data input unit in the order of input,
Counting means for counting the number set in the data storage capacity of the storage memory, counting a predetermined number, and setting a flag,
An interface device between a self-synchronizing system and a clock synchronizing system , wherein the input clock signal is output as the transfer permission signal in response to the flag being set . The data output unit, the transfer request signal input unit, the transfer permission signal output unit, and a plurality of data input units for the self-synchronization system are provided, respectively.
The self-synchronization system and the clock synchronization system according to claim 2 , wherein the transfer request signal input unit sets the flag by counting the number set in the storage capacity of the storage memory. Interface device. An interface device for outputting data of a self-synchronous system in synchronization with a clock signal of a clock synchronous system,
An absorption circuit for absorbing the output time interval of data received from the self-synchronous system and outputting the data;
It is detected that a predetermined amount of data is held in the absorption circuit and data transfer to the clock synchronous system is permitted. If the predetermined amount of data is not held, transfer to the clock synchronous system is performed. And a transfer control circuit for requesting data transfer to the self-synchronous system and an interface device between the self-synchronous system and the clock synchronous system. 5. The interface device between a self-synchronizing system and a clock synchronizing system according to claim 4 , wherein the transfer control circuit outputs a signal for identifying whether the output data is valid or invalid simultaneously with data output. 5. The interface device between a self-synchronization system and a clock synchronization system according to claim 4 , wherein the absorption circuit outputs a generation number of data together with data output. The absorption circuit is
A first self-synchronous transfer control circuit connected in series and having a function of performing a transfer operation at any desired timing; and a plurality of second self-synchronous transfer control circuits;
Each of the first self-synchronous transfer control circuit and the plurality of second self-synchronous transfer control circuits includes a transfer permission output terminal and a transfer permission input terminal;
The first self-synchronous transfer control circuit operates in synchronization with a clock signal in a predetermined mode,
The transfer control circuit includes:
5. The interface device between a self-synchronous system and a clock synchronous system according to claim 4 , wherein output control is performed by observing and determining a signal at a transfer permission output terminal in the plurality of second self-synchronous transfer control circuits. The transfer control circuit includes:
Either by synchronization with data transfer clock signal of the clock synchronization system, the self-synchronization comprising a circuit for switching whether to transfer data handshake with the system, self-synchronizing according to any of claims 4 to 7 Interface device between system and clock synchronization system.

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