JP3659345B2 - Bus system and signal transmission method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bus system including a bus master and a bus slave and a signal transmission method thereof, and more particularly, to a bus system and a signal transmission method thereof in which the degree of freedom of arrangement of the bus master and the bus slave is increased. It is.
[0002]
[Prior art]
FIG. 1 is a conceptual block diagram of a typical conventional bus system. The bus system is fabricated on a single chip. A plurality of bus masters 11 and a plurality of bus slaves 12 are connected to a common bus system 10. In FIG. 1, the numerical values between each bus master 11 and the bus system 10 and between each bus slave 12 and the bus system 10 are used to calculate the distance between each bus master 11 and each bus slave 12. The distance from each bus master 11 and each bus slave 12 to the reference point is shown in unit mm. The signal transmission time between the bus master 11 and the bus slave 12 in the bus system 10 increases as the signal transmission distance between them increases. In the example of FIG. 1, the maximum distance between the bus master 11 and the reference point is 2.0 mm, and the maximum distance between the bus slave 12 and the reference point is 7.3 mm. Therefore, the maximum distance between the bus master 11 and the bus slave 12 in the bus system of FIG. 1 is 9.3 (= 2.0 + 7.3) mm. Since the clock cycle of the bus system cannot be shorter than the signal transmission time between the bus master and the bus slave in the bus system, the operating frequency is determined by 9.3 mm in the bus system of FIG. Is done. In such a bus system, in order to ensure a constant operating frequency, it is necessary to reduce the distance between the bus master 11 and the bus slave 12 that has the maximum distance. The master 11 and the bus slave 12 are concentrated at the center, and particularly when the bus system is manufactured on one IC, the density of the center is limited. Even if the bus master 11 and the bus slave 12 are arranged in a peripheral space, it is preferable that a constant operating frequency can be secured for the bus system.
[0003]
In JP-A-8-335204, for example, two parallel buses are prepared for data transfer between two bus masters and one bus slave. Since buses must be prepared for the number of parallel transmissions, the number of buses increases by the number of parallel transfers.
[0004]
Japanese Patent Laid-Open No. 5-181817 discloses a bus system in which a plurality of components are arranged in a matrix and components in the same row and components in the same column (elements connected to the bus) constitute a ring bus. Is disclosed. Each component will belong to two ring buses, a row-wise ring bus and a column-wise ring bus, and each component will handle input and output for the two ring buses. It is necessary and the control becomes complicated.
[0005]
In Japanese Patent Application Laid-Open No. 5-28104, the bus master and the bus slave are connected to a common ring bus, and the ring bus has a latch corresponding to 1: 1 of the bus master and the bus slave. There is no latch provided separately from the 1: 1 correspondence, only being deployed in close proximity. In this bus system, if the interval between bus masters or bus slaves adjacent to the ring bus is increased, the interval between adjacent latches on the bus is also increased. If the interval between the bus and slave is increased, it will be reduced accordingly.
[0006]
[Problems to be solved by the invention]
An object of the present invention is to provide a bus system and a signal transmission method therefor that eliminate the necessity of reducing the distance between the bus master and the bus slave in order to ensure a constant operating frequency.
An object of the present invention is to increase the achievable operating frequency with respect to the distance between a bus master and a bus slave in a bus system and its signal transmission method.
An object of the present invention is to provide a bus system and a signal transmission method therefor that improve the efficiency of data transfer throughout.
An object of the present invention is to enable parallel data transfer in a bus system and its signal transmission method.
An object of the present invention is to ensure data coherency in a bus system equipped with a bus master with cache and a signal transmission method thereof.
[0007]
[Means for Solving the Problems]
The bus system according to the present invention includes at least one bus master connected to the bus, and the total number of bus masters combined with the number of bus masters is three or more. Latch means for interposing the bus path between the bus slave and the bus master and the bus slave to divide the bus path into a plurality of sections and to latch and output the transmission signal in synchronization with the clock, have. The period of the clock is longer than the signal transmission time in the first partition and the total signal transmission time of the first and second partitions for any adjacent first and second partitions on the bus. It is set short.
[0008]
Bus systems include, for example, tree, ring, and star bus systems. There are at least one bus master and one bus slave, and the minimum total number of bus masters and bus slaves is three. In the minimum configuration of the total number of bus masters and bus slaves in the bus system, there are cases where there are 1 and 2 bus masters and bus slaves, respectively, and cases where there are 2 and 1 respectively. is there.
[0009]
For convenience of explanation, the bus master, the bus slave, and the latch means are collectively referred to as components. The distance between adjacent components on the bus is preferably uniform in the bus system, but it need not be uniform. It is only necessary that the maximum distance between adjacent components on the bus by the latching means is tight enough to increase the operating frequency of the bus system. There are circumstances in which bus masters and bus slaves in a bus system cannot be placed close enough. In a bus system in which data must be transmitted between a bus master and a bus slave in one clock cycle, a bus system having a large number of bus masters and bus slaves is more likely to have a bus master and a bus slave. The maximum value of the distance to the slave increases, and the operating frequency applicable to the bus system decreases. In the present invention, the latch means is appropriately interposed between the bus master and the bus slave, so that the maximum distance between the bus master and the bus slave is increased per clock cycle. An increase in the data transfer distance is avoided. Therefore, in order to ensure a constant operating frequency of the bus system, it is possible to eliminate a design restriction in which the bus master and the bus slave are concentratedly arranged at the center of the bus system equipment such as an IC chip. Alternatively, the operating frequency of the bus system can be increased with respect to the maximum distance between the bus master and the bus slave in the bus system.
[0010]
The bus system of the present invention can be appropriately added with the specific modes described below in any combination.
・ The length of each section on the bus is set almost equally. Since the bus operating frequency is determined by the maximum length of the partition, by equalizing the length of each partition on the bus, the distribution of the latch means is improved and the number of latch means for obtaining a predetermined operating frequency is reduced. it can.
• The bus has a tree structure as seen from each bus master and each bus slave. Preferably, the bus path length between a specific bus master and a bus slave having a high demand for high-speed data reading and writing is between other bus masters and a bus slave having a low demand. And the number of latch means interposed between the specific bus master and the bus slave is less than the number interposed between the other bus master and the bus slave. Is set. The number of clock cycles required for signal transmission between the bus master and the bus slave increases with an increase in the number of latch means interposed between the bus master and the bus slave. By reducing the number of latch means interposed between bus masters and bus slaves that require rapid transmission, the number of clock cycles required for signal transmission is advantageously reduced.
[0011]
The bus system has at least two bus masters, and at least one latch means is an arbiter for signal transmission from the bus master to the bus slave. Alternatively, the bus system has at least two bus slaves, and at least one latch means is a decoder for signal transmission from the bus master to the bus slave. As mentioned above, the bus system requires signal transmission from the bus master to the bus slave, but in a bus system that does not require a read, signal transmission from the bus slave to the bus master is not necessary. It may become. In a bus system that performs signal transmission from the bus slave to the bus master, the arbiter for signal transmission from the bus master to the bus slave and the latch means as the decoder are respectively connected from the bus slave to the bus master. Decoder and arbiter for signal transmission. The bus master includes a first bus master and a second bus master equipped with a cache, and the arbiter has received a read request from the first bus master for a specific address range of the bus slave. When the second bus master inquires whether the second bus master holds data relating to a specific address range of the bus slave in its cache, the second bus master When data is held, the second bus master is made to write the data in the corresponding address range of the bus slave.
[0012]
Data transfer between the bus master and the bus slave is a packet method. The size of one packet may be larger than the size that can be transmitted in one clock cycle. When the size of one packet is larger than the size that can be transmitted in one clock cycle, one packet is divided into a plurality of blocks and transmitted. The header information portion of the packet is preferably transmitted in one clock cycle, but is not limited to this. The header information portion is transmitted in a plurality of clock cycles, or one clock cycle together with the head portion of the data range of the packet. It may be transmitted in cycles. In this bus system, a plurality of packets can exist at the same time on condition that the bus sections do not overlap. In addition, a plurality of packets with different transmission sources and a plurality of packets with different transmission destinations can exist on the bus system. Typically, packet-based data transfer is connectionless.
[0013]
The bus master, the bus slave, and the latch means are collectively referred to as components, and components adjacent to the upstream and downstream sides in the packet transfer direction with respect to each latch means are referred to as first and second components, respectively. , And three consecutive clock cycles in order from the front, referred to as the first, second, and third clock cycles, each latch means has the first clock cycle in the second clock cycle. In order to receive a packet from the component, an acknowledge signal is output to the first component in the first clock cycle. The latch means has first and second latches, and outputs an acknowledge signal to the first component and no acknowledge signal from the second component in the first clock cycle. The packet to the second component is held in the first latch in one clock cycle, the packet in the first latch is retransmitted to the second component in the second clock cycle, and the first component Is latched in the second latch. The latch means stops outputting the acknowledge signal to the first component in the second clock cycle, and if the acknowledge signal is input from the second component in the second clock cycle, the third means In the clock cycle, while sending the packet of the first latch to the second component, the packet of the second latch is latched to the first latch, and the acknowledge signal is output to the first component. The arbiter defines one of the plurality of first components as a priority component, and a parking state in which an acknowledge signal is issued to the priority component in a clock cycle in which a request signal is not received from any of the first components In addition, the latch means other than the arbiter are also parked for the only first component.
[0014]
In the bus system to which the signal transmission method for a bus system of the present invention is applied, there are at least one bus master and a bus slave connected via the bus, and the total number of both is 18 or more. . In the signal transmission method for the bus system, at least one latch means is interposed in the bus path between the bus master and the bus slave, and the bus path is divided into a plurality of sections and synchronized with the clock. The transmission signal is latched and output by the latch means, and the period of the clock is longer than the signal transmission time in the first partition for any adjacent first and second partitions on the bus and the first and second Set shorter than the total signal transmission time of the two sections.
[0015]
The bus system signal transmission method of the present invention can appropriately add the following various specific modes in any combination. Set the length of each section on the bus almost evenly. The bus has a tree structure when viewed from each bus master and each bus slave. The number of bus masters is at least two, and at least one latch means is an arbiter for signal transmission from the bus master to the bus slave. The number of bus slaves is at least two, and at least one latch means is a decoder for signal transmission from the bus master to the bus slave. The latch means as the arbiter and the decoder are a decoder and an arbiter for signal transmission from the bus slave to the bus master, respectively.
[0016]
In the signal transmission method of the tree-type bus system, the bus path length between a specific bus master and a bus slave having a high demand for high-speed data reading and writing is set to another bus having a low demand. Set the length less than the bus path length between the master and the bus slave, and set the number of latch means interposed between the specific bus master and the bus slave to the other bus master and the bus slave. Set to less than the number of intervening between.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 2 is a conceptual block diagram of the bus system 19 embodying the present invention. The bus system 19 is manufactured on one IC chip and is incorporated in a printer controller, for example, to process a large amount of image data. The bus system 19 has a plurality of bus masters 21 and a plurality of bus slaves 22. The bus master 21 is, for example, a CPU or a DMA (Direct Memory Access), and the bus slave 22 is, for example, a memory. The bus master 21 and the bus slave 22 are connected to each other via a pipeline element 23, an arbiter 24, and a decoder 25. For convenience of explanation, the signal transmission direction from the bus master 21 to the bus slave 22 will be appropriately referred to as an upward direction, and the opposite will be appropriately referred to as a downward direction. Further, the pipeline element 23, the arbiter 24, and the decoder 25 are collectively referred to as latch means as appropriate, and the latch means, the bus master 21, and the bus slave 22 are appropriately referred to as components as appropriate. The latch means includes at least one latch for each of the upward direction and the downward direction. The bus is composed of a plurality of bus portions 20, and each bus portion 20 connects adjacent components to each other in the signal transmission direction. This bus is pipelined, and each component has one or more signal ports, and when one component is connected to another component, both components are connected to the signal ports 1: 1. . In FIG. 2, the direction of the arrow between adjacent components on the bus is shown in the upward direction, and the signal from each bus master 21 to each bus slave 22 is sent to the pipeline element 23, arbiter 24, and / or Via the decoder 25. The bus master 21 is, for example, a CPU or a DMA (direct memory access) controller, and the bus slave 22 is, for example, various interfaces such as a video controller. The bus is composed of a plurality of bus portions 20, and each bus portion 20 connects adjacent components to each other on the bus. This bus has characteristics of a tree type, a pipeline type, a packet transfer type, a connectionless type, and a pipeline type. The bus master 21 and the bus slave 22 are connected to the terminal of the bus. When the bus is viewed from each bus master 21 and each bus slave 22, the bus spreads in a tree shape.
[0018]
Data is packetized and transmitted, and one packet is transmitted from each component over one or more clock cycles. A packet block having a length corresponding to one clock cycle is latched in the latch of each latch means. The arbiter 24 has an arbitration function in the packet transfer direction, selects one from a plurality of components connected in the previous stage, connects to the next component, and transfers the packet in the packet transfer direction. The decoder 25 has a branching function in the packet transfer direction, connects one component at the previous stage to one component selected from the plurality of components at the next stage, and transfers the packet in the packet transfer direction. The pipeline element 23 has a function of latching a signal input in a certain clock cycle and sending it to the next component in the packet transfer direction after the next clock cycle. The numerical value “0.9” shown for the bus portion 20 connecting adjacent components on the path indicates the distance between components connected to each other by the bus portion 20 in the unit mm. The distances d between adjacent components in the bus system 19 are designed to be all equal values, for example, 0.9 mm. If the pipeline element 23, the arbiter 24, and the decoder 25 are equipped with a latch and adjacent components are connected to each other by the pipeline, a signal can be transmitted between adjacent components per clock cycle. It will be enough. In the bus system 19, since the distance between adjacent components is sufficiently shortened, the operating frequency of the bus system 19 can be greatly increased. As long as there is enough space on the IC chip, the number of the pipeline elements 23 interposed can be increased to further increase the operating frequency of the bus system 19.
[0019]
In this bus system 19, even if the distance between the bus master 21 and the bus slave 22 is long, if the number of intervening pipeline elements 23 between the bus master 21 and the bus slave 22 is increased, the bus -The necessity of reducing the operating frequency of the slave 22 can be eliminated. Thus, in order to secure a constant operating frequency, the bus master 21 and the bus slave 22 are arranged at a distance from each other, and the restriction of concentrating them at the center of the IC chip is eliminated. It is possible to arrange it in a peripheral part with a margin.
[0020]
FIG. 2 shows the arbiter 24 and the decoder 25 in the upstream packet flow for the bus system 19, but the functions of the arbiter 24 and the decoder 25 are reversed in the downstream direction. That is, in the downstream direction, the arbiter 24 becomes a decoder and the decoder 25 becomes an arbiter. For example, when the bus system 19 is a bus system consisting only of a write command that does not require an acknowledge signal from the bus master to the bus slave, the packet flow direction in the bus system is determined from the bus master to the bus. Since it is only in one direction to the slave, the arbiter 24 and the decoder 25 do not need the decoder and arbiter functions for the downstream packets, respectively. In a typical bus system, the bus master issues a read request, and the read data is transmitted as a downstream packet. Therefore, each arbiter 24 and each decoder 25 have a decoder and a receiver to cope with the downstream packet transfer. Equipped with an arbiter function.
[0021]
3 and 4 show parallel transmission and suspension of signals in a bus system embodying the present invention. The bus masters 21a and 21b are connected to the bus slave 22a via the arbiter 24a and the decoder 25a. The bus masters 21a and 21b are also connected to the bus slaves 22b and 22c via the arbiter 24a, the decoder 25a, the arbiter 24b, and the decoder 25b. The bus master 21c is connected to the bus slaves 22b and 22c via the arbiter 24b and the decoder 25b. The bus portion 20 constitutes a bus as a whole and connects adjacent components to each other on the bus. The direction of each bus portion 20 in FIG. 3 is shown in the upward direction as in the case of FIG. Similarly to the arbiter and decoder of FIG. 2, the arbiter and decoder of FIG. 3 are also equipped with functions of a decoder and an arbiter, respectively, in order to cope with downstream packet transfer.
[0022]
In FIG. 3, f1 indicates a signal flow from the bus master 21b to the bus slave 22a, and f2 indicates a signal flow from the bus master 21c to the bus slave 22c. In the bus system of the present invention, a plurality of communications between the bus master and the bus slave can be established as long as the routes do not overlap. In the example of FIG. 3, the directions of f1 and f2 are both from the bus master to the bus slave, but one or both may be from the bus slave to the bus master. .
[0023]
In the state shown in FIG. 4, the arbiter 24b gives priority to the signal flow from the bus master 21c to the bus slave 22c. Progress has been paused at. The signal is advanced by one bus portion 20 every clock cycle in synchronism with the clock cycle. Further, since signal transmission / reception in the bus system is a connectionless type, even if communication is not established between the bus master and the bus slave, the signal can proceed. The tip of f3 advances to the front of the arbiter capable of traveling, that is, it can be paused at a position sufficiently close to the transmission destination, so that the arrival time at the transmission source is shortened.
[0024]
FIG. 5 is a configuration diagram of the bus system in which the distance between the bus master and the bus slave is set in consideration of the overall transmission efficiency. In FIG. 5, the distance on the drawing between the bus master and the bus slave reflects the distance between the bus master and the bus slave in an actual product such as an IC chip. ○ represents a bus master, □ represents a bus slave, Δ represents an arbiter for the upward direction, and ▼ represents a decoder for the upward direction. P1 and P2 indicate the directions of the request packet and the acknowledge packet, respectively. The bus masters are classified into high-speed bus masters 26a and 26b and low-speed bus masters 27a to 27d. The bus slaves are classified into high-speed bus slaves 30 a and 30 b and low-speed bus slaves 31. The high-speed bus masters 26a and 26b are bus masters that require higher-speed communication than the low-speed bus masters 27a to 27d. The high-speed bus slaves 30a and 30b are bus slaves that require higher-speed communication than the low-speed bus slave 31. Each bus master has a bus slave as a communication partner, and the arbiters 32a to 32f and the decoders 33a and 33b guarantee communication between all bus masters and bus slaves with which communication is possible. As shown, the bus master and the bus slave are connected. For example, the high-speed bus master 26b can communicate with all the bus slaves 30a, 30b, and 31, whereas the high-speed bus master 26a only communicates with the high-speed bus slave 30a. The masters 27e and 27f can communicate only with the low-speed bus slave 31. In FIG. 5, since the distance between the decoder 33a and the arbiter 32f is relatively longer than the distance between the other components, a predetermined number of pipelines are appropriately interposed between the decoder 33a and the arbiter 32f. It is preferable to make the distance between adjacent components uniform. In this bus system, communication between the high-speed bus master 26a and the high-speed bus slave 30a requires higher speed than communication between the low-speed bus masters 27b to 27d and the low-speed bus slave 31. The mutual distance between the high-speed bus master 26a and the high-speed bus slave 30a is made shorter than the mutual distance between the low-speed bus masters 27b to 27d and the low-speed bus slave 31 and the high-speed bus master 26a-high-speed bus. The number of latch means interposed between the slaves 30a is smaller than the number of latch means interposed between the low-speed bus masters 27b to d-the low-speed bus slaves 31. The arbiters 32a to 32f perform arbitration giving priority to communication that requires high-speed communication between the bus master and the bus slave.
[0025]
FIG. 6 shows the types and contents of packets issued by each pipeline element.
(A) Write Request Packet Data (WRPD): A packet in which the bus master requests the bus slave to write data.
(B) Read Request Packet Data (RRPD): A packet in which the bus master requests the bus slave to read data.
(C) Write Ack Packet Data (WAPD): An acknowledge packet issued from the bus slave to the bus master for WRPD.
(D) Read Ack Packet Data (RAPD); an acknowledge packet issued by the bus slave to the bus master for RRPD.
(E) Coherency Request Packet (CRP): A packet in which the arbiter inquires the coherency of data to the bus master with cache.
(F) Coherency Ack Packet (CAP): An acknowledge packet issued by the cached bus master to the arbiter for the CRP.
[0026]
The information held by WRPD is as follows.
Master ID: ID of the bus master that issued the WRPD.
Address: The start address of the write address range in the bus slave to which the WRPD is sent.
Size: Size of the write address range.
Data (Size): Data block (the number of the data block in the packet).
[0027]
The information held by the RRPD is as follows.
Master ID: ID of the bus master that issued the RRPD.
Address: The start address of the read address range in the bus slave to which the RRPD is sent.
Size: The size of the read address range.
Type: Type (details will be described later).
[0028]
The WAPD includes the following information.
Master ID: ID of the bus master addressed to the acknowledge for the write request.
Address: Start address of the write address range in the bus slave.
Status: The state of the bus slave such as an error or busy for a write request.
[0029]
The RAPD includes the following information.
Master ID: ID of the bus master addressed to the acknowledge for the read request.
Address: Start address of the read address range in the bus slave.
Size: The size of the read address range.
Data (Size): Data block (the number of the data block in the packet).
Status: The state of the bus slave such as an error or busy for a read request.
[0030]
The CRP includes the following information.
Address: Start address of the target address range for coherency.
Size: The size of the target address range for coherency.
[0031]
The CAP includes the following information.
Address: Start address of the target address range for coherency.
Status: The state of the bus master such as an error or busy for a coherency request.
[0032]
There are the following types (Type). Note that w / o means no (without) and w / means there.
Write w / o Ack: Write without acknowledge.
Write w / Ack: Write with acknowledge.
Read w / o Ack: Write without acknowledge.
Read w / Ack: Write with acknowledge.
Coherency Req w / o Ack: Coherency request without acknowledgment.
Coherency Req w / Ack; Coherency request with acknowledge.
[0033]
FIG. 7 shows a signal issued by each latch means separately from the packet. For convenience of explanation, it is assumed that components adjacent to the issuer side and the issuer side in the packet transfer direction by the latch means are represented by symbols Cu and Cd, respectively. Further, as already defined, the component is used as a concept including not only latch means but also a bus master and a bus slave. The master signal (Master Signals) is a general term for signals transmitted and received by each latch means with its component Cd. The slave signal (Slave Signals) is a general term for signals transmitted and received by each latch means with its component Cu. Arbiter signals (Arbiter Signals) are signals that only the arbiter in the latch means sends and receives to and from the components Cu and Cd. The decoder signal (Decoder Signals) is a signal that only the decoder in the latch means transmits / receives the components Cu and Cd. In FIG. 7, Mst and Slv at the head of the signal name mean signals flowing in the data packet transfer direction and the opposite direction, respectively. Req, Ack, ID, AD, Size, Type, and MID in the middle of the signal name mean request, acknowledge, master ID, address & data bus size, type, and master ID, respectively. Note that both ID and MID mean a master ID, but the master ID meaning Mst_ID means that the upstream component is between its upstream and downstream components adjacent to each other in the data transfer direction. In contrast to the ID that is output as the ID, the master ID that means Slv_ID is the ID of the bus master to which the downstream component forwards the packet between the upstream and downstream components adjacent in the data transfer direction. Is pointed to. The addition of (O) and (I) in the signal name indicates that the signal is a signal related to the output and input of the latch means, respectively. The master signals (Master Signals) include Mst_Req (O), Slv_Ack (I), Mst_ID (O), Mst_AD (O), Mst_Size (O), Mst_Type (O), Slv_Req (I), Mst_Ack (O), Slv_Size (Slv_Size). I), Slv_AD (I), Slv_Status (I), and Slv_ID (I). The slave signals (Slave Signals) include Mst_Req (I), Slv_Ack (O), Mst_ID (I), Mst_AD (I), Mst_Size (I), Mst_Type (I) Slv_Req (O), Mst_Ack (I), Slv_Sie (Slv_Siez). O), Slv_AD (O), Slv_Status (O), and Slv_ID (O).
[0034]
Here, N is the total number of components Cu in the arbiter (Master Connection), or the total number of components Cd in the decoder (Slave Connection). Each arbiter requires transmission / reception of the number of slave signals (Slave Signals) of latch means per component Cu, and transmission / reception of the number of master signals (Master Signals) of latch means per component Cd. It becomes. Therefore, in each arbiter, the number of upstream signal ports is the total number xN of slave signals (Slave Signals), and the number of downstream signal ports is the total number xN of master signals (Master Signals). Each decoder requires transmission / reception of the number of master signals (Master Signals) of the latch means per component Cu and transmission / reception of the number of slave signals (Slave Signals) of the latch means per component Cd. Accordingly, in each decoder, the number of upstream signal ports is the total number of master signals (Master Signals) xN, and the number of downstream signal ports is the total number of slave signals (Slave Signals) xN.
[0035]
8 and 9 are explanatory diagrams showing the flow of packets in the bus system in order. The process of packet flow is (a) → (b) → (c) in FIG. 8 → (a) → (b) → (c) in FIG. 9. In the example of FIGS. 8 and 9 for the bus system, the bus masters 34a and 34b are connected to the bus slaves 35a and 35b via the arbiters 36a and 36b and the decoder 37. The bus portion 40 constitutes a bus as a whole, and connects adjacent components to each other on the bus. Each step will be described in turn. Note that the communication request described in FIGS. 8 and 9 is an example.
[0036]
FIG. 8A: The bus masters 34a and 34b simultaneously issue a write request R0 and a read R1 to the arbiter 36a. In this example, R0 and R1 are both requested and packet headers.
FIG. 8B: The arbiter 36a prioritizes R0 over R1, and the arbiter 36b does not accept requests from other than the arbiter 36a. As a result, a total of four packet blocks R0, D0-1, D0-2, and D0-3 from the bus master 34 pass through the arbiters 36a and 36b and the decoder 37 in synchronism with the clock cycle. Ships to 35a. In a state where the first packet block R0 has arrived at the bus slave 35a, each of R0, D0-1, D0-2, D0-3 is between the bus slave 35a and the decoder 37, between the decoder 37 and the arbiter 36b, and between the arbiter. 36b between the arbiter 36a and between the arbiter 36a and the bus master 34a.
FIG. 8C: The arbiter 36a transmits the last packet block D0-3 from the bus master 34a to the arbiter 36b, and the read request R1 from the bus master 34b is directed to the bus slave 35a. Ship. As a result, the packet block R1 proceeds to the bus slave 35c following D0-3.
[0037]
FIG. 9A: Since the write request in this example does not require an acknowledge, when the bus slave 35a accepts D3, the bus slave 35a does not issue an acknowledge signal toward the bus master 34a. The request R1 from 34b is accepted.
FIGS. 9B and 9C: The bus slave 35a receives the packet blocks R, D1-1, D1-2, and D1-3 of the acknowledge packet for the packet R1 of the read request from the bus master 34b. , D1-4 are issued in order every clock cycle. In this example, R is an acknowledge signal and a packet header. The acknowledge packet travels in the opposite direction to the request packet toward the bus master 34b. For the acknowledge packet, the decoder 37b functions as an arbiter, the arbiter 36b functions as a decoder, and the arbiter 36a functions as a decoder.
[0038]
In the bus system to which the present invention is applied, data coherency is considered. That is, some bus masters are equipped with a cache, and even if a certain bus master changes the contents of the cache equipped with it, the data in the corresponding bus slave is updated. There are times when has not been completed. To deal with this, each arbiter knows all the bus masters equipped with cashiers among the bus masters requesting data read and write to it. When a certain bus master Ma requests to read data in the predetermined address range AW1 in the predetermined bus slave Sa, the address range AW1 and the duplicate address in the cache are sent to the bus master equipped with another cacher. Queries whether the range data has been rewritten. The inquired bus master responds to the inquirer's arbiter. If the answer is No, the arbiter waits for a read request from the bus master that requested the data read, Promptly send to the bus / slave component. If the answer is Yes, that is, if the address range AW1 and the overlapping address range are rewritten, the inquired bus master updates the required address range of the bus slave Sa based on the update data in the cache. Issue a write request. The bus master sends a read request waiting from the bus master Ma to the bus slave Sa after sending the write packet by the write request based on the update of the cache contents.
[0039]
FIG. 10 and FIG. 11 are upstream and downstream timing charts for each signal when each latch means has only one latch in both the upstream and downstream directions in the packet transfer model of FIG. 8 and FIG. is there. The latch means is equipped with a single latch for each of the upward and downward directions. FIG. 11 is a timing chart in the downstream direction. In order to clarify the relationship with the timing in the upstream direction, the timing chart in the upstream direction from the decoder 37 to the bus slave 35a is also shown in the upper part of FIG. ing. In this bus system, the acknowledge issued by each component means that the packet can be accepted. As in the description of FIG. 7, for each latch means, components adjacent to the upstream and downstream sides in the packet transfer direction are represented by symbols Cu and Cd, respectively. Since the latch means (as described above, the latch means is a general term for pipeline elements, arbiters, and decoders) has only one latch, the acknowledge signal from the component Cd in a certain clock cycle. Otherwise, in the next clock cycle, the latch data cannot be passed to the component Cd, so the latch data must be held for the next clock cycle, so the next clock cycle The data from the component Cu cannot be latched into the latch. Therefore, each latch means must issue an acknowledge signal to the component Cu after receiving the acknowledge signal from the component Cd in order to hold the packet from the component Cu in its own latch. 10 and 11, the same column indicates the same clock cycle.
[0040]
For convenience of explanation, in FIG. 10, the clock cycle in which the bus master 34a outputs the request R0 to the arbiter 36a for the first time is represented by T1, and each clock cycle is represented by T2, T3,. I will decide. In FIG. 10, the bus masters 34a and 34b output requests R0 and R1 as the first request signals to the arbiter 36a in the clock cycle T1. The bus master 34a, together with the request signal R0, a packet block a0 indicating a head address in a write destination bus slave, a signal 3 of a size (Size) obtained by converting a write target address range into a predetermined unit, A type Wn, which means that the write request does not require an acknowledge, and a signal M0 indicating its own ID are output to the arbiter 36a. Similarly, the bus master 34b, together with the request signal R1, has a packet block a0 indicating the head address in the read-out bus slave, size 4 obtained by converting the address range to be read into a predetermined unit, and the read request is acknowledged. Is output to the arbiter 36a. The type Ra means that it is necessary and M1 indicating its own ID.
[0041]
The arbiter 36a gives priority to the write request of the bus master 34a over the read request of the bus master 34b, and issues an acknowledge signal A to the bus master 34a in the clock cycle T2. On the other hand, in the clock cycle T3, the bus master 34a sends a data packet block d0 to the arbiter 36a instead of the head address information a0. In FIG. 10, all packet blocks of data are represented by the same symbol d0, but the first and second d0 out of a total of six d0 are the data packet block (1), the third The fourth d0 is the data packet block (2), and the fifth and sixth d0 are the data packet block (3). Since each latch means is equipped with only one latch in both the upward direction and the downward direction, an acknowledge signal cannot be issued to the component Cu in the clock cycle in response to the clock cycle that receives the acknowledge signal from the component Cd. An acknowledge signal can be issued to the component Cu in the next clock cycle. As long as there is no trouble such as an error, the transmission / reception signal pattern between the bus master 34a and the arbiter 36b in which an acknowledge is generated every other clock cycle propagates to the downstream component while being delayed by one clock cycle. Go.
[0042]
When the arbiter 36a receives the acknowledge signal from the arbiter 36b in the clock cycle T9, the arbiter 36a issues the acknowledge signal to the bus master 34b in the clock cycle 10. Based on the acknowledge signal from the arbiter 36a in the clock cycle T10, the bus master 34b detects that the transmission signal to the arbiter 36a in the clock cycle T9 has been accepted by the arbiter 36a. As long as there is no trouble such as an error, the transmission / reception signal pattern between the bus master 34b and the arbiter 36a is propagated between the downstream components while being delayed by one clock cycle. It is clock cycle T12 that the bus slave 35a issues an acknowledge to the decoder 37 with respect to R1.
[0043]
In FIG. 11, when the bus slave 35a receives the read request R1 from the decoder 37, the bus slave 35a sends a request (Slv_Req) R to the decoder 37 through a predetermined access time to the associated memory. For convenience of explanation, in FIG. 11, the clock cycle in which the bus slave 35a first issues R to the decoder 37 is T1, and hereinafter, each clock cycle after T1 is expressed as T2, T3,. To. In the clock cycle T1, the bus slave 35a, together with R, a1 indicating the leading address of the read address range, the signal 4 having a size obtained by converting the address range to be read into a predetermined unit, and the type of request request for the read request. AR indicating that the packet is a packet and M1 indicating which bus master is an acknowledge packet are output. In the downstream direction, the decoder 37 functions as an arbiter, and the arbiters 36b and a function as decoders. As in the case of signal transmission in the upward direction, each latch means receives the acknowledged component Cd (note: components Cd and Cu in the upward direction become components Cu and Cd in the downward direction, respectively). On the other hand, in the clock cycle next to the clock cycle that has received the acknowledge, the latch data is output and an acknowledge signal is issued to the component Cu. Thus, as long as there is no trouble such as an error, the transmission / reception signal pattern between the bus slave 35a and the decoder 37 is propagated between the downstream components while being delayed by one clock cycle. In FIG. 11, the description of Slv_AD, Slv_Size, and Slv_Type is omitted between the decoder 37 and the arbiter 36b and between the arbiter 36b and the arbiter 36a for the sake of simplicity of illustration. The bus master 34b outputs an acknowledge for the input of the last packet block to the arbiter 36a in the clock cycle T12.
[0044]
12 and 13 are timing charts for the upstream and downstream directions for each signal when each latch means is equipped with two latches in both the upstream and downstream directions. The latch means is equipped with two latches exclusively for the upward direction and the downward direction. FIG. 13 is a timing chart in the downstream direction. In order to clarify the relationship with the timing in the upstream direction, the timing chart in the upstream direction from the decoder 37 to the bus slave 35a is also shown in the upper part of FIG. ing. Only differences from FIGS. 10 and 11 will be described. For convenience of explanation, in FIG. 12, the clock cycle in which the bus master 34a outputs the request R0 to the arbiter 36a for the first time is denoted by T1, as in the explanation of FIG. .., And in FIG. 13, similarly to the description of FIG. 11, the clock cycle in which the bus slave 35a first issues R to the decoder 37 is denoted as T1. In the following description, T2, T3,... When the latch means has two latches, each latch means has a clock cycle in which no acknowledge signal is input from the component Cd even though it has issued an acknowledge signal to the component Cu, and the next clock cycle. Then, when the data of the latch must be sent again to the component Cd, the data from the component Cu can be latched in another latch in the next clock cycle. Therefore, each latch means can issue an acknowledge signal to the component Cd while receiving an acknowledge signal from the component Cu in the same clock cycle. In response to the first clock cycle from the component Cu, each latch means Lo issues an acknowledge to the component Cu in the clock cycle T2 next to the input clock cycle T1. The latch means Lo that has issued an acknowledge to the component Cu issues a request to the component Cd in the clock cycle T2. However, if the component Cd is an arbiter such as the arbiter 36b, the request from the latch means Lo Since there is no guarantee that the first component is accepted over the first component, the second acknowledge cannot be issued to the component Cu until the first acknowledge is input from the component Cd. Therefore, each latch means Lo can issue the second acknowledge to the component Cu in the clock cycle next to the clock cycle that received the acknowledge from the component Cd, and is the earliest clock cycle T4. Therefore, in each clock cycle Lo, the acknowledge can be issued to the component Cu continuously after the clock cycle T4. This can be improved by the parking method described later. Thus, in the bus system of FIGS. 12 and 13, the bus slave 35a issues an acknowledge to R1 to the decoder 37 at clock cycle T10. The bus master 34b outputs an acknowledge for the input of the last packet block to the arbiter 36a in the clock cycle T9.
[0045]
In FIG. 12, since the arbiter 36a issues an acknowledge signal to the bus master 34b in the clock cycle T7, the arbiter 36a issues an acknowledge signal in succession to the acknowledge signal to the bus master 34a in the clock cycle T6. However, the decoder 37b suspends issuing an acknowledge signal to the arbiter 36a in the clock cycle T8. This is because the arbiter 36b knows for the first time that the bus master 34b issues a read request in the clock cycle T8, and immediately arbitrates the acknowledge signal from the other bus master because of the need for arbitration with the acknowledge. This is because it cannot be issued to 36a. In the parking method described later, such a hold of the acknowledge signal can be omitted to improve the transmission efficiency.
[0046]
FIGS. 14 and 15 are upstream and downstream timing charts for respective signals in the improved bus system in which the parking technology is applied to the bus systems according to FIGS. Differences from the timing charts of FIGS. 12 and 13 will be described. For convenience of explanation, in FIG. 14, the clock cycle in which the bus master 34a outputs the request R0 to the arbiter 36a for the first time is denoted by T1, as in the explanation of FIG. 11, and each clock cycle is denoted by T1. .., And in FIG. 15, as in the description of FIG. 12, the clock cycle in which the bus slave 35a first issued R to the decoder 37 is denoted as T1. In the following description, T2, T3,... The pipeline element and the decoder are in a parking state that continuously issues an acknowledge signal to the only component Cu. Further, when no request signal is input from anywhere, the arbiter is in a parking state in which an acknowledge signal is continuously issued to one predetermined component Cu. Therefore, a packet from the arbiter 36a to which an acknowledge signal is issued preferentially from the arbiter does not wait for an acknowledge in all clock cycles including the arbiter from the first packet block as long as there is no trouble such as an error. Can progress. In this way, the bus slave 35a issues an acknowledge for R1 to the decoder 37 at clock cycle T7. It is also clock cycle T7 that the bus master 34b outputs an acknowledge for the input of the last packet block to the arbiter 36a.
[0047]
FIG. 16 is an example of a timing chart for a plurality of signals related to the operation of the pipeline element. The meaning of each signal is as follows. Note that the bus system described with reference to FIGS. 16 to 22 is different from the bus system described with reference to FIGS. The signal is different. In FIGS. 6 to 15, the packet size is defined by SIZE, whereas in FIG. 16 and subsequent ones, instead of the packet size, the start and end of the packet are determined by signals CMD and NXT. Is defined.
CLK: Each signal is transferred between adjacent components on the bus at the change point of CLK from 0 to 1.
RST: A signal that each component outputs to the component Cd. When this bit is 1, it indicates that the bus is in the reset state.
REQ: A signal output from each component to the component Cd. 1 indicates that there is an AD described later as a transfer packet.
CMD: A signal that each component outputs to the component Cd. 1 indicates that AD as a transfer packet is a command.
NXT: A signal output from each component to the component Cd. 1 indicates that the transfer packet continues.
AD: A signal that each component outputs to the component Cd. When CMD is 1, the contents of AD are commands, and when it is 0, the contents of AD are data.
ACK: A signal that each component outputs to the component Cu. 1 indicates that the current transfer information has been received.
[0048]
In FIG. 16, the AD packet includes only a command packet and there may be one or more data packets following the command packet. Each of the components described with reference to FIGS. 10 to 15 outputs a request signal to the component Cd from the component Cd to the acknowledge signal that receives the acknowledge signal. In all the acknowledge signals that output the AD signal to the component Cd, the request signal is output to the component Cd.
[0049]
FIG. 17 shows signal input / output in each component of the bus system in the case of packet transfer in the upward direction. Upstream packets from the bus masters 43a and 43b are sent to the bus slave 44a or 44b via the arbiter 46, the pipeline element 47, and the decoder 48. As shown in FIG. 16, each component outputs RST, REQ, CMD, NXT, and AD signals to the component Cu, and sends ACK to the component Cd. Each component also receives a common CLK supply. The logic of the bus masters 43a and 43b and the bus slaves 44a and 44b is entrusted to the user (User Logic).
[0050]
In FIG. 17, the circuit is described in relation to packet transfer from the bus master to the bus slave, but in order to cope with packet transfer from the bus slave to the bus master, the circuit of FIG. Is equipped with a circuit with the opposite signal direction. That is, in the downstream packet transfer circuit, the arbiter 46 and the decoder 48 of the upstream packet transfer circuit in FIG. 17 are replaced with the bus slave and the bus master, respectively, and the component Cu and the component Cd for each latch means. 17 is reversed from that in FIG. 17, and accordingly, RST, REQ, CMD, NXT, AD, and ACK are also reversed between the components in FIG.
[0051]
FIG. 18 is a block diagram of the pipeline element 47. In FIG. 18, a signal having MST at the beginning of the signal name means a signal input from the component Cu adjacent to the upstream side in the packet transfer direction to the pipeline element 47, and SLV is added at the beginning of the signal name. Means that the signal is input from the component Cd adjacent to the downstream side in the packet transfer direction, and the one prefixed with PIP indicates that the pipeline element 47 outputs to the component Cu and the component Cd. means. The pipeline element 47 has a latch A50 and a latch B51. AD, CD, and NXT from the component Cu side are input to D of the latch B51 and A of the selector 53. The controller 52 receives REQ and outputs ACK to the component Cu side, and outputs REQ and ACK to the component Cd side. The controller 52 sends control signals to the ENB terminal of the latch A50, the ENB terminal of the latch B51, and the SEL terminal of the selector 53.
[0052]
FIG. 19 is a truth table of the pipeline element 47 of FIG. The relationship between the current value of each signal (Current Value) and the next value (Next Value) is shown, and what happens to the next value of each signal relative to the current value of each signal in the same column. It is shown. Note that X means “1” or “0”, H means that the latch holds the value, that is, maintains the value in the previous clock cycle, and A means that the selector 53 A indicates that the data at the A terminal is latched in the latch A50, B indicates that the data at the B terminal of the selector 53 is latched in the latch A50, and D indicates that the data at the D terminal of the latch B51 is latched in the latch B51. , Meaning each. The truth table of FIG. 19 is a matrix of 12 rows × 9 columns. FIG. 20 is a state transition diagram of the pipeline element 47 based on the truth table of FIG. The four-digit numerical values in the four boxes are the truth values of PIP_ACK, PIP_REQ, Latch-A_Full, and Latch-B_Full in order from the left, and correspond to the truth values of lines 1 to 4 in FIG.
[0053]
The state transition of the pipeline element 47 will be described with reference to FIGS. 19 and 20. When each packet is transferred to the next component every clock cycle without an error or the like, in the truth table of FIG. 19, the truth value in the sixth column (1, 1 in order from the top) , 1, 0 | 1, 1 | 1, 1, 1, 0 | H, D), and corresponds to S3 in the state transition diagram of FIG. That is, in each clock cycle, the component outputs an acknowledge signal (PIP_ACK) and a request signal (PIP_REQ) to the component Cu and the component Cd, and transfers the packet of the latch A50 to the component Cd, while The process of latching the packet in the latch A50 is continued. The state of S3 is not only when the pipeline element 47 receives the request signal and the acknowledge signal from the component Cu and the component Cd, respectively, in the clock cycle, but also from the component Cu and the component Cd, respectively, in the clock cycle. Continue even if no acknowledge signal is input. When the acknowledge signal from the component Cd stops in the state of S3, the pipeline element 47 shifts to the state of S4. In the state of S4, the component does not output an acknowledge signal (PIP_ACK) to the component Cu and outputs a request signal (PIP_REQ) to the component Cd in each clock cycle. In S4, both the latch A50 and the latch B51 are in a full state, and the packet is held in the latch A50 and the latch B51. In S4, the latch A50 holds the packet latched in the last clock cycle of S3, and the latch B51 receives and latches the packet input from the component Cu in the first clock cycle of S4. Is holding. The state of S4 is maintained regardless of the presence or absence of a request signal from the component Cu (M_REQ = X) unless an acknowledge signal is input from the component Cd (S_ACK = 0). Then, as soon as the acknowledge signal is input from the component Cd, the pipeline element 47 latches the packet of the latch B51 in the latch A50, and returns from S4 to S3.
[0054]
FIG. 21 is a block diagram of the arbiter 46. The arbiter 46 includes pipeline logic 55, and the configuration of the pipeline logic 55 is the same as the configuration of the pipeline element 47 of FIG. Signals from the respective components Cu (in the example of FIG. 17, the bus master 43a and the bus master 43b) are respectively input to A and B of the selector 56. Signals output from the pipeline logic 55 to the respective components Cu are output from OUT0 and OUT1 of the decoder 57, respectively. The REQ and NXT signals from each component Cu are input not only to the selector 56 but also to the controller 58. The acknowledge signal (SLV_ACK) from the component Cd is input to the IN terminal of the decoder 57 and the controller 58 as ARB_ACK through the pipeline logic 55. The controller 58 controls switching between A and B in the selector 56 based on REQ (request signal) and NEXT (continuation signal), and based on REQ (request signal), NEXT (continuation signal), and so on. The switching of OUT0 and OUT1 in the decoder 57 is controlled. When the request signal (MST_REQ0, MST_REQ1) is simultaneously input from a plurality of components Cu, the selector 56 causes the selector 56 to select one component Cu according to a predetermined arbitration rule, and from the selected component Cu The selector 56 maintains the selection until the next NEXT signal is interrupted. Thus, the continuous packets from the component Cu selected by the arbiter 46 continue to be sent to the next component Cd (the pipeline element 47 in the example of FIG. 17) until the continuity is interrupted.
[0055]
FIG. 22 is a block diagram of the decoder 48. The arbiter 46 includes pipeline logic 61, and the configuration of the pipeline logic 61 is the same as that of the pipeline element 47 of FIG. Signals MST_REQ, MST_CMD, MST_NXT, and MST_AD from the component Cu are input as the signals DEC_REQ, DEC_CMD, DEC_NXT, and DEC_AD to the IN of the decoder 63 through the pipeline logic 61. DEC_CMD and DEC_AD are also input to the controller 64. The controller 64 switches IN0 and IN1 in the selector 62 based on the input signals DEC_CMD and DEC_AD, and switches OUT0 and OUT1 of the decoder 63. Thus, the packet from the component Cu side is sent out from OUT0 or OUT1 corresponding to the destination bus slave to the component Cd side, and the acknowledge signal from one component Cd side selected by the selector 62 ( SLV_ACK0, SLV_ACK1) are input to the pipeline logic 61 as SLV_ACK, and further output from the pipeline logic 61 to the component on the component Cu side as DEC_ACK.
[0056]
As a summary, the following matters are disclosed regarding the configuration of the present invention.
(1) At least one bus slave connected to the bus with at least one bus master connected to the bus, the total number of bus masters being three or more. And latch means for latching and outputting the transmission signal in synchronization with the clock by dividing the bus path into a plurality of sections through the bus path between the bus master and the bus slave,
The period of the clock is set longer than the signal transmission time in the first partition and shorter than the total signal transmission time of the first and second partitions for any adjacent first and second partitions on the bus. Bus system.
(2) The bus system according to (1), wherein the lengths of the sections on the bus are set to be approximately equal.
(3) The bus system according to (1), wherein the bus has a tree structure as viewed from each bus master and each bus slave.
(4) The bus system according to (1), comprising at least two bus masters, wherein the at least one latch means is an arbiter for signal transmission from the bus master to the bus slave.
(5) The bus system according to (1), comprising at least two bus slaves, wherein the at least one latch means is a decoder for signal transmission from the bus master to the bus slave.
[0057]
(6) The bus system according to (4) or (5), wherein the arbiter and the latch means as a decoder are a decoder and an arbiter for signal transmission from the bus slave to the bus master, respectively.
(7) The bus path length between a specific bus master and a bus slave with a high degree of demand for high-speed data reading and writing is between other bus masters and bus slaves with a low degree of demand. And the number of latch means interposed between the specific bus master and the bus slave is less than the number interposed between the other bus master and the bus slave. The bus system as set forth in (3).
(8) The bus system according to (1), wherein the data transfer between the bus master and the bus slave is a packet system.
(9) The bus system according to (8), wherein the packet type data transfer is connectionless.
(10) The bus master includes a first bus master and a second bus master equipped with a cache;
When the arbiter receives a read request for a specific address range of the bus slave from the first bus master, the arbiter transfers the second bus master to the cache to the second bus master. If the second bus master holds data, the data is sent to the second bus master at the corresponding address of the bus slave. The bus system according to (4), which is written in the range.
[0058]
(11) The bus master, the bus slave, and the latch means are collectively referred to as components, and the upstream and downstream components in the packet transfer direction with respect to each latch means are first and second components, respectively. And three consecutive clock cycles in order from the front are called the first, second and third clock cycles,
The bus system according to (1), wherein each latch means outputs an acknowledge signal to the first component in the first clock cycle in order to receive a packet from the first component in the second clock cycle.
(12) The latch means has the first and second latches, and outputs the acknowledge signal to the first component and does not input the acknowledge signal from the second component in the first clock cycle. When the first clock cycle holds the packet to the second component in the first latch, and the second clock cycle resends the packet of the first latch to the second component and The bus system according to (11), wherein a packet from one component is latched in a second latch.
(13) The latch means stops outputting the acknowledge signal to the first component in the second clock cycle, and if the acknowledge signal is input from the second component in the second clock cycle, In the third clock cycle, the packet of the second latch is sent to the second component, the packet of the second latch is latched to the first latch, and the acknowledge signal is output to the first component. (12) The bus system as described.
(14) The arbiter defines one of the plurality of first components as a priority component, and issues an acknowledge signal to the priority component in a clock cycle in which no request signal is received from any of the first components. The bus system according to (12), wherein the latching means other than the arbiter is also parked for the only first component.
(15) The bus system according to (1), wherein the bus master, the bus slave, and the latch means are manufactured in one chip.
[0059]
(16) In a signal transmission method for a bus system in which at least one bus master and a bus slave connected via a bus each have a total number of 18 or more,
Interposing at least one latch means in the bus path between the bus master and the bus slave and dividing the bus path into a plurality of partitions;
The transmission signal is latched and output in the latch means in synchronization with the clock,
The period of the clock is set to be longer than the signal transmission time in the first partition and shorter than the total signal transmission time of the first and second partitions for any adjacent first and second partitions on the bus. To
Signal transmission method for bus systems.
(17) The signal transmission method for a bus system according to (16), wherein the lengths of the respective sections on the bus are set almost uniformly.
(18) The signal transmission method for a bus system according to (16), wherein the bus has a tree structure when viewed from each bus master and each bus slave.
(19) The number of bus masters is at least two,
The signal transmission method for a bus system according to (16), wherein at least one latch means is an arbiter for signal transmission from a bus master to a bus slave.
(20) The number of bus slaves shall be at least two,
The signal transmission method for a bus system according to (16), wherein at least one latch means is a decoder for signal transmission from a bus master to a bus slave.
[0060]
(21) The bus system signal transmission method according to (19) or (20), wherein the latch means as the arbiter and the decoder is a decoder and an arbiter for signal transmission from the bus slave to the bus master, respectively.
(22) The bus path length between a specific bus master and a bus slave having a high degree of demand for high-speed data reading and writing is set between another bus master and a bus slave having a low degree of demand. Set the number of latch means between the specific bus master and the bus slave to be less than the number of interposed between the other bus master and the bus slave. (18) The signal transmission method for a bus system according to (18).
(23) The signal transmission method for a bus system according to (16), wherein the data transfer between the bus master and the bus slave is a packet system.
(24) The signal transmission method for a bus system according to (23), wherein packet-type data transfer is connectionless.
(25) The bus master includes a first bus master and a second bus master equipped with a cache.
In operation of the arbiter, when the arbiter receives a read request for a specific address range of the bus slave from the first bus master, the arbiter sends the second bus master to the second bus master. Queries whether the cache holds data related to a specific address range of the bus slave. If the second bus master holds the data, the data is bused to the second bus master. The signal transmission method for a bus system according to (19), wherein the operation for writing in the corresponding address range of the slave is set.
[0061]
(26) The bus master, the bus slave, and the latch means are collectively referred to as components, and the upstream and downstream components adjacent to each latch means in the packet transfer direction are the first and second components, respectively. And the 18 consecutive clock cycles in order from the front are called the first, second and third clock cycles,
As an operation of each latch means, each latch means operates to output an acknowledge signal to the first component in the first clock cycle in order to receive a packet from the first component in the second clock cycle. The signal transmission method for a bus system as set forth in (16).
(27) The latch means is equipped with first and second latches,
In operation of the latch means, the latch means outputs an acknowledge signal to the first component in the first clock cycle, and the first clock cycle when no acknowledge signal is input from the second component. Hold the packet to the second component in the first latch at, and in the second clock cycle, retransmit the packet of the first latch to the second component and send the packet from the first component to the second latch. (2) The signal transmission method for a bus system according to (26), wherein an operation of latching to the latch of 2 is set.
(28) As the operation of the latch means, the latch means stops outputting the acknowledge signal to the first component in the second clock cycle, and the acknowledge signal from the second component in the second clock cycle. In the third clock cycle, the first latch packet is sent to the second component while the second latch packet is latched into the first latch, and the first component (27) The signal transmission method for a bus system according to (27), wherein an operation for outputting an acknowledge signal is set.
(29) As the operation of the arbiter, the arbiter defines one of the plurality of first components as a priority component, and in a clock cycle in which no request signal is received from any of the first components, (27) The signal transmission method for a bus system according to (27), wherein the operation for setting the operation to be set to the parking state for issuing the acknowledge signal and for the latch means other than the arbiter to be set to the parking state for the only first component.
[0062]
【The invention's effect】
According to the present invention, even if the distance between the bus master and the bus slave increases, it is possible to avoid a decrease in the operating frequency of the bus system. Bus masters and bus slaves can be widely distributed and arranged on the bus system equipment.
[Brief description of the drawings]
FIG. 1 is a conceptual configuration diagram of a typical conventional bus system.
FIG. 2 is a conceptual configuration diagram of a bus system embodying the present invention.
FIG. 3 is a diagram illustrating parallel transmission of signals in a bus system embodying the present invention.
FIG. 4 is a diagram illustrating signal suspension in a bus system embodying the present invention.
FIG. 5 is a configuration diagram of a bus system in which a distance between a bus master and a bus slave is set in consideration of overall transmission efficiency.
FIG. 6 is a diagram showing the types of packets issued by each pipeline element and their contents.
FIG. 7 is a diagram showing signals issued by the respective latch means.
FIG. 8 is an explanatory diagram showing packet flows in the bus system in order.
9 is an explanatory diagram showing the flow of packets in the bus system in order, following FIG. 8. FIG.
10 is an upstream timing chart for each signal when each latch means has only one latch in both the upstream and downstream directions in the packet transfer model of FIGS. 8 and 9. FIG.
11 is a downstream timing chart for each signal when each latch means has only one latch in both the upstream and downstream directions in the packet transfer model of FIGS. 8 and 9. FIG.
FIG. 12 is an upstream timing chart for each signal when each latch means is equipped with two latches in both the upstream and downstream directions.
FIG. 13 is a downstream timing chart for each signal when each latch means has two latches in both the upstream and downstream directions.
FIG. 14 is an upstream timing chart for each signal in the improved bus system in which the parking technology is applied to the bus system according to FIGS. 12 and 13;
15 is a downlink timing chart for each signal in the improved bus system in which the parking technology is applied to the bus system according to FIGS. 12 and 13. FIG.
FIG. 16 is an example of a timing chart for a plurality of signals related to the operation of the pipeline element.
FIG. 17 is a diagram illustrating signal input / output in each component of the bus system in the case of uplink packet transfer.
FIG. 18 is a block diagram of a pipeline element.
19 is a truth table of the pipeline element of FIG.
20 is a state transition diagram of a pipeline element based on the truth table of FIG.
FIG. 21 is a block diagram of an arbiter.
FIG. 22 is a block diagram of a decoder.
[Explanation of symbols]
19 Bus system
21a-c Bus master (component)
22a-c Bus slave (component)
23 Pipeline element (latching means)
24a, b Arbiter (latch means, component)
25a, b decoder (latch means, component)
26a, b High-speed bus master (component)
27a-f Low-speed bus master (component)
30a, b High-speed bus slave (component)
31 Low-speed bus slave (component)
32a to f Arbiter (latch means, component)
33a, b decoder (latch means, component)
34a, b Bus master (component)
35a, b Bus slave (component)
36a, b Arbiter (latch means, component)
37 Decoder (latch means, component)
43a, 43b Bus master (component)
44a, 44b Bus slave (component)
46 Arbiter (latch means, component)
47 Pipeline element (latch means)
48 Decoder (latch means, component)

Claims (25)

At least one bus master connected to the bus;
At least one bus slave connected to the bus in a total number of three or more including the number of the bus masters, and between the bus master and the bus slaves Latch means for latching and outputting a transmission signal in synchronization with a clock by dividing the bus path into a plurality of sections through the bus path;
Have
The period of the clock is longer than the signal transmission time in the first partition and shorter than the total signal transmission time of the first and second partitions for any adjacent first and second partitions on the bus. Is set ,
The bus master, the bus slave, and the latch means are collectively referred to as components, and components adjacent to the upstream and downstream sides in the packet transfer direction with respect to each latch means are referred to as first and second components, And if we call three consecutive clock cycles in order from the first, the first, second, and third clock cycles,
Each latch means outputs an acknowledge signal to the first component in the first clock cycle to receive a packet from the first component in the second clock cycle;
The latch means has first and second latches, and outputs an acknowledge signal to the first component in the first clock cycle and does not input an acknowledge signal from the second component; In the first clock cycle, the packet to the second component is held in the first latch, and in the second clock cycle, the packet of the first latch is retransmitted to the second component, and the first A bus system, wherein a packet from a component is latched in a second latch .   2. The bus system according to claim 1, wherein the length of each section on the bus is set to be substantially equal.   2. The bus system according to claim 1, wherein the bus has a tree structure as viewed from each bus master and each bus slave. Have at least two bus masters,
2. The bus system according to claim 1, wherein the at least one latch means is an arbiter for signal transmission from the bus master to the bus slave.   2. The bus system according to claim 1, wherein the bus system has at least two bus slaves, and the at least one latch means is a decoder for signal transmission from the bus master to the bus slave.   6. The bus system according to claim 4, wherein the arbiter and the latch means as the decoder are a decoder and an arbiter for signal transmission from the bus slave to the bus master, respectively.   The bus path length between a specific bus master and a bus slave with high demands for high-speed data reading and writing is the bus path between other bus masters and bus slaves with low demands. The number of latch means interposed between the specific bus master and the bus slave is set to be less than the number interposed between the other bus master and the bus slave. 4. The bus system according to claim 3, wherein:   2. The bus system according to claim 1, wherein the data transfer between the bus master and the bus slave is a packet system.   9. The bus system according to claim 8, wherein the packet-based data transfer is connectionless. The bus master includes a first bus master and a second bus master equipped with a cache;
When the arbiter receives a read request for a specific address range of the bus slave from the first bus master, the arbiter transfers the second bus master to the cache of the second bus master. An inquiry is made as to whether or not data relating to a specific address range of the bus and slave is held, and when the second bus master holds the data, the data is sent to the second bus master. 5. The bus system according to claim 4, wherein the address is written in a corresponding address range of the bus slave. The latch means stops outputting the acknowledge signal to the first component in the second clock cycle, and if the acknowledge signal is input from the second component in the second clock cycle, The first latch packet is sent to the second component, while the second latch packet is latched into the first latch and an acknowledge signal is output to the first component. bus system according to claim 1, wherein. The arbiter defines one of a plurality of first components as a priority component, and a parking that issues an acknowledge signal to the priority component in a clock cycle in which a request signal is not received from any of the first components. It is the state, the bus system according to claim 1, characterized in that it is also latched means other than arbiter parking state for only the first component.   2. The bus system according to claim 1, wherein the bus master, the bus slave, and the latch means are manufactured in one chip. In a signal transmission method for a bus system in which at least one bus master and a bus slave are connected via a bus, and the total number of both is three or more,
Interposing at least one latch means in a bus path between the bus master and the bus slave, and dividing the bus path into a plurality of partitions;
The transmission signal is latched and output in the latch means in synchronization with the clock,
The period of the clock is longer than the signal transmission time in the first partition and shorter than the total signal transmission time of the first and second partitions, for any adjacent first and second partitions on the bus. set,
The bus master, the bus slave, and the latch means are collectively referred to as components, and components adjacent to the upstream and downstream sides in the packet transfer direction with respect to each latch means are referred to as first and second components, respectively. And if we call the 18 consecutive clock cycles in order from the front, the first, second, and third clock cycles,
As an operation of each latch means, each latch means operates to output an acknowledge signal to the first component in the first clock cycle in order to receive a packet from the first component in the second clock cycle. Set,
The latch means is equipped with first and second latches, and in operation of the latch means, the latch means outputs an acknowledge signal to the first component and a second in a first clock cycle. When no acknowledge signal is input from the first component, the packet to the second component is held in the first latch in the first clock cycle, and the second component is sent to the second component in the second clock cycle. with retransmitting the packet of the first latches, bus system for signal transmission method characterized by setting the operation of latching a packet from a first component to a second latch. 15. The signal transmission method for a bus system according to claim 14, wherein the lengths of the respective sections on the bus are set substantially evenly. 15. The signal transmission method for a bus system according to claim 14 , wherein the bus has a tree structure as viewed from each bus master and each bus slave. 15. The signal transmission for a bus system according to claim 14 , wherein the number of bus masters is at least two and at least one latch means is an arbiter for signal transmission from the bus master to the bus slave. Method. The number of bus slaves is at least 2,
15. The signal transmission method for a bus system according to claim 14, wherein at least one latch means is a decoder for signal transmission from a bus master to a bus slave. 19. The bus system signal transmission method according to claim 17, wherein the arbiter and the latch means as the decoder are a decoder and an arbiter for signal transmission from a bus slave to a bus master, respectively. The bus path length between a specific bus master and a bus slave with high demands for high-speed data reading and writing, and the bus path between other bus masters and bus slaves with low demands And setting the number of intervening latch means between the specific bus master and the bus slave to be less than the intervening number between the other bus master and the bus slave. 17. A signal transmission method for a bus system according to claim 16, characterized in that: 15. The signal transmission method for a bus system according to claim 14 , wherein the data transfer between the bus master and the bus slave is a packet system. 22. The signal transmission method for a bus system according to claim 21, wherein the packet-based data transfer is connectionless. The bus master includes a first bus master and a second bus master equipped with a cache;
As the operation of the arbiter, when the arbiter receives a read request for a specific address range of the bus slave from the first bus master, the arbiter sends the second bus master to the second bus master. Inquires about whether or not the data related to a specific address range of the bus slave is held in its cache, and if the second bus master holds the data, the second bus 18. The bus system signal transmission method according to claim 17 , wherein an operation for causing the master to write the data in a corresponding address range of the bus slave is set. As the operation of the latching means, the latching means stops outputting the acknowledge signal to the first component in the second clock cycle, and receives the acknowledge signal from the second component in the second clock cycle. If entered, in the third clock cycle, the second latch packet is latched into the first latch and the first latch packet is sent to the second component while being sent to the second component. 15. The signal transmission method for a bus system according to claim 14 , wherein an operation for outputting an acknowledge signal is set. As the operation of the arbiter, the arbiter defines one of a plurality of first components as a priority component, and in a clock cycle in which a request signal is not received from any of the first components, 15. The bus system according to claim 14 , wherein the operation is set to a parking state for issuing an acknowledge signal and a latching means other than the arbiter is set to a parking state for only the first component. Signal transmission method.

Images