JP3651886B2 - Electronic system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique that is useful when applied to, for example, a nonvolatile semiconductor memory such as a flash memory, or a system in which the nonvolatile semiconductor memory is mounted.
[0002]
[Prior art]
Non-volatile semiconductor memory that can electrically erase and write data has a limit on the number of times of rewriting, such as about 100,000 times in flash memory, and there are defective memory cells that cannot be normally written when the number approaches. It will gradually occur.
[0003]
Conventionally, various techniques for dealing with the defective memory cell as described above have been proposed. For example, the techniques disclosed in JP-A-6-180993, JP-A-8-306192, and JP-A-11-134880 are newly applied to the data of a memory cell to be written when data is rewritten. The comparison with the data to be written is performed, and only when these data are different, data erasure and data writing are performed to reduce the actual number of times of writing in each memory cell and to reduce the occurrence of defective memory cells.
[0004]
Japanese Patent No. 2818529 discloses a control that makes the number of writes in each sector equal by address conversion, and prevents writing from being concentrated on only one portion of memory cells. This is to reduce the number of defective memory cells.
[0005]
Japanese Patent Laid-Open No. 6-20483 discloses that a storage area is divided into a main storage area and an auxiliary storage area for replacement in advance, and the use of the main storage area is performed when a defective memory cell is generated in the main storage area. The auxiliary storage area is prohibited and used as an alternative.
[0006]
By the way, a nonvolatile storage device such as a flash ROM is a storage in which firmware is stored in peripheral devices of a computer such as a router, TA (Terminal Adapter), or a web accelerator that accesses a predetermined site on the Internet and prefetches homepage data. Often used as a device. By storing the firmware in a rewritable non-volatile storage device, it is possible to flexibly cope with function upgrades and changes by upgrading peripheral devices in response to computer upgrades and the like.
[0007]
As described above, when the nonvolatile storage device is used for storing firmware, the entire capacity of the storage device is rarely used for storing firmware, and some percent is left unused. Therefore, even if a defective memory cell occurs, if the number is not too large, the defective memory cell is replaced with a memory cell in the remaining area, so that the entire firmware is stored in a valid memory cell. It can be used as usual without any trouble.
[0008]
Also, even when the nonvolatile storage device is used for storing images of a digital camera or for storing music data of a digital music player, it cannot be said that it cannot be used unless the entire area of the nonvolatile storage device is valid. By replacing the memory cell with another memory cell when it occurs, the capacity of the data that can be stored in the storage device is reduced, but other than that, it can be used without causing any trouble. However, if there are too many memory cells to be replaced, it takes time for the replacement process, so that the data reading and writing speeds are out of the allowable range of the main device and can be used normally.
[0009]
[Problems to be solved by the invention]
As described above, even when defective memory cells occur in a small percentage in the nonvolatile memory device, the system does not usually cause a system abnormality. However, the above-mentioned JP-A-6-180993 and JP-A-8- In the technology disclosed in Japanese Patent No. 306192, Japanese Patent Laid-Open No. 11-134880, Japanese Patent No. 2818529, and Japanese Patent Laid-Open No. 6-20483, the system does not inform the user of the occurrence of defective memory cells. Only when the trouble occurs will the user know the occurrence of defective memory cells. This is unfriendly for the user, and there has been a demand for the user to be able to recognize it before he / she has a trouble in exchange.
[0010]
In addition, in the case where a defective memory cell occurs in the main memory block, an alternative to the auxiliary block requires more memory capacity than the user can freely use to secure the auxiliary block, which increases the cost. In addition, there is a waste that a main memory block including a memory cell that can still be used when a defective memory cell is generated is discarded.
[0011]
SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile storage device that can effectively use a storage area without waste and can notify a user of a sign before trouble occurs with a margin for replacement or the like.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a detection means for detecting a defective memory cell in which data cannot be written at the time of data writing in an electronic system equipped with a nonvolatile storage device capable of electrically rewriting data. An address storage means for storing the address of the defective memory cell; and an alternative control means for controlling to write to a memory cell at another address when a write request is made to the address of the defective memory cell, The replacement control unit replaces the defective memory cell for each write unit (for example, for each memory cell, for each byte, for each sector, etc.) , and the replacement control unit is provided outside the nonvolatile memory device. The above-mentioned other addresses that are used as substitutes for defective memory cells are addresses reserved in advance for substitution. It has a structure which is accessible normal address when not in use as an alternative for not scan.
[0013]
According to such means, a defective memory cell is replaced every writing unit, so there is no waste, and it is not necessary to separately install a replacement memory cell in the storage capacity, so that the cost can be reduced. .
[0014]
Further, the present invention comprises a counting means for counting an amount related to the number of defective memory cells, and an abnormality notifying means for outputting a system abnormality signal when the count value of the counting means exceeds a predetermined value. Is.
[0015]
According to such means, before the number of defective memory cells increases and a system abnormality occurs, the precursor can be notified by the output of the abnormal signal. Therefore, it is possible to avoid the inconvenience that the user is alerted before the system abnormality occurs, and the system suddenly becomes abnormal and no relief is provided.
[0016]
Preferably, the counting means counts the number related to the number and distribution of defective memory cells, and when the number of defective memory cells is the same, the number of defective memory cells is more concentrated than when defective memory cells are concentrated. It is better to configure so that the count value becomes larger. That is, when there are defective memory cells at a plurality of addresses and the addresses are continuous, it is preferable to count so that the count value is smaller than when the addresses are discrete.
[0017]
When defective memory cells are concentrated, it is often the case that the portion is specially defective and the other portions are not prone to failure so much. In many cases, the tendency is to reach an overall failure. Therefore, by performing the count as described above, it is possible to notify accurate information as a precursor of system abnormality.
[0018]
More preferably, a notification means for notifying the user of a system abnormality based on a notification from the abnormality notification means, such as an LED for notification by light emission, may be provided. By this notification, the user can take appropriate measures such as refraining from replacing the memory or writing new data into the memory.
[0019]
The nonvolatile storage device as described above is useful when applied to a firmware storage memory of a computer peripheral device. If rewriting of firmware fails due to memory failure, the system may not function at all, but if there is a memory abnormality notification means, the user refrains from rewriting to a new version of firmware by abnormality notification, and a normal nonvolatile storage device Appropriate measures can be taken, such as version upgrade after replacement.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0021]
FIG. 1 is a block diagram showing a schematic configuration of a flash memory 10 which is an embodiment of a nonvolatile memory device of the present invention.
[0022]
A flash memory 10 according to this embodiment includes a memory array 11 in which nonvolatile memory cells having floating gates and control gates are arranged in a matrix, and a word line addressed from the memory array 11 And an address decoder 12 for selecting a bit line, an R / W circuit 13 for reading or writing data in a specified memory cell, and a data writing operation and a verifying operation are repeated for complete data writing. R / W control circuit 14 for erasing, erasing circuit 15 for collectively erasing data in the memory array 11 for each predetermined unit larger than the writing unit, and control of the defective memory cell and its address in addition to the overall control of the flash memory 10 A control circuit 16 that performs management and a defective address that stores an address of the defective memory And 憶部 (address storage means) 17, count on the number of defective memory is provided with a counter 18 such as counting means to be performed.
[0023]
The control circuit 16 receives a read / write command R / W and an address signal ADD from the outside, and performs execution control of data write processing and read processing according to the command. When data writing is normally completed in the writing process, an end signal is output to the outside to notify the completion of writing. In addition, when a defective memory cell is detected, the control circuit 16 stores the defective address or alternative address in the address storage unit 17 or updates the counter 18 according to the address. Further, the control circuit 16 has a function as an alternative control means, and when there is a write request or a data read request to a defective memory cell, the address is converted into an alternative address of a normal memory cell and output to the address decoder 12 Address management such as to do. In addition, when the number of defective memory cells increases and the value of the counter 18 exceeds a predetermined value, an abnormality signal for notifying a system abnormality is output as abnormality notification means.
[0024]
The R / W control circuit 14 also functions as a detecting means for detecting a defective memory cell. When data is not correctly written even if the write operation and the verify operation are repeated a predetermined number of times during data write control, the R / W control circuit 14 A signal indicating the occurrence of the cell is output to the control circuit 16.
[0025]
The address storage unit 17 is configured by using an EEPROM that can be erased by a low voltage with one memory cell unit or byte unit, or by using a partial area of the memory array 11.
[0026]
FIG. 2 is a block diagram showing a configuration example of the router 1 as an example of a system using the nonvolatile storage device according to the present invention.
[0027]
The flash memory 10 described above is applied to a nonvolatile memory or the like that stores firmware in the router 1 and further includes a function for notifying a user according to the present invention in combination with other components in the system. A storage device is realized.
[0028]
That is, in the router 1 of this embodiment, the CPU 2 that performs communication processing and overall control of the apparatus, the RAM 20 that provides a work area to the CPU 2, and the above-described flash that stores firmware executed by the CPU 2 are stored. In addition to the display of the memory 10, the communication interface 30 on the telephone line side and the communication interface 40 on the Ethernet side, in addition to displaying notifications of incoming / outgoing calls, telephone numbers, etc., display regarding defects in the flash memory 10 is performed. The LED 50 is provided as a notification means for performing various notifications such as notification of outgoing / incoming calls and notification of abnormalities in the flash memory 10 by turning on and off.
[0029]
The display on the display relating to the abnormality of the flash memory 10 and the lighting of the LED are executed by the CPU 2 based on the output of the system abnormality signal from the flash memory 10. And since such notifications indicate that the user has an abnormality in the memory, even if a new version of firmware is provided, be careful not to rewrite the data in the flash memory 10 with the new version. Or the flash memory 10 can be prepared for replacement.
[0030]
Next, the writing process of the flash memory 10 will be described with reference to the flowchart of FIG. FIG. 3 is a flowchart of data write processing executed by the control circuit 16 of the flash memory 10.
[0031]
When an address signal ADD and a write command are input from the outside and there is a write request, this write process is started. First, in step S1, the input address is compared with the address in the defective address storage unit 17. As a result, if the input address is not the address of the defective memory cell, the process proceeds to the next step S2. If it is the address of the defective memory cell, a write request is issued again to another address, and the address is used again as the input address. The process from step S1 is executed.
[0032]
When address conversion to a different address is performed, the address management is performed by the control circuit 16 so that the same address conversion is performed and the corresponding data is read out when the data is read next time. Done. In addition, when there is a write request or read request to an alternative address, address management is performed so that another address is used alternatively. Such a control technique is similar to a conventional MMU (Memory Management Unit) and is a well-known technique.
[0033]
Instead of performing the address conversion as described above in the flash memory 10, an MMU may be provided outside the flash memory 10 and performed by the MMU, or may be performed by an external CPU. In that case, when it is determined that the address of the defective memory cell is determined in the determination process in step S1, a defective address signal indicating that the input address is that of the defective memory cell is output to the outside. What is necessary is just to comprise so that MMU and CPU may perform the above address conversion based on this defective address signal.
[0034]
If it is determined in step S1 that the address is not a defective address, the R / W control circuit 14 is caused to perform data write processing in subsequent step S2. Then, when the data write end signal is received from the R / W control circuit 14, the process proceeds to the next step S3.
[0035]
In step S3, the data written in step S2 is read, and in the next step S4, this data is collated. Subsequently, in step S5, if the write data matches the read data as a result of the data collation, the write process is terminated as it is. If the data does not match, the process proceeds to step S6 and the memory cell at the address is stored. The address is stored in the address storage unit 17 as a defective memory cell.
[0036]
Next, in step S7, the counter 18 relating to the defective memory cell is updated, and the process proceeds to step S8.
[0037]
FIG. 4 is a diagram illustrating a method for counting defective memory cells generated in the flash memory 10. For example, as shown in FIG. 4A, the updating of the counter 18 performed in the above step S7 is performed when the memory cells located at discrete positions on the arrangement of the memory array 11 are defective. When a plurality of memory cells are defective in a continuous arrangement as shown in FIG. 4B, the number of defective cells is counted regardless of the number of defective memory cells. The counter 18 is updated so as to be regarded as “1”.
[0038]
Also, the format of storing the addresses of the defective memory cells in the above step S6 is not to store the addresses of the plurality of memory cells individually when a plurality of memory cells arranged in succession are defective. It is only necessary to store the start address and end address of ID and identification information indicating that all of them are defective. By doing so, the capacity required for the address storage unit 17 can be reduced.
[0039]
In step S8, it is determined whether or not the value of the counter 18 is a predetermined number (for example, 10% of the memory capacity). If the value is less than the predetermined number, a write request is made again to another address, and the process from step S1 is started. Re-execute processing. On the other hand, if the value of the counter 18 is equal to or greater than the predetermined number, in step S9, a high level system abnormality signal is continuously output. Then, this writing process is terminated.
[0040]
On the system side, when a system abnormality signal is output from the flash memory 10, the CPU 2 of the router 1 detects it, and under the control of the CPU 2, a display for prompting replacement of the flash ROM and LED lighting are performed.
[0041]
As described above, according to the flash memory 10 of this embodiment, a defective memory cell is replaced for each writing unit, so there is no waste, and a replacement memory cell is separately incorporated in the storage capacity. Since it is not necessary, the cost can be reduced.
[0042]
In addition, since the abnormal signal can be signaled by the output of the abnormal signal before the number of defective memory cells increases and the system malfunctions, the user is alerted before the system malfunctions, and suddenly a system malfunction occurs and relief is performed. It is possible to avoid the inconvenience that there is no way.
[0043]
In addition, even when the number of defective memory cells is the same, an abnormal signal is earlier when the defective memory cells are distributed than when the defective memory cells are concentrated in the arrangement. Since it is output, it is possible to notify more accurate information as a precursor of system abnormality.
[0044]
The user can take appropriate measures such as replacing the flash memory 10 or refraining from upgrading the firmware by displaying a notice of system abnormality on the display unit or lighting the LED.
[0045]
The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, a flash memory or a storage system equipped with the flash memory is exemplified as a nonvolatile storage device, but various other nonvolatile memories such as EEPROM (electrically erasable programmable ROM) capable of erasing data in units of 1 bit or bytes. Can be used. In the embodiment, the nonvolatile memory device of the type having one memory cell as a writing unit is illustrated, but the present invention can be similarly applied to a type having a writing unit of bytes or sectors.
[0046]
Further, the nonvolatile storage device according to the present invention has been described as a flash memory for storing system firmware, but the present invention may be applied to a flash memory that stores general data and frequently rewrites data. It is effective.
[0047]
Further, the counting method for defective memory cells is not limited to that of the above embodiment, for example, the number of occurrences of defective memory cells may be counted as it is regardless of whether it is concentrated or distributed, or When memory cells arranged continuously become defective, a weighted number such as 1/2 or 1/3 of the number may be counted.
[0048]
【The invention's effect】
As described above, according to the present invention, defective memory cells are replaced for each write unit, so there is no waste, and there is no need to separately install a replacement memory cell in the storage capacity. Reduction can be achieved. In addition, since the abnormal signal can be signaled by the output of the abnormal signal before the number of defective memory cells increases and the system malfunctions, the user is alerted before the system malfunctions, and suddenly a system malfunction occurs and relief is performed. There is an effect that it is possible to avoid the inconvenience that there is no way out.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a flash memory according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a system configuration of a router equipped with a nonvolatile storage device according to the present invention.
FIG. 3 is a flowchart showing a procedure of data write processing executed by a control circuit of the flash memory.
FIG. 4 is a diagram illustrating a method for counting defective memory cells generated in a flash memory.
[Explanation of symbols]
1 Router 2 CPU
10 Flash memory (nonvolatile storage device)
11 Memory array 14 R / W control circuit 16 Control circuit 17 Defective address storage unit (address storage means)
18 Counter (Counting means)
50 Display unit 60 LED for notification

Claims (1)

In an electronic system equipped with a nonvolatile storage device that can electrically rewrite data,
Detecting means for detecting a defective memory cell that cannot normally write data at the time of data writing;
Address storage means for storing the address of the defective memory cell;
An alternative control means for substituting a defective memory cell for each write unit by writing data to a memory cell at another address when there is a write request to the address of the defective memory cell;
Counting means for counting the defective memory cells;
An abnormality notification means for outputting a system abnormality signal when the count value of the counting means exceeds a predetermined value;
An informing means for informing a user of a system abnormality by light emission of an LED based on a signal output from the abnormality notifying means,
The counting means counts such that when there are defective memory cells at a plurality of addresses and the addresses are continuous, the count value is smaller than when the addresses are discrete,
The substitution control means is constituted by a CPU provided outside the nonvolatile memory device, and the other address to be substituted for the defective memory cell is not an address reserved in advance for substitution but for substitution. An electronic system characterized by a normal address accessible when not in use.

Images