JP2000231483A - Computer with semiconductor recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a computer with a large-capacity semiconductor recording medium to easily change a program. SOLUTION: A mask ROM 4 is provided with areas 41 to 44 in which a first operating system to make access to an AND type flash memory 5 and a first driver, etc., are stored and the AND type flash memory 5 is provided with areas 51 to 53 in which a second operating system used when a graphic operation panel is normally operated and other systems are stored. A CPU 1 executes the first operating system from the mask ROM 4 when it is started, the first operating system reads the second operating system from the AND type flash memory 5 and executes it in place of itself. Thus, the second operating system is stored in the AND type flash memory 5 which is programmable but not randomly accessible and becomes easily changeable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, FA (F
The present invention relates to a computer having a semiconductor recording medium that requires high reliability, such as a computer that is preferably used in a poor environment such as an application.

[0002]

2. Description of the Related Art In a computer which is suitably used in a bad environment such as a computer for FA use, a semiconductor recording medium having no movable portion is widely used in order to improve reliability. Among the semiconductor recording media, a volatile semiconductor recording medium such as a RAM can be used for work during arithmetic processing. For example, a program (boot loader) that operates when the power is turned on is supplied with power. Since it is necessary to hold the program even when the program is not present, it is necessary to use a nonvolatile semiconductor recording medium.

Here, when a mask ROM is used as a non-volatile semiconductor recording medium, one memory cell can be composed of one transistor element, so that a relatively inexpensive, large-capacity, random-access medium can be realized. However, since data is stored based on the amount of implanted impurities or the pattern itself, there is a problem that rewriting cannot be performed. in this case,
When a problem occurs in a program recorded in the mask ROM or a function required for the program changes, and the program needs to be changed, the mask ROM itself needs to be replaced. As a result, it becomes difficult to quickly respond to a change or a malfunction in the function, and there is a possibility that the reliability of the computer having the semiconductor recording medium is reduced.

On the other hand, in an EEPROM in which one memory cell is constituted by two elements, random access and rewriting are possible, but it is difficult to increase the capacity. As a result, it may be difficult to improve the functions of the computer having the semiconductor recording medium.

In recent years, even for a computer for FA, for example, a GUI (Graphical User Interface) using a high-precision liquid crystal display device and a touch panel is often used, and is inexpensive, large-capacity and rewritable. There is a need for a nonvolatile semiconductor recording medium.

As one of the semiconductor recording media meeting this demand, there is an AND type flash memory in which one memory cell is realized by one element. In the above-mentioned AND type flash memory, at the time of erasing or writing, electric charges are transferred between the substrate and the floating gate, and the electric charges move in the tunnel oxide film. On the other hand, in the state where no voltage is applied or during reading, the tunnel oxide film insulates the substrate from the floating gate and retains electric charge.

[0007]

However, the above A
Since the ND type flash memory has a low random access speed, the ND type flash memory is manufactured so as to perform block access, and there is a problem that the ND type flash memory cannot be accessed when the CPU is started.

More specifically, in the above-mentioned AND type flash memory, since the random access speed is slow due to the configuration of the memory cell, the AND type flash memory is provided with a block access instruction in units of a predetermined length of sector. In order to execute the instruction, an address counter for sequentially generating an address following the designated start address, an input buffer for storing sequentially input write data, and an output buffer for storing sequentially read data are provided. It has. As a result, the number of address designations is reduced, and access to each memory cell and external input / output are performed in parallel, so that the apparent access speed at the time of block access of the flash memory can be improved.

However, the CPU is a conventional RAM or RO.
The program is set so as to read and execute the program while performing random access so that the program can be accessed from the M or the like. The CPU immediately after startup cannot access the AND flash memory.

As a result, in the conventional graphic operation panel, if the PLC control program can be stored in the mask ROM, the control program can be stored in the mask ROM. Or storing it.

However, the graphic operation panel is
When used in an application, it is often used in a poor environment such as near a control target, and if a recording device having a movable portion is used, the reliability of the graphic operation panel may be reduced.

On the other hand, in FA applications, since the scale and number of control objects are large, the effect of a defect in the control program is large, and the defect needs to be corrected immediately. In such a case, it is necessary to replace the mask ROM itself when changing the program, and it is difficult to change the program. As a result, the reliability of the graphic operation panel may be reduced.

Further, in order to prevent the occurrence of a defect, it is necessary to perform sufficient verification, so that the time and cost required for the verification become enormous, and there is a possibility that the response to a new device and the addition of a function may be delayed. is there.

The present invention has been made in view of the above problems, and an object of the present invention is to realize a computer having a large-capacity semiconductor recording medium in which a program can be easily changed.

[0015]

According to a first aspect of the present invention, there is provided a computer having a semiconductor recording medium storing a main program to be executed in normal processing after startup. A mask ROM storing a boot loader that is smaller in program size than the main program and executed by an arithmetic processing unit at the time of startup; and wherein the semiconductor recording medium is accessed in units of sectors of a predetermined length. When the boot loader is a flash memory, the boot loader accesses the AND-type flash memory at the time of startup, causes the arithmetic processing unit to execute the main program instead of itself, and when the replacement of the main program is instructed, Rewriting the main program stored in the AND flash memory It is characterized.

In the above configuration, the arithmetic processing unit reads and executes the boot loader from the mask ROM at the time of startup, so that the AND type flash memory is accessed in sector units, and the mask R which can be accessed immediately after startup is provided.
Despite not being able to access by random access in the same way as OM, the main program can be read,
The main program can be executed. Further, since the capacity of the AND flash memory can be relatively easily increased, the main program can be stored even if the memory capacity of the main program increases with the increase in functions required during normal processing. As a result, for example, in a computer having a semiconductor recording medium that is preferably used when high reliability is required, such as a computer for FA used in a poor environment, the operation immediately after the startup of the arithmetic processing unit is performed. Without changing, the recording capacity of the entire semiconductor recording medium including the mask ROM and the AND flash memory can be increased.

The boot loader has a smaller program size than the main program, and can use the same program irrespective of the type of the main program normally used. As a result, a sufficiently verified program can be used as a boot loader, and the reliability of the computer can be improved.

In addition, the boot loader is used when the main program needs to be rewritten, for example, when a problem occurs in the main program or when a function necessary for the main program changes, for example, by key input or communication. When a user's instruction is received, for example, the AND flash memory is accessed to rewrite the main program. Therefore, the main program can be changed more easily than when the entire main program is stored in the mask ROM. As a result,
The failure of the main program and the change of the required function can be promptly dealt with, and the reliability of the computer can be further improved.

Since the boot loader can rewrite the program in the AND type flash memory,
For example, if a program, such as a driver for a newly added device, which has not been sufficiently verified and a defect is easily detected is stored in an AND flash memory, the mask ROM that requires replacement of a chip for rewriting will be used. Programs can be removed and new devices can be added without compromising computer reliability.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
The following is a description based on FIG. That is, the graphic operation panel according to the present embodiment includes:
For example, an input / output device having no moving parts, such as a liquid crystal display device and a touch panel formed on a display screen, is provided.
It is suitably used when stable operation in a poor surrounding environment is required, such as when displaying information on a control target device received from a controller (PLC) and transmitting an operator's instruction to the PLC.

The graphic operation panel includes, for example,
As shown in FIG. 1, a CPU 1 serving as an arithmetic processing unit and a CP 1
RA used as a work area when U1 operates
M2 and an external interface unit 3 for communicating with the outside, such as an SIO (Serial Input / Output) port, an IrDA (Infrared Data Association) port, or an Ethernet (trademark: Xerox Corporation) port
And a mask ROM 4 referred to by the CPU 1 at startup. Further, the graphic operation panel according to the present embodiment is provided with an AND flash memory 5 as a rewritable nonvolatile recording medium. The AND type flash memory 5 has a low cost and is easy to increase the memory capacity as compared with other types of flash memories such as an OR type. Further, unlike a floppy disk drive or the like, the AND type flash memory 5 does not have a movable part, and therefore is inferior. It can operate stably even in a surrounding environment.

More specifically, in the above-mentioned AND type flash memory, at the time of erasing or writing, electric charges are transferred between the substrate and the floating gate, and the electric charges move through the tunnel oxide film. On the other hand, in the state where no voltage is applied or during reading, the tunnel oxide film insulates the substrate from the floating gate and retains electric charge.

In order to increase the recording capacity of the above-mentioned AND type flash memory, it is necessary to increase the degree of integration, and it is required to reduce the thickness of the tunnel oxide film. Then, it becomes difficult to hold the charge for a long time. In particular, in the above-mentioned AND type flash memory, when erasing or writing, electric charges move in the tunnel oxide film, and there is a possibility that the tunnel oxide film is deteriorated. Therefore, the thickness of the tunnel oxide film needs to be set in consideration of deterioration. Furthermore, since the thickness of the tunnel oxide film varies due to process variations at the time of manufacturing, setting a low margin lowers the yield. As a result, the thickness of the tunnel oxide film cannot be set too small in order to improve the reliability of information recording.

Here, in the AND type flash memory 5 according to the present embodiment, the film thickness of the tunnel oxide film is set to be relatively thin in order to achieve a large capacity.
Compared with the ROM, the probability of occurrence of initial failure, deterioration with time, or failure due to repeated access is higher. Therefore, as shown in FIG.
The flash memory 5 has a redundant configuration, and each sector S has, for example, an error correction code (EC) in the data area DA in addition to the data area DA for storing data.
C), for example, a control area CA in which control information of the sector S is stored.

The AND flash memory 5
Has a large recording capacity of, for example, 64 Mbits or 256 Mbits or more, but has a low random access speed. Therefore, in the AND type flash memory 5, an instruction for block access is provided in units of a predetermined length of sector S, and in order to execute the instruction, an address subsequent to the designated start address is sequentially generated. An address counter, an input buffer for storing sequentially input write data, and an output buffer for storing sequentially read data are provided. As a result, the number of address designations is reduced, and access to each memory cell and external input / output are performed in parallel, so that the apparent access speed at the time of block access of the AND-type flash memory 5 is reduced. Can be improved.

In the AND type flash memory 5 illustrated in FIG. 2, the memory capacity (the capacity of the entire data area DA) is 6
4 Mbits, the sector length (the length of the data area DA) is set to 512 bytes, and the length of the control area CA is set to 16 bytes. In this case, the total number of sectors is 163
The sector address for specifying each sector S is 0000H to 3FFFFH (H at the end of the number or 0x at the beginning indicates that the number is a hexadecimal number).
Range. At the time of shipment, it is guaranteed that 16057 sectors out of 16384 sectors can be used.

In the AND type flash memory 5, unlike a random access semiconductor recording medium such as the RAM 2 or the mask ROM 4, access such as reading or writing is performed in units of the sector S as described above. A serial read instruction r1 for reading and writing the entire sector S and a program instruction p1 are provided. Further, a serial read instruction r2 and a program instruction p3 are provided for accessing the control area CA. In the instruction r2 · p3, since only the control area CA is read, the application speed is different from that of the data area DA, and the access speed to the control area CA, which may be accessed independently, is set higher than when reading / writing the entire sector S. Can also be improved. In each of the program instructions p1 and p3, erasing is performed before writing. However, an erasing instruction e1 for performing erasing only, and a program instruction p2 used when erasing has been performed in advance and writing without erasing are also included. Stipulated.

Here, the CPU 1 according to the present embodiment accesses a predetermined address at the time of start-up such as when power is turned on so that it can be used even with a conventional random-accessible semiconductor recording medium, and then stores it at the address. It is designed to execute a program stored in a recording medium while randomly accessing the recording medium in accordance with the data (for example, an instruction or an interrupt vector).
Therefore, in the graphic operation panel according to the present embodiment, when the power is turned on, the mask ROM 4 is arranged in the memory space accessed by the CPU 1 at the time of startup, and when the power is turned on, the CPU 1 accesses the memory in the same manner as the conventional method.
However, the program in the mask ROM 4 can be executed without any problem.

As shown in FIG. 1, the mask ROM 4 includes a first OS storage area 41 in which a first operating system (OS) operating at the time of startup is stored, and
When a driver for accessing the ND type flash memory 5 or a normal access to the AND type flash memory 5 cannot be normally performed, an essential first driver such as a driver for accessing the external interface unit 3 used instead is stored. A first driver storage area 42, AND
System processing program storage area 43 in which a program for operating data in the flash memory 5 as a file is stored, and a second OS rewrite in which a rewrite program for rewriting a second OS stored in the AND flash memory 5 is stored. And a program storage area 44. Note that the first OS corresponds to a boot loader described in the claims, and the second OS corresponds to a main program.

In each of the areas 41 to 44, essential programs at the time of startup are stored after being sufficiently verified.
The insufficiently verified program is stored in the AND-type flash memory 5 even if it is a driver of the external interface unit 3 such as a driver for an IrDA port.
Note that the mask ROM 4 only needs to be able to store only essential programs at the time of startup, that is, from when the power is turned on to when a second OS described later is read from the AND-type flash memory 5 and executed. The size of the program can be reduced as compared with the second OS operating at the time of operation, and sufficient verification can be performed. Also,
The mask ROM 4 may store data that does not change, such as fonts.

On the other hand, the AND flash memory 5 stores a second driver that may be changed, such as an indispensable driver or a driver whose verification is insufficient among the drivers of the external interface unit 3. A driver storage area 51, a second OS storage area 52 for storing a second OS executed in place of the first OS during normal operation of the graphic operation panel, and various programs executed on the second OS are stored. Application storage area 53 is provided.

The programs in these areas 51 to 53 are often larger in size than the programs in the mask ROM 4 in order to realize various functions required for the graphic operation panel. The verification period may be short to accommodate the external interface unit 3 or the like. However, as described later, each program in the AND-type flash memory 5 is stored in the mask ROM 4.
Is different from the program in the first OS, while the AND flash memory 5 is mounted on the graphic operation panel, the first OS
Can be changed using. Therefore, even if a defect is found in the program or a required function is changed, it is possible to quickly respond. As a result, new functions can be added or functions can be changed without lowering the reliability of the graphic operation panel.

As described above, in the AND flash memory 5, bit errors are accumulated because the tunnel oxide film is deteriorated by repeated access. Therefore, even if an error correction code is used, it is difficult to maintain the reliability of data stored in the same position at a high level for a long time. Therefore, when the driver in the first driver storage area 42 according to the present embodiment detects an error when accessing the sector S in the AND-type flash memory 5, the error amount falls within a range that can be corrected by the error correction code. While registering the sector S as a bad sector,
The corrected correct information is stored in the spare sector SS. If the sector S to be accessed is a bad sector, the driver
To the spare sector SS that substitutes Thereby, the reliability of the AND flash memory 5 can be maintained at a high level for a long time.

Specifically, as shown in FIG.
The D-type flash memory 5 includes a data sector area 61 for storing a data sector DS to be accessed when no defect occurs, and a spare sector S for replacing the defective sector.
It is divided into a spare sector area 62 where S is stored, and a bad sector table area 63 where a table sector TS indicating the correspondence between the data sector DS and the spare sector SS is recorded.

In the following, when each data sector DS is specified, the data sector number d is assigned in order from the beginning of the data sector area 61 (smallest sector address).
In the case where each spare sector SS is identified by n, the spare sector is identified by a spare sector number sn which is sequentially assigned from the beginning of the spare sector area 62. On the other hand, in the bad sector table area 63, a table sector number tn for specifying each table sector TS is assigned in order from the end of the bad sector table area 63. Further, for distinguishing each sector S, for example, data sectors DS data sector number dn is 1, such as data sectors DS _1, representing assigned the respective sector numbers dn · sn · tn subscripts.

In the bad sector table area 63,
At a position corresponding to the data sector number dn of each data sector DS, a spare sector number (corresponding information) sn of the spare sector SS that substitutes each is stored. In the present embodiment, since the spare sector number can be represented by 2 bytes, each table sector TS can store 256 spare sector numbers. Thus, for example, (in this example, 1) spare sector number sn corresponding to the data sector DS ₂ is stored in the second table sector TS ₁ (from the third byte to the fourth byte). In this example, the other data sectors DS, not a bad sector, the remaining bytes of the table sector TS ₁ (in this example, 0) value indicating that the spare sectors SS does not correspond is stored ing.

The control area CA of each sector S includes a pass / fail identification area 71, a sector number area 72, an erase count area 73, a use identification area 74, a control area ECC area 75, and a data area ECC area shown in FIG. 76.

The pass / fail identification area 71 stores a pass / fail identification code indicating whether or not the sector S is a bad sector. Each pass / fail identification code is determined, for example, by setting the hamming distance between the codes to be sufficiently long, so that even if a bit error occurs at the time of access, the respective codes can be distinguished. For example, in the present embodiment, the pass / fail identification area 71 is set to have a 3-byte width of the first to third bytes, and each pass / fail identification code is a code indicating normality, a code indicating initial failure, and a 2-bit error. , A code indicating a one-bit error, and a code indicating that writing or erasing has failed.

The sector number area 72 is set to have a 2-byte width of the fourth and fifth bytes in order to store the sector number dn or tn.
, The data sector number dn is stored, and in the case of the table sector TS, the table sector number tn is stored. On the other hand, when the spare sector SS replaces the data sector DS, the data sector number dn of the data sector DS, and when the spare sector SS replaces the table sector TS, the table sector number of the table sector TS (sector information). tn is stored. Also, the spare sector SS
However, if none of the sectors S has been replaced, a value indicating that the sector S has not been replaced is stored.

Further, the erase count area 73 stores the erase count (rewrite count). In the AND-type flash memory 5, the number of times that normal rewriting is guaranteed is, for example, about 100,000 times. If rewriting is performed beyond this number, normal rewriting is not guaranteed. Therefore, the count value stored in the erase count area 73 is increased each time rewriting is performed, and if the count value exceeds a predetermined value, replacement with a spare sector SS is performed. Can be prevented in advance. Further, the application identification area 74 stores a code indicating whether the sector S is a data sector DS, a spare sector SS, or a table sector TS.

As described above, in the AND flash memory 5, a bit error occurs due to an initial failure or a change with time. Therefore, even if a bit error occurs, the control area CA
And the data sector DS are encoded with an error correction code (ECC). In the control area CA, a control area ECC area 75 is provided to store the respective error correction codes.
And a data area ECC area 76.
The control area ECC area 75 is set to have a two-byte width of the ninth and tenth bytes, and each of the areas 71 to 74 is set.
Is stored. Data area E
The CC area 76 is 4 bytes from the 13th to the 16th bytes.

In this embodiment, for example, an error correction code capable of correcting a one-bit error and detecting a two-bit error is used, and the first driver storage area 42 shown in FIG.
When accessing the sector S, the driver detects a bit error with reference to the ECC areas 75 and 76, and, while the generated bit error can be detected,
The correct information of the sector S is stored in the spare sector SS of the sector S, and the table sector TS related to the sector S (or the spare sector SS) is updated to store the correct spare sector number sn.

Here, if a bit error is detected in the data sector DS (or its spare sector SS), the head of the spare sector area 62 (the smaller physical address)
Vacant spare sectors SS are searched in order from
The found spare sector SS replaces the data sector DS (or the spare sector SS). When a bit error is detected in the table sector TS (or its spare sector SS), a vacant spare sector SS is searched in order from the end of the spare sector area 62, and the found spare sector SS is used as the table sector TS.
(Or its spare sector SS).

In the present embodiment, in the spare sector area 62, the spare sector SS of the data sector DS and the spare sector SS of the table sector TS are sequentially assigned from different ends, so that the vacant spare sector SS Arranged in between. As a result, unlike the case where a dedicated spare sector area is provided for each, the spare sector area 62 can be used up only by searching for an empty spare sector SS from each end regardless of the location of the defective sector. .

As described above, the driver stored in the first driver storage area 42 replaces the defective sector with the spare sector SS.
In the AND-type flash memory 5 in which it is difficult to predict which sector S allocated to which physical address is defective, even if a defective sector S occurs, the logical sector is The stored information can be retained without loss.

Further, since the data sector DS is arranged at the address corresponding to the logical sector, there is no need to refer to a table or the like when converting the logical address to the address of the data sector DS. Therefore, if the data sector DS corresponding to the logical address is normal, it is only necessary to access the data sector DS, and there is a case where the access speed is not substituted despite the replacement of the defective sector by the spare sector SS. Can be kept equal. Further, since the number of sectors to be accessed is small, the possibility of encountering a bad sector is low, and the access speed can be improved as compared with the case of referring to the table.

If the data sector DS is a bad sector, the table sector TS allocated to the address corresponding to the data sector DS is accessed, and if the spare sector number sn is obtained, the data is transferred to the spare sector SS of the data sector DS. Can access. In this case, three sectors S
The access speed can be improved as compared with the case where the address of the table sector TS is obtained using a conversion table or the like. In this embodiment, whether each sector S is a defective sector, a search for an empty spare sector SS, or a search for a spare sector SS of a table sector TS described later is performed in the control area of the AND-type flash memory 5. Since the determination is made by reading only the CA, the access can be performed at a higher speed than in the case where the entire sector S is read.

On the other hand, if the table sector TS is a bad sector, the spare sector SS of the table sector TS is searched from the spare sector area 62, and the data sector D
A spare sector number sn indicating the spare sector SS corresponding to S is obtained. In this case, the access speed is lower than when the data sector DS is normal, or when the data sector DS is defective, compared to when the table sector TS is normal. However, even in the case of the AND type flash memory 5 used in the present embodiment, the ratio of defective sectors is sufficiently low at 0.2% or less of all the sectors S, so that the data sector DS
Both the table sector TS and the table sector TS are extremely unlikely to be bad sectors, and in most cases, a high access speed can be maintained.

In this embodiment, the table sector T
The spare sectors SS of S are arranged in order from one end of the spare sector area 62, and information indicating a substitute table sector TS such as a table sector number tn is stored in the control area CA of each spare sector SS. .
Therefore, in order from the end, each spare sector SS
Just read the control area CA of the table sector T
The S spare sector SS can be searched at high speed.

The operation when the power is turned on to the graphic operation panel in the above configuration will be described below with reference to the flowchart shown in FIG. That is, in step 1 (hereinafter, abbreviated as S1), when the power is turned on to the graphic operation panel, the CPU 1 accesses the mask ROM 4 according to a predetermined procedure and accesses the first OS storage area 41. ,
The programs stored in the first driver storage area 42 and the file system processing program storage area 43 are executed. As a result, the first OS can directly access each logical sector in the AND-type flash memory 5 or access data stored in each logical sector as a file in the file system. Further, it becomes possible to access other start-up devices such as an SIO port.

Further, in S2, the first OS searches for a bootable device in accordance with a predetermined priority, and when the highest priority bootable device is other than the AND-type flash memory 5 (NO in S3). In the case), in S4, the second OS is read from a discovered device such as an SIO port of the external interface unit 3. Even if a certain device is set as a priority, if the device cannot be accessed correctly, for example, when the AND flash memory 5 is not mounted or when the data structure shown in FIG. 1 is not stored, The next priority device is searched.

If the AND type flash memory 5 has priority and can be accessed normally (at S3,
In the case of YES), in S5, for example, a predetermined setting file is read from the AND-type flash memory 5,
By searching for a specific data structure that has been determined in advance,
The second driver storage area 5 is stored in the AND type flash memory 5.
Check whether 1 exists. If it exists (YES in S5), the second driver is read from the area 51 in S6, and a new device such as the IrDA port of the external interface unit 3 becomes accessible. In this case, the first OS is S7
In steps S9 to S9, a device to be started is selected as in steps S2 to S4.

Here, for example, a driver, such as a driver for an IrDA port, which is determined at the time of manufacture that there is a possibility that correction is necessary is stored in the AND-type flash memory 5, so that, for example, a defect is found. Even when the driver is changed, for example, when the driver is changed or when the function is changed, the driver can be changed more easily than when the driver is stored in the mask ROM 4. Therefore, the optimum driver can always be used without deteriorating the reliability of the graphic operation panel.

A device accessed by the first driver;
Alternatively, as a result of searching for a device to be accessed by the second driver, if it is determined that the device is to be started from the AND-type flash memory 5 (in the case of YES in S8), the first O
S determines in S10, for example, the second OS storage area 52
, The second OS is read into the RAM 2, and in S11,
For example, the second OS is started instead of the first OS by instructing the CPU 1 to restart without erasing the contents of the RAM 2. As a result, the graphic operation panel
For example, normal processing such as monitoring and control of a PLC (not shown) can be executed.

Here, since the second OS is stored in the AND flash memory 5 having a larger memory capacity than the mask ROM 4, for example, control processing and display processing are performed.
The normal processing of the graphic operation panel becomes complicated,
Even if the OS is enlarged, there is no problem and AND
Can be stored in the flash memory 5. Further, since the AND flash memory 5 is rewritable, even when a defect is found or a function required for the graphic operation panel is changed, it can be changed more easily than when storing it in the mask ROM 4.

Specifically, as shown in FIG. 6, S in FIG.
Prior to reading of the second OS shown in FIG. 10, when a rewrite of the second OS is instructed by, for example, a user operation or communication (S21), the first OS and the first OS are read.
The second OS rewrite program that operates on the above-described program, in S22, includes the SIO port of the external interface unit 3 and the like.
Data indicating a new second OS is read from another device and stored in the second OS storage area 52. Here, the first
The OS can access the AND-type flash memory 5 by the AND-type flash memory driver of the first driver, and can also access other devices by the other first and second drivers. Therefore, the first OS can rewrite the second OS without any trouble. When the second driver is rewritten, the same processing as in S21 and S22 is performed before the reading of the second driver shown in FIG.
Reads a new second driver and stores it in the second driver storage area 51 of the AND flash memory 5.

Thus, the AND type flash memory 5
Even if a problem is found in the program inside, if the function required for the graphic operation panel changes, or if the device connected to the graphic operation panel is changed, rewriting the above program will It is possible to realize a highly reliable and high-performance graphic operation panel as compared with the case where all are stored in the mask ROM 4.

In this embodiment, in addition to the driver for accessing the AND type flash memory 5 in the first driver storage area 42 of the mask ROM 4, for example,
Although the case where an IO port driver and the like are stored has been described, the present invention is not limited to this. For example, A
If the ND type flash memory 5 is detachable and can be written by another device, only the driver for the AND type flash memory may be stored. Further, the number of the second OSs and the second drivers is limited, and when one of the plurality of OSs should be selected, only the driver for the AND type flash memory is stored in the mask ROM 4 and the AN
If all of them are stored in the D-type flash memory 5 and one of them is selected at the time of use, the second OS and the second driver can be changed only by the driver for the AND-type flash memory. In particular, when the number of changes is limited to the time of shipment or installation, if the remaining second OS and second driver are deleted, a decrease in the memory efficiency of the AND flash memory 5 can be prevented.

However, program defects are difficult to predict and cannot be stored in advance. Also,
A device capable of writing to the AND flash memory 5 is not always located near the graphic operation panel. Therefore, in the case described above, the change of the program that can be dealt with is limited, and there is a possibility that the trouble when the change is increased. Therefore, as in the present embodiment, it is better to store at least one fully verified driver in addition to the driver for the AND flash memory. Thus, the AND flash memory 5 can be rewritten by data from an external device accessed by the driver, or can be directly started from the external device. As a result, it is possible to more easily and reliably deal with program changes that include defects,
The reliability of the graphic operation panel can be improved.

[0060]

According to the first aspect of the present invention, a computer comprises:
As described above, the program size is smaller than that of the main program, the mask ROM storing the boot loader executed by the arithmetic processing unit at the time of startup, and the AND which is accessed in units of sectors of a predetermined length and stores the main program. The boot loader accesses the AND-type flash memory at the time of startup, causes the arithmetic processing unit to execute the main program instead of itself, and instructs to replace the main program. In this configuration, the main program stored in the AND flash memory is rewritten.

Therefore, even though the main program is stored in the AND-type flash memory that cannot be accessed immediately after the operation processing unit is started, the main program can be executed. Recording capacity can be increased without the need to improve the function of a computer having a semiconductor recording medium that is preferably used when high reliability is required, such as a computer for FA used in a poor environment. It has the effect of being able to.

The boot loader can correct the main program in the AND-type flash memory when the main program needs to be rewritten, so that the main program can be changed more easily than when the entire main program is stored in the mask ROM. become. Further, since the boot loader is smaller than the main program and can be shared regardless of the type of the main program, the boot loader can be sufficiently verified. As a result, it is possible to quickly cope with a failure of the main program or a change in a necessary function, and to improve the reliability of a computer having a semiconductor recording medium.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, wherein AND
FIG. 2 is a block diagram showing a configuration of a main part of a graphic operation panel having a type flash memory.

FIG. 2 is an explanatory diagram showing the AND flash memory before formatting.

FIG. 3 is an explanatory diagram showing a data structure stored in the AND flash memory after formatting.

FIG. 4 is an explanatory diagram showing a sector structure in the AND flash memory after formatting.

FIG. 5 is a flowchart illustrating an operation at the time of starting the graphic operation panel.

FIG. 6 is a flowchart showing an operation of rewriting a second operating system in the graphic operation panel.

[Explanation of symbols]

 Reference Signs List 1 CPU (arithmetic processing unit) 4 Mask ROM 5 AND-type flash memory

Claims (1)

[Claims] 1. A computer having a semiconductor recording medium storing a main program to be executed in normal processing after startup, wherein the computer has a program size smaller than the main program and stores a boot loader executed by an arithmetic processing unit at startup. The semiconductor recording medium is an AND-type flash memory accessed in units of a sector of a predetermined length, and the boot loader accesses the AND-type flash memory at the time of start-up. A computer that causes an arithmetic processing unit to execute the main program instead of itself and, when instructed to replace the main program, rewrites the main program stored in the AND flash memory.