JP2009026062A - Memory controller, memory system, and memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller, a memory system and a memory control method suitable for storing data whose rewrite frequency is high and data whose rewrite frequency is low in a flash memory and a nonvolatile memory whose random access is possible. <P>SOLUTION: A memory controller 1 controls access to a flash memory 2 and a nonvolatile RAM 3 on the basis of a logical address applied from a host system 4. A logical group including a plurality of sector regions and a logical block including one or more logical groups are formed. A plurality of logical group data storage areas are secured in the nonvolatile RAM 3. Also, the corresponding relation of the logical groups and the logical group data storage areas and the priority order of the data of each logical group data storage area are managed. Data from the host system 4 are written in the logical group data storage area corresponding to the data. The data of the logical group data storage area are transferred to a corresponding physical block in the flash memory 2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory controller, a memory system, and a memory control method for controlling access to a flash memory and a nonvolatile memory based on a logical address in units of sectors given from a host system.

As a conventional storage device, a storage device provided with a flash memory (card type memory), a non-volatile memory (NVRAM) capable of random access, and a RAM (volatile RAM) is known. In this storage device, data that needs to be stored even after the power is turned off is distributed and stored in a nonvolatile memory and a flash memory. That is, system data before update is stored in the flash memory, and update information (difference data) is stored in the nonvolatile memory when the system data read from the flash memory to the RAM is updated. Therefore, if a power failure occurs before the updated system data copy stored in the RAM is stored in the flash memory, the update information stored in the nonvolatile memory is read out from the flash memory. By reflecting the previous system data, the system data before power-off is reconstructed (see, for example, Patent Document 1).
JP 2006-350572 A

  In the above storage device, the system data actually used is read from the flash memory and stored in the RAM, and when updating the system data stored in the RAM, the update information is sequentially stored in the nonvolatile memory (NVRAM). Yes. If an unexpected power failure occurs, the latest (updated) system data is restored based on the system data saved in the flash memory and the update information saved in the nonvolatile memory at the time of restart. . However, since this storage device targets specific data (system data) as data to be stored in the non-volatile memory, the data is destroyed due to power interruption and cannot be used or the latest data cannot be restored. The main purpose is to avoid doing this. Therefore, it is not suitable when there is data other than that (such as user data) that has a high rewrite frequency.

  Accordingly, an object of the present invention is to provide a memory controller, a memory system, and a memory control method that are suitable for storing frequently rewritten data and low data in a flash memory and a random accessible nonvolatile memory. .

  In order to achieve the above object, the present invention relates to a flash memory in which stored data is erased in units of physical blocks and a non-volatile memory capable of random access based on logical addresses in units of sectors given from a host system. A memory controller for controlling access is provided. The memory controller includes: a logical group forming unit that forms a logical group including a plurality of sectors having consecutive logical addresses; and a logical group data storage area for storing data corresponding to the logical group in the nonvolatile memory A first area management means for managing a correspondence relationship between the logical group and the logical group data storage area, and a logical block forming means for forming a logical block including one or a plurality of logical groups Second area management means for managing the correspondence between the logical block and the physical block in the flash memory; and priority order management means for managing the priority order of data stored in each logical group data storage area And the data given from the host system, the logical group corresponding to the data Writing means for writing to the logical group data storage area in a flexible relationship, and data stored in the logical group data storage area for the flash corresponding to the logical block to which the logical group corresponding to the data belongs Data transfer means for transferring to a physical block in the memory. When there is no logical group data storage area corresponding to the logical group corresponding to the data given from the host system, the first area management means corresponds to the data given from the host system. The logical group data in which data stored by the logical group data storage area or the data transfer means not corresponding to any logical group is transferred to a physical block in the flash memory with respect to a logical group A new storage area is allocated. The data transfer means does not have the logical group data storage area corresponding to the logical group corresponding to the data given from the host system, and does not correspond to any logical group. When there is no storage area, the lowest priority data managed by the priority management means is transferred to the physical block in the flash memory.

In the above memory controller, the number of logical groups included in the logical block is preferably 2 ⁿ (n is an integer of 1 or more).

  The present invention also provides a memory system comprising the memory controller described above, a flash memory in which stored data is erased in units of physical blocks, and a non-volatile memory capable of random access.

  Furthermore, the present invention provides a memory control method for controlling access to a flash memory in which stored data is erased in units of physical blocks and a non-volatile memory capable of random access, based on logical addresses in units of sectors given from a host system. Is provided. The memory control method includes: a logical group forming step for forming a logical group including a plurality of sector areas having consecutive logical addresses; and a logical group data storage for storing data corresponding to the logical group in the nonvolatile memory A first area management step for securing a plurality of areas and managing the correspondence between the logical group and the logical group data storage area, and a logical block formation step for forming a logical block including one or a plurality of logical groups A second area management step for managing the correspondence between the logical block and the physical block in the flash memory; and priority management for managing the priority of data stored in each logical group data storage area Step and data given by the host system before the corresponding data A write step for writing to the logical group data storage area corresponding to the logical group; and data stored in the logical group data storage area in correspondence with the logical block to which the logical group corresponding to the data belongs. A data transfer step of transferring to a physical block in the flash memory. In the first area management step, when there is no logical group data storage area corresponding to the logical group corresponding to the data given from the host system, the data corresponding to the data given from the host system is stored. The logical group data in which the logical group data storage area not corresponding to any logical group or the data stored by the data transfer step is transferred to a physical block in the flash memory with respect to the logical group A new storage area is allocated. In the data transfer step, the logical group data that does not correspond to any logical group and does not have the logical group data storage area corresponding to the logical group corresponding to the data given from the host system When there is no storage area, the data having the lowest priority managed by the priority management step is transferred to the physical block in the flash memory.

  In the above memory control method, when a plurality of physical blocks in the flash memory are allocated to one logical block, the data transfer step includes physical data in the flash memory in which data having consecutive logical addresses are different. It is preferred that the data be transferred so that it is allocated to the block.

  According to the memory controller, the memory system, and the memory control method according to the present invention, data given from the host system is temporarily stored in a non-volatile memory that can be randomly accessed. The priority of the data stored in the nonvolatile memory is managed by the priority management means. When new data cannot be stored in the nonvolatile memory, the data with the lowest priority is flashed. Transferred to physical block in memory. On the other hand, since the priority of data that is frequently rewritten is unlikely to be the lowest priority, it is highly likely that it is stored in the non-volatile memory without being transferred to the flash memory. Therefore, for data that is frequently rewritten, data stored in the nonvolatile memory is rewritten, and it is not necessary to frequently rewrite data stored in the flash memory. For this reason, the number of rewrites of data stored in the flash memory is reduced, and the life of the flash memory can be improved.

  A memory controller, a memory system, and a memory control method according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the memory system 100 includes a flash memory 2, a nonvolatile RAM 3, and a memory controller 1 that controls the flash memory 2 and the nonvolatile RAM 3.

  The memory system 100 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the memory system 100, and the like. The host system 4 is various information processing apparatuses such as a personal computer and a digital still camera that process various kinds of information such as characters, sounds, and image information.

  As shown in FIG. 1, the memory controller 1 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC block 11, and a ROM (Read Only Memory). ) 12 and a RAM interface block 16. The memory controller 1 is connected to the flash memory 2 and the nonvolatile RAM 3 via internal buses 14 and 15, respectively. The memory controller 1 constituted by these functional blocks is integrated on one semiconductor chip. Hereinafter, each functional block will be described.

  The host interface block 7 exchanges data, address information, status information, external commands, etc. with the host system 4. The external command is a command for the host system 4 to instruct the memory system 100 to execute processing. Data or the like supplied from the host system 4 to the memory system 100 is taken into the memory system 100 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the memory system 100 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The work area 8 is a work area that temporarily holds data necessary for controlling the flash memory 2 and is configured by a plurality of SRAM (Static Random Access Memory) cells. The work area 8 stores, for example, an address conversion table indicating the relationship between logical blocks and physical blocks.

  The buffer 9 holds the data read from the flash memory 2 or the nonvolatile RAM 3 until the host system 4 can receive the data. Further, data to be written to the flash memory 2 or the nonvolatile RAM 3 is held until each memory is in a writable state.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14. Here, the internal command is a command for the memory controller 1 to instruct the flash memory 2 to execute processing. The flash memory 2 and the nonvolatile RAM 3 operate in accordance with an internal command given from the memory controller 1. The RAM interface block 16 writes data to the nonvolatile RAM 3 or reads data from the nonvolatile RAM 3 via the internal bus 15. At this time, an address signal and various control signals are supplied to the nonvolatile RAM 3 via the internal bus 15.

  The ECC block 11 generates an error correction code for the data to be written to the flash memory 2 and detects an error included in the read data based on the error correction code added to the data read from the flash memory. Detect and correct.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure by the microprocessor 6. For example, a program that defines a procedure of processing (described later) for allocating an area of the nonvolatile RAM 3 to user data given from the host system 4 is stored.

  The microprocessor 6 controls the overall operation of the memory controller 1 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set defining various processes from the ROM 12 and causes the flash memory interface block 10 to execute various processes.

  The flash memory 2 is a NAND flash memory. The NAND flash memory is a non-volatile memory, and includes a register and a memory cell array composed of a plurality of memory cells. The memory cell array includes a plurality of memory cell groups and word lines. Here, the memory cell group is a group in which a plurality of memory cells are connected in series. Each word line is for selecting a specific memory cell in the memory cell group. Data is written or read between the selected memory cell and the register via the word line, that is, data is written from the register to the selected memory cell or data is transferred from the selected memory cell to the register. Reading is performed. That is, data input to the flash memory 2 is written to the memory cell via the register, and data read from the memory cell is output from the flash memory 2 via the register.

  In the NAND flash memory, a data read operation and a data write operation are performed in units of pages, and a data erase operation is performed in units of blocks (physical blocks). As shown in FIG. 2, the physical block is composed of a plurality of pages. The configuration of the physical block of the flash memory has changed as the capacity of the flash memory has increased. In this embodiment, one page is composed of a user area 21 of 4 sectors (2048 bytes) and a redundant area 22 of 64 bytes, and one physical block (block 0, block 1,. .) Uses a flash memory composed of 64 pages. Although not used in this embodiment, one page is composed of one sector (512 bytes) user area 21 and 16 bytes of redundant area 22, and one physical block is composed of 32 pages. There are also known flash memories.

  The user area 21 is an area for storing data given from the host system 4. The redundant area 22 is an area for storing additional data such as an error correcting code (ECC), logical address information, and a block status (flag).

  The logical address information is information for specifying a logical block corresponding to the physical block in which the logical address information is written. For a physical block that is not associated with any logical block, that is, a physical block that does not have a corresponding logical block, no logical address information is written in the redundant area 22 of the block. Therefore, by determining whether or not the logical address information is stored in the redundant area 22, it is possible to determine whether or not the physical block including the redundant area 22 is an empty block.

  The correspondence relationship between the logical block and the physical block is usually managed by an address conversion table (second area management means). This address conversion table is created based on the logical address information stored in the redundant area 22 of each physical block.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area 22. Note that a block status (flag) indicating a defective block is written in the defective block with an initial defect before shipment.

  The non-volatile RAM 3 is a memory that can retain stored contents even when power supply is interrupted, and is a memory that can be randomly written and read (Random Access Memory). In addition, since the nonvolatile RAM 3 can overwrite data, it is not necessary to perform data writing and erasing separately as in a flash memory. In general, the capacity of the nonvolatile RAM 3 is smaller than that of the flash memory 2. Examples of the nonvolatile RAM 3 include FeRAM (Ferroelectric Random Access Memory) also called FRAM (registered trademark), and MRAM (Magnetic Random Access Memory).

  Next, the configuration of the nonvolatile RAM 3 will be described with reference to FIG. As shown in FIG. 3, the nonvolatile RAM 3 according to the present embodiment includes a management area 31 (first area management means, priority order management means) and a logical group data storage area 32. The management area 31 is an area for managing logical groups and priorities of data stored in the logical group data storage area 32. The management area 31 stores a highest-order storage area 31A for storing the highest-priority area, and a table for managing logical groups and priorities of data stored in the logical group data storage area 32. And a table storage area 31B.

  The logical group data storage area 32 is an area for storing data given from the host system 4. In this embodiment, the logical group data storage area 32 is divided into 16 areas assigned with area numbers # 0 to # 15. Each area has a capacity of 32 kB (kilobytes). Each storage area stores data belonging to one logical group.

  Next, the relationship between logical sectors, logical groups, and logical blocks will be described with reference to FIG. The address space (logical address space) on the host system 4 side is managed by an LBA (Logical Block Address) 41 that is a serial number assigned to an area divided in units of sectors (512 bytes).

  In the present embodiment, a 64-sector area with continuous LBAs is managed as a logical group, and a logical group number (LGN) 42 is assigned to each logical group. For example, as shown in FIG. 4, the 64 sector area of LBA # 0 to # 63 belongs to the logical group of LGN # 0, and the 64 sector area of LBA # 64 to # 127 belongs to the logical group of LGN # 1. belong to. Similarly, for the areas after LBA # 128, an area of 64 sectors is managed as a logical group. An area included in one logical group has a capacity of 32 kB (logical group forming means).

  In this embodiment, an area of 256 sectors in which LBAs are continuous is managed as a logical block, and a logical block number (LBN) 43 is assigned to this logical block. For example, the 256 sector area of LBA # 0 to # 255 belongs to the logical block of LBN # 0, and the 256 sector area of LBA # 256 to # 511 belongs to the logical block of LBN # 1. Similarly for the area below LBA # 512, the area of 256 sectors is managed as a logical block (logical block forming means).

  As described above, the logical block of LBN # 0 is composed of logical groups of LGN # 0 to # 3, and the logical block of LBN # 1 is composed of logical groups of LGN # 4 to # 7. That is, one logical block corresponds to four logical groups.

  FIG. 5 shows an LBA, a logical group number (LGN), a logical block number (LBN), and the like that are displayed in bits (binary number). The symbol “*” represents each bit. For convenience of illustration, only the upper 4 bits and the lower 12 bits are shown, and the intermediate bits are omitted. In FIG. 5, the entire bit string represents LBA 41. The bit string excluding the lower 8 bits represents the logical block number (LBN) 43, and the bit string excluding the lower 6 bits represents the logical group number (LGN) 42. The lower 8 bits represent a logical sector number (LSN) 44 that is a serial number of each sector in each logical block. The logical sector number (LSN) 44 takes values from # 0 to # 255. Further, the lower 2 bits of the logical group number (LGN) 42 (2 bits of the 7th and 8th bits counted from the least significant bit side of the LBA) are the group numbers in the logical block (group numbers within the logical block). LBIGN) 45. The logical block group number (LBIGN) 45 takes values of # 0 to # 3.

As described above, in the present embodiment, the number of logical groups included in one logical block is set to 2 ⁿ (n is an integer of 1 or more, and n = 2 in the above example). 2 ⁿ represents a power of 2. With this setting, it is possible to determine the logical block group number (LBIGN) based on the values of some of the bits when the LBA is displayed in bits (binary display). Note that the logical group and the logical block may be allocated to an area in the same LBA range without dividing the area in the logical block into a plurality of logical groups.

  Next, the logical address used in this embodiment will be described.

  In a general flash memory system, in a physical block assigned to one logical block, LBAs are continuous in 256 physical sector areas to which physical sector numbers (PSNs) # 0 to # 255 are assigned. The logical block data is stored in order. In other words, the value of the logical sector number (LSN) 44 of the data stored in the physical sector area matches the value of the physical sector number (PSN) of the physical sector area. Actually, since writing is performed in units of pages, it can be said that the logical page number (LPN) matches the physical page number (PPN). Each page includes four physical sector areas. Accordingly, the logical page number (LPN) and the physical page number (PPN) take values from # 0 to # 63.

  On the other hand, in this embodiment, it is possible to change the order of data written to the physical block in units of logical groups. That is, the values of the logical sector number (LSN) of data stored in the physical sector area and the physical sector number (PSN) of the physical sector area do not necessarily match. Actually, since writing is performed in units of pages, it can be said that the logical page number (LPN) and the physical page number (PPN) do not always match. More specifically, as shown in FIG. 6, data belonging to LGN # 0 (LSN # 0 to # 63) in LBN # 0 is stored in PSN # 128 to # 191 in PBA # 0. . Data belonging to LGN # 1 (LSN # 64 to # 127) in LBN # 0 is stored in PSN # 192 to # 255 in PBA # 0. However, data of logical groups belonging to the same LBN is stored in a PBA physical block corresponding to the logical block of the LBN.

  Therefore, in the flash memory 2, the logical address of the data and the data are stored by writing the information indicating the correspondence relationship between the logical group and the physical group in the first page in each physical group or the redundant area 22 of each page. You can see the correspondence with the physical address. For example, the intra-logical block group number (LBIGN) may be written in the first page in each physical group or the redundant area 22 of each page. Here, the physical group is an area in the physical block divided into the same number of areas as the logical group included in the logical block. In this embodiment, the physical pages of PPN # 0 to # 15, PPN # 16 to The physical page # 31, the physical pages PPP # 32 to # 47, and the physical pages PPP # 48 to # 63 are managed as physical groups, respectively.

  Next, an overview of data read and write processing based on commands from the host system 4 will be described.

  When reading data from the memory system 100, a read command designating a logical address of the desired data (more specifically, an LBA or LBA range corresponding to the read data) is given to the memory controller 1 from the host system 4. . The microprocessor 6 receives this command via the host interface block 7 and determines the LGN of the logical group including the area to be accessed from the designated LBA. The microprocessor 6 first checks whether or not the data corresponding to the LGN is stored in the nonvolatile RAM 3, and if it is stored, reads this data to the buffer 9 via the RAM interface block 16. If the data corresponding to the LGN is not stored in the nonvolatile RAM 3, the data stored in the flash memory 2 is read into the buffer 9 via the flash memory interface block 10. The read data is provided to the host system 4 via the host interface block 7. That is, data corresponding to the same LBA (LGN) may be stored in both the flash memory 2 and the nonvolatile RAM 3, and the data contents may be different between the flash memory 2 and the nonvolatile RAM 3. In this case, as will be described later, since the data in the nonvolatile RAM 3 is newer, the data in the nonvolatile RAM 3 is read preferentially. Note that when the ECC block 11 reads data from the flash memory 2, the ECC block 11 stores the data based on the error correction code added to the read data (the error correction code written in the redundant area 22). Detect and correct contained errors.

  On the other hand, when data is written to the memory system 100, a write command designating the data to be written from the host system 4 and its logical address (more specifically, the LBA or LBA range indicating the write destination) is sent to the memory controller. Is given to 1. The data given from the host system 4 is once held in the buffer 9. The microprocessor 6 receives this command via the host interface block 7 and determines the LGN of the logical group including the area to be accessed from the designated LBA. As will be described later, when an area corresponding to this LGN is allocated in the nonvolatile RAM 3, the microprocessor 6 writes the data in that area, and when not allocated, an area corresponding to this LGN. Is newly allocated and the data is written in the newly allocated area. This writing process will be described in more detail below with reference to FIGS.

  7 to 9 show a management table 50 for managing the correspondence between each area in the nonvolatile RAM 3 (logical group data storage area 32) and the logical group, and the priority order of data stored in each area. Is shown. The management table 50 includes the area number 51 (# 0 to # 15) of each area in the logical group data storage area 32, the LGN 52 of the logical group assigned to each area, and the data stored in each area. It is a table showing the correspondence with the priority link 53, and is stored in the table storage area 31B.

  The priority link 53 is used to indicate the priority order of data stored in each area. The value of the priority link 53 indicates the area number of the area having the next highest priority after the area corresponding to the priority link. In addition to the management table 50, the area number of the area where the highest priority (highest) data is stored is stored in the highest storage area 31A of the nonvolatile RAM 3. On the other hand, the data with the lowest priority (lowest order) is data corresponding to the area number whose priority link value is NULL.

  For example, in the state of FIG. 7, # 3, which is the highest area number, is stored in the highest storage area 31A. The priority link of the highest region number # 3 indicates # 6. Therefore, the second area is the area of area number # 6. Similarly, the third area is the area of the area number # 10 indicated by the priority link of the second area number # 6. In the same manner, the fourth to the lowest order are instructed. The priority link of the lowest area (area number # 9) has a NULL value because there is no area to be indicated.

  Processing when a new logical group is allocated to the logical group data storage area 32 in the nonvolatile RAM 3 will be described with reference to FIGS. Assuming that the area of the non-volatile RAM 3 is in the state as shown in FIG. 7, in this state, the area included in the logical group of LGN # 33 (area corresponding to all or part of the logical group) Suppose that the host system gives a command for instructing the writing of data. As shown in the flowchart of FIG. 10, first, it is determined whether or not an area corresponding to the logical group of LGN # 33 is allocated in the nonvolatile RAM 3 (logical group data storage area 32). In the state of FIG. 7, the logical group of LGN # 33 is not assigned to any of the area numbers # 0 to # 15 (S10: No). Further, there is no area (empty area) that does not correspond to any logical group (S20: No). The step is abbreviated as “S”.

  Therefore, first, the data of area number # 9 (data corresponding to the logical group of LGN # 155) which is the lowest priority area in FIG. 7 is transferred to the physical block in the flash memory 2 via the buffer 9. (S30, data transfer means). That is, the data stored in the area of area number # 9 is read to the buffer 9, and the data read to the buffer 9 is written to the physical block in the flash memory 2 as the data of the logical block to which the logical group of LGN # 155 belongs. More specifically, the microprocessor 6 first determines the LBN of the logical block to which the logical group of the LGN # 155 belongs from the upper bits excluding the lower 2 bits of the LGN of the data (FIG. 5). Next, it is determined whether or not a physical block corresponding to the obtained logical block of LBN exists in the flash memory 2. If there is a physical block corresponding to the logical block of the LBN and there is a free area in which one group of data (32 kB data corresponding to one logical group) is written in the physical block, the data is written in the free area. When there is no empty area or when there is no physical block corresponding to the logical block of the LBN, the empty block is searched and data is written into the empty block. The ECC block 11 generates an error correction code for the data to be written. The generated error collection code is written in the redundant area 22. Also, logical address information indicating the correspondence between physical blocks and logical blocks, and information indicating the correspondence between physical groups and logical groups in each physical block are also written in the redundant area 22.

  Next, a logical group of LGN # 33 is newly allocated to the area of area number # 9 where the data has been transferred to the flash memory 2 as described above (S40). FIG. 8 shows a state in which the logical group is newly assigned. More specifically, the LGN value corresponding to the area number # 9 is overwritten with # 33 and the priority link value is overwritten with # 3. This priority link value # 3 is the highest area number stored in the highest storage area 31A (FIG. 7). The highest storage area 31A is overwritten with the area number # 9 of the area to which the logical group of LGN # 33 is assigned. At this time, the priority link is changed when a new logical group LGN # 33 is assigned. In FIG. 7, the area whose priority is one level higher than the lowest is the area where the priority link indicates the lowest area number # 9, that is, the area of area number # 12. Since the new logical group LGN # 33 is assigned to the area of the lowest area number # 9 in FIG. 7, the area of the area number # 12 becomes the lowest priority area as shown in FIG. Therefore, the priority link corresponding to the area number # 12 is set to NULL.

  Next, it is determined whether or not data corresponding to the logical group of LGN # 33 is stored in the flash memory 2, and if stored (S50: Yes), LGN # 33 stored in the flash memory 2 is stored. Is transferred to the area of area number # 9 in the nonvolatile RAM 3 (logical group data storage area 32) via the buffer 9 (S60). At this time, all of the data corresponding to LGN # 33 stored in the flash memory 2 may be transferred to the nonvolatile RAM 3, or only the data that is not to be rewritten may be transferred to the nonvolatile RAM 3. This is because the data to be rewritten is given from the host system 4. In this way, all or part of the data corresponding to the newly assigned logical group is transferred from the flash memory 2 to the nonvolatile RAM 3, so that the entire data belonging to the corresponding logical group is stored in each area of the nonvolatile RAM 3. Will be memorized. For this reason, it is not necessary to manage differential data (updated data or unupdated data) in a state where only a part of a certain logical group is updated and the remaining part is not updated. It can be simplified.

  On the other hand, when the data corresponding to the logical group of LGN # 33 is not stored in the flash memory 2 (S50: No), the process of S60 is skipped. At this time, data corresponding to the erased state of the flash memory is written in an area in which data given from the host system 4 in the area of area number # 9 is not written.

  Data given from the host system 4 is written in the area of area number # 9 of the nonvolatile RAM 3. That is, the data instructed to be written in the area included in the logical group of LGN # 33 is written in the area of area number # 9 in the logical group data storage area 32 (S70, writing means).

  On the other hand, the processing when the logical group including the area designated as the write destination by the host system 4 has already been assigned to any area in the nonvolatile RAM 3 (logical group data storage area 32) is as follows. . This will be described with reference to FIGS. Here, as an example, a case will be described in which the data of the logical group of LGN # 0 assigned to the area of area number # 0 is updated in the state of FIG.

  In the state shown in FIG. 8, the host system 4 gives a command instructing an area included in the logical group of LGN # 0 (an area corresponding to all or part of the logical group) as a data write destination. In this case, since the logical group of LGN # 0 is assigned to the area of area number # 0 (S10: Yes), the data given from the host system 4 is written to the area of area number # 0, and this area number # 0 By writing data to the area, the priority of the data stored in the area of area number # 0 becomes the highest. Accordingly, the information regarding the priority link held in the management table 50 and the highest-level storage area 31A is changed. First, as shown in FIG. 9, the area number # 0 of the area to which the logical group of LGN # 0 is assigned is written in the highest-order storage area 31A. In the management table 50, the area number # 9 of the area that is the highest in FIG. 8 is written as the value of the priority link corresponding to the area number # 0. In the state of FIG. 8, the priority link of the area of area number # 12 is NULL, the priority link of the area of area number # 0 is # 12, and the priority link of the area of area number # 13 is # 0. Therefore, it can be determined that the priorities are set in the order of # 13 → # 0 → # 12 (area number). However, since region number # 0 is the highest priority in FIG. 9, the priority is # 13 → # 12 (region number). In order to reflect this change, the priority link of area number # 13 is rewritten to # 12 (S80).

  Thereafter, in the area of area number # 0 in the nonvolatile RAM 3 (logical group data storage area 32), the data given from the host system 4 (data instructed with the area included in the logical group of LGN # 0 as the write destination) ) Is actually written (S90, writing means). At this time, the data given from the host system 4 is overwritten on the data stored in the area of area number # 0.

  On the other hand, the logical group including the area instructed by the host system 4 as the data write destination is not assigned to an area in the nonvolatile RAM 3 (logical group data storage area 32) (S10: No). If the logical group data storage area 32 of the nonvolatile RAM 3 includes an area (empty area) that does not correspond to any logical group (not allocated) (S20: Yes), the following processing is performed. . That is, the free space is allocated to the logical group including the area designated as the write destination by the host system 4, and the management table 50 and the data stored in this area have the highest priority. The information on the priority link held in the highest level storage area 31A is changed (S100). The process for changing the information about the priority link is the same as described above. Then, data given from the host system 4 is written in the allocated area (S110).

  According to the memory controller, the memory system, and the memory control method according to the above-described embodiments, the lowest priority data managed by the priority management means is transferred to the physical block in the flash memory. On the other hand, since the priority of data that is frequently rewritten is unlikely to be the lowest priority, the data that is frequently rewritten is highly likely to be stored in a nonvolatile memory (nonvolatile RAM). Therefore, data that is frequently rewritten is often stored in a non-volatile memory (non-volatile RAM), so that data is often rewritten on the non-volatile memory (non-volatile RAM). Therefore, the necessity for frequently rewriting data in the flash memory is reduced, and the life of the flash memory can be improved.

  In addition, since data can be overwritten in a nonvolatile memory (nonvolatile RAM), it is not necessary to separately write and erase data as in a flash memory, and data can be rewritten efficiently.

  The memory controller, the memory system, and the memory control method according to the present invention are not limited to the above-described embodiments, and various modifications and improvements can be made within the scope described in the claims. For example, in the above-described embodiment, the number of logical (physical) sector areas in the logical (physical) group is 64, but the number is not limited to this number, and may be 32, for example.

  In the above-described embodiment, the memory system 100 includes only one flash memory. However, a memory system including a plurality of flash memories may be used. In this example, a physical block is allocated from each of a plurality of flash memories to one logical block. That is, a plurality of physical blocks are assigned to one logical block. In such a configuration, when data is transferred from the nonvolatile RAM to the flash memory, data having consecutive logical addresses is sequentially allocated to the plurality of physical blocks. In this way, since different flash memories can be accessed in parallel, the access speed can be increased.

1 is a block diagram schematically showing a memory system according to an embodiment of the present invention. Explanatory drawing which shows notionally the storage area of the flash memory used by this Embodiment. Explanatory drawing which shows notionally the memory area of the non-volatile RAM used by this Embodiment. Explanatory drawing which shows the relationship between a logical sector, a logical group, and a logical block. Explanatory drawing which shows LBA, the logical group number, the logical block number, etc. which were bit-displayed (binary number display). Explanatory drawing which shows the condition where data are written in a physical block in the state in which the physical sector number and the logical sector number were switched in a logical group unit. Explanatory drawing which shows the table for managing the correspondence of each area | region in a non-volatile RAM, and a logical group, and the priority of the data memorize | stored in each area | region. FIG. 8 is an explanatory diagram illustrating a state in which a new logical group is assigned to an area in which data with the lowest priority is stored in the table of FIG. 7. FIG. 9 is an explanatory diagram showing a state in which data corresponding to a logical group number # 0 assigned to an area number # 0 is rewritten in the table of FIG. 10 is a flowchart showing data writing processing.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory controller, 2 ... Flash memory, 3 ... Nonvolatile RAM, 4 ... Host system, 6 ... Microprocessor, 7 ... Host interface block, 8 ... Work area 9 ... Buffer, 10 ... Flash memory interface block, 11 ... ECC block, 12 ... ROM, 13 ... External bus, 14, 15 ... Internal bus, 16 ... RAM Interface block 21 ... User area 22 ... Redundant area 31 ... Management area 31A ... Highest storage area 31B ... Table storage area 32 ... Logical group data storage area 41 ... LBA, 42 ... LGN, 43 ... LBN, 44 ·· LSN, 45 ··· LBIGN, 50 ··· management table, 51 ... region number, 52 ... LGN, 53 ... priority link, 100 ... memory system.

Claims (5)

A memory controller for controlling access to a flash memory in which stored data is erased in units of physical blocks and a non-volatile memory capable of random access based on a logical address in units of sectors given from a host system,
Logical group forming means for forming a logical group including areas of a plurality of sectors in which the logical addresses are continuous;
First area management means for securing a plurality of logical group data storage areas for storing data corresponding to the logical groups in the nonvolatile memory and managing the correspondence between the logical groups and the logical group data storage areas When,
Logical block forming means for forming a logical block including one or a plurality of logical groups;
Second area management means for managing the correspondence between the logical block and the physical block in the flash memory;
Priority management means for managing the priority of data stored in each logical group data storage area;
Writing means for writing data given from the host system to the logical group data storage area in a correspondence relationship with the logical group corresponding to the data;
Data transfer means for transferring data stored in the logical group data storage area to a physical block in the flash memory corresponding to the logical block to which the logical group corresponding to the data belongs;
When there is no logical group data storage area corresponding to the logical group corresponding to the data given from the host system, the first area management means corresponds to the data given from the host system. The logical group data in which data stored by the logical group data storage area or the data transfer means not corresponding to any logical group is transferred to a physical block in the flash memory with respect to a logical group Allocate new storage space,
The data transfer means does not have the logical group data storage area corresponding to the logical group corresponding to the data given from the host system, and does not correspond to any logical group. A memory controller for transferring data having the lowest priority managed by the priority management means to a physical block in the flash memory when there is no storage area. The memory controller according to claim 1, wherein the number of logical groups included in the logical block is 2 ⁿ (n is an integer of 1 or more).   A memory system comprising: the memory controller according to claim 1; a flash memory in which stored data is erased in units of physical blocks; and a non-volatile memory capable of random access. A memory control method for controlling access to a flash memory in which stored data is erased in units of physical blocks and a non-volatile memory capable of random access, based on a logical address in units of sectors given from a host system,
A logical group forming step of forming a logical group including a plurality of sector areas in which the logical addresses are continuous;
A first area management step for securing a plurality of logical group data storage areas for storing data corresponding to the logical groups in the nonvolatile memory and managing a correspondence relationship between the logical groups and the logical group data storage areas When,
A logical block forming step of forming a logical block including one or a plurality of logical groups;
A second area management step for managing the correspondence between the logical block and the physical block in the flash memory;
A priority management step for managing the priority of data stored in each logical group data storage area;
A step of writing data given from the host system to the logical group data storage area corresponding to the logical group corresponding to the data;
A data transfer step of transferring data stored in the logical group data storage area to a physical block in the flash memory corresponding to the logical block to which the logical group corresponding to the data belongs;
In the first area management step, when there is no logical group data storage area corresponding to the logical group corresponding to the data given from the host system, the data corresponding to the data given from the host system is stored. The logical group data in which the logical group data storage area not corresponding to any logical group or the data stored by the data transfer step is transferred to a physical block in the flash memory with respect to the logical group Allocate new storage space,
In the data transfer step, there is no logical group data storage area corresponding to the logical group corresponding to the data given from the host system, and the logical group data does not correspond to any logical group A memory control method comprising: transferring data having the lowest priority managed by the priority management step to a physical block in the flash memory when there is no storage area. When a plurality of physical blocks in the flash memory are allocated to one logical block,
5. The memory control method according to claim 4, wherein in the data transfer step, data transfer is performed such that data having consecutive logical addresses are allocated to physical blocks in the flash memory different from each other.

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