JP3651449B2 - Silicon carbide semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high breakdown voltage vertical MOSFET (field effect transistor) using silicon carbide.
[0002]
[Prior art]
Silicon carbide (hereinafter referred to as SiC) has a large band gap and is a chemically stable material. Therefore, silicon carbide can operate in a higher temperature environment than silicon (hereinafter referred to as Si). Expected and research is underway.
[0003]
Particularly in the power electronics field, with the demand for higher power and higher frequency of power converters and the like, expectations for semiconductor switching elements that operate at high speed with high breakdown voltage and low loss are increasing. Although the performance of existing devices made of Si is being further improved, the performance of such devices is limited by the physical theoretical limits of Si, and no significant improvement in device performance can be expected. It is becoming. On the other hand, research is being conducted to realize a high-performance power semiconductor element that far exceeds the limit of Si using SiC.
[0004]
It is known that when the MOSFET is formed of SiC, the avalanche breakdown electric field can be made ten times higher than that of silicon, so that the resistance of the drift layer of the element can be reduced by about two orders of magnitude. As a result, the on-resistance can be lowered and the power loss can be reduced.
[0005]
In the conventional Si device, heat generation due to generated loss during operation cannot be ignored. Also in the above-described power converter and the like, it is necessary to provide a cooling mechanism for suppressing this, and the apparatus has been enlarged due to the cooling fins and the cooling mechanism. In SiC, these cooling mechanisms can be greatly reduced in size and simplified. In automotive applications, the reduction in size and weight of power converters also leads to improved fuel efficiency, and is expected to be effective in terms of environmental conservation.
[0006]
The vertical MOSFET is an important device in considering application of SiC to a power semiconductor device. Since the MOSFET is a voltage-driven device, the elements can be driven in parallel and the drive circuit is simple. Moreover, since it is a unipolar device, high-speed switching is possible.
[0007]
As a SiC power MOSFET in the prior art, for example, one described in Japanese Patent Laid-Open No. 2000-200907 (hereinafter referred to as a conventional example) is known. As a feature of the conventional example, a low concentration (high resistance) surface layer is formed on the surface of the N-drift region where the P-type base region is not formed. A gate electrode is formed on the surface layer via a gate insulating film. In the conventional example, the presence of this surface layer has the effect of improving the reliability of the gate insulating film.
[0008]
[Problems to be solved by the invention]
When the electric field applied to the gate insulating film is Ei and the electric field applied to the semiconductor is Es at the interface between the gate insulating film and the semiconductor, the relationship shown in the equation (1) is established.
[0009]
εi · Ei = εs · Es (1)
Here, εi is the dielectric constant of the insulating film, and εs is the dielectric constant of the semiconductor.
[0010]
When the equation (1) is modified, the following equation (2) is obtained.
[0011]
Ei / Es = εs / εi (2)
Here, the expression (2) is compared in the case of silicon and SiC.
[0012]
If εs = 11.7 (Si) and εs = 10.0 (4H—SiC as an example) and the insulating film is a silicon oxide film (hereinafter referred to as SiO ₂ ), the dielectric constant is εi = 3.8. /Es=3.1 (Si), Ei / Es = 2.6 (SiC). That is, in the conventional structure, a much larger electric field is applied to the gate insulating film than the semiconductor portion.
[0013]
Furthermore, since the maximum electric field Esmax of the semiconductor is Esmax = 3 × 10 ⁵ [V / cm] (Si) and Esmax = 3 × 10 ⁶ [V / cm] (for example, 4H—SiC), the maximum electric field of the insulating film Eimax may be Eimax = about 9 × 10 ⁵ [V / cm] (Si), Eimax = about 7 × 10 ⁶ [V / cm] (for example, 4H—SiC).
[0014]
Considering that the dielectric breakdown voltage of SiO ₂ is on the order of 10 ⁶ [V / cm], in SiC, a large electric field close to the dielectric breakdown voltage is applied to the gate insulating film before the avalanche breakdown occurs inside the semiconductor. It will be. Alternatively, before the avalanche breakdown occurs, the gate insulating film (oxide film) breaks down, and a desired breakdown voltage cannot be obtained.
[0015]
Furthermore, in a normal power device, when an avalanche current flows, it is required to withstand a constant current. However, in a conventional SiC-MOSFET, the avalanche resistance is defined by the dielectric breakdown of the gate insulating film, which is very small. There was a problem that it was value.
[0016]
The present invention has been made in order to solve such a conventional problem, and an object of the present invention is to improve silicon breakdown voltage and to make avalanche resistance sufficiently large. It is to provide a semiconductor device.
[0017]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a second conductivity type base region formed on a first main surface of a first conductivity type silicon carbide semiconductor substrate, and a first conductivity type formed in the base region. In a MOSFET having a type source region and a drift region of a first conductivity type formed in a part of the silicon carbide semiconductor substrate, and a gate electrode formed on the base region via a gate insulating film,
The gate insulating film is formed such that a part of the entire region in contact with the silicon carbide semiconductor substrate of the first conductivity type is thinner than the other region, and the part of the region is smaller than the other region. A silicon carbide semiconductor device characterized by having a small area .
[0018]
【The invention's effect】
According to the present invention, it is possible to effectively weaken the electric field at the point where the electric field applied to the gate insulating film becomes the strongest, and it is possible to realize a silicon carbide MOSFET having a high withstand voltage. Further, since the breakdown voltage of the element is determined by the avalanche breakdown at the PN junction between the base region and the substrate, there is an effect that a silicon carbide MOSFET having a high avalanche resistance can be realized.
[0019]
Further, by adopting the manufacturing method described in the first embodiment, the electric field can be effectively relaxed, and a highly reliable inversion type silicon carbide power MOSFET with high breakdown voltage can be realized. Furthermore, in the silicon carbide semiconductor device described in the second embodiment, a storage silicon carbide power MOSFET with high reliability and high breakdown voltage can be realized for the same reason.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the first conductivity type is described as “N type”, and the second conductivity type is described as “P type”, but these may be reversed.
[0021]
(First embodiment)
A silicon carbide semiconductor device according to a first embodiment of the present invention will be described. FIG. 1 shows a device cross-sectional structure of the silicon carbide semiconductor device according to the first embodiment. In the figure, a state in which two unit cells are connected in parallel is shown. Actually, a plurality of unit cells are connected in parallel.
[0022]
First, the configuration of the device will be described. An N− type SiC epi layer is formed on the N + type SiC substrate 1. Here, since the N− type SiC epi layer functions as a drift layer as a device, it will be referred to as an N− type drift layer 2. The N + type SiC substrate 1 and the N− type drift layer 2 constitute the silicon carbide semiconductor substrate described in the claims.
[0023]
The impurity concentration of the N- type drift layer 2, for example 1E14~1E17cm ^{- 3} holds true, the thickness, several tens of [mu] m is true of several [mu] m. P-type base regions 3 a to 3 c are formed on the surface of the N − -type drift layer 2.
[0024]
On the inner surface of the P-type base region 3, N + type source regions 4a to 4c are formed. Gate electrodes 6a and 6b are formed on the surface of the N − type drift layer 2 and the surfaces of the P type base regions 3a to 3c via gate insulating films 5a and 5b. A part of the surface of the N + source region 4 is connected to the source electrode 8.
[0025]
As a feature of the configuration of the present embodiment, regions 10 a and 10 b where the gate insulating film 5 is locally thin are present on a part of the surface of the N − -type drift layer 2. A drain electrode 9 is formed on the back side of the N + type SiC substrate 1. The gate electrode 6 and the source electrode 8 are electrically insulated by interlayer insulating films 7a and 7b.
[0026]
Although not shown, the base region 3 is connected to the source electrode 8 at a desired location in the depth direction of the paper, and the potential is fixed to the source potential.
[0027]
Next, the planar layout structure of the device according to the present embodiment will be described with reference to FIGS. In FIG. 7, since the entire surface is covered with the source electrode 8 originally, it is not possible to see the inside of the paper in the depth direction. However, the position of the region where the gate insulating film, which is a feature of the present invention, is thin is shown. For the purpose of expression, the source electrode 8 is seen through.
[0028]
As shown in FIG. 7, round source cells 13 including round N + source regions 4 and round contact holes connecting the source electrodes 8 connected to the round N + source regions 4 are regularly arranged. In other portions, a gate electrode 15 made of polysilicon is formed with a gate insulating film (oxide film) interposed in the depth direction of the drawing. Here, the region 14 in which the gate insulating film is thin is disposed at a point equidistant from the four round source cells 13.
[0029]
This point is also a point equidistant from the four base regions, and by disposing at such a position, the gate insulating film becomes thin while maintaining a high density without disturbing the original arrangement of the source cells 13 and the cell pitch. There is an effect that the area 14 can be arranged.
[0030]
Further, as another example of the planar layout, as shown in FIG. 8, the source cell 16 may be a square with a corner portion. Reference numeral 17 shown in the figure is a portion where the gate insulating film is thinned, and reference numeral 18 is a gate electrode. Furthermore, as shown in FIG. 9, even when the hexagonal source cells 19 are densely arranged, a region 20 in which the gate insulating film is thin is arranged at a portion equidistant from the three hexagonal source cells. Can be considered. Reference numeral 21 shown in the figure is a gate electrode.
[0031]
Next, the operation of the silicon carbide semiconductor device according to this embodiment will be described. The basic structure of the device shown in FIG. 1 is a vertical power MOSFET. When a voltage higher than the threshold voltage is applied to the gate electrode 6 in a state where a voltage is applied between the drain and drain electrodes on the back surface. A channel is formed at the gate insulating film interface below the gate electrode on the surface of the P-type base region 3, and the current flows between the drain electrode 9, the N + SiC substrate 1, the N− type drift layer 2, the channel, the source region 4, and the source electrode 8. Flowing.
[0032]
The drain electrode 9 and the source electrode 8 are connected with low resistance, and the potential of the drain electrode 9 is lowered (the element is turned on).
[0033]
Next, when the potential of the gate electrode 6 is made equal to or lower than the threshold voltage with a voltage applied between the drain electrode 9 and the source electrode 8, the channel disappears and the current path is interrupted. When the voltage between the drain electrode 9 and the source electrode 8 rises, a reverse bias is applied to the PN junction formed by the base region 3 and the N − type drift layer 2, and the depletion layer extends to the N − type drift layer 2. .
[0034]
2 and 3 schematically show how the depletion layer 11 extends between the base region 3a and the adjacent base region 3b when the device is turned off. FIG. 2 shows a configuration according to the present invention, and FIG. 3 shows a conventional example. In the conventional example of FIG. 3, the depletion layer extends along the base regions 3a and 3b. Further, when a high voltage is applied, the depletion layers on both sides cross and connect.
[0035]
In such a state, the distance between the depletion layer 11 extending from the surface of the N− type drift layer 2 is relatively short at the intermediate portion between the base region 3a and the base region 3b. The electric field applied to the gate insulating film between the type drift layers is locally increased.
[0036]
On the other hand, in the configuration of the present invention shown in FIG. 2, since the gate insulating film is locally thinned at an intermediate portion between the base region 3a and the base region 3b, the field plate effect of the gate electrode 6 The depletion layer 11 is more easily extended at this portion. As shown in FIG. 2, the depletion layer 11 extends along the base region 3 and also deeper in this portion.
[0037]
Then, in this portion, the electric field applied to the gate insulating film 5 is relaxed. Therefore, it is possible to prevent a large electric field close to the breakdown voltage from being applied to the gate insulating film before the avalanche breakdown occurs inside the SiC semiconductor, and to prevent the gate insulating film from breaking down before the avalanche breakdown occurs. Since this can be prevented, there is an effect that a desired high breakdown voltage can be obtained.
[0038]
Furthermore, the avalanche resistance is not defined by the dielectric breakdown of the gate insulating film, can withstand a constant current, and the avalanche resistance can be made sufficiently large.
[0039]
Next, a method for manufacturing the silicon carbide semiconductor device according to this embodiment will be described. 5 and 6 are device cross-sectional structure diagrams showing the flow of the manufacturing method. In FIG. 5A, an N− epitaxial layer (N− type drift layer) 2 is grown on an N + type SiC substrate 1.
[0040]
In FIG. 6B, after introducing impurities into a desired position using means such as ion implantation on the surface of the N-epitaxial layer 2, a heat treatment at about 1600 ° C. is obtained, and the P-type base regions 3a˜3 3c and N + type source regions 4a-4c are formed.
[0041]
In FIG. 2C, an oxide film is formed on the surface of the N− epitaxial layer 2 by thermal oxidation or the like. Here, the oxide film is etched from the surface at a position just at the center between the base region 3a and the adjacent base region 3b, and is partially thinned. Thus, the structure of the silicon carbide semiconductor device according to the present embodiment can be formed by thinning the thermal oxide film once formed from the surface side by wet etching or the like.
[0042]
In this case, the regions 10a and 10b in which the gate insulating film 5 is thin have a curved shape (semicircular shape), and when polysilicon is deposited on the regions 10a and 10b, the polysilicon has no corners. No electric field concentration occurs.
[0043]
This manufacturing method has a special effect that electric field relaxation can be performed effectively. As another manufacturing method, a thin oxide film is once formed on the entire surface by thermal oxidation or the like, and a second region is selectively applied to a region other than the central position between the base region 3a and the base region 3b. It can also be created by depositing an oxide film.
[0044]
In FIG. 4D, polysilicon to be the gate electrode 6 is deposited on the entire surface of the gate insulating film 5 and patterned into a desired shape by photolithography and etching. In FIG. 4E, after the interlayer insulating film 7 is deposited on the entire surface of the gate electrodes 6a to 6b, the underlying gate insulating film 5 and a part thereof are connected to the source regions 4a to 4c. An opening (contact hole) is formed. In FIG. 5F, a metal that becomes the source electrode 8 connected to the source regions 4a to 4c is formed on the front surface side, and a metal that becomes the drain electrode 9 is connected to the entire surface of the N + silicon carbide substrate 1 on the back surface side. Formed as follows.
[0045]
Thus, the silicon carbide semiconductor device according to the present embodiment can be configured, and can be manufactured at low cost without requiring a particularly difficult process.
[0046]
In this manner, in the silicon carbide semiconductor device according to the first embodiment, the electric field applied to the gate insulating film can be locally weakened, and a high-breakdown-voltage silicon carbide MOSFET can be realized. In addition, since the breakdown voltage of the element is determined by the avalanche breakdown at the PN junction between the base region and the substrate, a silicon carbide MOSFET having a high avalanche resistance can be realized. (Effect of Claim 1)
In addition, since the gate insulating film is thinly formed between the base region 3a and the base region 3b (3a and 3b are adjacent to each other), the electric field is effective in that the electric field applied to the gate insulating film is the strongest. Therefore, it is possible to realize a silicon carbide MOSFET having a high breakdown voltage. In addition, since the breakdown voltage of the element is determined by the avalanche breakdown at the PN junction between the base region and the substrate, it is possible to realize a silicon carbide MOSFET having a high avalanche resistance. (Effect of Claim 2) Further, by adopting a planar layout structure as shown in FIGS. 7 to 9, a reduction in element density is minimized, and an area-efficient and low on-resistance MOSFET is realized. Can do. (Effect of claim 3)
(Second Embodiment)
Next, a second embodiment of the silicon carbide semiconductor device according to the present invention will be described with reference to FIG. Since the configuration is basically the same as that shown in FIG. 1 shown in the first embodiment, only the differences will be described.
[0047]
In the present embodiment, on the surface of the N − type drift layer 2, the N type channel region 12 a, the N + type source region 4 inside the base region 3 is connected to the N + type source region 4 of the adjacent base region 3. 12b is formed. This is a vertical power MOSFET that forms a so-called storage-type channel.
[0048]
The operation of the present embodiment is basically the same as that of the first embodiment described above, and the gate insulating film is locally thin just in the middle of the base region 3b adjacent to the base region 3a. Therefore, due to the field plate effect of the gate electrode 6, the depletion layer 11 is more easily extended at this portion.
[0049]
As shown in FIG. 2, the depletion layer 11 extends along the base region 3 and also deeper in this portion. Then, in this portion, the electric field applied to the gate insulating film 5 is relaxed. Therefore, before the avalanche breakdown occurs in the SiC semiconductor, a large electric field close to the breakdown breakdown voltage is prevented from being applied to the gate insulating film, and the gate insulating film breaks down before the avalanche breakdown occurs. Since this can be prevented, there is an effect that a desired high breakdown voltage can be obtained.
[0050]
Furthermore, the avalanche resistance is not defined by the dielectric breakdown of the gate insulating film, can withstand a constant current, and the avalanche resistance can be made sufficiently large.
[0051]
In the configuration of the present embodiment, an accumulation type channel is used, so that it is not easily affected by the interface state of the MOS interface, the channel resistance can be easily reduced, and a low on-resistance element can be easily obtained. A unique effect that the advantageous characteristics inherent in the power MOSFET of the channel can be realized together can be exhibited. In the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, a process for forming the N-type channel region 12 by ion implantation or the like is added. can do.
[0052]
(Third embodiment)
A third embodiment of the silicon carbide semiconductor device according to the present invention will be described below. In the present embodiment, the thickness of the gate insulating film in the present invention and the thickness of the part where the gate insulating film is partially thinned will be described.
[0053]
The thickness of the gate insulating film may be about several tens to several thousand, but for example, a gate insulating film of 500 mm may be used. In the present invention, the thinned portion of the gate insulating film means that the insulating film can be protected from a high electric field by the field plate effect even if it is about 250 mm, which is a half thickness. .
[0054]
Regarding the field plate effect, it can be said that the thinner the remaining thin insulating film portion, the higher the effect. Interpreting this in a developmental manner, it is conceivable that the gate insulating film is partially lost and the gate electrode is in direct contact with the drift region that is silicon carbide. Since the key connection is established and a voltage higher than the Schottky junction forward voltage Vf with respect to the source potential cannot be applied to the gate electrode, this is not a realistic configuration.
[0055]
Therefore, in the present invention, such a configuration is not included. The lower limit of the thin oxide film has the following limitations.
[0056]
That is, it is necessary to apply a sufficiently high gate voltage to the gate electrode so that the element conducts with a low on-resistance. For example, when it is necessary to apply up to about 20 V as the gate voltage, assuming that the dielectric breakdown electric field of the insulating film is 10 [MV / cm], it is necessary to set the voltage to 200 V or more, and it is necessary to apply up to about 30 V. In some cases, it is necessary to keep it at least 300 mm. As described above, the minimum value of the thickness of the thin portion of the gate insulating film is defined according to the voltage applied to the gate, and it is most desirable to make the thickness as thin as possible.
[Brief description of the drawings]
1 is a device cross-sectional structure diagram of a silicon carbide semiconductor device according to a first embodiment of the present invention;
FIG. 2 is an explanatory diagram showing the spread of a depletion layer when the silicon carbide semiconductor device according to the first embodiment of the present invention is turned off.
FIG. 3 is an explanatory diagram showing the spread of a depletion layer when the semiconductor device according to the prior art is off.
FIG. 4 is a device cross-sectional structure diagram of a silicon carbide semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a first partial diagram of an explanatory diagram showing a manufacturing step of the silicon carbide semiconductor device according to the first embodiment of the invention.
FIG. 6 is a second partial view of the explanatory view showing the manufacturing process of the silicon carbide semiconductor device according to the first embodiment of the invention.
FIG. 7 is a plan layout view of the silicon carbide semiconductor device according to the first embodiment of the present invention.
FIG. 8 is another planar layout diagram of the silicon carbide semiconductor device according to the present invention.
FIG. 9 is another planar layout diagram of the silicon carbide semiconductor device according to the present invention.
[Explanation of symbols]
1 N + type silicon carbide semiconductor substrate 2 N− type drift layers 3a to 3c P type base regions 4a to 4c N + type source regions 5a and 5b Gate insulating films 6a and 6b Gate electrodes 7a and 7b Interlayer insulating film 8 Source electrode 9 Drain electrode 10a, 10b Portion where gate insulating film is thin 11 Depletion layer 12a, 12b N-type channel region 13 Round source cell 14 Portion where gate insulating film is thin 15 Gate electrode 16 Square source cell 17 with corners removed Portion where gate insulating film is thin 18 Gate electrode 19 Hexagonal source cell 20 Portion where gate insulating film is thin 21 Gate electrode

Claims (3)

A second conductivity type base region formed on the first main surface of the first conductivity type silicon carbide semiconductor substrate, a first conductivity type source region formed in the base region, and the silicon carbide semiconductor substrate In a MOSFET having a drift region of a first conductivity type formed in a part of the gate electrode and a gate electrode formed on the base region via a gate insulating film,
The gate insulating film is formed such that a part of the entire region in contact with the silicon carbide semiconductor substrate of the first conductivity type is thinner than the other region, and the part of the region is smaller than the other region. A silicon carbide semiconductor device characterized by having a small area . The silicon carbide semiconductor device according to claim 1,
The MOSFET is a MOSFET in which the gate insulating film and the gate electrode are planarly formed on the silicon carbide semiconductor substrate, and a portion where the gate insulating film is formed thinly includes the base region and the base region. And a base region adjacent to the silicon carbide semiconductor device. In the silicon carbide semiconductor device according to claim 1 or 2,
The base region has a cell structure that is a quadrangle in a plan view, a quadrangle with a rounded corner, or a circle, and the base regions are regularly arranged at regular intervals in a plan view, and the gate insulating film The thinly formed portions are arranged in the form of dots at positions equidistant from a plurality of the regularly arranged cells adjacent to each other.

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