JP3644614B2 - Dynamic intermediate code processor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for executing a program described in an intermediate code, and more particularly to an apparatus capable of high-speed instruction interpretation and branch processing when executing an intermediate code instruction.
[0002]
[Prior art]
In a conventional dynamic intermediate code processing device, when a program written in intermediate code is executed, instructions are interpreted by sequentially comparing instruction codes with software, and processing is performed by branching to each instruction process. It was broken.
[0003]
Here, the intermediate code is a virtual machine language created when a source program is converted into an object program by a compiler.
[0004]
FIG. 9 is a block diagram showing the configuration of a conventional apparatus for processing a program described in intermediate code.
[0005]
In the figure, 100 is a central processing unit (hereinafter referred to as “CPU: Center Processing Unit”), and 200 is a memory. The execution program for the intermediate code is read from the memory 200 according to the address output from the CPU 100, and the instruction code is interpreted and executed by the processing unit in the CPU 100.
[0006]
Japanese Patent Laid-Open No. 62-98427 proposes an “associative micro control system” so that an instruction word of an arbitrary virtual machine can be decoded and executed at high speed in a microprogrammable data processing apparatus. .
[0007]
The "associative micro control system" disclosed in this publication is a system that speeds up the execution of instructions by setting an instruction in a register and branching to the start address of a microcode.
[0008]
[Problems to be solved by the invention]
The following problems have been pointed out in the apparatus for processing the program described in the conventional intermediate code shown in FIG.
[0009]
That is, since the instructions are sequentially compared and interpreted, each time the instruction is executed, the comparison process is performed, so that an efficient process cannot be performed.
[0010]
In addition, since the interpretation of the instruction and the conditional branch to the processing unit are continuous, interruption of pipeline processing in the CPU frequently occurs, so that efficient processing cannot be performed.
[0011]
Further, the following problems have been pointed out in the “associative micro control system” proposed in Japanese Patent Laid-Open No. 62-98427.
[0012]
In other words, since the address obtained from the associative memory is not converted but is used as it is to branch, similarly, the pipeline processing in the CPU is interrupted.
[0013]
The present invention has been made in view of the above technical problem, and can perform high-speed processing without interfering with CPU pipeline processing while being able to interpret instructions of intermediate codes and branch to a processing unit at high speed. An object of the present invention is to provide a dynamic intermediate code processing apparatus capable of achieving the above.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a dynamic intermediate code processing device according to claim 1 is provided for interpreting an intermediate code and converting it into a physical address based on a virtual address output from a central processing unit. A storage unit for storing the intermediate code instruction; a storage unit for storing a physical address of a page storing the intermediate code instruction process; an address extracted from the storage unit; And conversion means for combining with a virtual address output from the processing device and converting it into a physical address.
[0015]
A dynamic intermediate code processing device according to a second aspect of the present invention is the dynamic intermediate code processing device according to the first aspect, wherein the storage means stores instruction processing of the intermediate code that is frequently used. The physical address of the page is stored, and the conversion means stores the address fetched from the storage means and the virtual output from the central processing unit when there is an instruction stored in the storage means in the storage means. In the case of an instruction that is combined with an address to be converted into a physical address and does not have an entry in the storage means, output means for directly outputting the address output from the central processing unit is included.
[0016]
A dynamic intermediate code processing device according to a third aspect of the present invention is the dynamic intermediate code processing device according to the first aspect, wherein the storage means stores instruction processing of the intermediate code that is frequently used. A physical address of the page is stored, and a physical address of the page in which an instruction interpretation unit for processing an operation code that does not exist in the storage unit is stored is provided.
[0017]
A dynamic intermediate code processing device according to a fourth aspect of the present invention is the dynamic intermediate code processing device according to any one of the first to third aspects, wherein the storage means is an operation stored in the storage means. Corresponding to the code, a page size entry that stores the size of the page in which the instruction processing of the intermediate code is stored, based on the value of the page size entry, a virtual address output from the central processing unit, In order to convert an address to be output between the address taken out from the storage means, a selection means for selecting one of the bits of both addresses is included.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0019]
Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of the dynamic intermediate code processing apparatus according to the first embodiment of the present invention.
[0020]
In the figure, 1 is a CPU, 2 is a memory, 3 is an operation code register, 4 is a conversion reference buffer, 5 is an address conversion unit, and 6 is a memory management unit.
[0021]
The conversion reference buffer 4 and the address conversion unit 5 are included in the memory management unit 6.
[0022]
The conversion reference buffer 4 includes a plurality of entries corresponding to the number of instruction codes. For example, if the number of instruction codes is 256, it has an entry of a physical address of a page in which 256 operation codes and instruction code processing units are stored.
[0023]
Here, the processing operation of the dynamic intermediate code processing apparatus according to the first embodiment will be described with reference to FIG.
[0024]
The processing program for the intermediate code writes the physical address information corresponding to the operation code in the conversion reference buffer 4 in advance as an initialization process.
[0025]
The program for processing the intermediate code is performed by setting the instruction code of the intermediate code in the operation code register 3 provided outside the CPU 1, rather than sequentially comparing the interpretation of the instructions. At this time, the CPU 1 writes an instruction code and outputs a virtual address to the address line in conjunction with the writing.
[0026]
In the memory management unit 6, the physical address stored in the conversion reference buffer 4 is extracted from the instruction code set in the operation code register 3, and in the address conversion unit 5, the lower bits (pages) of the virtual address output from the CPU 1. ) And the physical address obtained from the conversion reference buffer 4 is used to generate a physical address in which the instruction processing unit is stored.
[0027]
FIG. 2 is a diagram illustrating an address generation method performed by the address conversion unit.
[0028]
In the figure, 11 is a virtual address output from the CPU 1 (hereinafter referred to as “CPU output address”), 12 is a physical address extracted from the instruction code set in the operation code register 3 (hereinafter referred to as “translation reference buffer”). "Output address")), 13 is a generated address.
[0029]
Here, with reference to FIG. 2, an address generation method performed by the address conversion unit 5 will be described.
[0030]
In FIG. 2, it is assumed that the logical address output from the CPU 1 is 32 bits, the physical address generated by the address conversion unit 5 is 32 bits, and the size of the page where the instruction code processing is stored is 4 Kbytes. The lower 12 bits indicate a page offset.
[0031]
The address conversion unit 5 extracts the lower 12 bits of the CPU output address 11 as they are, and combines the lower 12 bits of the extracted CPU output address 11 with the upper 20 bits extracted from the conversion reference buffer output address 12. The generation address 13, that is, the physical address where the instruction code processing unit is stored is obtained.
[0032]
As described above, in the first embodiment, since the physical address storing the instruction code processing unit is automatically generated, the software (program) branch does not occur. Thereby, the following effects are produced.
[0033]
That is, it is possible to interpret the intermediate code instruction from the conversion reference buffer 4 and branch to the processing unit at high speed only by setting the intermediate code instruction in the operation code register 3.
[0034]
In addition, by mapping the virtual address and the physical address, the address accessed from the CPU 1 is constant, and the pipeline processing of the CPU 1 can be prevented. Therefore, high-speed processing of dynamic intermediate code can be achieved.
[0035]
The above matters can be understood more clearly by referring to FIG.
[0036]
FIG. 3 is a diagram showing a simplified comparison of intermediate code instruction interpretation and processing time flow between the processing method of the first embodiment and the conventional processing method.
[0037]
In the figure, 15 is a time required for interpretation of an instruction, 16 is a processing time of a corresponding instruction, and 17 is a time required for setting an instruction in the operation code register 3.
[0038]
As apparent from FIG. 3, in the conventional processing method, it takes time to interpret the instruction and branch to the processing unit. According to the first embodiment, the instruction is interpreted in the operation code register. Only the time set to 3 is required, and as a result, the entire processing time can be shortened.
[0039]
Embodiment 2. FIG.
In the second embodiment, in the first embodiment, the conversion reference buffer 4 is provided with entries for all the instruction codes of the intermediate code, whereas the frequently used instruction codes and instruction codes are used. Only the physical address of the page in which the processing unit is stored is stored in the conversion reference buffer 4, and other less frequently used instructions are combined with conventional processing, thereby reducing the memory of the conversion reference buffer 4 and intermediate processing. This will improve the efficiency of code processing.
[0040]
FIG. 4 is a block diagram showing a configuration of the dynamic intermediate code processing device according to the second exemplary embodiment of the present invention.
[0041]
Referring to the figure, the dynamic intermediate code processing apparatus according to the second embodiment is characterized in that a selector 7 for switching output between an address output from the CPU 1 and an address generated by the address conversion unit 5 is newly provided. The other configuration is substantially the same as that of the first embodiment.
[0042]
Here, the operation of the selector will be described with reference to FIG.
[0043]
The selector 7 outputs the physical address generated by the address conversion unit 5 when the instruction code exists in the conversion reference buffer 4 when the program for processing the intermediate code sets the instruction code in the operation code register 3. When the instruction code does not exist in the conversion reference buffer 4, in order to output the address output from the CPU 1 as it is, the address output between the two is switched to perform the conventional processing.
[0044]
Note that the address generation process when the instruction code is present in the conversion reference buffer 4 is the same as that in the first embodiment, and thus the description thereof is omitted.
[0045]
As described above, in the second embodiment, the selector 7 switches between two types of systems, that is, a system that outputs the address from the CPU 1 as it is and a system that outputs the converted address using the conversion reference buffer 4. Therefore, as in the past, it is possible to dynamically select a method for interpreting a sequential instruction code and branching to instruction processing, and a method for performing instruction processing at high speed using the conversion reference buffer 4 based on the instruction code. it can. This makes it possible to interpret and execute the intermediate code without having the conversion reference buffer 4 have the addresses of the processing codes of all instructions.
[0046]
In other words, it is possible to divide into frequently used instruction codes and other instruction codes, and to give only information on frequently used instructions to the conversion reference buffer 4, so that the memory constituting the conversion reference buffer 4 The amount can be reduced. At this time, although the processing of the instruction code not in the conversion reference buffer 4 is not speeded up, it is possible to reduce expensive memory. That is, while achieving high-speed processing of frequently used instructions, processing efficiency and memory reduction can be realized as compared with the conventional method.
[0047]
Embodiment 3 FIG.
FIG. 5 is a block diagram showing the configuration of the dynamic intermediate code processing apparatus according to the third embodiment of the present invention.
[0048]
Referring to the figure, the dynamic intermediate code processing apparatus according to the third embodiment is characterized in that in the second embodiment described above, the output address of CPU 1 is converted when there is no instruction code in conversion reference buffer 4. In contrast, the page 7 in which the processing of the interpreter of the intermediate code instruction is described as the conversion address when the instruction code does not exist in the conversion reference buffer 4 whereas the selector 7 that directly outputs is provided. The physical address is prepared in the entry, and other configurations are almost the same as those in the first embodiment.
[0049]
This entry is prepared in the conversion reference buffer 4 as a special entry whose contents are read when the instruction code written in the operation code does not exist in the conversion reference buffer 4.
[0050]
Here, the processing operation of the dynamic intermediate code processing apparatus according to the third embodiment will be described with reference to FIG.
[0051]
When the intermediate code processing program sets an instruction code in the operation code register 3, an address is generated. At this time, the address generation when the instruction code is present in the conversion reference buffer 4 is the same as that in the first embodiment, and thus the description thereof is omitted. On the other hand, if it does not exist in the conversion reference buffer 4, the physical address of the page in which the processing of the instruction interpretation unit is described is output. Therefore, the address conversion unit 5 generates an address to be obtained from the page offset part of the output address of the CPU 1 and the physical address output from the conversion reference buffer 4.
[0052]
As described above, in the third embodiment, the conversion reference buffer 4 stores the physical address of the page in which the frequently used intermediate code instruction process is stored and does not exist in the conversion reference buffer 4. Since the instruction interpreter for processing the code has the physical address of the page in which it is stored, it is divided into frequently used instruction codes and other instruction codes, and frequently used instructions in the conversion reference buffer 4 It is possible to have only this information. Therefore, while achieving high-speed processing of frequently used instructions, processing efficiency and memory reduction can be realized as compared with the conventional method.
[0053]
Embodiment 4 FIG.
In the first to third embodiments, since the instruction processing unit needs to be stored in one page, the page size needs to be determined in accordance with the maximum size of the instruction code processing unit.
[0054]
FIG. 6 is a diagram showing a memory map of the main memory at this time.
[0055]
In the figure, 18 is the size of one page, 19 is the size of the processing unit corresponding to the instruction, and 20 is an unused area in the page.
[0056]
As can be seen from FIG. 6, when the size of the processing unit corresponding to the instruction is smaller than the page size, a large number of unused areas 20 are generated in the page, and as a result, the memory use efficiency decreases.
[0057]
In view of this, the fourth embodiment makes it possible to dynamically allocate the page size for storing the instruction processing unit, and to improve the use efficiency of the memory.
[0058]
FIG. 7 is a block diagram showing a configuration of a dynamic intermediate code processing apparatus according to the fourth embodiment of the present invention, and FIG. 8 is a diagram showing an address generation method according to the fourth embodiment.
[0059]
Referring to these figures, the feature of the fourth embodiment is that an entry (hereinafter referred to as “page”) stores the size of a page in which the instruction code processing unit is stored in the instruction code entry of conversion reference buffer 4. The size entry ") is newly added, and the page size fetched from the translation reference buffer 4 is used for each of the address output from the CPU 1 and the physical address fetched from the translation reference buffer 4. A plurality of selectors 7 are provided for selecting which address is output for each bit, and the other configuration is substantially the same as in the first embodiment.
[0060]
In FIG. 8, 14 is the page size of the operation code in the conversion reference buffer 4.
[0061]
Here, with reference to FIG. 7 and FIG. 8, the processing operation when the minimum page size in which the instruction processing unit is stored is 256 bytes and the maximum page size is 4 Kbytes will be described.
[0062]
A program for processing the intermediate code sets an instruction code of the intermediate code in an operation code register 3 provided outside the CPU 1, and in accordance with this setting, the CPU 1 outputs a virtual address to an address line.
[0063]
In the memory management unit 6, the physical address and page size stored in the conversion reference buffer 4 are extracted from the instruction code set in the operation code register 3.
[0064]
In the address conversion unit 5, address generation processing is performed using bits corresponding to a portion whose page size can be changed according to the page size. This page offset is the lower 8 bits when the page size is 256 bytes, and the lower 12 bits when the page size is 4K bytes.
[0065]
Therefore, as shown in FIG. 8, the address conversion unit 5 uses the lower 8 bits of the CPU output address 11 and the upper 20 bits of the conversion reference buffer output address 12 as they are.
[0066]
Next, the 8th to 11th bits of the generation address 13 indicate the page size of the process included in the page size 14 of the operation code in the conversion reference buffer 4 in which the instruction code is stored to the selector 7 corresponding to each bit. Notification is made to switch between the output of the CPU output address 11 and the output of the conversion reference buffer output address 12. For example, when the page size is 1, the 8th bit of the CPU output address 11 is used, and when the page size is 2, the 8th and 9th bits of the CPU output address 11 are used.
[0067]
Thereafter, similarly, the output of the 8th to 11th bits of the address of the CPU output address 11 is selected based on the page size value.
[0068]
In this way, the address conversion unit 5 can generate a physical address in which the instruction processing unit is stored by combining the virtual address output from the CPU 1 and the physical address obtained from the conversion reference buffer 4. It becomes possible.
[0069]
As described above, in the fourth embodiment, a page size entry that stores the size of the page in which the instruction code processing unit is stored is newly added to the instruction code entry of the conversion reference buffer 4, and conversion reference is made. A plurality of selectors for selecting which address is output for the address output from the CPU 1 and each bit of the physical address extracted from the conversion reference buffer 4 using the page size extracted from the buffer 4 7 so that the size of the processing code stored can be known from the value of the page size entry, and the correct start address where the processing code is stored can be extracted for each instruction to be executed. It becomes. That is, the address to be selected can be switched by controlling the selector 7 with the value of this entry for each instruction code. For this reason, it is possible to subdivide and specify the position of the address on the memory to be accessed.
[0070]
In other words, when the conversion reference buffer 4 does not have the page size entry and the selector 7, the page is fixed, whereas the conversion reference buffer 4 has the page size of the instruction processing code as described above. As a result, the instruction code hits in the conversion reference buffer 4, and the selector 7 reads the page size and selects each bit of the CPU output address 11 and the conversion reference buffer output address 12, for example, in the range of 8 to 12 bits. The address can be generated by changing the page size. Therefore, it is possible to dynamically assign a page size for storing the instruction processing unit. As a result, the memory usage efficiency can be increased.
[0071]
The present invention is not limited to the above-described embodiments, and various design changes and modifications can be made within the scope of the claims of the present invention.
[0072]
【The invention's effect】
As is apparent from the above description, according to the present invention, by storing the intermediate code instruction in the storage means, it is possible to interpret the intermediate code instruction from the storage means and branch to the processing unit at high speed. Become.
[0073]
Further, by mapping the virtual address and the physical address, the address accessed from the CPU becomes constant, and the pipeline processing of the CPU is not hindered, so that high speed processing can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a dynamic intermediate code processing device according to a first exemplary embodiment of the present invention;
FIG. 2 is a diagram illustrating an address generation method performed by an address conversion unit.
FIG. 3 is a diagram showing simplified comparison of intermediate code instruction interpretation and processing time flow between the processing method of the first embodiment and a conventional processing method;
FIG. 4 is a block diagram showing a configuration of a dynamic intermediate code processing device according to a second exemplary embodiment of the present invention;
FIG. 5 is a block diagram illustrating a configuration of a dynamic intermediate code processing device according to a third embodiment of the present invention;
FIG. 6 is a diagram illustrating a usage state in one page in a memory map of the main memory when the page size is fixed.
FIG. 7 is a block diagram showing a configuration of a dynamic intermediate code processing apparatus according to a fourth embodiment of the present invention.
8 is a diagram illustrating an address generation method according to Embodiment 4. FIG.
FIG. 9 is a block diagram showing the configuration of a conventional apparatus for processing a program described in intermediate code.
[Explanation of symbols]
1 CPU
2 Memory 3 Operation code register 4 Conversion reference buffer 5 Address conversion unit 6 Memory management unit 7 Selector 11 CPU output address 12 Conversion reference buffer output address 13 Generated address 14 Operation code page size in the conversion reference buffer 15 Required for instruction interpretation Time 16 Instruction processing time 17 Time required to set an instruction 18 One page size 19 Size of processing unit corresponding to an instruction 20 Unused area in a page 100 CPU
200 memory

Claims (4)

A device for interpreting an intermediate code based on a virtual address output from a central processing unit and converting it into a physical address,
Storage means for storing the intermediate code instructions;
Storage means for storing a physical address of a page in which instruction processing of the intermediate code is stored;
A dynamic intermediate code processing apparatus comprising: a conversion means for combining an address extracted from the storage means and a virtual address output from the central processing unit into a physical address. The dynamic intermediate code processing device according to claim 1,
The storage means stores a physical address of a page in which instruction processing of the intermediate code that is frequently used is stored,
When the instruction stored in the storage means exists in the storage means, the conversion means combines the address fetched from the storage means and the virtual address output from the central processing unit into a physical address. Converted,
A dynamic intermediate code processing apparatus comprising output means for directly outputting an address output from the central processing unit in the case of an instruction having no entry in the storage means. The dynamic intermediate code processing device according to claim 1,
The storage means stores a physical address of a page in which the frequently used intermediate code instruction processing is stored, and an instruction interpretation unit for processing an operation code that does not exist in the storage means. A dynamic intermediate code processing apparatus comprising a physical address of a page. The dynamic intermediate code processing device according to any one of claims 1 to 3,
The storage means includes a page size entry that stores a size of a page in which instruction processing of the intermediate code is stored, corresponding to the operation code stored in the storage means,
Based on the value of this page size entry, in order to convert the output address between the virtual address output from the central processing unit and the address extracted from the storage means, either one of the two addresses is used. A dynamic intermediate code processing apparatus comprising selection means for selecting a bit.

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