JP3642965B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a wiring formation method, an electrode formation method, and a contact hole formation method in a semiconductor device.
[0002]
[Prior art]
  Conventionally, there has been one shown in FIG. 3 as a technique in this field. Hereinafter, a dynamic random access memory (hereinafter abbreviated as DRAM) will be taken as an example and described in detail with reference to the drawings.
[I] (first prior art)
  (1) First, as shown in FIG. 3A, through a normal semiconductor device manufacturing process, an element isolation region (not shown), a transfer gate 202, andplugUp to 203 is formed. thisplugReference numeral 203 is formed on the silicon substrate 201 at a position where it makes contact with the bit line and the capacitor electrode. Note that 201A is an insulating film.
[0003]
  (2) Next, as shown in FIG. 3B, after depositing an insulating film 204, it is planarized by a chemical mechanical polishing method (hereinafter abbreviated as CMP), and a hole pattern 205 is formed by a normal lithography process. Then, by etching the insulating film 204,plugA bit line contact hole 206 is opened to 203.
[0004]
  (3) Next, as shown in FIG. 3C, by depositing a conductive material constituting the bit line, the bit line contact hole 206 is filled, and then through a normal lithography process and an etching process, Bit line 207 is formed.
[0005]
  (4) Next, as shown in FIG. 3D, an insulating film 208 is deposited on the bit line 207 and then flattened by CMP. After a hole pattern 209 is formed by a normal lithography process, insulation is performed. Membranes 208 and 204And bit line 207By etchingplugA capacitor electrode contact hole 210 is opened to 203.
[0006]
  Thereafter, through the normal manufacturing process of the semiconductor device, the capacitor electrodes and thereafter are formed, and the semiconductor device is manufactured.
[II] (Second Prior Art)
  With the miniaturization of semiconductor devices, both transfer gate widths and contact hole dimensions are steadily decreasing. However, since the alignment margin in the lithography process is not scaled, an etching technique that absorbs the alignment margin and secures insulation between the contact hole and the transfer gate is indispensable in the manufacture of semiconductor devices in the future.
[0007]
  Conventionally, there are technologies shown in FIGS. 4 and 5 as techniques in this field. Hereinafter, it demonstrates in detail according to a figure.
[0008]
  (1) First, as shown in FIG. 4A, after forming an element isolation region 302 on a silicon substrate 301, a transfer gate 304 loaded with an offset silicon oxide film 303 is formed by ordinary lithography and etching. Thereafter, a mask pattern is formed by ordinary lithography, and n-type impurities are implanted into the silicon substrate 301 by ion implantation. For simplicity, the resist pattern at the time of ion implantation is not shown.
[0009]
  (2) Next, as shown in FIG. 4B, a silicon oxide film is deposited on the entire surface of the wafer by a chemical vapor deposition method (hereinafter abbreviated as a CVD method) and anisotropically etched to form a side surface. A wall 305 is formed.
[0010]
  (3) Next, as shown in FIG. 4C, a mask pattern is formed by a normal lithography process, and n-type impurities and p-type impurities are implanted into the silicon substrate 301 by ion implantation. For simplicity, the resist pattern at the time of ion implantation is not shown.
[0011]
  (4) Next, as shown in FIG.(Not shown)After depositing a silicon nitride film 307 having a thickness that functions as a stopper, a silicon oxide film 308 is deposited and planarized by CMP.
[0012]
  (5) Next, as shown in FIG. 5 (a), the silicon substrate is obtained by normal lithography.301A hole pattern 309 for opening the contact hole 310 is formed on the silicon oxide film 308 and the silicon oxide film 308 is etched using the silicon nitride film 307 as a stopper.7And silicon oxide film(Not shown)The contact hole 310 is opened in the silicon substrate 301 by etching.
[0013]
  (6) Next, as shown in FIG. 5B, the contact hole 310 is filled with a polycrystalline silicon film and etched back.plug311 is formed.
[0014]
  (7) Next, as shown in FIG. 5C, after depositing a silicon oxide film 312, a silicon substrate is formed by ordinary lithography.301After forming a contact hole pattern 313 for connecting the bit line and the silicon nitride film 307 as a stopper, the silicon oxide films 312 and 308 are etched, and then the silicon nitride film 307 and the silicon oxide film(Not shown)The bit line contact hole 314 is formed in the silicon substrate 301 by etching.
[0015]
  Thereafter, the semiconductor device is manufactured through a normal semiconductor device manufacturing process.
[III] (Third prior art)
  Conventionally, there are technologies disclosed in FIGS. 6 and 7 as techniques in this field. Hereinafter, it demonstrates in detail according to a figure.
[0016]
  (1) First, as shown in FIG. 6A, after forming up to the bit line 403 by a normal DRAM manufacturing process, a silicon oxide film 404 is deposited as an interlayer insulating film, and then flattened by CMP, for example. A silicon nitride film 405 is deposited. Although the transfer gate is originally formed to face the bit line, it is not shown for simplicity.
[0017]
  (2) Next, as shown in FIG. 6B, after depositing a polycrystalline silicon film 406, a hole pattern 407 is formed by a normal lithography process. Thereafter, the polycrystalline silicon film 406 is anisotropically etched using the silicon nitride film 405 as a stopper to form a hole 408.
[0018]
  (3) Next, as shown in FIG.Hole pattern (Resist)After the 407 is ashed, a polycrystalline silicon film is deposited and anisotropically etched to form a sidewall 409, and an etching mask 410 made of a polycrystalline silicon film having a smaller opening diameter than the hole 408 is formed. Form.
[0019]
  (4) Next, as shown in FIG. 6D, under the condition that a sufficient selection ratio is obtained with respect to the etching mask 410, the layers below the silicon nitride film 405, the silicon oxide film 404, and the bit line 403 are provided. A contact hole 411 is opened on the silicon substrate 401 by etching the insulating film 402 at once. Hereafter, this contact hole411Is called a cell contact hole.
[0020]
  (5) Next, as shown in FIG. 7A, by depositing a polycrystalline silicon film, filling the cell contact hole 411, and then etching back the polycrystalline silicon film,plug412 is formed.
[0021]
  (6) Next, as shown in FIG. 7B, after the silicon oxide film 413 is deposited, the inside of the cell contact hole 411plugA hole pattern 414 for opening a contact hole 415 with respect to 412 is formed by a normal lithography process. Hereafter, this contact hole415Is referred to as a capacitor electrode contact hole. Thereafter, in the cell contact hole 411 under the condition that the selection ratio is sufficiently high with respect to the silicon nitride film 405.plugBy etching the silicon oxide film 413 until reaching 412, a capacitor electrode contact hole 415 is opened.
[0022]
  (7) Next, as shown in FIG.Hole pattern (Resist)After ashing 414, a polycrystalline silicon film 416 constituting the capacitor electrode and a silicon oxide film 417 for embedding the capacitor electrode contact hole 415 are sequentially deposited. Thereafter, the silicon oxide film 417 is etched back until the polycrystalline silicon film 416 is exposed, and then the exposed portion of the polycrystalline silicon film 416 is etched.
[0023]
  (8) Next, as shown in FIG. 7D, by using the silicon nitride film 405 as a stopper, the silicon oxide films 417 and 413 are removed with an aqueous hydrogen fluoride solution, thereby forming a capacitor electrode 418. Thereafter, a capacitor insulating film 419 and a polycrystalline silicon film for forming a cell plate electrode are deposited, and a cell plate electrode 420 is formed by normal lithography and etching.
[0024]
[Problems to be solved by the invention]
  However, in the conventional method for manufacturing a semiconductor device of [I] described above, as the semiconductor device is further miniaturized, the wiring interval is also reduced, so that it is difficult to secure an alignment margin in the lithography process. However, it is difficult to open contact holes stably. On the other hand, in order to secure an alignment margin in the lithography process, the wiring width must be reduced rather than the miniaturization ratio of the semiconductor device, but it is not easy to form a fine wiring pattern in the lithography process. was there.
[0025]
  As described above, [1] described above.ofThe conventional method for manufacturing a semiconductor device has a fatal problem that it is difficult to increase the yield of semiconductor device manufacturing.
[0026]
  In the above-described conventional method for manufacturing a semiconductor device of [II], the semiconductor device is manufactured through two steps of opening the contact hole in a self-aligning manner using the silicon nitride film as a stopper. In order to increase the manufacturing yield, a contact hole with a fine opening diameter is formed with a fine slit width corresponding to the progress of miniaturization of semiconductor devices.Silicon nitrideA technology that opens stably to the membrane is indispensable. In general, the selectivity to a silicon nitride film and the workability of a fine contact hole are difficult to achieve at the same time, so that there is a problem that it is not always easy to realize a high manufacturing yield by the above method.
[0027]
  Further, in the above-described conventional method for manufacturing a semiconductor device [III], it is indispensable to ensure an alignment margin in the lithography process when opening the capacitor electrode contact hole with respect to the cell contact hole.
[0028]
  If the alignment margin cannot be secured, the capacitor electrode contact hole is opened with a deviation from the cell contact hole. Therefore, in the step of etching the silicon oxide film with a hydrogen fluoride aqueous solution using the silicon nitride film as a stopper, the side wall of the cell contact hole is formed. This is because the silicon oxide film is etched and the manufacturing yield decreases due to a short circuit between the capacitor electrode and the bit line or collapse of the capacitor electrode. To avoid this,plugRecesses in(Indentation: recessIt is necessary to make the amount smaller than the silicon nitride film thickness.plugLise ofTheIt is not easy to stably reduce the thickness below the thickness of the silicon nitride film.
[0029]
  In general, the processing size of each process is reduced corresponding to the miniaturization of the semiconductor device, but the alignment margin of the lithography process is not reduced corresponding to the miniaturization of the semiconductor device. The problem becomes more and more obvious.
[0030]
  The first object of the present invention is to eliminate the above-mentioned problems, to stably form contact holes between wirings even when the semiconductor device is miniaturized, and to easily form wirings and electrodes. It is to provide a method of manufacturing a semiconductor device that can be performed.
[0031]
  A second object of the present invention is to provide a method of manufacturing a semiconductor device that eliminates the above-described problems, can easily and self-align contact holes, and has a high manufacturing yield. It is.
[0032]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention provides
  [1] In a method of manufacturing a semiconductor device, (a) a second insulating film deposited in a second stage(107)First insulating film capable of ensuring a sufficient selectivity with respect to(105)The top layerInsulationThe upper bit line on the film(110)And for connecting with the capacitor electrodePlug (106)And (b) the first insulating film(105)Second insulating film capable of securing a sufficient selectivity with respect to(107)Deposit and planarize the bit line(110)Inversion pattern(108)As a mask, and a first insulating film(105)The second insulating film using as a stopper(107)(C) the bit line(110)With conductive materialPreviousRecordInversionpattern(108)Embedded,The height of this embedded conductive materialSecond insulating film(107) heightAgainstLower and form a recessRemoving the conductive material so that the bit line(110)And (d) the second insulating film(107)Third insulating film capable of securing a sufficient selectivity with respect to(111)By depositing saidRecessEmbedded in the second insulating film(107)3rd insulating film until exposed(111)After removing the second insulating film(107)And (e) the third insulating film(111)Same asSame materialThe bit line is deposited by anisotropically etching after depositing the insulating film(110)(F) the first and third insulating films;(105,111)Insulating film that can secure a sufficient selectivity relative to(113)After depositing and planarizing the bit line(110)UpsurfaceAnd side third insulating film(111)And first insulating film(105)4th insulating film using as a stopper(113) and second insulating film (107)And a step of forming a contact hole (115) for forming a capacitor electrode.
[0033]
  [2] In the method of manufacturing a semiconductor device according to [1], the first insulating film(105)And the third insulating film(111)Are made of the same material.
[0034]
  [3] In the method of manufacturing a semiconductor device according to [1], the second insulating film(107)And the fourth insulating film(113)Are made of the same material.
[0035]
  [4] In the method of manufacturing a semiconductor device according to [1], the first insulating film(105)And the third insulating film(111)And second insulating film(107)And the fourth insulating film(113)Are made of the same material.
[0036]
  [5] In the method of manufacturing a semiconductor device according to [4], the first insulating film(105)And the third insulating film(111)Is a silicon nitride film, and the second insulating film(107)And the fourth insulating film(113)Is a silicon oxide film.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described in detail.
[0038]
  FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device showing a first embodiment of the present invention. Here, a DRAM will be taken as an example and described in detail with reference to the drawings. Note that the memory cell array portion shown in FIG. 1 schematically shows a cross section observed in the AA ′ direction in FIG.
[0039]
  (1) First, as shown in FIG. 1A, through a normal semiconductor device manufacturing process, a transfer gate 104 loaded with an element isolation region 102 and an offset insulating film 103, andplugUp to 106 are formed. thisplug106 is formed on the silicon substrate 101 at a position where contact is made with the bit line and the capacitor electrode, and at a position where contact is made between the bit line and the transfer gate 104. here,plugThe uppermost layer of the interlayer insulating film on which the layer 106 is formed is composed of a first insulating film 105 that can ensure a selection ratio with respect to the insulating film deposited in the next step.
[0040]
  (2) Next, as shown in FIG. 1B, a second insulating film 107 is deposited and then planarized by CMP. Thereafter, the inverted pattern 108 of the bit line is formed by a normal lithography process, and the first insulating film 105 is used as a stopper.plugThe groove (contact hole) 109 is formed by etching the second insulating film 107 until it reaches 106.
[0041]
  (3) Next, as shown in FIG. 1 (c), the groove 109 is embedded with the bit line 110, and the upper surface of the second insulating film 107 isRecessThe bit line 110 is formed by removing so as to generate. Thereafter, by depositing a third insulating film 111 that can ensure a sufficient selection ratio with respect to the second insulating film 107,RecessThen, the third insulating film 111 is removed until the second insulating film 107 is exposed.
[0042]
  Here, the recess when the bit line 110 is removed(Concave)The amount is set so that the third insulating film 111 can secure the withstand voltage of the capacitor electrode and the bit line 110 and can secure the remaining thickness of the bit line film that satisfies the predetermined bit line resistance. .
[0043]
  (4) Next, as shown in FIG. 1D, after the second insulating film 107 is selectively removed, the same as the third insulating film 111 existing on the bit line 110 is obtained.Same materialA sidewall 112 is formed by depositing an insulating film and anisotropically etching back. Here, the amount of removal of the second insulating film 107 may be at least the thickness of the third insulating film 111 on the bit line 110, and may be part or all of it.
[0044]
  (5) Next, as shown in FIG. 1E, after depositing a fourth insulating film 113 capable of ensuring a sufficient selection ratio with respect to the first insulating film 105 and the third insulating film 111. Then, the hole pattern 114 is formed by a normal lithography process. Thereafter, the fourth insulating film 113 is etched while securing insulation from the bit line 110 by using the third insulating film 111 and the sidewall 112 as a stopper,When the second insulating film 107 is leftBy etching the second insulating film 107 with a sufficient over-etching amount using the first insulating film 105 as a stopper,plugA capacitor electrode contact hole 115 is opened in 106.
[0045]
  Thereafter, through the normal semiconductor device manufacturing process, the capacitor electrode and subsequent parts are formed, and the semiconductor device is manufactured.
[0046]
  As described above, according to the first embodiment, (1) an interlayer having the first insulating film 105 as the uppermost layer capable of ensuring a sufficient selection ratio with respect to the second insulating film 107 deposited in the second stage. To connect the upper bit line 110 and the capacitor electrode to the insulating filmplugAnd (2) depositing and planarizing a second insulating film 107 that can ensure a sufficient selection ratio with respect to the first insulating film 105, and then inversion pattern of the bit line 110108A step of etching the second insulating film 107 using the first insulating film 105 as a stopper, and (3) the conductive material constituting the bit line 110 with the conductive materialInversionpattern108The conductive material is embedded in the second insulating film 107.Has recessA step of forming the bit line 110 by removing the conductive material, and (4) depositing a third insulating film 111 capable of securing a sufficient selection ratio with respect to the second insulating film 107. By the aboveRecessAfter removing the third insulating film 111 until the second insulating film 107 is exposed, and then removing the second insulating film 107; and (5) the same process as the third insulating film 111.Same materialAnd (6) sufficient for the first insulating film 105 and the third insulating film 111; After depositing and planarizing the fourth insulating film 113 that can ensure the selectivity, the fourth insulating film 113 and the third insulating film 111 and the first insulating film 105 on the upper and side surfaces of the bit line 110 are used as stoppers. Since the semiconductor device is manufactured through the step of forming the contact hole 115 for forming the capacitor electrode by etching the second insulating film 107, the bit line corresponding to the miniaturization of the semiconductor device is manufactured. Formation is possible. In addition, since the bit line can be formed without going through a special lithography process, it is possible to reduce the number of manufacturing steps and the manufacturing cost.
[0047]
  Next, a second embodiment of the present invention will be described.
[0048]
  In the second embodiment, the first insulating film 105 and the third insulating film 111 in the first embodiment are made of the same material.
[0049]
  like thisIn addition,According to the second embodiment, since the materials of the first insulating film 105 and the third insulating film 111 in the first embodiment are the same, the same effect as in the first embodiment can be realized. Is possible.
[0050]
  Next, a third embodiment of the present invention will be described.
[0051]
  In the third embodiment, the materials of the second insulating film 107 and the fourth insulating film 113 in the first embodiment are the same.
[0052]
  like thisIn addition,According to the third embodiment, since the second insulating film 107 and the fourth insulating film 113 in the first embodiment are made of the same material, the same effect as in the first embodiment can be realized. Is possible.
[0053]
  Next, a fourth embodiment of the present invention will be described.
[0054]
  In the fourth embodiment, the materials of the first insulating film 105 and the third insulating film 111 in the first embodiment are the same, and the materials of the second insulating film 107 and the fourth insulating film 113 are the same. It is a thing.
[0055]
  like thisIn addition,According to the fourth embodiment, the materials of the first insulating film 105 and the third insulating film 111 in the first embodiment are the same, and the materials of the second insulating film 107 and the fourth insulating film 113 are the same.AlsoSince they are the same, it is possible to achieve the same effect as in the first embodiment.
[0056]
  Next, a fifth embodiment of the present invention will be described.
[0057]
  In the fifth embodiment, a silicon nitride film is used for the first insulating film 105 and the third insulating film 111 in the fourth embodiment, and a silicon oxide film is used for the second insulating film 107 and the fourth insulating film 113. It is a thing.
[0058]
  Here, when the conductive material forming the bit line 110 is tungsten polycide, the second insulating film 107, that is, the silicon oxide film is used.Has recessAs a method for removing the conductive material, for example, using an electron cyclotron resonance type etching apparatus, a pressure of 5 mTorr, Cl₂/ O₂Some etch back at 190/10 cc / min, microwave power = 400 W, RF power = 40 W, electrode temperature = 20 ° C.
[0059]
  Next, as a method for removing the second insulating film 107, that is, the silicon oxide film, for example, there is a method in which the silicon oxide film is wet-etched with a hydrogen fluoride aqueous solution.
[0060]
  The third insulating film 111, that is, a silicon nitride film, is used to form the bit line 110.RecessAs a method for removing the silicon nitride film until the upper surface of the second insulating film 107, that is, the silicon oxide film is exposed after the burying is performed, for example, using a microwave downflow etching apparatus, pressure = 80 Pa, CF_Four/ O₂/ Cl₂/ N₂= 270/270/170/80 cc / min, microwave power = 600 W, electrode temperature = 20 ° C. Sidewalls by anisotropically etching after depositing the third insulating film 111112For example, using a parallel plate etching apparatus, the pressure is 300 mTorr, Ar / CHF_Three/ CF_FourSome are etched at 400/25/15 cc / min, RF power = 350 W, electrode temperature = 0 ° C.
[0061]
  As a condition for etching the fourth insulating film 113, that is, the silicon oxide film, using the third insulating film 111 and the first insulating film 105, that is, the silicon nitride film, as a stopper, using a magnetron etching apparatus, pressure = 40 mTorr, Ar / C_FourF₈/ CH₂F₂= 500/20/7 cc / min, RF power = 1500 W, cooling He pressure, center / edge = 3/40 Torr, electrode temperature = 40 ° C.
[0062]
  like thisIn addition,According to the fifth embodiment, a silicon nitride film is used as the first insulating film 105 and the third insulating film 111 in the fourth embodiment, and a silicon oxide film is used as the second insulating film 107 and the fourth insulating film 113. Since it is used, it is possible to achieve the same effect as the first embodiment.
[0063]
  In the following, examples of the present invention will be described as reference examples.
[0064]
  Next, a sixth embodiment of the present invention will be described.
[0065]
  FIG. 8 is a sectional view of a manufacturing process of a semiconductor device showing a sixth embodiment of the present invention, and FIG. 9 is a schematic view of a contact hole pattern thereof.
[0066]
  (1) First, as shown in FIG. 8A, after forming an element isolation region on a silicon substrate 501, a transfer gate 503 loaded with an offset insulating film 502 is formed by normal lithography and etching. Transfer gate503It goes without saying that the transfer gate 503 is set to perform a desired operation by performing a normal semiconductor device manufacturing process after forming the gate.
[0067]
  (2) Next, as shown in FIG. 8B, after depositing the first insulating film 504 and the second insulating film 505, the second insulating film 505 is planarized by CMP. Note that the first insulating film 504 and the second insulating film 505 are combined so that the value of the etch rate ratio, that is, the selectivity is sufficiently high.
[0068]
  (3) Next, as shown in FIG. 8C, a contact hole pattern (resist) 506 is formed by a normal lithography process. As shown in FIG. 9, the contact hole pattern 506 is used to connect the activation region formed in the step of FIG. 8A to the upper layer wiring or electrode and the silicon substrate.Plug 508It is designed to be able to etch the region where the regions where the gas exists are collectively connected.
[0069]
  (4) Next, as shown in FIG. 8D, by etching the second insulating film 505 using the first insulating film 504 as a stopper, the first insulating film 504 is etched.Plug 508A contact hole 507 for filling in is opened in the silicon substrate.
[0070]
  (5) Next, as shown in FIG. 8E, after the contact pattern (resist) 506 is ashed, the contact hole 507 is formed.Plug 508The conductive material is removed until it reaches a position lower than the uppermost surface of the offset insulating film 502 after being embedded with the conductive material constitutingplug508 is formed.
[0071]
  Less than,Plug 508Against the contact hole507A semiconductor device is manufactured by connecting an electrode or a wiring through the wiring.
[0072]
  like thisIn addition,According to the sixth embodiment, after forming the element isolation region and the transfer gate 503 through a normal semiconductor device manufacturing method, (1) a combination of insulating films that can ensure a sufficient selection ratio504,505And (2) this insulating film504,505In contrast, the active region is connected to the upper layer wiring and electrodes.Plug 508It is possible to etch the region that connects the regions where there iscontactpattern506And the process of forming the film by ordinary lithography and the laminated insulating film504,505Among them, the insulating film present in the lower layer504A self-aligning upper insulating film with a stopper505After etching, the lower insulating film504Silicon substrate by etching501A step of opening a contact hole 507, and filling the contact hole 507 with a conductive material,503Since the conductive material is removed until reaching a position lower than the upper surface of the upper offset insulating film 502, the depth to be etched is suppressed when the contact hole 507 is formed in a self-aligning manner. Therefore, it is possible to provide a semiconductor device manufacturing method with a high manufacturing yield.
[0073]
  In addition, a combination of insulating films that can ensure a sufficient selectivity504,505As a mask, the pattern disclosed in the present embodiment is used as a mask to perform a self-aligned etching process.plugAfter forming 508, contact holes 507 for connecting wirings and electrodes are formed after depositing one or both of the insulating films.plugWhen opening against 508, thisplugEven when the contact hole 507 is shifted from the opening 508, the insulating film504,505Therefore, it is possible to manufacture a semiconductor device with only one step of opening the contact hole 507 in a self-aligning manner, and manufacturing a semiconductor device with a high manufacturing yield. It is possible to provide a method.
[0074]
  Next, a seventh embodiment of the present invention will be described.
[0075]
  In the seventh embodiment, after the upper (second) insulating film 505 in the sixth embodiment is planarized, the lower insulating film 504 is exposed until the lower (first) insulating film 504 on the transfer gate is exposed. In contrast, the upper insulating film 505 is removed with a sufficiently high selection ratio.
[0076]
  like thisIn addition,According to the seventh embodiment, the upper insulating film 505 in the sixth embodiment is planarized and then transferred to the transfer gate.503Since the upper insulating film 505 is removed with a sufficiently high selection ratio with respect to the lower insulating film 504 until the upper lower insulating film 504 is exposed, the contact hole is more than the sixth embodiment.507Therefore, it is possible to provide a method for manufacturing a semiconductor device with a high manufacturing yield.
[0077]
  Next, an eighth embodiment of the present invention will be described.
[0078]
  In the eighth embodiment, the offset insulating film 502 is made of a silicon oxide film, the lower insulating film 504 used as an etching stopper is made of a silicon nitride film, and the upper insulating film 505 is made of a silicon oxide film in the sixth embodiment. Is. When a silicon nitride film is used for the lower insulating film 504, the transfer gate 503 and the silicon substrate 501plugIn order to ensure the insulating property of 508, the lower insulating film 504 may be deposited after the side surfaces of the silicon substrate 501 and the transfer gate 503 are oxidized.But this tooIt is not excluded from the scope of the present invention.
[0079]
  Here, as a condition for etching the silicon oxide film of the upper insulating film 505 using the silicon nitride film of the lower insulating film 504 as a stopper, for example, using a magnetron etching apparatus, pressure = 40 mTorr, Ar / CO / C_FourF₈= 200/150/9 cc / min, RF power = 1300 W, electrode temperature = 30 ° C., electrode spacing = 27 mm, cooling He pressure, center / edge = 3/45 Torr.
[0080]
  Next, as a condition for etching the lower insulating film 504, for example, using a magnetron etching apparatus, pressure = 50 mTorr, Ar / CHF_Three/ O₂= 100/20/20 cc / min, RF power = 300 W, electrode temperature = 30 ° C., electrode interval = 32 mm, cooling He pressure, center / edge = 3/45 Torr.
[0081]
  like thisIn addition,According to the eighth embodiment, in the sixth embodiment, a silicon oxide film is used as the offset insulating film 502, a silicon nitride film is used as the lower insulating film 504 used as an etching stopper, and a silicon oxide film is used as the upper insulating film 505. It is possible to achieve the same effect as the sixth embodiment.
[0082]
  Next, a ninth embodiment of the present invention will be described.
[0083]
  In the ninth embodiment, a silicon nitride film is used as the offset insulating film 502 in the eighth embodiment.
[0084]
  like thisIn addition,According to the ninth embodiment, since the silicon nitride film is used for the offset insulating film 502 in the eighth embodiment, it is possible to achieve the same effect as that of the sixth embodiment.
[0085]
  Next, a tenth embodiment of the present invention will be described.
[0086]
  In the tenth embodiment, the offset insulating film 502 in the sixth embodiment is formed of a laminated film, and a silicon oxide film is used as the uppermost insulating film.
[0087]
  like thisIn addition,According to the tenth embodiment, since the offset insulating film 502 in the sixth embodiment is formed of a laminated film and the silicon oxide film is used as the uppermost insulating film, the same effect as in the sixth embodiment can be obtained. It is possible to realize. Next, an eleventh embodiment of the present invention will be described.
[0088]
  In the eleventh embodiment, the offset insulating film 502 in the sixth embodiment is formed of a laminated film, and a silicon nitride film is used as the uppermost insulating film.
[0089]
  like thisIn addition,According to the eleventh embodiment, since the offset insulating film 502 in the sixth embodiment is formed of a laminated film and the silicon nitride film is used as the uppermost insulating film, the same effect as in the sixth embodiment can be obtained. It is possible to realize. Next, a twelfth embodiment of the present invention will be described.
[0090]
  FIG. 10 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention (part 1). FIG. 11 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention (part 2). Hereinafter, it demonstrates in detail according to a figure.
[0091]
  (1) First, as shown in FIG. 10A, through a normal semiconductor device manufacturing process, an element isolation region, a word line (both not shown), and a silicon substrate 600 are formed.plugA silicon oxide film 602 and a bit line 603 are sequentially formed. Here, the bit line 603 is characterized by being covered with an upper silicon nitride film 604 and a sidewall silicon nitride film 605. As a typical example, a bit line603Silicon nitride film on sidewall605The interval is set to about 0.08 μm. Thereafter, a silicon oxide film 606 is deposited and planarized by CMP, and then a silicon nitride film 607 is deposited.
[0092]
  (2) Next, as shown in FIG. 10B, after a silicon oxide film 608 and a polycrystalline silicon film 609 are sequentially deposited, a hole pattern 610A for forming a capacitor electrode is formed by a normal lithography process. Form. Thereafter, using the silicon oxide film 608 as a stopper, for example, using a parallel plate etching apparatus, the pressure is 20 mTorr, SF₆After etching the polycrystalline silicon film 609 under the conditions of / HBr = 26/8 cc / min, RF power = 300 W, and cooling He pressure = 4 Torr, the pressure is measured using the silicon nitride film 607 as a stopper, for example, using a magnetron etching apparatus. = 40 mTorr, Ar / CO / C_FourF₈= 250/100/8 cc / min, RF power = 1300 W, electrode temperature = 40 ° C., cooling He pressure Center / edge = 3/45 Torr The silicon oxide film 608 is etched using, for example, a magnetron etching apparatus, Pressure = 50 mTorr, Ar / CHF_Three/ O₂The silicon nitride film 607 is etched under the following conditions: 100/25/15 cc / min, RF power = 300 W, electrode temperature = 40 ° C., cooling He pressure, center / edge = 3/45 Torr.
[0093]
  (3) Next, as shown in FIG. 10C, after the resist 610 is ashed, the bit line603Using the upper silicon nitride film 604 and the side silicon nitride film 605 as a stopper, for example, using a magnetron etching apparatus, pressure = 40 mTorr, Ar / CO / C_FourF₈By etching the silicon oxide films 606 and 602 under the conditions of = 200/150/8 cc / min, RF power = 1300 W, electrode temperature = 40 ° C., cooling He pressure, center / edge = 3/45 Torr,plugA cell contact hole 611 is opened in a self-aligned manner with respect to 601.
[0094]
  (4) Next, as shown in FIG. 11A, after depositing a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611, the cell contact hole 611 is buried with the silicon oxide film 613. . Thereafter, the silicon oxide film 613 is formed using, for example, a parallel plate etching apparatus, pressure = 500 mTorr, Ar / CHF._Three/ CF_FourEtch back until the polycrystalline silicon film 612 is exposed under the conditions of 400/20/20 cc / min, RF power = 200 W, electrode temperature = 0 ° C., cooling He pressure = 15 Torr.
[0095]
  (5) Next, as shown in FIG. 11B, using a silicon oxide film 613 as a stopper, for example, using a microwave downflow etching apparatus, pressure = 40 Pa, CF_Four/ O₂= 150/60 cc / min, microwave power = 700 W, electrode temperature = 25 ° C., the polycrystalline silicon films 612 and 609 are isotropically etched back to expose the silicon oxide film 608.
[0096]
  (6) Next, as shown in FIG. 11C, the silicon oxide film 608 and 613 are etched with an aqueous hydrogen fluoride solution using the silicon nitride film 607 as a stopper, thereby forming a capacitor electrode 614.
[0097]
  Then, after depositing a capacitor insulating film, a polycrystalline silicon film is deposited, and a semiconductor device is manufactured through a process of forming a cell plate electrode by a normal lithography process and an etching process.
[0098]
  According to the twelfth embodiment, (1) a process of processing a laminated film of the polycrystalline silicon film 609, the silicon oxide film 608 and the silicon nitride film 607 by a normal lithography process and an etching process; and (2) the polycrystalline film Using the silicon film 609 as a mask, a silicon nitride film is formed on the top and side walls, which are formed in advance.604,605The silicon oxide films 606 and 602 were previously formed by etching the bit line 603 having a structure covered with the above using the silicon nitride films 605 and 604 as stoppers.plugA step of forming a cell contact hole 611 with respect to 601; and (3) depositing a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611, and then depositing a silicon oxide film 613. A step of filling the contact hole 611; and (4) using the polycrystalline silicon film 612 of the step (3) as a stopper, the silicon oxide film 613 filling the cell contact hole 611 is etched back, and then the silicon oxide film 613 Using as a mask, the step of isotropically etching back the polycrystalline silicon film 612 in the step (3) and the polycrystalline silicon film 609 in the step (1), and (5) using the silicon nitride film 607 as a stopper. The silicon oxide film 613 in step (4) and the silicon oxide film 608 in step (1) are combined with hydrogen fluoride. By etching using a solution, and a process of forming a capacitor electrode 614, since so as to manufacture the semiconductor device, it is possible to improve the problem of alignment margin in lithography process. As a result, a semiconductor device with a high manufacturing yield can be manufactured.
[0099]
  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.
[0100]
  Further, in the twelfth embodiment, since the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 609 as a mask when the cell contact hole 611 is etched, the etching can be performed while suppressing the mask height. Therefore, it is possible to cope with further miniaturization.
[0101]
  In the twelfth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted,plugFrom the viewpoint of securing a contact area with respect to 601, it is necessary to form the hole pattern 610 </ b> A for forming the capacitor electrode 614 to the extent of the gap between the silicon nitride films 605 on the side walls + 2 × the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated for the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the twelfth embodiment, the step of forming a sidewall using a polycrystalline silicon film, which was disclosed in the prior art, can be completely eliminated. It is.
[0102]
  Next, a thirteenth embodiment of the present invention will be described.
[0103]
  In the thirteenth embodiment, the polycrystalline silicon films 609 and 612 in the twelfth embodiment are anisotropically etched back, and then the silicon oxide film 608 is etched with an aqueous hydrogen fluoride solution using the silicon nitride film 607 as a stopper. Thus, the capacitor electrode 614 is formed.
[0104]
  According to the thirteenth embodiment, (1) a process of processing a laminated film of a polycrystalline silicon film 609, a silicon oxide film 608 and a silicon nitride film 607 by a normal lithography process and an etching process; and (2) the polycrystalline film A silicon oxide film using the silicon nitride films 604 and 605 as a stopper for a bit line 603 having a structure in which the upper and side walls are covered with the silicon nitride films 604 and 605 using the silicon film 609 as a mask. Films 606 and 602 were etched and pre-formedplugA step of forming a cell contact hole 611 with respect to 601; and (3) depositing a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611, and then depositing a silicon oxide film 613. A step of filling the cell contact hole 611; and (4) etching back the silicon oxide film 613 filling the cell contact hole 611 using the polycrystalline silicon film 612 of the step (3) as a stopper. 613 as a mask, anisotropically etching back the polycrystalline silicon film 612 in the step (3) and the polycrystalline silicon film 609 in the step (1), and using the silicon nitride film 607 as a stopper The silicon oxide film 613 of 4) and the silicon oxide film 608 of the above step (1) are combined with hydrogen fluoride water. By etching using a liquid, and after the step of forming the capacitor electrode 614, since so as to manufacture the semiconductor device, it is possible to improve the problem of alignment margin in lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.
[0105]
  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.
[0106]
  Further, in the thirteenth embodiment, since the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 609 as a mask when the cell contact hole 611 is etched, the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.
[0107]
  In the thirteenth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted,plugFrom the viewpoint of securing a contact area with respect to 601, it is necessary to form a hole pattern 610 </ b> A for forming a capacitor electrode to the extent of the gap between the silicon nitride films 605 on the side walls + 2 × the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated for the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the thirteenth embodiment, it is possible to completely eliminate the step of forming a sidewall using a polycrystalline silicon film, which was disclosed in the prior art. is there.
[0108]
  Next, a fourteenth embodiment of the present invention will be described.
[0109]
  In the fourteenth embodiment, the cell contact hole 611 for forming the capacitor electrode 614 is filled using the organic film in the twelfth embodiment, and the organic film and the polycrystalline silicon films 609 and 612 are etched back collectively. Is. In this etch back process, for example, using a magnetron etching apparatus, pressure = 20 mTorr, Cl₂/ O₂= 30/3 cc / min, RF power = 400 W, magnetic field strength = 30 Gauss, electrode temperature = 20 ° C.
[0110]
  According to the fourteenth embodiment, (1) a step of processing a laminated film of the polycrystalline silicon film 609, the silicon oxide film 608 and the silicon nitride film 607 by a normal lithography process and an etching process; and (2) the polycrystalline film A silicon oxide film using the silicon nitride films 605 and 604 as a stopper with respect to the bit line 603 having a structure in which the upper and side walls are covered with the silicon nitride films 605 and 604 using the silicon film 609 as a mask. Films 606 and 602 were etched and pre-formedplugA step of forming a cell contact hole 611 with respect to 601; and (3) depositing a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611, and then depositing an organic film, thereby A step of burying the contact hole 611; (4) a step of etching back the organic film, the polycrystalline silicon film 612 in the step (3) and the polycrystalline silicon film 609 in the step (1); ) After the organic film is ashed, a step of forming the capacitor electrode 614 is performed by etching the silicon oxide film 608 of the above step (1) with an aqueous hydrogen fluoride solution using the silicon nitride film 607 as a stopper. Since the semiconductor device is manufactured, it is possible to completely solve the alignment margin problem in the lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.
[0111]
  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.
[0112]
  Further, in the fourteenth embodiment, since the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 609 as a mask when the cell contact hole 611 is etched, the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.
[0113]
  In the fourteenth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted,plugFrom the viewpoint of securing a contact area with respect to 601, it is necessary to form a hole pattern 610 </ b> A for forming the capacitor electrode 614 to the extent of the interval between the silicon nitride films 605 on the sidewalls + 2 × the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated for the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the fourteenth embodiment, it is possible to completely eliminate the step of forming a sidewall using a polycrystalline silicon film, which was disclosed in the prior art. is there.
[0114]
  Next, a fifteenth embodiment of the present invention is described.
[0115]
  The fifteenth embodiment is the same as the twelfth embodimentplugThe uppermost layer of the interlayer insulating film on which 601 is formed is a silicon nitride film.
[0116]
  According to the fifteenth embodiment, in the twelfth embodimentplugSince the uppermost layer of the interlayer insulating film formed with 601 is a silicon nitride film, in addition to the effect of the twelfth embodiment, even if the overetching time is increased by etching the cell contact hole 611,plugThe interlayer insulating film on which 601 is formed is not excessively etched. This allows cell contact holes611The processing margin of the etching process can be expanded, and the yield of the semiconductor device can be further improved.
[0117]
  Next, a sixteenth embodiment of the present invention will be described.
[0118]
  In the sixteenth embodiment, after etching the polycrystalline silicon film 609 in the twelfth embodiment and then ashing the resist 610, the silicon oxide film 608 and the silicon nitride film 607 are etched using the polycrystalline silicon film 609 as a mask. Then, the silicon oxide films 606 and 602 were previously formed by etching the silicon nitride films 605 and 604 on the bit line 603 and on the sidewalls as stoppers.plugA cell contact hole 611 is opened with respect to 601.
[0119]
  According to the sixteenth embodiment, (1) a process of processing the polycrystalline silicon film 609 by a normal lithography process and an etching process, and (2) a silicon oxide film 608 and a nitrided film using the polycrystalline silicon film 609 as a mask. After etching the laminated film of the silicon film 607, the silicon nitride films 605 and 604 are formed on the bit line 603 formed in advance and covered with the silicon nitride films 605 and 604 at the top and side walls. The silicon oxide films 606 and 602 are etched and formed in advance using as a stopper.plugA step of forming a cell contact hole 611 with respect to 601; and (3) depositing a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611, and then depositing a silicon oxide film 613. A step of filling the cell contact hole 611; and (4) etching back the silicon oxide film 613 filling the cell contact hole 611 using the polycrystalline silicon film 612 of the step (3) as a stopper. 613 as a mask, isotropically etching back the polycrystalline silicon film 612 in the step (3) and the polycrystalline silicon film 609 in the step (1), and (5) using the silicon nitride film 607 as a stopper. The silicon oxide film 613 in the step (4) and the silicon oxide film 608 in the step (1) By etching with an aqueous solution of hydrogen. Thus the production of semiconductor devices by performing the steps of forming a capacitor electrode 614, it is possible to improve the problem of alignment margin in lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.
[0120]
  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.
[0121]
  Further, in the sixteenth embodiment, when the cell contact hole 611 is etched, the silicon oxide film 608, the silicon nitride film 607, and the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 609 as a mask. Etching with reduced thickness becomes possible, and it becomes possible to cope with further miniaturization of the semiconductor device.
[0122]
  In the sixteenth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted,plugFrom the viewpoint of securing a contact area with respect to 601, it is necessary to form a hole pattern 610 </ b> A for forming the capacitor electrode 614 to the extent of the interval between the silicon nitride films 605 on the sidewalls + 2 × the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated as the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the sixteenth embodiment, it is possible to completely eliminate the process of forming the sidewall using the polycrystalline silicon film.
[0123]
  Next, a seventeenth embodiment of the present invention will be described.
[0124]
  In the seventeenth embodiment, after etching the polycrystalline silicon film 609 and the silicon oxide film 608 in the twelfth embodiment and then ashing the resist 610, the silicon nitride film 607 is etched using the polycrystalline silicon film 609 as a mask. Then, the silicon oxide films 606 and 602 were previously formed by etching the silicon nitride films 605 and 604 on the bit line 603 and on the sidewalls as stoppers.plugA cell contact hole 611 is opened with respect to 601.
[0125]
  According to the seventeenth embodiment, (1) a process of processing the polycrystalline silicon film 609 and the silicon oxide film 608 by a normal lithography process and an etching process, and (2) nitriding using the polycrystalline silicon film 609 as a mask. After etching the silicon film 607, the silicon nitride films 605 and 604 are used as stoppers for the bit line 603 formed in advance and covered with the silicon nitride films 605 and 604. The silicon oxide films 606 and 602 were etched and previously formedplugA step of forming a cell contact hole 611 with respect to 601; and (3) depositing a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611, and then depositing a silicon oxide film 613. A step of filling the cell contact hole 611; and (4) etching back the silicon oxide film 613 filling the cell contact hole 611 using the polycrystalline silicon film 612 of the step (3) as a stopper. 613 as a mask, isotropically etching back the polycrystalline silicon film 612 in the step (3) and the polycrystalline silicon film 609 in the step (1), and (5) using the silicon nitride film 607 as a stopper. The silicon oxide film 613 in the step (4) and the silicon oxide film 608 in the step (1) By etching with an aqueous solution of hydrogen, subjected to a step of forming a capacitor electrode 614, since so as to manufacture the semiconductor device, it is possible to improve the problem of alignment margin in lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.
[0126]
  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.
[0127]
  Further, in the seventeenth embodiment, since the silicon nitride film 607 and the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 612 as a mask when the cell contact hole 611 is etched, the etching with reduced mask height is performed. Therefore, it becomes possible to cope with further miniaturization of the semiconductor device.
[0128]
  In the seventeenth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted,plugFrom the viewpoint of securing a contact area with respect to 601, it is necessary to form a hole pattern 610 </ b> A for forming the capacitor electrode 614 to the extent of the interval between the silicon nitride films 605 on the sidewalls + 2 × the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated as the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the seventeenth embodiment, it is possible to completely eliminate the step of forming the sidewall using the polycrystalline silicon film.
[0129]
  Next, an eighteenth embodiment of the present invention will be described.
[0130]
  In the eighteenth embodiment, a capacitor electrode film other than the polycrystalline silicon film in the twelfth embodiment is used.
[0131]
  FIG. 12 is a sectional view of a semiconductor device according to an eighteenth embodiment of the present invention (part 1), and FIG. 13 is a sectional view of a semiconductor device according to an eighteenth embodiment of the present invention (part 2).
[0132]
  (1) First, FIGS. 12A to 12C are not different from the twelfth embodiment of the present invention shown in FIG. In addition, 700 is a silicon substrate, 701 isplug, 702 is a silicon oxide film, 703 is a bit line, 704 and 705 are silicon nitride films, 706 is a silicon oxide film, 707 is a silicon nitride film, 708 is a silicon oxide film, 709 is a polycrystalline silicon film, 710 is a resist, 711 Is a hole pattern, and 712 is a cell contact hole.
[0133]
  (2) Next, as shown in FIG. 12D, a titanium film having a thickness that does not block the cell contact hole 712 is deposited by, for example, CVD, and then heat treatment is performed.plugThe polycrystalline silicon film 701 and the titanium film are reacted to form a titanium silicide layer 713. Thereafter, for example, titanium in an unreacted portion is removed with a mixed aqueous solution of ammonia and hydrogen peroxide. At this time, the silicide layer 713 also exists in the mask due to the reaction between the polycrystalline silicon film constituting the mask (polycrystalline silicon film) 709 and the titanium film.
[0134]
  (3) Next, as shown in FIG. 13A, a titanium nitride film 714 having a thickness that does not block the cell contact hole 712 is deposited by, for example, CVD. Thereafter, the cell contact hole 712 is filled with the silicon oxide film 715, and the silicon oxide film 715 is etched back until the titanium nitride film 714 is exposed.
[0135]
  (4) Next, as shown in FIG. 13B, using the silicon oxide film 715 as a mask, the titanium nitride film 714, the silicide layer 713 generated by the reaction with the mask, and the polycrystalline silicon film 709 of the mask are oxidized. Etch back until the silicon film 708 is exposed.
[0136]
  (5) Next, as shown in FIG. 13C, this step is the same as the twelfth embodiment of the present invention shown in FIG. That is, the capacitor electrode 716 is formed by etching the silicon oxide film 708 and the silicon oxide film 715 with a hydrogen fluoride aqueous solution using the silicon nitride film 707 as a stopper.
[0137]
  Then, after depositing a tantalum oxide film as a capacitor insulating film, for example, by CVD, and then depositing a titanium nitride film as a cell plate electrode film, for example, by CVD, and forming a cell plate electrode by normal lithography and etching After that, the semiconductor device is manufactured.
[0138]
  According to the eighteenth embodiment, (1) a process of processing a laminated film of a polycrystalline silicon film 709, a silicon oxide film 708 and a silicon nitride film 707 by a normal lithography process and an etching process; With respect to the bit line 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705 using the silicon film 709 as a mask, silicon oxide is used with the silicon nitride films 704 and 705 as a stopper. Films 708 and 706 were etched and pre-formedplugA step of forming a cell contact hole 712 with respect to 701, and (3) by depositing a titanium film and then by heat treatment,plug701 is obtained by reacting a polycrystalline silicon film 701 with a titanium film.ofSilicide layer713(4) a step of filling the cell contact hole 712 by depositing a silicon oxide film 715 after depositing a titanium nitride film 714, and (5) a titanium nitride film in the above step (4). The silicon oxide film 715 with the cell contact hole 712 buried is etched back using 714 as a stopper, and then the titanium nitride film 714 in the step (4) and the silicide in the step (3) using the silicon oxide film 715 as a mask. Etching back the layer 713 and the polycrystalline silicon film 709 in the step (1), and (6) oxidizing the silicon oxide film 715 in the step (5) and the oxidation in the step (1) using the silicon nitride film 707 as a stopper. By etching the silicon film 708 using an aqueous hydrogen fluoride solution, a capacitor electrode 16 by performing the step of forming a. Thus the production of semiconductor devices, it is possible to improve the problem of alignment margin in lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.
[0139]
  In addition, since the cell contact hole 712 and the capacitor electrode 716 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.
[0140]
  Further, in the eighteenth embodiment, since the silicon oxide films 708 and 706 are etched using the polycrystalline silicon film 709 as a mask when the cell contact hole 712 is etched, the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.
[0141]
  In addition to the above, titanium nitride film714By capacitor electrode716Therefore, it is possible to use a capacitor insulating film having a high relative dielectric constant such as tantalum oxide.
[0142]
  In the eighteenth embodiment, even when the alignment of the cell contact hole 712 is shifted from the bit line 703,plugFrom the viewpoint of securing a contact area with respect to 701, it is necessary to form the hole pattern 711 for forming the capacitor electrode 716 to the extent of the interval between the silicon nitride films 705 on the side walls + 2 × the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 705 is 0.08 μm, if 0.1 μm is estimated for the alignment margin in the lithography process, the minimum size of the hole pattern 711 to be formed is 0.28 μm. Since this can be formed by a normal lithography process, in the eighteenth embodiment, it is possible to completely eliminate the step of forming the sidewall using the polycrystalline silicon film.
[0143]
  Next, a nineteenth embodiment of the present invention is described.
[0144]
  In the nineteenth embodiment, the cell contact hole 712 for forming the capacitor electrode 716 is filled using the organic film in the eighteenth embodiment, and the organic film, the titanium nitride film 714, the silicide layer 713, and the polycrystalline silicon film 709 are collectively formed. Etch back.
[0145]
  According to the nineteenth embodiment, (1) a process of processing a laminated film of a polycrystalline silicon film 709, a silicon oxide film 708, and a silicon nitride film 707 by a normal lithography process and an etching process, and (2) the polycrystalline film Using the silicon film 709 as a mask, the silicon nitride films 704 and 705 are stoppers for a bit line 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705.-As previously described, the silicon oxide films 706 and 702 were formed by etching.plugA step of forming a cell contact hole 712 with respect to 701, (3) a step of forming a silicide layer 713 by heat treatment after depositing a titanium film having a thickness that does not block the cell contact hole 712; ) A step of filling the cell contact hole 712 by depositing an organic film after depositing the titanium nitride film 714; (5) the organic film; the titanium nitride film 714 in the step (4); and the step (3) ) The silicide layer 713 and the polycrystalline silicon film 709 in the step (1) at a time, and (6) the step (1) using the silicon nitride film 707 as a stopper after the organic film is ashed. A step of forming the capacitor electrode 716 by etching the silicon oxide film 708 using an aqueous hydrogen fluoride solution. To. Thus the production of semiconductor devices, it is possible to improve the problem of alignment margin in lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.
[0146]
  In addition, since the cell contact hole 712 and the capacitor electrode 716 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.
[0147]
  Further, in the nineteenth embodiment, since the silicon oxide films 706 and 702 are etched using the polycrystalline silicon film 709 as a mask when the cell contact hole 712 is etched, the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.
[0148]
  In addition to the above, titanium nitride film714Thus, the capacitor electrode 716 is formed, so that a capacitor insulating film having a high relative dielectric constant such as tantalum oxide can be used.
[0149]
  In the nineteenth embodiment, even when the alignment of the cell contact hole 712 with respect to the bit line 703 is shifted,plugFrom the viewpoint of securing a contact area with respect to 701, it is necessary to form the hole pattern 711 for forming the capacitor electrode 716 to the extent of the interval between the silicon nitride films 705 on the side walls + 2 × the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 705 is 0.08 μm, the minimum size of the hole pattern 711 to be formed is 0.28 μm when the alignment margin in the lithography process is estimated to be 0.1 μm. Since this can be formed by a normal lithography process, in the nineteenth embodiment, it is possible to completely eliminate the step of forming the sidewall using the polycrystalline silicon film.
[0150]
  Next, a twentieth embodiment of the present invention will be described.
[0151]
  In the twentieth embodiment, after the cell contact hole 712 in the nineteenth embodiment is opened, the cell contact hole 712 is filled with an organic film, and the polycrystalline silicon film 709 constituting the organic film and the mask is etched back collectively. The titanium film is deposited after the organic film is ashed.
[0152]
  According to the twentieth embodiment, (1) a process of processing a laminated film of a polycrystalline silicon film 709, a silicon oxide film 708 and a silicon nitride film 707 by a normal lithography process and an etching process, and (2) the polycrystalline film Using the silicon film 709 as a mask, a bit line 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705 is etched using the silicon nitride films 704 and 705 as a stopper. , PreformedplugA step of forming a cell contact hole 712 with respect to 701, and (3) a step of filling the cell contact hole 712 with an organic film and etching back the organic film and the polycrystalline silicon film 709 of the above step (1) at a time. (4) ashing the organic film, depositing titanium having a thickness that does not block the cell contact hole 712, and then forming a silicide layer 713 by heat treatment; and (5) forming a titanium nitride film 714. (6) a step of burying the contact hole 712 by depositing an organic film after the deposition; (6) a step of etching back the organic film and the titanium nitride film 714 of the above step (5); After the organic film is ashed, the silicon oxide film 708 in the first step is converted into a hydrogen fluoride aqueous solution using the silicon nitride film 707 as a stopper. By etching with, subjected to a step of forming a capacitor electrode 716, since so as to manufacture the semiconductor device, it is possible to improve the problem of alignment margin in lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.
[0153]
  In addition, since the cell contact hole 712 and the capacitor electrode 716 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.
[0154]
  Further, in the twentieth embodiment, since the silicon oxide films 708 and 702 are etched using the polycrystalline silicon film 709 as a mask when the cell contact hole 712 is etched, the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.
[0155]
  In addition to the above, titanium nitride film714Thus, the capacitor electrode 716 is formed, so that a capacitor insulating film having a high relative dielectric constant such as tantalum oxide can be used.
[0156]
  In the twentieth embodiment, even when the alignment of the cell contact hole 712 with respect to the bit line 703 is shifted,plugFrom the viewpoint of securing a contact area with respect to 701, it is necessary to form the hole pattern 711 for forming the capacitor electrode 716 to the extent of the interval between the silicon nitride films 705 on the side walls + 2 × the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 705 is 0.08 μm, the minimum size of the hole pattern 711 to be formed is 0.28 μm when the alignment margin in the lithography process is estimated to be 0.1 μm. Since this can be formed by a normal lithography process, in this embodiment, it is possible to completely eliminate the step of forming the sidewall using the polycrystalline silicon film.
[0157]
  Next, a twenty-first embodiment of the present invention will be described.
[0158]
  FIG. 14 is a sectional view of a semiconductor device according to a twenty-first embodiment of the present invention (part 1). FIG. 15 is a sectional view of a semiconductor device according to a twenty-first embodiment of the present invention (part 2).
[0159]
  (1) First, as shown in FIG. 14A, through a normal semiconductor device manufacturing process, an element isolation region, a word line (both not shown), a silicon substrate 801,plug801A and bit line 804 are sequentially formed. here,Plug 801AAnd bit lines804The interlayer insulating film is characterized in that the lower layer is composed of a silicon nitride film 802 and the upper layer is composed of a silicon oxide film 803. Thereafter, a silicon oxide film 805 is deposited and planarized by CMP, and then a silicon nitride film 806 is deposited.
[0160]
  (2) Next, as shown in FIG. 14B, a silicon oxide film 807 and a polycrystalline silicon film 808 are sequentially deposited, and then a hole pattern 809 is formed by a normal lithography process. Thereafter, for example, using a parallel plate etching apparatus, the pressure is 20 mTorr, SF₆/ HBr = 26/8 cc / min, RF power = 300 W, cooling He pressure = 4 Torr, the polycrystalline silicon film 808 is anisotropically etched using the silicon oxide film 807 as a stopper, for example, a magnetron etching apparatus Pressure = 40 mTorr, Ar / CO / C_FourF₈= 250/100/8 cc / min, RF power = 1300 W, electrode temperature = 40 ° C., cooling He pressure, center / edge = 3/45 Torr, silicon nitride film 806 as a stopper and silicon oxide film 807 anisotropic A hole 810 is formed by etching.
[0161]
  (3) Next, as shown in FIG.(Hole pattern)After ashing 809, a polycrystalline silicon film is deposited, and for example, pressure = 5 mTorr, Cl using an electron cyclotron resonance (hereinafter abbreviated as ECR) etching apparatus.₂= Sidewall 811 is formed by anisotropic etching under the conditions of 100 cc / min, microwave power 400 W, RF power = 50 W, and electrode temperature = -20 ° C.810An etching mask 812 made of a polycrystalline silicon film having a smaller opening diameter is formed.
[0162]
  (4) Next, as shown in FIG. 14 (d), under a condition that a sufficient selection ratio is obtained with respect to the etching mask 812, for example, using a magnetron etching apparatus in the first step, a pressure of 35 mTorr, CHF_ThreeThe silicon nitride film 806 is etched under the conditions of / CO = 30/170 cc / min, RF power = 1600 W, cooling He back pressure center / edge = 3/70 Torr, and electrode temperature −10 ° C.
[0163]
  Next, in the second step, using a magnetron etching apparatus, pressure = 30 mTorr, Ar / C_FourF₈/ 02 = 300/10/8 cc / min, RF power = 1500 W, cooling He back pressure, center / edge = 3/45 Torr, electrode temperature = −10 ° C., lower than silicon oxide film 805 and bit line 804 The silicon oxide film 803 is anisotropically etched using the silicon nitride film 802 as a stopper, and then in a third step, pressure = 40 mTorr, Ar / CH₂F₂/ O₂By etching the silicon nitride film 802 under the conditions of = 100/10/20 cc / min, RF power = 300 W, cooling He back pressure center / edge = 3/45 Torr, electrode temperature = −10 ° C.plugA contact hole 813 is opened over 801A. Less than,Contact hole 813 as cell contact holeWhenCalled.
[0164]
  (5) Next, as shown in FIG. 15A, after depositing a polycrystalline silicon film 814 having a thickness that does not embed the cell contact hole 813, a silicon oxide film 815 is deposited to thereby form the cell contact hole 813. Embed.
[0165]
  Thereafter, the silicon oxide film 815 is subjected to pressure = 500 mTorr, Ar / CHF using, for example, a parallel plate etching apparatus until the polycrystalline silicon film 814 is exposed._Three/ CF_FourEtch back under the conditions of 400/20/20 cc / min, RF power = 200 W, electrode temperature = 0 ° C., cooling He pressure = 15 Torr.
[0166]
  (6) Next, as shown in FIG. 15B, the polycrystalline silicon film 814 using the silicon oxide film 815 as a mask.And 808For example, using a microwave downflow etching apparatus, pressure = 40 Pa, CF_Four/ O₂= 150/60 cc / min, microwave power = 700 W, electrode temperature = 25 ° C.
[0167]
  (7) Next, as shown in FIG. 15C, the silicon oxide films 807 and 815 are etched with a hydrogen fluoride aqueous solution using the silicon nitride film 806 as a stopper to form a capacitor electrode 816.
[0168]
  Thereafter, after depositing a capacitor insulating film, a polycrystalline silicon film for forming a cell plate electrode is deposited, and a step of forming a cell plate electrode by a normal lithographic process is performed to manufacture a semiconductor device.
[0169]
  According to the twenty-first embodiment, (1) a hole opened in the laminated film of the polycrystalline silicon film 808 and the silicon oxide film 807 using the silicon nitride film 806 as a stopper by a normal lithography process and an etching process.810(2) reducing the opening diameter of the polycrystalline silicon film 812 by using a sidewall 811 made of polycrystalline silicon.etchingAs a mask,plugUsing the silicon nitride film 802 immediately above 801A as a stopper,plugFor 801AcellA step of forming a contact hole 813; and (3) depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing a silicon oxide film 815, thereby forming the cell contact hole 813. And (4) using the polycrystalline silicon film 814 of the above step (3) as a stopper and etching back the silicon oxide film 815 in which the cell contact hole 813 is buried, and using the silicon oxide film 815 as a mask, The step of isotropically etching back the polycrystalline silicon film 814 in the step (3) and the polycrystalline silicon film 812 in the step (2), and the silicon oxide in the step (4) using the silicon nitride film 806 as a stopper Etch the film 815 and the silicon oxide film 807 of the above step (1) using an aqueous hydrogen fluoride solution. Since the semiconductor device is manufactured by performing the process of forming the capacitor electrode 816, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography process, and the manufacturing cost is reduced. A semiconductor device which is low and has a high manufacturing yield can be manufactured.
[0170]
  In the twenty-first embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit lines 804, a sufficient alignment margin can be secured for the mask size in the direction perpendicular to the bit lines 804 with respect to the interval between the bit lines 804. It must be reduced to a degree. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.
[0171]
  Next, a twenty-second embodiment of the present invention is described.
[0172]
  In the twenty-second embodiment, the polysilicon film 814 and the etching mask 812 are anisotropically etched back using the silicon oxide film 815 in which the cell contact hole 813 in the twenty-first embodiment is buried as a mask, and then the silicon nitride film The capacitor electrode 816 is formed by etching the silicon oxide films 815 and 807 with an aqueous hydrogen fluoride solution using 806 as a stopper.
[0173]
  According to the twenty-second embodiment, (1) a hole 810 opened by using a silicon nitride film 806 as a stopper in a laminated film of a polycrystalline silicon film 808 and a silicon oxide film 807 by a normal lithography process and an etching process is formed in the polycrystalline silicon film. (2) using the polycrystalline silicon film 812 whose opening diameter is reduced as a mask,plugUsing the silicon nitride film 802 immediately above 801A as a stopper,plugA step of forming a cell contact hole 813 for 801A, and (3) depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing a silicon oxide film 815, A step of filling the contact hole 813; and (4) etching back the silicon oxide film 815 filling the cell contact hole 813 using the polycrystalline silicon film 814 of the step (3) as a stopper, and then the silicon oxide film 815. Using the mask as a mask, anisotropically etching back the polycrystalline silicon film 814 in the step (3) and the polycrystalline silicon film 812 in the step (2), and (5) using the silicon nitride film 806 as a stopper The silicon oxide film 815 in the step (4) and the silicon oxide film 807 in the step (1) Since the semiconductor device is manufactured by performing the step of forming the capacitor electrode 816 by etching using an aqueous solution, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography step. Thus, it is possible to manufacture a semiconductor device with a low manufacturing cost and a high manufacturing yield.
[0174]
  In the twenty-second embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit lines 804, a sufficient alignment margin can be secured for the mask size in the direction perpendicular to the bit lines 804 with respect to the interval between the bit lines 804. It must be reduced to a degree. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.
[0175]
  Next, a twenty-third embodiment of the present invention is described.
[0176]
  In the twenty-third embodiment, the cell contact hole 813 in the twenty-first embodiment is filled with an organic film, the organic film, the polycrystalline silicon film 814 and the etching mask 812 are etched back together, and then the organic film is incinerated. After that, the capacitor electrode 816 is formed by etching the silicon oxide film 807 with an aqueous hydrogen fluoride solution using the silicon nitride film 806 as a stopper.
[0177]
  According to the twenty-third embodiment, (1) a hole 810 having an opening with a silicon nitride film 806 as a stopper is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 by a normal lithography process and an etching process. (2) using the polycrystalline silicon film 812 whose opening diameter is reduced as a mask,plugUsing the silicon nitride film 802 immediately above 801A as a stopper,plugA step of forming a cell contact hole 813 with respect to 801A, and (3) depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing an organic film, thereby A step of burying the contact holes 813; (4) a step of etching back the organic film, the polycrystalline silicon film 814 in the step (3) and the polycrystalline silicon film 812 in the step (2); ) After ashing the organic film, the silicon oxide film 807 in the above step (1) is etched using an aqueous hydrogen fluoride solution using the silicon nitride film 806 as a stopper to form a capacitor electrode 816. Since the semiconductor device is manufactured, the cell contact hole 813 and the capacitor electrode 816 are formed in one lithography process. It becomes possible to manufacture low cost, it is possible manufacturing yield is higher semiconductor device fabrication.
[0178]
  In the twenty-third embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, a sufficient alignment margin is ensured for the mask size in the direction perpendicular to the bit line 804 with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.
[0179]
  Next, a twenty-fourth embodiment of the present invention will be described.
[0180]
  In the 24th embodiment, after the pad formation in the 21st embodiment,plugThe interlayer insulating film between 801A and the bit line 804 is constituted by a silicon nitride film 802 as an upper layer and a silicon oxide film 803 as a lower layer.
[0181]
  According to the twenty-fourth embodiment, (1) a hole 810 opened by using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 in a stacked film. (2) using the polycrystalline silicon film 812 with a reduced opening diameter as a mask, and using the silicon nitride film 802 immediately below the bit line 804 as a stopper,plugA step of forming a cell contact hole 813 for 801A, and (3) depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing a silicon oxide film 815, A step of filling the cell contact hole 813; and (4) etching back the silicon oxide film 815 filling the cell contact hole 813 using the polycrystalline silicon film 814 of the step (3) as a stopper. 815 is used as a mask, the step of isotropically etching back the polycrystalline silicon film 814 in the step (3) and the polycrystalline silicon film 812 in the step (2), and (5) the silicon nitride film 806 is used as a stopper. The silicon oxide film 815 in the step (4) and the silicon oxide film 807 in the step (1) Since the semiconductor device is manufactured by performing the step of forming the capacitor electrode 816 by etching using an aqueous hydrogen solution, the cell contact hole 813 and the capacitor electrode 816 can be formed in one step of lithography. Thus, it is possible to manufacture a semiconductor device with a low manufacturing cost and a high manufacturing yield.
[0182]
  In the twenty-fourth embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, a sufficient alignment margin is secured for the mask size in the direction perpendicular to the bit line 804 with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.
[0183]
  Next, a twenty-fifth embodiment of the present invention is described.
[0184]
  In the twenty-fifth embodiment, after the steps of FIGS. 14 (a) to (d) are performed, the steps of FIG. 12 (d) and the steps of FIGS. 13 (a) to (c) are performed. .
[0185]
  That is, in the twenty-fifth embodiment, after the cell contact hole 813 in the twenty-first embodiment is opened, (1) a titanium film having a thickness that does not block the cell contact hole 813 is deposited by CVD, and then heat treatment is performed. A step of forming a silicide layer by reacting the polycrystalline silicon film of the pad with a titanium film; and (2) removing the unreacted portion of the titanium film with a mixed aqueous solution of ammonia and hydrogen peroxide, and then performing the cell by CVD. A step of depositing a titanium nitride film having a thickness that does not block the contact hole 813; and (3) filling the cell contact hole 813 with the silicon oxide film 815 and etching back the silicon oxide film 815 until the titanium nitride film is exposed. And (3) a titanium nitride film using the silicon oxide film 815 as a mask. Etching back the silicide layer and the mask polycrystalline silicon film 812 until the silicon oxide film 807 is exposed, and (4) using the silicon nitride film 806 as a stopper, the silicon oxide film 815 and the silicon oxide film 807 used for filling After performing the step of forming the capacitor electrode 816 by etching with an aqueous hydrogen fluoride solution, after depositing a tantalum oxide film as a capacitor insulating film, for example, by CVD, as a cell plate electrode film, for example, as CVD A semiconductor device is manufactured by depositing a titanium nitride film and performing a process of forming a cell plate electrode by normal lithography and etching.
[0186]
  According to the twenty-fifth embodiment, (1) a hole 810 opened by using a silicon nitride film 806 as a stopper by a normal lithography process and etching process is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 in a multilayer film. (2) using the polycrystalline silicon film 812 whose opening diameter is reduced as a mask,plugUsing the silicon nitride film 802 immediately above 801A as a stopper,plugA step of forming a contact hole 813 with respect to 801A, and (3) a titanium film having a thickness that does not block the cell contact hole 813 is deposited by CVD and then heat-treated.plugA step of forming a silicide layer by reacting a 801A polycrystalline silicon film with a titanium film; and (4) removing the unreacted portion of the titanium film with a mixed aqueous solution of ammonia and hydrogen peroxide, and then performing a cell by CVD. A step of depositing a titanium nitride film having a thickness that does not block the contact hole 813; and (5) a step of filling the contact hole 813 with the silicon oxide film 815 and etching back the silicon oxide film 815 until the titanium nitride film is exposed. (6) Etching back the titanium nitride film, the silicide layer, and the polycrystalline silicon film 812 of the mask until the silicon oxide film 807 is exposed using the silicon oxide film 815 as a mask, and (7) the silicon nitride film 806. And the silicon oxide film 815 in the above step (5) Since the silicon oxide film 807 in the step (1) is etched with an aqueous hydrogen fluoride solution to form the capacitor electrode 816, the semiconductor device is manufactured. Therefore, the cell contact hole 813 and the capacitor electrode 816 are manufactured. Can be formed in one lithography process, and a semiconductor device with a low manufacturing cost and a high manufacturing yield can be manufactured.
[0187]
  Further, in the twenty-fifth embodiment, since the capacitor electrode 816 is made of a titanium nitride film, a capacitor electrode having a high relative dielectric constant such as tantalum oxide can be used.
[0188]
  In the twenty-fifth embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line 804 has a sufficient alignment margin with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.
[0189]
  Next, a twenty-sixth embodiment of the present invention is described.
[0190]
  In the twenty-sixth embodiment, the cell contact hole 813 for forming the capacitor electrode 816 is filled using the organic film in the twenty-fifth embodiment, and the organic film and the titanium nitride film / silicide layer / polycrystalline silicon film 812 are etched together. It is something to be backed.
[0191]
  According to the twenty-sixth embodiment, (1) a hole 810 having an opening with a silicon nitride film 806 as a stopper is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 by a normal lithography process and etching process. (2) using the polycrystalline silicon film 812 whose opening diameter is reduced as a mask,plugUsing the silicon nitride film 802 immediately above 801A as a stopper,plugA step of forming a contact hole 813 with respect to 801A, and (3) a titanium film having a thickness that does not block the cell contact hole 813 is deposited by CVD and then heat-treated.plugA step of forming a silicide layer by reacting a 801A polycrystalline silicon film with a titanium film; and (4) removing the unreacted portion of the titanium film with a mixed aqueous solution of ammonia and hydrogen peroxide, and then performing a cell by CVD. A step of depositing a titanium nitride film having a thickness that does not block the contact hole 813; and (5) filling the cell contact hole 813 with an organic film, the organic film, the titanium nitride film, the silicide layer, and the polycrystalline silicon of the mask. A step of etching back the film 812 in a lump; and (6) ashing the organic film, and then etching the silicon oxide film 807 in the step (1) with a hydrogen fluoride aqueous solution using the silicon nitride film 806 as a stopper. And the step of forming the capacitor electrode 816 to manufacture the semiconductor device. The contact hole 813 and the capacitor electrode 816 it is possible to form a lithographic 1 step, manufacturing cost is low, it is possible to produce a high production yield semiconductor device.
[0192]
  Further, in the twenty-sixth embodiment, since the capacitor electrode 816 is made of a titanium nitride film, a capacitor electrode having a high relative dielectric constant such as tantalum oxide can be used.
[0193]
  In the twenty-sixth embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, a sufficient alignment margin is secured for the mask size in the direction perpendicular to the bit line 804 with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.
[0194]
  Next, a twenty-seventh embodiment of the present invention is described.
[0195]
  In the twenty-seventh embodiment, after the cell contact hole 813 in the twenty-fifth embodiment is opened, the cell contact hole 813 is filled with an organic film, and the polycrystalline silicon film 812 constituting the organic film and the mask is etched back collectively. The titanium film is deposited after the organic film is ashed.
[0196]
  According to the twenty-seventh embodiment, (1) a hole 810 opened by using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 in a stacked film. (2) using the polycrystalline silicon film 812 whose opening diameter is reduced as a mask,plugUsing the silicon nitride film 802 immediately above 801A as a stopper,plugA step of forming a contact hole 813 with respect to 801A, and (3) a step of burying the cell contact hole 813 with an organic film and etching back the organic film and the polycrystalline silicon film 812 in the step (2) collectively. (4) ashing the organic film, depositing a titanium film having a thickness that does not block the contact hole 813, and then forming a silicide layer by heat treatment; and (5) depositing the titanium nitride film. A step of filling the contact hole 813 by depositing an organic film, (6) a step of etching back the organic film and the titanium nitride film of the step (5), and (7) ashing the organic film. Then, using the silicon nitride film 806 as a stopper, the silicon oxide film 807 in the step (1) is etched using a hydrogen fluoride aqueous solution. Thus, since the semiconductor device is manufactured by performing the process of forming the capacitor electrode 816, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography process, the manufacturing cost is low, and the manufacturing is performed. A semiconductor device with a high yield can be manufactured.
[0197]
  Further, in the twenty-seventh embodiment, since the capacitor electrode 816 is made of a titanium nitride film, a capacitor electrode having a high relative dielectric constant such as tantalum oxide can be used.
[0198]
  In the twenty-seventh embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line 804 has a sufficient alignment margin with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.
[0199]
  In addition, this invention is not limited to the said Example, A various deformation | transformation is possible based on the meaning of this invention, and these are not excluded from the scope of the present invention.
[0200]
【The invention's effect】
  As described above in detail, according to the present invention, the following effects can be obtained.
[0201]
  (A) Pre-formedplugSince a bit line can be formed without a special lithography process after a contact hole is opened, a bit line suitable for miniaturization of a semiconductor device can be formed. It is possible to reduce the number and manufacturing cost.
[0202]
  (B) Since a contact hole can be formed in a self-aligned manner with respect to the substrate and then a pad for connecting the bit line and the capacitor electrode can be formed without going through a special lithography process. It is possible to reduce the number and manufacturing cost.
[0203]
  (C) Pre-formedplugOn the other hand, since the capacitor electrode can be formed without a special lithography process after the contact hole is opened, it is possible to reduce the number of manufacturing steps and the manufacturing cost.
[Brief description of the drawings]
FIG. 1 is a manufacturing process cross-sectional view of a semiconductor device showing a first embodiment of the invention;
FIG. 2 is a schematic view showing an observation direction of the semiconductor device showing the first embodiment of the invention.
FIG. 3 is a manufacturing process cross-sectional view of a first conventional semiconductor device.
FIG. 4 is a sectional view (No. 1) of a manufacturing process of a second conventional semiconductor device;
FIG. 5 is a sectional view (No. 2) of a manufacturing process of the second conventional semiconductor device;
FIG. 6 is a manufacturing process cross-sectional view (No. 1) of a third conventional semiconductor device;
FIG. 7 is a manufacturing process cross-sectional view (No. 2) of the third conventional semiconductor device;
FIG. 8 is a cross-sectional view of a manufacturing step of a semiconductor device showing a sixth embodiment of the invention.
FIG. 9 is a schematic view of a contact hole pattern of a semiconductor device showing a sixth embodiment of the present invention.
FIG. 10 is a sectional view of the semiconductor device according to the twelfth embodiment of the present invention in the manufacturing process (No. 1).
FIG. 11 is a sectional view of the semiconductor device according to the twelfth embodiment of the present invention in the manufacturing process (No. 2).
FIG. 12 is a sectional view of the semiconductor device according to the eighteenth embodiment of the present invention in the manufacturing process (part 1);
FIG. 13 is a sectional view of the semiconductor device according to the eighteenth embodiment of the present invention in the manufacturing process (No. 2).
FIG. 14 is a sectional view of the semiconductor device according to the twenty-first embodiment of the present invention in the manufacturing process (part 1);
FIG. 15 is a manufacturing process cross-sectional view (No. 2) of the semiconductor device showing the twenty-first embodiment of the invention;
[Explanation of symbols]
  101, 501, 600, 700, 801 Silicon substrate
  102 element isolation region
  103,502 Offset insulating film
  104,503 Transfer gate
  105, 504 First insulating film
  106,508,601,701,801Aplug
  107,505 Second insulating film
  108 Bit line inversion pattern
  109 groove (contact hole)
  110,603,703,804 bit lines
  111 Third insulating film
  112 sidewall
  113 4th insulating film
  114,610A, 711,809 hole pattern
  115 Capacitor electrode contact hole
  506    Contact hole pattern (resist)
  507    Contact hole
  602, 606, 608, 613, 702, 706, 708, 715, 803, 805, 807, 815 Silicon oxide film
  604,704 Upper silicon nitride film
  605,705 Side wall silicon nitride film
  607, 707, 802, 806 Silicon nitride film
  609, 612, 709, 808,814 Polycrystalline silicon film
  610, 710  Resist
  611, 712, 813 Cell contact hole
  614, 716, 816 Capacitor electrode
  713 Titanium silicide layer
  714 Titanium nitride film
  810 holes
  811 sidewall
  812 Polycrystalline silicon film (etching mask)

Claims (5)

In a method for manufacturing a semiconductor device,
(A) An upper layer bit line and a capacitor electrode are connected to an interlayer insulating film whose uppermost layer is the first insulating film that can ensure a sufficient selection ratio with respect to the second insulating film deposited in the second stage. Forming a plug for
(B) After depositing and planarizing a second insulating film capable of securing a sufficient selection ratio with respect to the first insulating film, the inverted pattern of the bit line is used as a mask, and the first insulating film is used as a stopper. Etching the second insulating film;
(C) The pattern is embedded with a conductive material constituting the bit line, the height of the embedded conductive material is lower than the height of the second insulating film , and the recess is formed. Forming a bit line by removing the conductive material;
(D) depositing a third insulating film capable of securing a sufficient selection ratio with respect to the second insulating film, and then filling the recess to fill the third insulating film until the second insulating film is exposed. Removing the second insulating film after removing the film;
(E) the after the third insulating film and depositing an insulating film of the same material, a step of covering the complete side of the bit lines by etching anisotropically,
(F) After depositing and planarizing a fourth insulating film capable of securing a sufficient selection ratio with respect to the first and third insulating films, the third insulating film and the first insulation on the bit lines and on the side surfaces Forming a contact hole for forming a capacitor electrode by etching the fourth insulating film using the film as a stopper.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film and the third insulating film are made of the same material.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film and the fourth insulating film are made of the same material.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film, the third insulating film, the second insulating film, and the fourth insulating film are made of the same material. Method.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the first insulating film and the third insulating film are silicon nitride films, and the second insulating film and the fourth insulating film are silicon oxide films. A method for manufacturing a semiconductor device.

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