JP2000183308A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably form a contact hole between fine bit lines, and to reduce the number of manufacturing processes. SOLUTION: A pad 106 is formed in an insulating film 105, and an insulating film 107 is accumulated on this and flattened, and a groove (contact hole) 109 is formed by using the insulating film 105 as an etching stopper. Then, conductive materials are embedded in the groove 109, and the conductive materials are removed so that recesses (dents) are formed in the insulating film 107, and a bit line 110 is formed. Then, an insulating film 111 is formed on the bit line 110, and the same kinds of insulating films 112 are formed on the side faces of the bit line 110. An insulating film 113 is accumulated, and a contact hole for forming a capacitor electrode is formed in the insulating film 113 with the insulating films 111, 112, and 105 as an etching stopper.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a wiring in a semiconductor device.
The present invention relates to a method for forming an electrode and a method for forming a contact hole.

[0002]

2. Description of the Related Art Conventionally, there is a technique shown in FIG. Hereinafter, a dynamic random access memory (hereinafter, abbreviated as DRAM) will be described as an example in detail with reference to the drawings. [I] (First Prior Art) (1) First, as shown in FIG. 3A, through a normal semiconductor device manufacturing process, an element isolation region (not shown), a transfer gate 202, and a pad 203 Form up to. The pad 203 is formed on the silicon substrate 201 at a position where it contacts the bit line and the capacitor electrode. Note that 201A is an insulating film.

(2) Next, as shown in FIG. 3B, after an insulating film 204 is deposited, a chemical mechanical polishing method (hereinafter referred to as CM
P), and a hole pattern 205 is formed by a normal lithography process, and then the insulating film 204 is etched to open a bit line contact hole 206 with respect to the pad 203.

(3) Next, as shown in FIG. 3C, a bit line contact hole 206 is buried by depositing a conductive material forming a bit line, and then a normal lithography step and an etching step are performed. After that, the bit line 207 is formed.

(4) Next, as shown in FIG. 3D, an insulating film 208 is deposited on the bit line 207, flattened by CMP, and a hole pattern 209 is formed by a normal lithography process. Then, by etching the insulating films 208 and 204, a capacitor electrode contact hole 210 is opened for the pad 203.

[0006] Hereinafter, through a normal semiconductor device manufacturing process, the portion after the capacitor electrode is formed, and the semiconductor device is manufactured. [II] (Second Prior Art) With the miniaturization of semiconductor devices, transfer gate widths and contact hole dimensions have been steadily reduced. However, since the alignment margin in the lithography process is not scaled, an etching technique that absorbs the alignment margin and secures the insulation between the contact hole and the transfer gate is indispensable in the manufacture of semiconductor devices in the future.

Conventionally, there is a technique shown in FIGS. 4 and 5 as a technique in this field. The details will be described below with reference to the drawings.

(1) First, as shown in FIG. 4A, after forming an element isolation region 302 on a silicon substrate 301, a transfer gate 304 on which an offset silicon oxide film 303 is mounted is formed by ordinary lithography and etching. I do. Thereafter, a mask pattern is formed by normal lithography, and an n-type impurity is implanted into the silicon substrate 301 by ion implantation. Note that, for simplicity, a resist pattern at the time of ion implantation is not shown.

(2) Next, as shown in FIG. 4B, a silicon oxide film is formed on the entire surface of the wafer by a chemical vapor deposition method (hereinafter referred to as C
The side wall 305 is formed by depositing by VD method and etching anisotropically.

(3) Next, as shown in FIG. 4C, a mask pattern is formed by a normal lithography process, and
Type impurities and p-type impurities are implanted into the silicon substrate 301 by ion implantation. Note that, for simplicity, a resist pattern at the time of ion implantation is not shown.

(4) Next, as shown in FIG. 4D, a silicon oxide film is deposited, a silicon nitride film 307 having a thickness functioning as a stopper is deposited, and then a silicon oxide film 308 is deposited. Flatten by CMP.

(5) Next, as shown in FIG. 5A, a hole pattern 309 for opening a contact hole 310 is formed in the silicon substrate by ordinary lithography, and oxidation is performed using the silicon nitride film 307 as a stopper. After etching the silicon film 308, the silicon nitride film 307 and the silicon oxide film are etched,
A contact hole 310 is opened in the silicon substrate 301.

(6) Next, as shown in FIG. 5B, the contact hole 310 is filled with a polycrystalline silicon film.
The pads 311 are formed by etching back.

(7) Next, as shown in FIG. 5C, after depositing a silicon oxide film 312, a contact hole pattern 313 for connecting the silicon substrate to the bit line is formed by ordinary lithography. Then, using the silicon nitride film 307 as a stopper, the silicon oxide films 312 and 312
After etching 08, a bit line contact hole 314 is formed in the silicon substrate 301 by etching the silicon nitride film 307 and the silicon oxide film.

Hereinafter, a semiconductor device is manufactured through a normal semiconductor device manufacturing process. [III] (Third Prior Art) Conventionally, there is a technology disclosed in FIGS. 6 and 7 as a technology in this field. The details will be described below with reference to the drawings.

(1) First, as shown in FIG. 6A, a silicon oxide film 404 is deposited as an interlayer insulating film after forming up to a bit line 403 by a normal DRAM manufacturing process, and flattened by, for example, CMP. Then, a silicon nitride film 405 is deposited. Although the transfer gate is originally formed facing the bit line, it is not shown for simplicity.

(2) Next, as shown in FIG. 6B, after a polycrystalline silicon film 406 is deposited, a hole pattern 407 is formed by a usual lithography process. Thereafter, the polycrystalline silicon film 406 is anisotropically etched using the silicon nitride film 405 as a stopper to form holes 408.
To form

(3) Next, as shown in FIG. 6 (c), a polycrystalline silicon film is deposited after the resist 407 is ashed and anisotropically etched to form a side wall 409 to form a hole. With an opening diameter smaller than 408,
Etching mask 410 composed of polycrystalline silicon film
To form

(4) Next, as shown in FIG. 6D, the silicon nitride film 405 and the silicon oxide film 404 are set under a condition that a sufficient selectivity with respect to the etching mask 410 can be obtained.
A contact hole 411 is formed on the silicon substrate 401 by simultaneously etching the interlayer insulating film 402 below the bit line 403. Hereinafter, this contact hole is referred to as a cell contact hole.

(5) Next, as shown in FIG. 7A, a polycrystalline silicon film is deposited and a cell contact hole 411 is formed.
Is embedded, and the polycrystalline silicon film is etched back to form the pad 412.

(6) Next, as shown in FIG. 7B, after a silicon oxide film 413 is deposited, a hole pattern for opening a contact hole 415 with respect to a pad 412 in the cell contact hole 411 is formed. 414 is formed by a normal lithography process. Hereinafter, this contact hole is referred to as a capacitor electrode contact hole. Thereafter, the capacitor electrode contact hole 415 is opened by etching the silicon oxide film 413 until the silicon oxide film 405 reaches the pad 412 in the cell contact hole 411 under a condition that the selectivity is sufficiently high with respect to the silicon nitride film 405.

(7) Next, as shown in FIG. 7C, after the resist 414 is ashed, a polycrystalline silicon film 416 constituting a capacitor electrode and a silicon oxide film for filling a capacitor electrode contact hole 415 are formed. 417 are sequentially deposited. After that, the silicon oxide film 417 is etched back until the polysilicon film 416 is exposed, and then the exposed portion of the polysilicon film 416 is etched.

(8) Next, as shown in FIG. 7D, by using the silicon nitride film 405 as a stopper, the silicon oxide films 417 and 413 are removed with an aqueous solution of hydrogen fluoride to form a capacitor electrode 418. . Thereafter, a polycrystalline silicon film for forming a capacitor insulating film 419 and a cell plate electrode is deposited, and a cell plate electrode 420 is formed by ordinary lithography and etching.

[0024]

However, in the above-mentioned conventional method for manufacturing a semiconductor device of [I], a margin for alignment in the lithography process is secured because the wiring interval is reduced as the miniaturization of the semiconductor device progresses. And it is difficult to stably open a contact hole between wirings. On the other hand, in order to secure an alignment margin in the lithography process, the wiring width must be smaller than the miniaturization ratio of the semiconductor device, but it is not easy to form a fine wiring pattern in the lithography process. was there.

As described above, there is a fatal problem that it is difficult to increase the yield of semiconductor device manufacturing in the above [1] conventional semiconductor device manufacturing method.

In the conventional method for manufacturing a semiconductor device of the above [II], the semiconductor device is manufactured by performing two steps of self-aligningly opening a contact hole using the silicon nitride film as a stopper. In order to increase the manufacturing yield of semiconductor devices, a technology for stably opening a contact hole having a fine opening diameter with respect to a silicon nitride film having a fine slit width in response to the miniaturization of semiconductor devices has advanced. It is essential. In general, it is difficult to achieve a balance between selectivity to a silicon nitride film and workability of a fine contact hole. Therefore, there is a problem that it is not always easy to realize a high production yield by the above method.

Furthermore, in the above-mentioned conventional method of manufacturing a semiconductor device of [III], it is essential to secure a margin for alignment in a lithography step when opening a capacitor electrode contact hole with respect to a cell contact hole. .

If the alignment margin cannot be ensured, the capacitor electrode contact hole is opened with a deviation from the cell contact hole. Therefore, in the step of etching the silicon oxide film with an aqueous solution of hydrogen fluoride using the silicon nitride film as a stopper, This is because the silicon oxide film is etched from the side wall of the contact hole, and the production yield is reduced due to a short circuit between the capacitor electrode and the bit line, collapse of the capacitor electrode, and the like. To avoid this, it is necessary to make the amount of recess of the pad smaller than the silicon nitride film thickness.However, it is impossible to stably reduce the recess of the pad in the etch back to the thickness of the silicon nitride film or less. It's not easy.

In general, the processing size of each process is reduced in accordance with the miniaturization of the semiconductor device. However, the margin of the lithography process does not decrease in accordance with the miniaturization of the semiconductor device. Then, the above problems become more apparent.

A first object of the present invention is to eliminate the above-mentioned problems and to stably form a contact hole between wirings even if the miniaturization of a semiconductor device is advanced. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming electrodes.

A second object of the present invention is to provide a method of manufacturing a semiconductor device which eliminates the above-described problems, can easily and self-align contact holes, and has a high manufacturing yield. To provide.

[0032]

In order to achieve the above object, the present invention provides: (1) a method of manufacturing a semiconductor device, wherein (a) a second insulating film deposited in a second stage is sufficiently formed; Forming a pad for connecting to an upper bit line and a capacitor electrode in an interlayer film having the first insulating film as an uppermost layer capable of ensuring a high selectivity; and (b) forming a pad with respect to the first insulating film. Depositing and planarizing a second insulating film capable of securing a sufficient selectivity by etching, and then etching the second insulating film using the inverted pattern of the bit line as a mask and the first insulating film as a stopper; (C) forming a bit line by burying the pattern with a conductive material forming the bit line and removing the conductive material so that the conductive material is recessed with respect to a second insulating film; (D) the second insulating film After the recess is buried by depositing a third insulating film capable of securing a sufficient selectivity with respect to the second insulating film, the third insulating film is removed until the second insulating film is exposed. (E) depositing an insulating film of the same type as the third insulating film, and then anisotropically etching to completely cover the side surface of the bit line; (f) After depositing and flattening a fourth insulating film capable of ensuring a sufficient selectivity with respect to the first and third insulating films, the third insulating film and the first insulating film on the bit lines and side surfaces are removed. Forming a contact hole for forming a capacitor electrode by etching the fourth insulating film and the second insulating film as a stopper.

[2] The method for manufacturing a semiconductor device according to [1], wherein the first insulating film and the third insulating film are made of the same material.

[3] The method of manufacturing a semiconductor device according to the above [1], wherein the second insulating film and the fourth insulating film are made of the same material.

[4] In the method of manufacturing a semiconductor device according to [1], the first insulating film and the third insulating film, and the second insulating film and the fourth insulating film are made of the same material. It was done.

[5] In the method of manufacturing a semiconductor device according to the above [4], the first insulating film and the third insulating film are silicon nitride films, and the second insulating film and the fourth insulating film are formed. Is a silicon oxide film.

[6] In the method of manufacturing a semiconductor device,
(A) a step of forming an element isolation region and a transfer gate; (b) a step of stacking a combination of insulating films capable of securing a sufficient selection ratio; and (c) an active region and an upper layer with respect to the insulating film. A step of forming a pattern by lithography capable of etching a region connected to a region where a pad for connecting to a wiring or an electrode is present, and
(D) Of the laminated insulating films, the upper insulating film is etched in a self-aligned manner using the lower insulating film as a stopper, and then the lower insulating film is etched to form a contact hole in the silicon substrate. Process and
(E) after filling the contact hole with a conductive material, removing the conductive material until the contact hole reaches a position lower than the upper surface of the offset insulating film on the transfer gate.

[7] In the method for manufacturing a semiconductor device according to the above [6], after the upper insulating film is flattened, it is sufficiently higher than the lower insulating film until the lower insulating film on the transfer gate is exposed. The upper insulating film is removed at a selectivity.

[8] In the method of manufacturing a semiconductor device according to the above [6], a silicon oxide film is used as an offset insulating film, a silicon nitride film is used as an insulating film of an etching stopper, and a silicon oxide film is used as an insulating film above the insulating film. It is like that.

[0040]

[9] The method for manufacturing a semiconductor device according to [8], wherein a silicon nitride film is used for the offset insulating film.

[10] The method for manufacturing a semiconductor device according to the above [8], wherein the offset insulating film is formed of a laminated film, and a silicon oxide film is used as the uppermost insulating film.

[11] The method for manufacturing a semiconductor device according to the above [8], wherein the offset insulating film is formed of a laminated film, and a silicon nitride film is used as the uppermost insulating film.

[12] In a method of manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate and a capacitor electrode forming step, (a) a polycrystalline silicon film, a silicon oxide film, Processing a laminated film of a silicon nitride film by a lithography step and an etching step; and (b) forming the silicon nitride film in advance using the polycrystalline silicon film as a mask;
(C) etching a bit line having a structure in which an upper part and a side wall are covered with a silicon nitride film using the silicon nitride film as a stopper to form a contact hole with a pad formed in advance; A) depositing a polycrystalline silicon film having a thickness that does not block the contact hole, and then depositing a silicon oxide film to bury the contact hole; and (d) the step (c).
The silicon oxide film in which the contact holes are buried is etched back using the polycrystalline silicon film as a stopper, and then the polycrystalline silicon film of the above step (c) and the polycrystalline silicon of the above step (a) are etched using this silicon oxide film as a mask. (E) isotropically etching back the silicon film;
Using the silicon nitride film as a stopper, etching the silicon oxide film of the step (d) and the silicon oxide film of the step (a) using an aqueous solution of hydrogen fluoride to form a capacitor electrode; f) A contact hole for connecting a capacitor electrode and a silicon substrate, and a capacitor electrode are formed in one lithography step.

[13] In the method of manufacturing a semiconductor device according to the above [12], the polycrystalline silicon film in the step (c) and the polycrystalline silicon film in the step (a) are anisotropically using the silicon oxide film as a mask. It is designed to be etched back.

[14] In the method of manufacturing a semiconductor device according to the above [12], after the organic film is deposited, the organic film, the polycrystalline silicon film of the step (c) and the polycrystalline silicon film of the step (a) are deposited. Are collectively etched back.

[15] The method of manufacturing a semiconductor device according to the above [12], wherein the uppermost layer of the interlayer insulating film on which the pads are formed is a silicon nitride film.

[16] In the method of manufacturing a semiconductor device according to the above [12], after the polycrystalline silicon film is etched and the resist is ashed, a silicon oxide film and a silicon nitride film are formed using the polycrystalline silicon film as a mask. Is etched, and then the silicon oxide film is etched using the silicon nitride films on the bit line upper and side walls as stoppers.

[17] In the method of manufacturing a semiconductor device according to the above [12], after the polycrystalline silicon film and the silicon oxide film are etched and the resist is ashed, the silicon nitride film is formed using the polycrystalline silicon film as a mask. After the etching, the silicon oxide film is etched using the silicon nitride films on the bit lines and on the side walls as stoppers.

[18] In a method of manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate and a capacitor electrode forming step, (a) a polycrystalline silicon film, a silicon oxide film, Processing a laminated film of a silicon nitride film by a normal lithography process and an etching process;
(B) Using the polycrystalline silicon film as a mask, a bit line having a structure in which an upper portion and a side wall are covered with a silicon nitride film is etched using the silicon nitride film as a stopper. Forming a contact hole for the formed pad; (c)
Depositing a titanium film having a thickness that does not block the contact hole, and then forming a silicide layer by heat treatment; and (d) depositing a titanium nitride film and then depositing a silicon oxide film to form the contact. (E) etching back the silicon oxide film with the contact hole embedded therein using the titanium nitride film of step (d) as a stopper, and then using the silicon oxide film as a mask, Anisotropically etching back the titanium nitride film, the silicide layer of the step (c) and the polycrystalline silicon film of the step (a), and (f) the step (d) of using the silicon nitride film as a stopper. The silicon oxide film and the silicon oxide film obtained in the above step (a) are etched by using an aqueous solution of hydrogen fluoride to obtain a capacitor. Subjected to a step of forming a lower electrode, contact hole, and lithography capacitor electrodes 1 connected to (g) capacitor electrode and the silicon substrate
It is formed in a process.

[19] In the method of manufacturing a semiconductor device according to the above [13], after the organic film is deposited, the organic film and the titanium nitride film / silicide layer / polycrystalline silicon film are collectively etched back. Things.

[20] In the method for manufacturing a semiconductor device according to the above [13], after opening the contact hole,
This contact hole is buried with an organic film, and the organic film and the polycrystalline silicon film are simultaneously etched.

[21] In a method of manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate and a capacitor electrode forming step, (a) forming a polycrystalline silicon film and a silicon oxide film A step of using a sidewall made of polycrystalline silicon to reduce a hole opened by a lithography step and an etching step using a silicon nitride film as a stopper, and (b) masking the polycrystalline silicon film with a reduced opening diameter. A step of forming a contact hole on the pad formed in advance using the silicon nitride film immediately above the pad as a stopper, and (c) depositing a polycrystalline silicon film having a thickness that does not block the contact hole. Later, the contact hole is buried by depositing a silicon oxide film. A step, (d) the step (c)
The silicon oxide film in which the contact holes are buried is etched back using the polycrystalline silicon film as a stopper, and then the polycrystalline silicon film of the above step (c) and the polycrystalline silicon of the above step (a) are etched using this silicon oxide film as a mask. (E) isotropically etching back the silicon film;
Using the silicon nitride film as a stopper, etching the silicon oxide film of the step (d) and the silicon oxide film of the step (a) using an aqueous solution of hydrogen fluoride to form a capacitor electrode; f) A contact hole for connecting a capacitor electrode and a silicon substrate, and a capacitor electrode are formed in one lithography step.

[22] In the method of manufacturing a semiconductor device according to the above [21], the polycrystalline silicon film in the step (c) and the polycrystalline silicon film in the step (a) are anisotropically using the silicon oxide film as a mask. It is designed to be etched back.

[23] In the method of manufacturing a semiconductor device according to the above [21], after the organic film is deposited, the organic film and the polycrystalline silicon film of the above step (c) and the polycrystalline silicon of the above step (a) are obtained. The film is etched back collectively.

[24] In the method for manufacturing a semiconductor device according to the above [21], the interlayer insulating film after the formation of the pad is configured such that the upper layer is composed of a silicon nitride film and the lower layer is composed of a silicon oxide film.

[25] In a method of manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate and a capacitor electrode forming step, (a) forming a polycrystalline silicon film and a silicon oxide film A step of reducing a hole opened by using a silicon nitride film as a stopper in the laminated film by a normal lithography step and an etching step by using a side wall made of polycrystalline silicon; and (b) polycrystalline silicon having a reduced opening diameter. Forming a contact hole for the pad using the film as a mask and the silicon nitride film immediately above the pad as a stopper; and (c) depositing a titanium film having a thickness that does not block the contact hole, followed by heat treatment. By reacting the polysilicon film of the pad with the titanium film, (D) removing the titanium film in the unreacted portion with an aqueous solution of a mixture of an ammonia film and a hydrogen peroxide solution, and then depositing a titanium nitride film having a thickness that does not block the cell contact holes. (E) filling the contact hole with a silicon oxide film, and etching back the silicon oxide film until the titanium nitride film is exposed in the step (d); (f)
Using the silicon oxide film as a mask, etching back the titanium nitride film, the silicide layer, and the polycrystalline silicon film as a mask; and (g) using the silicon nitride film as a stopper, the silicon oxide film of the above step (e) and the above step (A) etching the silicon oxide film with an aqueous solution of hydrogen fluoride to form a capacitor electrode; and (h) forming a contact hole connecting the capacitor electrode and the silicon substrate and a capacitor electrode in one lithography step. It is made to be formed by.

[26] In the method of manufacturing a semiconductor device according to the above [25], after the organic film is deposited, the organic film, the titanium nitride film, the silicide layer, and the polycrystalline silicon film are collectively etched back. Things.

[27] In the method for manufacturing a semiconductor device according to the above [25], after opening the contact hole,
This contact hole is buried with an organic film, and the organic film and the polycrystalline silicon film are simultaneously etched.

[0059]

Embodiments of the present invention will be described below in detail.

FIG. 1 is a sectional view showing a semiconductor device manufacturing process according to a first embodiment of the present invention. Here, a DRAM will be described as an example and will be described in detail with reference to the drawings. Note that the memory cell array section shown in FIG. 1 schematically shows a cross section observed in the AA ′ direction in FIG.

(1) First, as shown in FIG. 1A, an element isolation region 10 is formed through a normal semiconductor device manufacturing process.
2. The transfer gate 104 on which the offset insulating film 103 is mounted and the pad 106 are formed. The pad 106 is formed on the silicon substrate 101 at a position where the bit line and the capacitor electrode are in contact, and at a position where the bit line and the transfer gate 104 are in contact. Here, the uppermost layer of the interlayer insulating film on which the pad 106 is formed is constituted by the first insulating film 105 which can secure a selectivity with respect to the insulating film deposited in the next step.

(2) Next, as shown in FIG. 1B, a second insulating film 107 is deposited and planarized by CMP. Thereafter, an inverted pattern 108 of the bit line is formed by a normal lithography process, and the first insulating film 105 is formed.
Is used as a stopper until the pad 106 is reached.
A groove (contact hole) 109 is formed by etching the insulating film 107 of FIG.

(3) Next, as shown in FIG. 1C, the groove 109 is buried with the bit line 110, and the groove 109 is removed so as to generate a recess (dent) on the upper surface of the second insulating film 107. Thus, the bit line 110 is formed. After that, a third insulating film 111 capable of securing a sufficient selection ratio with respect to the second insulating film 107 is deposited, so that the recess is completely buried, and then the third insulating film 111 is exposed until the second insulating film 107 is exposed. The insulating film 111 is removed.

Here, the amount of recess when the bit line 110 is removed is determined by the fact that the third insulating film 111
It is set so that a withstand voltage of 10 can be ensured and the remaining thickness of the bit line film that satisfies a predetermined bit line resistance can be ensured.

(4) Next, as shown in FIG. 1D, after the second insulating film 107 is selectively removed,
An insulating film of the same type as the third insulating film 111 existing in 10 is deposited, and is etched back anisotropically to form a sidewall 112. Here, the amount of the second insulating film 107 to be removed may be at least the thickness of the third insulating film 111 on the bit line 110, and may be a part or all of the thickness.

(5) Next, as shown in FIG. 1E, a fourth insulating film 113 capable of securing a sufficient selection ratio with respect to the first insulating film 105 and the third insulating film 111 is deposited. Then, the hole pattern 11 is formed by a normal lithography process.
4 is formed. Thereafter, the fourth insulating film 113 is etched while securing insulation from the bit line 110 by using the third insulating film 111 and the side wall 112 as a stopper, and the second insulating film 105 is used as a stopper with the first insulating film 105 as a stopper. By etching the insulating film 107 with a sufficient overetching amount, a capacitor electrode contact hole 115 is opened in the pad 106.

Hereinafter, through a normal semiconductor device manufacturing process, the portion after the capacitor electrode is formed, and the semiconductor device is manufactured.

As described above, according to the first embodiment, (1)
The upper bit line 110 and the capacitor electrode are connected to an interlayer insulating film having the first insulating film 105 as an uppermost layer, which can secure a sufficient selection ratio with respect to the second insulating film 107 deposited in the second stage. Forming a pad 106 for
(2) After depositing and planarizing the second insulating film 107 that can secure a sufficient selectivity with respect to the first insulating film 105, the first insulating film 105 is formed by using the inverted pattern of the bit line 110 as a mask. A step of etching the second insulating film 107 as a stopper, and (3) embedding the pattern with a conductive material forming the bit line 110 to form the second insulating film 107.
7) forming the bit line 110 by removing the conductive material so that the conductive material is recessed with respect to 7; and (4) the step of securing a sufficient selectivity to the second insulating film 107. By depositing the third insulating film 111,
Removing the third insulating film 111 until the second insulating film 107 is exposed after the recess is buried, and then removing the second insulating film; and (5) the same type as the third insulating film 111. A process of completely covering the side surface of the bit line 110 by anisotropically etching after depositing an insulating film of
(6) After depositing and flattening a fourth insulating film 113 capable of securing a sufficient selection ratio with respect to the first insulating film 105 and the third insulating film 111, the third upper surface and the side surface of the bit line 110 Forming a contact hole 115 for forming a capacitor electrode by etching the fourth insulating film 113 and the second insulating film 107 using the insulating film 111 and the first insulating film 105 as stoppers. Since the semiconductor device is manufactured, a bit line corresponding to the miniaturization of the semiconductor device can be formed. In addition, a bit line can be formed without going through a special lithography step, so that the number of manufacturing steps and the manufacturing cost can be reduced.

Next, a second embodiment of the present invention will be described.

In the second embodiment, the first embodiment is similar to the first embodiment.
The material of the insulating film 105 and the material of the third insulating film 111 are the same.

With this structure, according to the second embodiment, the first insulating film 105 and the third insulating film 111 in the first embodiment are made of the same material.
The same effect as that of the embodiment can be realized.

Next, a third embodiment of the present invention will be described.

In the third embodiment, the second embodiment in the first embodiment
And the fourth insulating film 113 are made of the same material.

With this configuration, according to the third embodiment, the second insulating film 107 and the fourth insulating film 113 in the first embodiment are made of the same material.
The same effect as that of the embodiment can be realized.

Next, a fourth embodiment of the present invention will be described.

In the fourth embodiment, the first embodiment is similar to the first embodiment.
Of the insulating film 105 and the third insulating film 111 are the same,
The materials of the second insulating film 107 and the fourth insulating film 113 are the same.

With this configuration, according to the fourth embodiment, the first insulating film 105 and the third insulating film 111 in the first embodiment are made of the same material, and the second insulating film 107 and the third insulating film 111 are the same. Because the same material was used for the insulating film 113 of No. 4,
The same effect as that of the first embodiment can be realized.

Next, a fifth embodiment of the present invention will be described.

In the fifth embodiment, the first embodiment of the fourth embodiment
A silicon nitride film is used for the insulating film 105 and the third insulating film 111, and a silicon oxide film is used for the second insulating film 107 and the fourth insulating film 113.

Here, when the conductive material forming the bit line 110 is tungsten polycide, as a method of removing the conductive material so as to recess the second insulating film 107, that is, the silicon oxide film, for example, Pressure of 5 m using an electron cyclotron resonance type etching apparatus
Torr, Cl ₂ / O ₂ = 190/10 cc / mi
n, microwave power = 400 W, RF power = 40
W, some etch back at electrode temperature = 20 ° C.

Next, as a method for removing the second insulating film 107, that is, the silicon oxide film, there is, for example, a method in which the silicon oxide film is wet-etched with a hydrogen fluoride aqueous solution.

After the recess of the bit line 110 is buried with the third insulating film 111, ie, the silicon nitride film, the silicon nitride film is removed until the second insulating film 107, ie, the upper surface of the silicon oxide film is exposed. For example, using a microwave downflow type etching apparatus, pressure = 80 Pa, CF ₄ / O ₂ / Cl ₂ / N ₂ = 270 /
Some etching is performed at 270/170/80 cc / min, microwave power = 600 W, and electrode temperature = 20 ° C. As a condition for forming a sidewall by anisotropically etching after depositing the third insulating film 111, for example, using a parallel plate type etching apparatus,
Pressure 300 mTorr, Ar / CHF ₃ / CF ₄ = 40
0/25/15 cc / min, RF power = 350
W, some etch at 0 ° C. electrode temperature.

As a condition for etching the fourth insulating film 113, that is, the silicon oxide film, using the third insulating film 111 and the first insulating film 105, that is, the silicon nitride film as stoppers, pressure is applied using a magnetron etching apparatus. = 40 mTorr, Ar / C ₄ F ₈ / CH ₂ F ₂ = 5
00/20/7 cc / min, RF power = 1500
W, cooling He pressure center / edge = 3/40 Torr
r, some etch at electrode temperature = 40 ° C.

With this structure, according to the fifth embodiment, the first insulating film 105 and the third insulating film 111 of the fourth embodiment are formed of a silicon nitride film and the second insulating film 107.
Since the silicon oxide film is used for the fourth insulating film 113, the same effect as that of the first embodiment can be realized.

Next, a sixth embodiment of the present invention will be described.

FIG. 8 is a cross-sectional view of a semiconductor device showing a sixth embodiment of the present invention in the manufacturing process, and FIG. 9 is a schematic view of the contact hole pattern.

(1) First, as shown in FIG. 8A, after forming an element isolation region on a silicon substrate 501, a transfer gate 503 on which an offset insulating film 502 is mounted is formed by ordinary lithography and etching. In addition,
After the transfer gate is formed, it goes without saying that the transfer gate 503 is set to perform a desired operation through a normal semiconductor device manufacturing process.

(2) Next, as shown in FIG. 8B, a first insulating film 504 and a second insulating film 505 are deposited, and then the second insulating film 505 is planarized by CMP. . Note that the first insulating film 504 and the second insulating film 505 are combined so that the value of the ratio of the etch rates, that is, the selection ratio becomes a sufficiently high value.

(3) Next, as shown in FIG. 8C, a contact hole pattern (resist) 506 is formed by a usual lithography process. As shown in FIG. 9, the contact hole pattern 506 is a region connecting the activated region formed in the step of FIG. 8A and the region where the pad for connecting the upper layer wiring or electrode to the silicon substrate is present. Are designed to be etched at once.

(4) Next, as shown in FIG. 8D, the second insulating film 50 is formed using the first insulating film 504 as a stopper.
5 and then the first insulating film 504 is etched, so that a contact hole 507 to be filled with a pad is opened in the silicon substrate.

(5) Next, as shown in FIG. 8E, after the contact pattern (resist) 506 is ashed,
The pad 508 is formed by removing the conductive material from filling the contact hole 507 with the conductive material forming the pad and reaching a position lower than the uppermost surface of the offset insulating film 502.

Hereinafter, a semiconductor device is manufactured by connecting an electrode or a wiring to the pad via a contact hole.

With this structure, according to the sixth embodiment, after the element isolation region and the transfer gate 503 are formed by the usual semiconductor device manufacturing method, (1) a sufficient selection ratio is obtained. A step of laminating a combination of insulating films that can be secured, and (2) a region where the active region is connected to a region where a pad for connecting to an upper layer wiring or an electrode is present is collectively etched with respect to the insulating film. Forming a possible pattern by ordinary lithography, and etching the upper insulating film in a self-aligned manner using the lower insulating film as a stopper of the laminated insulating film, and then forming the lower insulating film. Forming a contact hole 507 in the silicon substrate by etching the contact hole 507; Offset insulating film on the Ageto 5
Since the step of removing the conductive material is performed until the contact hole 507 reaches a position lower than the upper surface of the contact hole 507, the depth to be etched in the step of forming the contact hole 507 in a self-aligned manner can be suppressed. Therefore, it is possible to provide a semiconductor device manufacturing method with a high manufacturing yield.

In addition, since a combination of insulating films capable of ensuring a sufficient selectivity is deposited, the pad 508 is formed through a process of self-aligned etching using the pattern disclosed in this embodiment as a mask. After depositing one or both of the insulating films, a contact hole 507 for connecting a wiring or an electrode is formed on the pad 508.
Even when the contact hole is shifted from the pad 508 and opened, it is possible to prevent one of the insulating films from being excessively etched.
A semiconductor device can be manufactured with only one step of opening the contact hole 507 in a self-aligned manner, and a semiconductor device manufacturing method with a high manufacturing yield can be provided.

Next, a seventh embodiment of the present invention will be described.

In the seventh embodiment, after the upper (second) insulating film 505 in the sixth embodiment is flattened, the lower insulating film 504 on the transfer gate is exposed until the lower (first) insulating film 504 is exposed. The upper insulating film 505 is removed at a sufficiently high selectivity with respect to the film 504.

With this structure, according to the seventh embodiment, after the upper insulating film 505 in the sixth embodiment is flattened, the lower insulating film 504 is exposed until the lower insulating film 504 on the transfer gate is exposed. The upper insulating film 505 is removed with a sufficiently high selectivity to the semiconductor device, so that the depth of the contact hole can be reduced more than in the sixth embodiment, and a method of manufacturing a semiconductor device with a high manufacturing yield can be provided. Is possible.

Next, an eighth embodiment of the present invention will be described.

The eighth embodiment is different from the sixth embodiment in that
The offset insulating film 502 is made of a silicon oxide film, the lower insulating film 504 used as an etching stopper is made of a silicon nitride film, and the upper insulating film 505 is made of a silicon oxide film. When a silicon nitride film is used for the lower insulating film 504, the transfer gate 5
03 and the silicon substrate 501 and the pad 508, the side surfaces of the silicon substrate 501 and the transfer gate 503 are oxidized before the lower insulating film 50 is formed.
4 may be deposited and is not excluded from the scope of the present invention.

Here, as a condition for etching the silicon oxide film of the upper insulating film 505 using the silicon nitride film of the lower insulating film 504 as a stopper, for example, using a magnetron etching apparatus, pressure = 40 mTorr, Ar
/ CO / C ₄ F ₈ = 200/150/9 cc / mi
n, RF power = 1300 W, electrode temperature = 30 ° C., electrode spacing = 27 mm, cooling He pressure, center / edge = 3
/ 45 Torr. Next, as conditions for etching the lower insulating film 504, for example, using a magnetron etching apparatus, pressure = 50 mTorr, Ar / CH
F ₃ / O ₂ = 100/20/20 cc / min, RF power = 300 W, electrode temperature = 30 ° C., electrode spacing = 32 m
m, cooling He pressure center / edge = 3/45 Torr
There is r.

With this configuration, according to the eighth embodiment, in the sixth embodiment, a silicon oxide film is used as the offset insulating film 502, a silicon nitride film is used as the lower insulating film 504 used as an etching stopper, and an upper insulating film 505 is used. Since the silicon oxide film is used, the same effect as that of the sixth embodiment can be realized.

Next, a ninth embodiment of the present invention will be described.

The ninth embodiment is different from the eighth embodiment in that
A silicon nitride film is used for the offset insulating film 502.

With this configuration, according to the ninth embodiment, since the silicon nitride film is used for the offset insulating film 502 in the eighth embodiment, the same effect as that of the sixth embodiment is realized. It is possible.

Next, a tenth embodiment of the present invention will be described.

The tenth embodiment is different from the sixth embodiment in that the offset insulating film 502 is formed of a laminated film and a silicon oxide film is used as the uppermost insulating film.

With this configuration, according to the tenth embodiment, the offset insulating film 502 in the sixth embodiment is formed of a laminated film, and the silicon oxide film is used as the uppermost insulating film. It is possible to achieve the same effect as that of the sixth embodiment.

Next, an eleventh embodiment of the present invention will be described.

In the eleventh embodiment, the offset insulating film 502 in the sixth embodiment is formed of a laminated film, and a silicon nitride film is used as the uppermost insulating film.

With this structure, according to the eleventh embodiment, the offset insulating film 502 in the sixth embodiment is composed of a laminated film, and the silicon nitride film is used as the uppermost insulating film. It is possible to achieve the same effect as that of the sixth embodiment.

Next, a twelfth embodiment of the present invention will be described.

FIG. 10 is a sectional view of a semiconductor device showing a twelfth embodiment of the present invention (part 1), and FIG. 11 is a sectional view of a semiconductor device showing a twelfth embodiment of the present invention (part 2). It is. The details will be described below with reference to the drawings.

(1) First, as shown in FIG.
After a normal semiconductor device manufacturing process, an element isolation region, a word line (both not shown), a pad 601 on a silicon substrate 600, a silicon oxide film 602, and a bit line 603 are sequentially formed. Here, the bit line 603 is characterized by being covered with an upper silicon nitride film 604 and a silicon nitride film 605 on a side wall. As a typical example, the interval between the silicon nitride films on the side walls of the bit line is set to about 0.08 μm. After that, a silicon oxide film 606 is deposited and planarized by CMP, and then a silicon nitride film 607 is deposited.

(2) Next, as shown in FIG.
After sequentially depositing the silicon oxide film 608 and the polycrystalline silicon film 609, a hole pattern 610A for forming a capacitor electrode is formed by a normal lithography process. Thereafter, using the silicon oxide film 608 as a stopper, for example, using a parallel plate type etching apparatus, the pressure is 20 mTorr, SF ₆ / HBr = 26/8 cc / m.
in, RF power = 300 W, cooling He pressure = 4 Torr
After etching the polycrystalline silicon film 609 under the conditions of r, the pressure = 40 m using the silicon nitride film 607 as a stopper, for example, using a magnetron etching apparatus.
Torr, Ar / CO / C ₄ F ₈ = 250/100/8
cc / min, RF power = 1300 W, electrode temperature = 4
0 ° C, cooling He pressure center / edge = 3 / 45To
The silicon oxide film 608 is etched under the condition of rr, and for example, using a magnetron etching apparatus, pressure = 5.
0 mTorr, Ar / CHF ₃ / O ₂ = 100/25 /
15 cc / min, RF power = 300 W, electrode temperature =
40 ° C, cooling He pressure center / edge = 3 / 45T
The silicon nitride film 607 is etched under the conditions of orr.

(3) Next, as shown in FIG.
After the resist 610 is ashed, using the silicon nitride film 604 on the bit lines and the silicon nitride film 605 on the side walls as stoppers, for example, using a magnetron etching apparatus, pressure = 40 mTorr, Ar / CO / C ₄ F _8.
= 200/150 / 8cc / min, RF power = 13
00W, electrode temperature = 40 ° C, cooling He pressure center /
Silicon oxide film 60 under the condition of edge = 3/45 Torr
6 and 602, the pad 60
A cell contact hole 611 is opened in a self-aligned manner with respect to 1.

(4) Next, as shown in FIG.
After depositing a polycrystalline silicon film 612 with a thickness that does not block the cell contact hole 611, the cell contact hole 611 is filled with a silicon oxide film 613. Thereafter, the silicon oxide film 613 is subjected to pressure = 500 mTorr by using, for example, a parallel plate type etching apparatus.
Ar / CHF ₃ / CF ₄ = 400/20/20 cc / m
in, RF power = 200 W, electrode temperature = 0 ° C., cooling H
e, the polycrystalline silicon film 61 under the condition of pressure = 15 Torr.
Etch back until 2 is exposed.

(5) Next, as shown in FIG.
Using the silicon oxide film 613 as a stopper, for example, using a microwave downflow etching apparatus, pressure =
40 Pa, CF ₄ / O ₂ = 150/60 cc / min,
The polycrystalline silicon films 612 and 609 are isotropically etched back under the condition of microwave power = 700 W and electrode temperature = 25 ° C. to expose the silicon oxide film 608.

(6) Next, as shown in FIG.
The capacitor electrodes 614 are formed by etching the silicon oxide films 608 and 613 with an aqueous solution of hydrogen fluoride using the silicon nitride film 607 as a stopper.

Thereafter, a semiconductor device is manufactured through a process of forming a cell plate electrode by a normal lithography process and an etching process after depositing a capacitor insulating film and then depositing a polycrystalline silicon film.

According to the twelfth embodiment, (1) a process of processing a laminated film of a polycrystalline silicon film 609, a silicon oxide film 608, and a silicon nitride film 607 by ordinary lithography and etching, and (2) Using the polycrystalline silicon film 609 as a mask, the silicon nitride films 605 and 6 are formed on a bit line 603 having a structure in which an upper portion and a side wall are covered with a silicon nitride film.
Using the silicon oxide films 606 and 60 as stoppers
Forming a cell contact hole 611 with respect to the pad 601 previously formed;
(3) a step of burying the contact hole 611 by depositing a polycrystalline silicon film 612 having a film thickness that does not block the cell contact hole 611, and then depositing a silicon oxide film 613; The silicon oxide film 613 embedded in the cell contact hole 611 is etched back using the polycrystalline silicon film 612 of (3) as a stopper, and then the polycrystalline silicon film of the above step (3) is used by using the silicon oxide film 613 as a mask. 612
And a step of isotropically etching back the polycrystalline silicon film 609 in the above step (1); and (5) a silicon nitride film 60
7 is used as a stopper to etch the silicon oxide film 613 in the above step (4) and the silicon oxide film 608 in the above step (1) using an aqueous solution of hydrogen fluoride to form a capacitor electrode 614. Since the semiconductor device is manufactured, it is possible to improve the problem of margin for alignment in the lithography process. Thus, a semiconductor device having a high production yield can be manufactured.

In addition to this, cell contact holes 61
1 and the capacitor electrode 614 are formed in one lithography step, so that a semiconductor device with low manufacturing cost can be manufactured.

Furthermore, in the twelfth embodiment, the polycrystalline silicon film 60 is
Since the silicon oxide films 606 and 602 are etched using the mask 9 as a mask, etching can be performed with the mask height suppressed, and it is possible to cope with further miniaturization of the semiconductor device.

In the twelfth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is displaced, from the viewpoint of securing the contact area with the pad 601, the distance of the silicon nitride film 605 on the side wall is increased by +2.
X It is necessary to form a hole pattern 610A for forming the capacitor electrode 614 with a margin and an alignment in the lithography process. For example, a silicon nitride film 605
Is 0.08 μm, if the alignment margin in the lithography process is estimated to be 0.1 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm.
Since this can be formed by a normal lithography process, in the twelfth embodiment, the process of forming a sidewall using a polycrystalline silicon film, which has been disclosed in the related art, can be completely eliminated. It is.

Next, a thirteenth embodiment of the present invention will be described.

In the thirteenth embodiment, after the polycrystalline silicon films 609 and 612 in the twelfth embodiment are anisotropically etched back, the silicon oxide film 608 is made of a hydrogen fluoride aqueous solution using the silicon nitride film 607 as a stopper. By etching, a cap-sita electrode 614 is formed.

According to the thirteenth embodiment, (1) a step of processing a laminated film of the polycrystalline silicon film 609, the silicon oxide film 608, and the silicon nitride film 607 by a normal lithography step and an etching step; and (2) Using the polycrystalline silicon film 609 as a mask, the bit lines 603 having a structure in which the upper and side walls are covered with the silicon nitride films 604 and 605 are formed in advance by using the silicon nitride films 604 and 605 as stoppers. Etching the silicon oxide films 606 and 602 to form a cell contact hole 611 for the pad 601 previously formed; and (3) forming the cell contact hole 61
A step of depositing a polycrystalline silicon film 612 having a film thickness that does not block 1 and then depositing a silicon oxide film 613 to bury the cell contact hole 611;
(4) The silicon oxide film 613 embedded in the cell contact hole 611 is etched back using the polycrystalline silicon film 612 of the above step (3) as a stopper, and then the silicon oxide film 613 is used as a mask and the above step (3) is performed.
Anisotropically etching back the polycrystalline silicon film 612 of the above and the polycrystalline silicon film 609 of the above step (1);
The step of forming the capacitor electrode 614 by etching the silicon oxide film 613 in the above step (4) and the silicon oxide film 608 in the above step (1) using an aqueous solution of hydrogen fluoride using the silicon nitride film 607 as a stopper. After that, the semiconductor device is manufactured, so that it is possible to improve the problem of the alignment margin in the lithography process. As a result, a semiconductor device with a high production yield can be manufactured.

In addition to this, cell contact holes 61
1 and the capacitor electrode 614 are formed in one lithography step, so that a semiconductor device with low manufacturing cost can be manufactured.

Further, in the thirteenth embodiment, when the cell contact hole 611 is etched,
Since the silicon oxide films 606 and 602 are etched using the mask 09 as a mask, the etching can be performed with the mask height suppressed, and it is possible to cope with further miniaturization of the semiconductor device.

In the thirteenth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is displaced, from the viewpoint of securing the contact area with the pad 601, the distance between the silicon nitride films 605 on the side walls +2
X It is necessary to form a hole pattern 610A for forming a capacitor electrode with a margin and a degree of alignment in a lithography process. For example, when the interval between the silicon nitride films 605 is 0.08 μm and the alignment margin in the lithography process is estimated to be 0.1 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm. Since this can be formed by a normal lithography process, in the thirteenth embodiment, the step of forming a sidewall using a polycrystalline silicon film, which has been disclosed in the related art, can be completely eliminated. is there.

Next, a fourteenth embodiment of the present invention will be described.

The fourteenth embodiment is different from the twelfth embodiment in that a cell contact hole 611 for forming a capacitor electrode 614 is buried using an organic film, and the organic film and the polycrystalline silicon films 609 and 612 are collectively etched back. It is like that. In this etch-back step, for example, using a magnetron etching apparatus, pressure = 2
0 mTorr, Cl ₂ / O ₂ = 30/3 cc / min,
The conditions of RF power = 400 W, magnetic field strength = 30 Gauss, and electrode temperature = 20 ° C. are applied.

According to the fourteenth embodiment, (1) a step of processing a laminated film of the polycrystalline silicon film 609, the silicon oxide film 608, and the silicon nitride film 607 by a usual lithography step and an etching step; and (2) Using the polycrystalline silicon film 609 as a mask, the bit line 603 having a structure in which the upper and side walls are covered with the silicon nitride films 605 and 604 is used as a stopper. Etching the silicon oxide films 606 and 602 to form a cell contact hole 611 for the pad 601 previously formed; and (3) forming the cell contact hole 61
A step of burying the cell contact hole 611 by depositing a polycrystalline silicon film 612 having a film thickness not to block the cell contact hole 1 and then depositing an organic film; (4) the organic film; And (5) a step of collectively etching back the polycrystalline silicon film 612 and the polycrystalline silicon film 609 of the above step (1), and (5) ashing the organic film and then using the silicon nitride film 607 as a stopper to form the above step (1). A) forming a capacitor electrode 614 by etching the silicon oxide film 608 using an aqueous solution of hydrogen fluoride to manufacture a semiconductor device. It is possible to solve. As a result, a semiconductor device with a high production yield can be manufactured.

In addition to this, cell contact holes 61
1 and the capacitor electrode 614 are formed in one lithography step, so that a semiconductor device with low manufacturing cost can be manufactured.

Further, in the fourteenth embodiment, when the cell contact hole 611 is etched,
Since the silicon oxide films 606 and 602 are etched using the mask 09 as a mask, the etching can be performed with the mask height suppressed, and it is possible to cope with further miniaturization of the semiconductor device.

In the fourteenth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is displaced, from the viewpoint of securing the contact area with the pad 601, the distance of the silicon nitride film 605 on the side wall +2
X It is necessary to form a hole pattern 610A for forming the capacitor electrode 614 with a margin and an alignment in the lithography process. For example, a silicon nitride film 605
Is 0.08 μm, if the alignment margin in the lithography process is estimated to be 0.1 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm.
Since this can be formed by a normal lithography process, in the fourteenth embodiment, the process of forming a sidewall using a polycrystalline silicon film, which has been disclosed in the prior art, can be completely eliminated. is there.

Next, a fifteenth embodiment of the present invention will be described.

The fifteenth embodiment is different from the twelfth embodiment in that the uppermost layer of the interlayer insulating film 601A on which the pad 601 is formed is a silicon nitride film.

According to the fifteenth embodiment, the uppermost layer of the interlayer insulating film 601A on which the pad 601 is formed in the twelfth embodiment is made of a silicon nitride film. Even if the over-etching time is increased by etching the contact hole 611, the interlayer insulating film 601A on which the pad 601 is formed is not excessively etched. As a result, the processing margin of the cell contact hole etching process can be increased, and the yield of the semiconductor device can be further improved.

Next, a sixteenth embodiment of the present invention will be described.

In the sixteenth embodiment, after the polycrystalline silicon film 609 is etched and the resist 610 is ashed in the twelfth embodiment, the silicon oxide film 608 and the silicon nitride film 607 are formed using the polycrystalline silicon film 609 as a mask. And then etching the silicon oxide films 606 and 602 using the silicon nitride films 605 and 604 on the bit lines 603 and the sidewalls as stoppers, thereby forming the cell contact holes 611 with the pads 601 formed in advance. It is an opening.

According to the sixteenth embodiment, (1) a step of processing the polycrystalline silicon film 609 by ordinary lithography and etching steps, and (2) a silicon oxide film using the polycrystalline silicon film 609 as a mask. After etching the laminated film of the silicon nitride film 608 and the silicon nitride film 607, the upper and side walls formed in advance are formed of the silicon nitride film 605.
The silicon oxide films 606 and 602 are etched using the silicon nitride films 605 and 604 as stoppers for the bit lines 603 having the structure covered by A step of forming 611; and (3) depositing a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611 and then depositing a silicon oxide film 613 to bury the cell contact hole 611. And (4) etching back the silicon oxide film 613 embedded in the cell contact hole 611 using the polycrystalline silicon film 612 of the above step (3) as a stopper, and then using the silicon oxide film 613 as a mask, The polycrystalline silicon film 612 of (3) and the polycrystalline of the above step (1) A step of isotropically etching back the silicon film 609, (5) the silicon nitride film 607 as a stopper, the silicon oxide film 613 of the above step (4)
And a step of forming the capacitor electrode 614 by etching the silicon oxide film 608 in step (1) using an aqueous solution of hydrogen fluoride to manufacture a semiconductor device. It is possible to improve the problem of the alignment margin. As a result, a semiconductor device with a high production yield can be manufactured.

In addition to this, cell contact holes 61
1 and the capacitor electrode 614 are formed in one lithography step, so that a semiconductor device with low manufacturing cost can be manufactured.

Further, in the sixteenth embodiment, when the cell contact hole 611 is etched,
Since the silicon oxide film 608, the silicon nitride film 607, and the silicon oxide films 606 and 602 are etched using the mask 09 as a mask, the etching can be performed with the mask height suppressed, and the semiconductor device can be further miniaturized. Becomes possible.

In the sixteenth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is displaced, from the viewpoint of securing the contact area with the pad 601, the distance of the silicon nitride film 605 on the side wall is increased by +2.
X It is necessary to form a hole pattern 610A for forming the capacitor electrode 614 with a margin and an alignment in the lithography process. For example, when the interval between the silicon nitride films 605 is 0.08 μm and the alignment margin in the lithography process is estimated to be 0.1 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm. Since this can be formed by a normal lithography process,
In the sixteenth embodiment, the step of forming a sidewall using a polycrystalline silicon film can be omitted completely.

Next, a seventeenth embodiment of the present invention will be described.

In the seventeenth embodiment, after the polycrystalline silicon film 609 and the silicon oxide film 608 in the twelfth embodiment are etched and the resist 610 is ashed, the silicon nitride film 60 is etched using the polycrystalline silicon film 609 as a mask.
7 is etched, and then the silicon oxide films 606 and 602 are etched using the silicon nitride films 605 and 604 on the bit lines 603 and the side walls as stoppers, so that the cell contact holes 611 are formed in the pads 601 formed in advance. Are opened.

According to the seventeenth embodiment, (1) a step of processing the polycrystalline silicon film 609 and the silicon oxide film 608 by a normal lithography step and an etching step;
(2) After etching the silicon nitride film 607 using the polycrystalline silicon film 609 as a mask, the upper and side walls formed in advance are silicon nitride films 605 and 60
The silicon oxide films 606 and 602 are etched using the silicon nitride films 605 and 604 as stoppers for the bit line 603 having the structure covered with the silicon nitride film 4 and the cell contact holes 611 with respect to the pads 601 formed in advance. And (3) a polycrystalline silicon film 61 having a thickness that does not block the cell contact holes 611.
2) and then depositing a silicon oxide film 613 to bury the cell contact hole 611; and (4) the polycrystalline silicon film 61 in the above step (3).
The silicon oxide film 613 embedded in the cell contact hole 611 is etched back using the silicon oxide film 613 as a mask, and the polycrystalline silicon film 612 of the above-mentioned step (3) and the above-mentioned step (1) are used as a mask.
(5) isotropically etching back the polycrystalline silicon film 609, and (5) using the silicon nitride film 607 as a stopper to form the silicon oxide film 613 of the above step (4) and the silicon oxide film 608 of the above step (1). , By using an aqueous solution of hydrogen fluoride, the capacitor electrode 61 is etched.
Since the semiconductor device is manufactured by performing the steps of forming the semiconductor device 4, it is possible to improve the problem of the alignment margin in the lithography process. As a result, a semiconductor device with a high production yield can be manufactured.

In addition to this, cell contact holes 61
1 and the capacitor electrode 614 are formed in one lithography step, so that a semiconductor device with low manufacturing cost can be manufactured.

Further, in the seventeenth embodiment, when the cell contact hole 611 is etched,
Since the silicon nitride film 607 and the silicon oxide films 606 and 602 are etched using the mask 12 as a mask, etching can be performed with the mask height suppressed, and it is possible to cope with further miniaturization of the semiconductor device.

In the seventeenth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is misaligned, from the viewpoint of securing the contact area with the pad 601, the distance of the silicon nitride film 605 on the side wall +2
X It is necessary to form a hole pattern 610A for forming the capacitor electrode 614 with a margin and an alignment in the lithography process. For example, when the interval between the silicon nitride films 605 is 0.08 μm and the alignment margin in the lithography process is estimated to be 0.1 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm. Since this can be formed by a normal lithography process,
In the seventeenth embodiment, the step of forming a sidewall using a polycrystalline silicon film can be completely eliminated.

Next, an eighteenth embodiment of the present invention will be described.

The eighteenth embodiment uses a capacitor electrode film other than the polycrystalline silicon film in the twelfth embodiment.

FIG. 12 is a sectional view showing a semiconductor device manufacturing process according to the eighteenth embodiment of the present invention (part 1), and FIG. 13 is a sectional view showing a semiconductor device manufacturing process according to the eighteenth embodiment of the present invention. It is.

(1) First, FIG.
Until (c), there is no difference from the twelfth embodiment of the present invention shown in FIG. Note that 700 is a silicon substrate, 701
Is a pad, 702 is a silicon oxide film, 703 is a bit line, 704 and 705 are silicon nitride films, 706 is a silicon oxide film, 707 is a silicon nitride film, 707 is a silicon oxide film, 708 is a polycrystalline silicon film, 709 is a resist. , 711 are hole patterns, and 712 is a cell contact hole.

(2) Next, as shown in FIG.
For example, after depositing a titanium film having a thickness that does not block the cell contact hole 712 by CVD, the polycrystalline silicon film of the pad 701 is reacted with the titanium film by heat treatment to form a titanium silicide layer 713. Thereafter, for example, an unreacted portion of titanium is removed with a mixed aqueous solution of ammonia and hydrogen peroxide solution. At this time, a silicide layer 713 also exists in the mask due to a reaction between the polycrystalline silicon film constituting the mask (polycrystalline silicon film) 709 and the titanium film.

(3) Next, as shown in FIG.
For example, a titanium nitride film 714 having a thickness that does not block the cell contact hole 712 is deposited by CVD. After that, the cell contact hole 712 is
Then, the silicon oxide film 715 is etched back until the titanium nitride film 714 is exposed.

(4) Next, as shown in FIG.
Using the silicon oxide film 715 as a mask, the titanium nitride film 714 and the silicide layer 71 generated by the reaction with the mask
3 and the polycrystalline silicon film 709 of the mask are etched back until the silicon oxide film 708 is exposed.

(5) Next, as shown in FIG.
This step is the same as the twelfth embodiment of the present invention shown in FIG. That is, using the silicon nitride film 707 as a stopper, the silicon oxide film 708 and the silicon oxide film 715
Is etched with an aqueous solution of hydrogen fluoride to form a capacitor electrode 716.

Thereafter, a tantalum oxide film is deposited as a capacitor insulating film by CVD, for example, and then a titanium nitride film is deposited as a cell plate electrode film by CVD, and the cell plate electrode is formed by ordinary lithography and etching. The semiconductor device is manufactured through the forming process.

According to the eighteenth embodiment, (1) a process of processing a laminated film of a polycrystalline silicon film 709, a silicon oxide film 708, and a silicon nitride film 707 by ordinary lithography and etching, and (2) Using the polycrystalline silicon film 709 as a mask, the silicon nitride films 704 and 705 are used as stoppers for bit lines 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705. Etching the silicon oxide films 708 and 706 to form a cell contact hole 712 for the pad 701 formed in advance, and (3) depositing a titanium film
The step of forming a titanium silicide layer by reacting the polycrystalline silicon film and the titanium film of the pad 701 by heat treatment, and (4) depositing a titanium nitride film 714 and then depositing a silicon oxide film 715 Burying the cell contact hole 712, (5)
The silicon oxide film 715 embedded in the cell contact hole 712 is etched back using the titanium nitride film 714 of the above step (4) as a stopper, and then the titanium nitride film of the above step (4) is used with the silicon oxide film 715 as a mask. 714, silicide layer 7 in step (3) above
13 and the step (1) of etching back the polycrystalline silicon film 709; and (6) the silicon oxide film 7 of the step (5) using the silicon nitride film 707 as a stopper.
15 and the silicon oxide film 708 in the above step (1) were etched using an aqueous hydrogen fluoride solution to form a capacitor electrode 716 to manufacture a semiconductor device. Can be improved. As a result, a semiconductor device with a high production yield can be manufactured.

In addition to this, cell contact hole 71
2 and the capacitor electrode 716 are formed in one lithography step, so that a semiconductor device with low manufacturing cost can be manufactured.

Furthermore, in the eighteenth embodiment, when the cell contact hole 712 is etched,
Since the silicon oxide films 708 and 706 are etched using the mask 09 as a mask, etching can be performed with the mask height suppressed, and it is possible to cope with further miniaturization of a semiconductor device.

In addition to the above, since the capacitor electrode is constituted by the titanium nitride film, it is possible to use a capacitor insulating film having a high relative dielectric constant such as tantalum oxide.

In the eighteenth embodiment, even when the cell contact hole 712 is misaligned with respect to the bit line 703, from the viewpoint of securing a contact area with the pad 701, the distance of the silicon nitride film 705 on the side wall +2
X It is necessary to form a hole pattern 711 for forming the capacitor electrode 716 to the extent of the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 705 is 0.08 μm, when the alignment margin in the lithography process is estimated to be 0.1 μm, the minimum size of the hole pattern 711 to be formed is 0.28 μm. Since this can be formed by a normal lithography process, the step of forming a sidewall using a polycrystalline silicon film in the eighteenth embodiment can be completely eliminated.

Next, a nineteenth embodiment of the present invention will be described.

The nineteenth embodiment is different from the eighteenth embodiment in that a cell contact hole 712 for forming a capacitor electrode 716 is buried using an organic film, and an organic film and a titanium nitride film 714, a silicide layer 713, a polycrystalline silicon film are formed. 709 is collectively etched back.

According to the nineteenth embodiment, (1) a step of processing a laminated film of a polycrystalline silicon film 709, a silicon oxide film 708 and a silicon nitride film 707 by a usual lithography step and etching step, and (2) Using the polycrystalline silicon film 709 as a mask, the silicon nitride films 704 and 705 are used as stoppers for bit lines 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705. As a result, the silicon oxide films 706 and 702 are etched to make the cell contact holes 712 with respect to the pads 701 formed in advance.
And (3) the cell contact hole 7
Forming a silicide layer 713 by heat treatment after depositing a titanium film having a film thickness that does not block 12;
(4) By depositing a titanium nitride film 714 and then depositing an organic film, the cell contact hole 712 is formed.
And (5) the organic film, the step (4)
Titanium nitride film 714, the silicide layer 713 in the above step (3), and the polycrystalline silicon film 70 in the above step (1)
And (6) etching the organic film and then using the silicon nitride film 707 as a stopper to etch the silicon oxide film 708 of the above process (1) using an aqueous solution of hydrogen fluoride. Thus, since the semiconductor device is manufactured by performing the step of forming the capacitor electrode 716, it is possible to improve the problem of the alignment margin in the lithography step. As a result, a semiconductor device with a high production yield can be manufactured.

In addition to this, cell contact holes 71
2 and the capacitor electrode 716 are formed in one lithography step, so that a semiconductor device with low manufacturing cost can be manufactured.

Further, in the nineteenth embodiment, when etching the cell contact hole 712, the polysilicon film 7
Since the silicon oxide films 706 and 702 are etched using the mask 09 as a mask, the etching can be performed with the mask height suppressed, and it is possible to cope with further miniaturization of the semiconductor device.

In addition to the above, since the capacitor electrode 716 is made of a titanium nitride film, it is possible to use a capacitor insulating film having a high relative dielectric constant such as tantalum oxide.

In the nineteenth embodiment, even when the cell contact hole 712 is misaligned with respect to the bit line 703, from the viewpoint of securing the contact area with the pad 701, the distance of the silicon nitride film 705 on the side wall +2
X It is necessary to form a hole pattern 711 for forming the capacitor electrode 716 to the extent of the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 705 is 0.08 μm, when the alignment margin in the lithography process is estimated to be 0.1 μm, the minimum size of the hole pattern 711 to be formed is 0.28 μm. Since this can be formed by a normal lithography process, in the nineteenth embodiment, the step of forming a sidewall using a polycrystalline silicon film can be completely eliminated.

Next, a twentieth embodiment of the present invention will be described.

In the twentieth embodiment, after the cell contact hole 712 of the nineteenth embodiment is opened, the cell contact hole 712 is buried with an organic film, and the organic film and the polycrystalline silicon film 709 constituting the mask are collectively etched. After the backing, the titanium film is deposited after the organic film is ashed.

According to the twentieth embodiment, (1) a step of processing a laminated film of a polycrystalline silicon film 709, a silicon oxide film 708 and a silicon nitride film 707 by ordinary lithography and etching, and (2) Using the polycrystalline silicon film 709 as a mask, the silicon nitride films 704 and 705 are used as stoppers for bit lines 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705. (3) burying the cell contact hole 712 with an organic film to form a cell contact hole 712 for the pad 701 formed in advance; A step of collectively etching back the crystalline silicon film 709; and (4) ashing the organic film,
After depositing titanium with a thickness that does not block the cell contact hole 712, the silicide layer 71 is heat-treated.
Forming a contact hole 712 by depositing a titanium nitride film 714 and then depositing an organic film; and (6) nitriding the organic film and the nitriding step (5). A step of collectively etching back the titanium film 714; and (7) ashing the organic film, and then using the silicon nitride film 707 as a stopper to form the first
The silicon oxide film 708 in the step is etched using an aqueous solution of hydrogen fluoride to form a capacitor electrode 716.
Is performed to manufacture a semiconductor device, so that it is possible to improve the problem of margin for alignment in the lithography process. As a result, a semiconductor device with a high production yield can be manufactured.

In addition to this, cell contact holes 71
2 and the capacitor electrode 716 are formed in one lithography step, so that a semiconductor device with low manufacturing cost can be manufactured.

Furthermore, in the twentieth embodiment, the polycrystalline silicon film 7
Since the silicon oxide films 708 and 702 are etched using the mask 09 as a mask, the etching can be performed with the mask height suppressed, and it is possible to cope with further miniaturization of the semiconductor device.

In addition to the above, since the capacitor electrode 716 is constituted by a titanium nitride film, it is possible to use a capacitor insulating film having a high relative dielectric constant such as tantalum oxide.

In the twentieth embodiment, even when the cell contact hole 712 is misaligned with respect to the bit line 703, from the viewpoint of securing the contact area with the pad 701, the distance of the silicon nitride film 705 on the side wall +2
X It is necessary to form a hole pattern 711 for forming the capacitor electrode 716 to the extent of the alignment margin in the lithography process. For example, when the interval between the silicon nitride films 705 is 0.08 μm, when the alignment margin in the lithography process is estimated to be 0.1 μm, the minimum size of the hole pattern 711 to be formed is 0.28 μm. Since this can be formed by a normal lithography process, in this embodiment, the step of forming a sidewall using a polycrystalline silicon film can be completely eliminated.

Next, a twenty-first embodiment of the present invention will be described.

FIG. 14 is a sectional view of a semiconductor device showing a twenty-first embodiment of the present invention in a manufacturing process (part 1), and FIG. 15 is a sectional view of a semiconductor device showing a twenty-first embodiment of the present invention in a manufacturing process (part 2). It is.

(1) First, as shown in FIG.
After a normal semiconductor device manufacturing process, an element isolation region, a word line (both not shown), a silicon substrate 801, a pad 801A, and a bit line 804 are sequentially formed. Here, the interlayer insulating film between the pad and the bit line is characterized in that the lower layer is composed of a silicon nitride film 802 and the upper layer is composed of a silicon oxide film 803. After that, the silicon oxide film 805
Is deposited and planarized by CMP.
06 is deposited.

(2) Next, as shown in FIG.
After a silicon oxide film 807 and a polycrystalline silicon film 808 are sequentially deposited, a hole pattern 809 is formed by a normal lithography process. Thereafter, for example, using a parallel plate type etching apparatus, the pressure is 20 mTorr, SF ₆
/ HBr = 26/8 cc / min, RF power = 300
Under the conditions of W, cooling He pressure = 4 Torr, the polycrystalline silicon film 808 is anisotropically etched using the silicon oxide film 807 as a stopper, and then, for example, using a magnetron etching apparatus, pressure = 40 mTorr, Ar /
CO / C ₄ F ₈ = 250/100/8 cc / min, R
Under the conditions of F power = 1300 W, electrode temperature = 40 ° C., cooling He pressure center / edge = 3/45 Torr, the silicon oxide film 807 is anisotropically etched using the silicon nitride film 806 as a stopper to form the hole 8.
Form 10.

(3) Next, as shown in FIG.
After the resist 809 is ashed, a polycrystalline silicon film is deposited, for example, by electron cyclotron resonance (hereinafter, ECR).
Pressure = 5 mTorr using an etching apparatus
r, Cl ₂ = 100 cc / min, microwave power 4
The side wall 811 is formed by performing anisotropic etching under the conditions of 00 W, RF power = 50 W, and electrode temperature = −20 ° C., and an etching mask 812 made of polycrystalline silicon having an opening diameter smaller than the hole. To form

(4) Next, as shown in FIG.
Under a condition that a sufficient selectivity can be obtained with respect to the etching mask 812, for example, in the first step, using a magnetron etching apparatus, a pressure of 35 mTorr and CHF ₃ /
CO = 30 / 170cc / min, RF power = 160
0W, cooling He back pressure center / edge = 3 / 70To
rr, electrode temperature −10 ° C., silicon nitride film 80
6 is etched. Next, in a second step, using a magnetron etching apparatus, pressure = 30 mTorr.
_{r, Ar / C 4 F 8} /02 = 300/10 / 8cc / m
in, RF power = 1500 W, cooling He back pressure Center / edge = 3/45 Torr, electrode temperature = −10 ° C., silicon oxide film 805 and silicon oxide film 803 below bit line 804 are replaced with silicon nitride film 802
Is etched anisotropically with the
Pressure = 40 mTorr, Ar / CH ₂ F
₂ / O ₂ = 100/10 / 20cc / min, RF power = 300W, cooling He back pressure center / edge = 3/4
The pad 801A is etched by etching the silicon nitride film 802 under the conditions of 5 Torr and electrode temperature = −10 ° C.
An upper contact hole 813 is opened. Hereinafter, the contact hole is referred to as a cell contact hole.

(5) Next, as shown in FIG.
After depositing a polycrystalline silicon film 814 having a thickness not filling the cell contact hole 813, the silicon oxide film 8
The cell contact hole 813 is deposited by depositing
Embed

Thereafter, until the polycrystalline silicon film 814 is exposed, the silicon oxide film 815 is subjected to pressure = 500 mTorr and Ar by using, for example, a parallel plate type etching apparatus.
/ CHF ₃ / CF ₄ = 400/20 / 20cc / mi
n, RF power = 200 W, electrode temperature = 0 ° C., cooling He
Etch back under the condition of pressure = 15 Torr.

(6) Next, as shown in FIG.
Using the silicon oxide film 815 as a mask, the polycrystalline silicon film 814 and the etching mask 812 are formed by, for example, using a microwave downflow etching apparatus at a pressure = 4.
Etching is isotropically performed under the conditions of 0 Pa, CF ₄ / O ₂ = 150/60 cc / min, microwave power = 700 W, and electrode temperature = 25 ° C.

(7) Next, as shown in FIG.
By using the silicon nitride film 806 as a stopper, the silicon oxide films 807 and 815 are etched with an aqueous solution of hydrogen fluoride to form a capacitor electrode 816.

Thereafter, a semiconductor device is manufactured by depositing a capacitor insulating film, depositing a polycrystalline silicon film for forming a cell plate electrode, and performing a process of forming a cell plate electrode by a usual lithography process. .

According to the twenty-first embodiment, (1) In the laminated film of the polycrystalline silicon film 808 and the silicon oxide film 807, holes formed using the silicon nitride film 806 as a stopper by a usual lithography process and etching process are formed. A step of reducing the size by using the sidewall 811 made of crystalline silicon; and (2) using the polycrystalline silicon film 812 having the reduced opening diameter as a mask, and using the silicon nitride film 802 immediately above the pad 801A as a stopper, and Forming a contact hole 813; (3)
After depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, the silicon oxide film 8
By depositing No. 15, a step of burying the cell contact hole 813 and (4) Etching back the silicon oxide film 815 burying the cell contact hole 813 using the polycrystalline silicon film 814 of the step (3) as a stopper. Then, using the silicon oxide film 815 as a mask, isotropically etching back the polycrystalline silicon film 814 in the above step (3) and the polycrystalline silicon film 812 in the above step (2); Using the silicon oxide film 815 of the above step (4) as a stopper
And a step of forming a capacitor electrode 816 by etching the silicon oxide film 807 in the above step (1) using an aqueous solution of hydrogen fluoride to manufacture a semiconductor device. And the capacitor electrode 816 can be formed in one lithography step, so that a semiconductor device with low manufacturing cost and high manufacturing yield can be manufactured.

In the twenty-first embodiment, since the self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line
It has to be reduced to such a degree that a sufficient margin for four intervals can be secured. However, in the direction parallel to the bit line 804, the mask size can be increased without exceeding the unit cell area. This allows
Since a sufficient capacitor capacity can be ensured, a semiconductor device can be manufactured without sacrificing performance.

Next, a twenty-second embodiment of the present invention will be described.

In the twenty-second embodiment, the polycrystalline silicon film 814 and the etching mask 812 are anisotropically etched back using the silicon oxide film 815 having the cell contact holes 813 buried in the twenty-first embodiment as a mask. The capacitor electrodes 816 are formed by etching the silicon oxide films 815 and 807 with an aqueous solution of hydrogen fluoride using the silicon nitride film 806 as a stopper.

According to the twenty-second embodiment, (1) a hole 810 opened in a laminated film of a polycrystalline silicon film 808 and a silicon oxide film 807 using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process.
And (2) using the polysilicon film 812 having a reduced opening diameter as a mask, using the silicon nitride film 802 immediately above the pad 801A as a stopper, as a stopper. 8
A step of forming a cell contact hole 813 with respect to 01A, and (3) depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing a silicon oxide film 815. Burying the contact hole 813; and (4) using the polycrystalline silicon film 814 of the step (3) as a stopper.
After etching back the silicon oxide film 815 in which the cell contact hole 813 is buried, using the silicon oxide film 815 as a mask, the polycrystalline silicon film 814 of the above step (3) and the polycrystalline silicon film 81 of the above step (2) are used.
And (5) using the silicon nitride film 806 as a stopper, the silicon oxide film 815 of the above step (4) and the silicon oxide film 807 of the above step (1) using an aqueous hydrogen fluoride solution. The step of forming the capacitor electrode 816 is performed by etching using the semiconductor device to manufacture the semiconductor device. Therefore, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography step. It is possible to manufacture a semiconductor device with low cost and high manufacturing yield.

In the twenty-second embodiment, since the self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line
It has to be reduced to such a degree that a sufficient margin for four intervals can be secured. However, in the direction parallel to the bit line 804, the mask size can be increased without exceeding the unit cell area. This allows
Since a sufficient capacitor capacity can be ensured, a semiconductor device can be manufactured without sacrificing performance.

Next, a twenty-third embodiment of the present invention will be described.

In the twenty-third embodiment, the cell contact hole 813 of the twenty-first embodiment is buried with an organic film, and this organic film, the polycrystalline silicon film 814 and the etching mask 812 are collectively etched back, and then the organic film is removed. After ashing, the silicon oxide film 807 is etched with an aqueous solution of hydrogen fluoride using the silicon nitride film 806 as a stopper to form the capacitor electrode 816.

According to the twenty-third embodiment, (1) a hole 810 opened in a laminated film of a polycrystalline silicon film 808 and a silicon oxide film 807 by using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process.
(2) using a polysilicon film 812 having a reduced opening diameter as a mask, and using a silicon nitride film 802 immediately above the pad 801A as a stopper, as a stopper. 8
Forming a cell contact hole 813 with respect to the cell contact hole 01A, and (3) depositing a polycrystalline silicon film 814 having a film thickness not blocking the cell contact hole 813 and then depositing an organic film. A step of filling the contact hole 813, (4) the organic film, the polycrystalline silicon film 814 of the step (3), and the step (2).
Etching back the polycrystalline silicon film 812 at once, and (5) ashing the organic film to form a silicon nitride film 8
Since the step of forming the capacitor electrode 816 is performed by etching the silicon oxide film 807 of the above step (1) using an aqueous solution of hydrogen fluoride with the use of the stopper 06 as a stopper, the semiconductor device is manufactured. The contact hole 813 and the capacitor electrode 816 can be formed in one lithography step, so that a semiconductor device with low manufacturing cost and high manufacturing yield can be manufactured.

In the twenty-third embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line
The distance must be reduced to the extent that a sufficient alignment margin can be secured for the interval of 4. However, in the direction parallel to the bit line 804, the mask size can be increased without exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, so that a semiconductor device can be manufactured without sacrificing performance.

Next, a twenty-fourth embodiment of the present invention will be described.

In the twenty-fourth embodiment, the interlayer insulating film between the pad 801A and the bit line 804 after the pad is formed in the twenty-first embodiment is configured such that the upper layer is composed of the silicon nitride film 802 and the lower layer is composed of the silicon oxide film 803. It was done.

According to the twenty-fourth embodiment, (1) a hole 810 formed in a laminated film of a polycrystalline silicon film 808 and a silicon oxide film 807 by using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process.
(2) using the polysilicon film 812 having a reduced opening diameter as a mask, and using the silicon nitride film 802 immediately below the bit line 804 as a stopper, Pad 8
A step of forming a cell contact hole 813 with respect to 01A, and (3) depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing a silicon oxide film 815. A step of burying the cell contact hole 813 and (4) etching back the silicon oxide film 815 burying the cell contact hole 813 using the polycrystalline silicon film 814 of the step (3) as a stopper. 815 is used as a mask, isotropically etching back the polycrystalline silicon film 814 in the above step (3) and the polycrystalline silicon film 812 in the above step (2), and (5) using the silicon nitride film 806 as a stopper. The above step (4)
And etching the silicon oxide film 815 of step (1) and the silicon oxide film 807 of step (1) using an aqueous solution of hydrogen fluoride to form a capacitor electrode 816, thereby manufacturing a semiconductor device. In addition, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography step, so that a semiconductor device having a low manufacturing cost and a high manufacturing yield can be manufactured.

In the twenty-fourth embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line
The distance must be reduced to the extent that a sufficient alignment margin can be secured for the interval of 4. However, in the direction parallel to the bit line 804, the mask size can be increased without exceeding the unit cell area. This makes it possible to secure a sufficient capacitance of the capacitor, so that the semiconductor device can be manufactured without sacrificing performance.

Next, a twenty-fifth embodiment of the present invention will be described.

In the twenty-fifth embodiment, after performing the steps of FIGS. 14A to 14D, the step of FIG.
1 to (c).

That is, in the twenty-fifth embodiment, after the cell contact hole 813 in the twenty-first embodiment is opened,
(1) forming a silicide layer by depositing a titanium film having a thickness that does not block the cell contact hole 813 by CVD, and then reacting the polycrystalline silicon film of the pad with the titanium film by heat treatment; 2)
Removing the unreacted portion of the titanium film with a mixed aqueous solution of ammonia and hydrogen peroxide, and then depositing a titanium nitride film having a thickness not blocking the cell contact hole 813 by CVD; (3) the cell contact A step of filling the holes 813 with a silicon oxide film 815 and etching back the silicon oxide film 815 until the titanium nitride film is exposed; and (3) using the silicon oxide film 815 as a mask, a multi-layer of a titanium nitride film, a silicide layer, and a mask. Etching back the crystalline silicon film 812 until the silicon oxide film 807 is exposed; and (4) etching the silicon oxide film 815 and the silicon oxide film 807 used for embedding with a hydrogen fluoride aqueous solution using the silicon nitride film 806 as a stopper. To form the capacitor electrode 816 After performing the extent, as a capacitor insulating film, for example, after depositing a tantalum oxide film by CVD, as the cell plate electrode film, for example, CVD
To form a cell plate electrode by ordinary lithography and etching to manufacture a semiconductor device.

According to the twenty-fifth embodiment, (1) a hole 810 opened in a laminated film of a polycrystalline silicon film 808 and a silicon oxide film 807 using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process.
(2) using a polysilicon film 812 having a reduced opening diameter as a mask, and using a silicon nitride film 802 immediately above the pad 801A as a stopper, as a stopper. 8
Forming a contact hole 813 with respect to 01A, and (3) depositing a titanium film having a thickness not blocking the cell contact hole 813 by CVD, and then performing a heat treatment on the polysilicon film and the titanium film of the pad 801A. And (4) removing the unreacted portion of the titanium film with a mixed aqueous solution of ammonia and hydrogen peroxide, followed by CVD.
Depositing a titanium nitride film having a film thickness that does not block the cell contact hole 813, and (5) filling the contact hole 813 with a silicon oxide film 815 and etching back the silicon oxide film 815 until the titanium nitride film is exposed. And (6) the silicon oxide film 8
(7) a step of etching back the titanium nitride film, the silicide layer, and the polycrystalline silicon film 812 of the mask until the silicon oxide film 807 is exposed, using the mask 15 as a mask;
A step of forming a capacitor electrode 816 by etching the silicon oxide film 815 in the step (5) and the silicon oxide film 807 in the step (1) with an aqueous solution of hydrogen fluoride using the silicon nitride film 806 as a stopper. Thus, since the semiconductor device is manufactured, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography step, so that a semiconductor device with low manufacturing cost and high manufacturing yield can be manufactured.

Further, in the twenty-fifth embodiment, since the capacitor electrode 816 is made of a titanium nitride film, it is possible to use a capacitor electrode having a high relative dielectric constant such as tantalum oxide.

In the twenty-fifth embodiment, since the self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line
The distance must be reduced to the extent that a sufficient alignment margin can be secured for the interval of 4. However, in the direction parallel to the bit line 804, the mask size can be increased without exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, so that a semiconductor device can be manufactured without sacrificing performance.

Next, a twenty-sixth embodiment of the present invention will be described.

In the twenty-sixth embodiment, a cell contact hole 813 for forming a capacitor electrode 816 is buried using the organic film of the twenty-fifth embodiment, and an organic film and a titanium nitride film / silicide layer / polycrystalline silicon film 812 are formed.
Are collectively etched back.

According to the twenty-sixth embodiment, (1) a hole 810 opened in a laminated film of a polycrystalline silicon film 808 and a silicon oxide film 807 by using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process.
(2) using a polysilicon film 812 having a reduced opening diameter as a mask, and using a silicon nitride film 802 immediately above the pad 801A as a stopper, as a stopper. 8
Forming a contact hole 813 with respect to 01A, and (3) depositing a titanium film having a thickness not blocking the cell contact hole 813 by CVD, and then performing a heat treatment on the polysilicon film and the titanium film of the pad 801A. And (4) removing the unreacted portion of the titanium film with a mixed aqueous solution of ammonia and hydrogen peroxide, followed by CVD.
Depositing a titanium nitride film having a film thickness that does not block the cell contact hole 813, and (5) burying the cell contact hole 813 with an organic film, and forming a multi-layer of the organic film, the titanium nitride film, the silicide layer, and the mask. A step of collectively etching back the crystalline silicon film 812;
(6) After the organic film is ashed, the silicon oxide film 8 of the above step (1) is used with the silicon nitride film 806 as a stopper.
07 with an aqueous solution of hydrogen fluoride,
Since the semiconductor device is manufactured by performing the step of forming the capacitor electrode 816, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography step, so that the manufacturing cost is low and the manufacturing yield is high. A semiconductor device can be manufactured.

Further, in the twenty-sixth embodiment, since the capacitor electrode 816 is made of a titanium nitride film, it is possible to use a capacitor electrode having a high dielectric constant such as tantalum oxide.

In the twenty-sixth embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line
The distance must be reduced to the extent that a sufficient alignment margin can be secured for the interval of 4. However, in the direction parallel to the bit line 804, the mask size can be increased without exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, so that a semiconductor device can be manufactured without sacrificing performance.

Next, a twenty-seventh embodiment of the present invention will be described.

In the twenty-seventh embodiment, after the cell contact hole 813 of the twenty-fifth embodiment is opened, the cell contact hole 813 is buried with an organic film, and the organic film and the polycrystalline silicon film 812 constituting the mask are collectively etched. After the backing, the titanium film is deposited after the organic film is ashed.

According to the twenty-seventh embodiment, (1) a hole 810 opened in a laminated film of a polycrystalline silicon film 808 and a silicon oxide film 807 using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process.
(2) using a polysilicon film 812 having a reduced opening diameter as a mask, and using a silicon nitride film 802 immediately above the pad 801A as a stopper, as a stopper. 8
A step of forming a contact hole 813 for 01A, and (3) a step of burying the cell contact hole 813 with an organic film, and collectively etching back the organic film and the polycrystalline silicon film 812 of the step (2). (4) ashing the organic film and depositing a titanium film having a thickness that does not block the contact hole 813, and then forming a silicide layer by heat treatment; and (5) depositing the titanium nitride film. A step of burying the contact hole 813 by depositing an organic film, (6) a step of collectively etching back the organic film and the titanium nitride film of the step (5), and (7) ashing the organic film. Then, using the silicon nitride film 806 as a stopper, the above step (1)
Forming a capacitor electrode 816 by etching the silicon oxide film 807 using an aqueous solution of hydrogen fluoride to manufacture a semiconductor device. Therefore, the cell contact hole 813 and the capacitor electrode 8
16 can be formed by one lithography step, and a semiconductor device with low manufacturing cost and high manufacturing yield can be manufactured.

Further, in the twenty-seventh embodiment, since the capacitor electrode 816 is constituted by a titanium nitride film, it is possible to use a capacitor electrode having a high relative dielectric constant such as tantalum oxide.

In the twenty-seventh embodiment, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line
The distance must be reduced to the extent that a sufficient alignment margin can be secured for the interval of 4. However, in the direction parallel to the bit line 804, the mask size can be increased without exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, so that a semiconductor device can be manufactured without sacrificing performance.

The present invention is not limited to the above embodiments, but various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0221]

As described above, according to the present invention, the following effects can be obtained.

(A) Since a bit line can be formed without opening a contact hole to a pad formed in advance and performing a special lithography step, a bit line suitable for miniaturization of a semiconductor device can be formed. In addition to the above, the number of manufacturing steps and the manufacturing cost can be reduced.

(B) Since a contact hole is opened in a self-aligned manner with respect to a substrate, a pad for connecting a bit line and a capacitor electrode can be formed without going through a special lithography step. Thus, it is possible to reduce the number of manufacturing steps and the manufacturing cost.

(C) Since a capacitor electrode can be formed without opening a contact hole for a pad formed beforehand and without performing a special lithography step, the number of manufacturing steps and the manufacturing cost can be reduced. It can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic view showing an observation direction of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of the first conventional semiconductor device.

FIG. 4 is a cross-sectional view (No. 1) of a manufacturing process of the second conventional semiconductor device.

FIG. 5 is a sectional view (part 2) of a process for manufacturing a second conventional semiconductor device.

FIG. 6 is a cross-sectional view (part 1) illustrating a manufacturing process of a third conventional semiconductor device.

FIG. 7 is a sectional view (part 2) of a third manufacturing step of the conventional semiconductor device;

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 9 is a schematic view of a contact hole pattern of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view (part 1) of a semiconductor device showing a twelfth embodiment of the present invention in the manufacturing process.

FIG. 11 is a sectional view (part 2) of a process for manufacturing a semiconductor device according to a twelfth embodiment of the present invention.

FIG. 12 is a sectional view (part 1) of a semiconductor device showing a manufacturing step according to an eighteenth embodiment of the present invention;

FIG. 13 is a sectional view (part 2) of a process for manufacturing a semiconductor device according to an eighteenth embodiment of the present invention;

FIG. 14 is a cross-sectional view (part 1) illustrating a semiconductor device manufacturing process according to a twenty-first embodiment of the present invention.

FIG. 15 is a sectional view (part 2) of a process for manufacturing a semiconductor device according to the twenty-first embodiment of the present invention.

[Explanation of symbols]

101, 501, 600, 700, 801 Silicon substrate 102 Element isolation region 103, 502 Offset insulating film 104, 503 Transfer gate 105, 504 First insulating film 106, 508, 601, 701, 801A Pad 107, 505 Second Insulating film 108 Inversion pattern of bit line 109 Groove (contact hole) 110, 603, 703, 804 Bit line 111 Third insulating film 112 Side wall 113 Fourth insulating film 114, 610A, 711, 809 Hole pattern 115 Capacitor electrode Contact hole 601A Interlayer insulating film 604,704 Silicon nitride film on top 605,705 Silicon nitride film on side wall 607,707,802,806 Silicon nitride film 602,606,608,613,702,70 , 7
08,715,803,805,807,815 Silicon oxide film 609,612,709,808,812,814
Polycrystalline silicon film 610, 710, 809 Resist 611, 712, 813 Cell contact hole 614, 716, 816 Capacitor electrode 713 Titanium silicide layer 714 Titanium nitride film 810 Hole 811 Side wall 812 Polycrystalline silicon film (etching mask)

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Claims (27)

[Claims] 1. A method for manufacturing a semiconductor device, comprising:
A pad for connecting an upper bit line and a capacitor electrode to an interlayer insulating film having the first insulating film as an uppermost layer capable of ensuring a sufficient selectivity with respect to the second insulating film deposited in the second step. And (b) depositing and planarizing a second insulating film capable of ensuring a sufficient selectivity with respect to the first insulating film, and then using a bit line inversion pattern as a mask to form a first insulating film. Etching the second insulating film using the insulating film as a stopper, and (c) embedding the pattern with a conductive material forming the bit line so that the conductive material is recessed in the second insulating film. Forming a bit line by removing the conductive material;
After the recess is buried by depositing a third insulating film capable of ensuring a sufficient selectivity with respect to the second insulating film, the third insulating film is removed until the second insulating film is exposed. After removing, the step of removing the second insulating film;
(E) a step of completely covering the side surface of the bit line by anisotropically etching after depositing an insulating film of the same type as the third insulating film; and (f) the first and third insulating films. After depositing and flattening a fourth insulating film capable of ensuring a sufficient selectivity with respect to, the fourth insulating film is etched using the third insulating film and the first insulating film on the bit lines and side surfaces as stoppers. Forming a contact hole for forming a capacitor electrode. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first insulating film and said third insulating film are made of the same material. 3. The method for manufacturing a semiconductor device according to claim 1, wherein said second insulating film and said fourth insulating film are made of the same material. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film and the third insulating film, and the second insulating film and the fourth insulating film are made of the same material. Semiconductor device manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 4, wherein said first and third insulating films are silicon nitride films, and said second and fourth insulating films are oxidized. A method for manufacturing a semiconductor device, wherein the method is a silicon film. 6. A method for manufacturing a semiconductor device, comprising:
Forming an element isolation region and a transfer gate;
(B) a step of laminating a combination of insulating films capable of securing a sufficient selectivity; and (c) a step of forming an active region and a region where a pad for connecting to an upper layer wiring or electrode is present on the insulating film. (D) forming a pattern by lithography capable of simultaneously etching the connected regions;
After etching the upper insulating film in a self-aligned manner with the insulating film present in the lower layer of the stacked insulating films as a stopper, a step of opening a contact hole in the silicon substrate by etching the lower insulating film, (E)
After filling the contact hole with a conductive material,
Removing the conductive material until it reaches a position lower than the upper surface of the offset insulating film on the transfer gate. 7. The method of manufacturing a semiconductor device according to claim 6, wherein after the upper insulating film is flattened, a sufficiently high selectivity to the lower insulating film is obtained until the lower insulating film on the transfer gate is exposed. A method of manufacturing a semiconductor device, comprising removing an upper insulating film by using the method. 8. The method of manufacturing a semiconductor device according to claim 6, wherein a silicon oxide film is used as an offset insulating film, a silicon nitride film is used as an insulating film of an etching stopper, and a silicon oxide film is used as an insulating film above the insulating film. A method for manufacturing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 8, wherein a silicon nitride film is used as the offset insulating film. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the offset insulating film is formed of a laminated film, and a silicon oxide film is used as an uppermost insulating film. 11. The method for manufacturing a semiconductor device according to claim 8, wherein the offset insulating film is formed of a laminated film, and a silicon nitride film is used as an uppermost insulating film. 12. A method for manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate, and a capacitor electrode forming step, wherein (a) a polycrystalline silicon film, a silicon oxide film, and a nitrided film. A step of processing a laminated film of a silicon film by a lithography step and an etching step; and (b) having a structure in which an upper part and a side wall are formed in advance by using the polycrystalline silicon film as a mask and covered with a silicon nitride film. Etching a bit line using the silicon nitride film as a stopper to form a contact hole in a pad formed in advance, and (c) a polycrystalline silicon film having a thickness that does not block the contact hole. Filling the contact hole by depositing a silicon oxide film after depositing a film And (d) etching back the silicon oxide film in which the contact hole is buried using the polycrystalline silicon film of the step (c) as a stopper, and then using the silicon oxide film as a mask to form the polycrystalline silicon of the step (c). (E) isotropically etching back the film and the polycrystalline silicon film in the step (a); and (e) using the silicon nitride film as a stopper to oxidize the silicon oxide film in the step (d) and the oxidation in the step (a). Forming a capacitor electrode by etching the silicon film using an aqueous solution of hydrogen fluoride, and (f) forming a contact hole connecting the capacitor electrode and the silicon substrate, and a capacitor electrode in one lithography step. A method for manufacturing a semiconductor device, comprising: 13. The method of manufacturing a semiconductor device according to claim 12, wherein the polycrystalline silicon film in the step (c) and the polycrystalline silicon film in the step (a) are anisotropically etched using the silicon oxide film as a mask. A method for manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 12, wherein after depositing the organic film, the organic film, the polycrystalline silicon film of the step (c) and the polycrystalline silicon film of the step (a) are collectively formed. A method of manufacturing a semiconductor device, characterized by performing etch-back. 15. The method according to claim 12, wherein the uppermost layer of the interlayer insulating film on which the pad is formed is a silicon nitride film. 16. The method for manufacturing a semiconductor device according to claim 12, wherein after etching the polycrystalline silicon film and ashing the resist, the silicon oxide film and the silicon nitride film are etched using the polycrystalline silicon film as a mask. And thereafter etching the silicon oxide film using the silicon nitride films on the bit lines above and on the side walls as stoppers. 17. The method for manufacturing a semiconductor device according to claim 12, wherein after etching the polycrystalline silicon film and the silicon oxide film, the resist is ashed, and then the silicon nitride film is etched using the polycrystalline silicon film as a mask. And etching the silicon oxide film using the silicon nitride films on the bit lines above and on the side walls as stoppers. 18. A method for manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate and a capacitor electrode forming step, wherein (a) a polycrystalline silicon film, a silicon oxide film, and a nitride A step of processing the laminated film of the silicon film by a normal lithography step and an etching step; and (b) the upper and side walls previously formed using the polycrystalline silicon film as a mask are covered with a silicon nitride film. Etching a bit line having a structure using the silicon nitride film as a stopper to form a contact hole in a pad formed in advance; and (c) forming a contact hole having a thickness not blocking the contact hole. Forming a silicide layer by heat treatment after depositing the titanium film;
(D) a step of burying the contact hole by depositing a titanium nitride film and then depositing a silicon oxide film; and (e) an oxidation step of filling the contact hole by using the titanium nitride film of step (d) as a stopper. After etching back the silicon film, using the silicon oxide film as a mask, the titanium nitride film of the above step (d);
Anisotropically etching back the silicide layer of step (c) and the polycrystalline silicon film of step (a);
(F) forming a capacitor electrode by etching the silicon oxide film of step (d) and the silicon oxide film of step (a) using an aqueous solution of hydrogen fluoride using the silicon nitride film as a stopper; Subject to
(G) A method for manufacturing a semiconductor device, wherein a contact hole for connecting a capacitor electrode to a silicon substrate and a capacitor electrode are formed in one lithography step. 19. The method for manufacturing a semiconductor device according to claim 13, wherein an organic film is deposited, and then the organic film, the titanium nitride film, the silicide layer, and the polycrystalline silicon film are collectively etched back. A method for manufacturing a semiconductor device. 20. The method for manufacturing a semiconductor device according to claim 13, wherein the contact hole is opened, the contact hole is buried with an organic film, and the organic film and the polycrystalline silicon film are collectively etched. Semiconductor device manufacturing method. 21. A method of manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate and a capacitor electrode forming step, wherein (a) lamination of a polycrystalline silicon film and a silicon oxide film A step of using a sidewall made of a polycrystalline silicon film to reduce a hole opened by using a silicon nitride film as a stopper by a lithography step and an etching step, and (b) a polycrystalline silicon film having a reduced opening diameter. A step of forming a contact hole using a silicon nitride film immediately above the pad as a stopper for a pad formed in advance as a mask, and (c) depositing a polycrystalline silicon film having a thickness that does not block the contact hole After that, the contact holes are buried by depositing a silicon oxide film. And (d) etching back the silicon oxide film in which the contact hole is buried using the polycrystalline silicon film of the above step (c) as a stopper, and then using the silicon oxide film as a mask,
(A) isotropically etching back the polycrystalline silicon film and the polycrystalline silicon film in the step (a); (e) using the silicon oxide film in the step (d) with the silicon oxide film as a stopper, a) etching the silicon oxide film using an aqueous solution of hydrogen fluoride to form a capacitor electrode; and (f) forming a contact hole connecting the capacitor electrode and the silicon substrate and a capacitor electrode in one lithography step. A method for manufacturing a semiconductor device, comprising: 22. The method of manufacturing a semiconductor device according to claim 21, wherein the polycrystalline silicon film in the step (c) and the polycrystalline silicon film in the step (a) are anisotropically etched using the silicon oxide film as a mask. A method for manufacturing a semiconductor device, comprising: 23. The method of manufacturing a semiconductor device according to claim 21, wherein after depositing the organic film, the organic film, the polycrystalline silicon film of the step (c) and the polycrystalline silicon film of the step (a) are collectively formed. A method of manufacturing a semiconductor device, characterized by performing etch-back. 24. The method of manufacturing a semiconductor device according to claim 21, wherein the interlayer insulating film after the pad is formed is composed of a silicon nitride film as an upper layer and a silicon oxide film as a lower layer. Method. 25. A method of manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate and a capacitor electrode forming step, wherein (a) lamination of a polycrystalline silicon film and a silicon oxide film A step of reducing a hole opened by using a silicon nitride film as a stopper by a normal lithography step and an etching step by using a sidewall made of a polycrystalline silicon film; and (b) polycrystalline silicon having a reduced opening diameter Forming a contact hole for the pad using the film as a mask and a silicon nitride film immediately above the pad as a stopper; and (c) depositing a titanium film having a thickness not to cover the contact hole, and then performing heat treatment on the pad. Silicide layer by reacting polycrystalline silicon film with titanium film (D) removing an unreacted portion of the titanium film by using a mixed aqueous solution of ammonia and hydrogen peroxide, and then depositing a titanium nitride film having a thickness that does not block the contact hole. e)
Filling the contact hole with a silicon oxide film, and etching back the silicon oxide film until the titanium nitride film is exposed in the step (d); and (f) using the silicon oxide film as a mask, a titanium nitride film and a silicide layer. And (g) etching the silicon oxide film of step (e) and the silicon oxide film of step (a) with an aqueous solution of hydrogen fluoride using the silicon nitride film as a stopper. And (h) forming a contact hole connecting the capacitor electrode and the silicon substrate, and the capacitor electrode in one lithography step. 26. The method of manufacturing a semiconductor device according to claim 25, wherein the organic film, the titanium nitride film, the silicide layer, and the polycrystalline silicon film are collectively etched back after the organic film is deposited. Device manufacturing method. 27. The method of manufacturing a semiconductor device according to claim 25, wherein after the contact hole is opened, the contact hole is filled with an organic film, and the organic film and the polycrystalline silicon film are etched at a time. A method for manufacturing a semiconductor device.