JP3631716B2 - W-CDMA radio base station and delay time difference correction method thereof - Google Patents

W-CDMA radio base station and delay time difference correction method thereof Download PDF

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JP3631716B2
JP3631716B2 JP2001357670A JP2001357670A JP3631716B2 JP 3631716 B2 JP3631716 B2 JP 3631716B2 JP 2001357670 A JP2001357670 A JP 2001357670A JP 2001357670 A JP2001357670 A JP 2001357670A JP 3631716 B2 JP3631716 B2 JP 3631716B2
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signal
transmission signal
baseband transmission
delay time
transmitter
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JP2003158774A (en
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哲也 宇崎
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埼玉日本電気株式会社
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Description

【0001】
【発明の属する技術分野】
本発明は、送信ダイバーシチ構成の各送信機の遅延時間偏差を自動補正するW−CDMA無線基地局及びその遅延時間差補正方法に関する。
【0002】
【従来の技術】
従来の技術について、図6を参照して説明する。送信ダイバーシチ構成のW−CDMA無線基地局(以下BTSとする)では、送信機テスタや高周波用オシロスコープなどの測定器をBTS出力端5及びBTS出力端15に接続し遅延時間偏差を測定していた。その測定した遅延時間偏差をもとに遅延調整回路2,12を制御し、遅延時間を調整していた。
【0003】
また、本出願人は、特願2000−368785にて、TSTD(Time Switched Transmit Diversity)回路によるSCH(Synchronization Channel)信号に基づいて遅延時間偏差を検出して、遅延時間を調整するWCDMA無線基地局を開示している。
【0004】
【発明が解決しようとする課題】
しかしながら、従来の遅延時間調整方法では、遅延時間偏差の調整時に高価な測定器を用意する必要があり、かつ、遅延時間の測定時間及び人件費を要していた。
【0005】
また、上記従来のWCDMA無線基地局では、TSTD方式によるSCH信号を用いることを前提としている。
【0006】
そこで本発明は、送信ダイバーシチ構成の各送信機の遅延時間偏差を簡易な構成で自動補正するW−CDMA無線基地局及びその遅延時間差補正方法を提供することを目的とする。
【0007】
【課題を解決するための手段】
上述の課題を解決するため、本発明は、図1において、IPDL時にアイドル回路1,11にて送信データであるBB(Base Bandの略)入力信号(Sig1,Sig11)を無送信状態(BB信号がオール0)で出力し、BTS出力端5,15前で方向性結合器4,14にて各送信キャリアを分配して検波器6,16にて検波する。検波した0系アイドル期間の立ち下がりエッジと検波した1系アイドル期間の立ち下がりエッジの時間偏差を制御回路20で検出する。検出した0系と1系の時間偏差において0系立ち下がりエッジの方が速い場合、0系の遅延調整回路2にて進んでいる時間偏差分だけの時間を遅延させ0系の送信機100と1系の送信機110との時間偏差を無くす。検出した0系と1系の時間差において1系立ち下がりエッジの方が速い場合、1系の遅延調整回路12にて進んでいる時間偏差分だけの時間を遅延させ0系の送信機100と1系の送信機110との時間偏差を無くすことを特徴とする。
【0008】
以上の構成によって、0系の送信機100と1系の送信機110での遅延時間偏差が無くなる。
【0009】
【発明の実施の形態】
次に、本発明の実施の形態について図面を参照して説明する。
【0010】
図1を参照すると、アイドル回路1と遅延調整回路2とRF回路3と方向性結合器4とBTS出力端5とにより構成された部分を0系の送信機100とし、アイドル回路11と遅延調整回路12とRF回路13と方向性結合器14とBTS出力端15とにより構成された部分を1系の送信機110とする。
【0011】
0系の送信機100は、IPDL時に無送信状態にすべく送信データであるBB入力信号(Sig1)をオールゼロに変換し0系のBB送信信号(Sig2)を出力するアイドル回路1と、アイドル回路1より出力された0系の送信信号(Sig2)を制御信号(Sig4)により所望の遅延時間に設定し0系の送信信号(Sig2)を遅延させて出力させる遅延調整回路2と、遅延調整回路2にて遅延された0系の送信信号(Sig2)で搬送波を変調しかつ所望の電力まで増幅してRF(無線周波数)信号を出力するRF回路3と、RF回路3から出力された0系のRF信号を2分配する方向性結合器4と、方向性結合器4から出力された0系のRF信号を入力しアンテナ0へ出力するBTS出力端5と、方向性結合器4より分配された0系のRF信号を検波して0系のBB送信信号(Sig3)に変換する検波器6とを有する。
【0012】
1系の送信機110は、IPDL時に無送信状態にすべく送信データであるBB入力信号(Sig11)をオールゼロに変換し1系のBB送信信号(Sig12)を出力するアイドル回路11と、アイドル回路11より出力された1系の送信信号(Sig12)を制御信号(Sig14)により所望の遅延時間に設定し1系の送信信号(Sig12)を遅延させて出力させる遅延調整回路12と、遅延調整回路12にて遅延された1系の送信信号(Sig12)で搬送波を変調しかつ所望の電力まで増幅してRF(無線周波数)信号を出力するRF回路13と、RF回路13から出力された1系のRF信号を2分配する方向性結合器14と、方向性結合器14から出力された1系のRF信号を入力しアンテナ10へ出力するBTS出力端15と、方向性結合器14より分配された1系のRF信号を検波して1系のBB送信信号(Sig13)に変換する検波器16とを有する。
【0013】
送信機100の検波器6により出力された0系の送信信号(Sig3)と、送信機110の検波器16により出力された1系の送信信号(Sig13)を入力し、遅延時間偏差を補正する為に0系の制御信号(Sig4)及び1系の制御信号(Sgi14)をそれぞれ遅延調整回路2,12に出力する制御回路20をさらに有する。
【0014】
図2は、本発明における制御回路20を示すブロック図である。制御回路20は、検波器6より出力された0系のアナログ送信信号(Sig3)をデジタル信号に変換するA/Dコンバータ21と、検波器16より出力された1系のアナログ送信信号(Sig13)をデジタル信号に変換するA/Dコンバータ22と、A/Dコンバータ21より出力された0系のデジタル送信信号とA/Dコンバータ22より出力された1系のデジタル送信信号とを入力し、遅延時間偏差を補正する為に0系の制御信号(Sig4)及び1系の制御信号(Sig14)をそれぞれ遅延調整回路2,12に出力するCPU23と、CPU23に接続され遅延時間偏差制御を行うためのプログラムをあらかじめ格納しておくメモリー24とにより構成される。
【0015】
次に上記回路の動作について説明する。なお、IPDLとは、位置情報サービスに必要な時間差測定のためにBTSからの送信を一時的に無送信状態にするものである(3GPP仕様書 TS.25.214による)。
【0016】
RNC(ネットワーク制御装置)などの上位装置からIPDL情報を受け取りアイドル期間と呼ばれる無送信状態を生成すべくアイドル回路1,11でBB入力信号(Sig1,Sig11)をオールゼロにする。IPDLを行わない通常のシステム運用時は、アイドル回路1,11は、入力されたBB信号(Sig1,Sig11)をそのまま出力する。BB入力信号(Sig1,Sig11)は、RNCなどの上位装置から送られた信号をBTS内部で拡散変調、誤り訂正符号化、フレーム化等を施した信号である。出力された0系の送信信号(Sig2)によって搬送波(2110〜2170MHz)が変調され、かつ所望の電力まで増幅されてRF信号として出力される。出力された0系のRF信号は、方向性結合器4で2分配されBTS出力端5に出力され、分配されたもう一方の0系のRF信号は、検波器6で検波されて制御回路20に入力される。同様に1系の送信信号(Sig12)もRF回路13、方向性結合器14、検波器16を経て制御回路20に入力される。制御回路20は、メモリー24にあらかじめ格納されたプログラムに基づきCPU23が動作する。
【0017】
制御回路20では、図3に示すように、0系の送信信号(Sig3)と1系の送信信号(Sig13)の立ち下がりエッジをもとに遅延時間偏差を検出し、その遅延時間偏差を補正するために遅延調整回路2,12へそれぞれ制御信号(Sig4,Sig14)を出力する。制御回路20より出力された制御信号(Sig4,Sig14)により遅延調整回路2,12は、遅延時間を調整する。遅延調整回路2,12は、一般的なシフトレジスタ回路で遅延時間の調整が実現できる。
【0018】
図4のフローチャートを参照して遅延時間偏差の補正制御方法を説明する。例えば、0系の送信信号(Sig3)と1系の送信信号(Sig13)の立ち下がりエッジが同じタイミング(A=B)で制御回路20に入力された場合(St2)、制御回路20は、0系の送信機100と1系の送信機110の遅延時間偏差が無いと判断し(St12)、0系及び1系の遅延調整回路2,12を現状のままの遅延時間に制御する(St13)。これにより0系の送信機100と1系の送信機110の遅延時間偏差がないままとなる。
【0019】
0系の立ち下がりエッジが1系の立ち下がりエッジより50ns速く制御回路に入力され(St2,3,4)、かつ、現在の0系及び1系の遅延調整回路2,12の制御量が各0nsの場合(St6)、0系の遅延調整回路2を50ns間遅延させるように制御し、1系の遅延調整回路12の遅延時間を現状の0nsのままとする(St8)。これにより0系の送信機100と1系の送信機110の遅延時間偏差が無くなる。
【0020】
1系の立ち下がりエッジが0系の立ち下がりエッジより150ns速く制御回路13に入力され(St2,3,5)、かつ、現在の0系の遅延調整回路2の制御量が50nsで1系の遅延調整回路12の制御量が0nsである時(St7)、0系の遅延調整回路2の遅延時間を0nsに制御し、1系の遅延調整回路12の遅延時間を100nsとする(St10)。これにより、遅延時間調整を150ns行ったことになり、0系の送信機100と1系の送信機110の遅延時間偏差が無くなる。
【0021】
0系のBTS出力端5及び1系のBTS出力端15より出力される送信信号の遅延時間偏差を無くすことが本発明の目的であるため、0系の方向性結合器4からBTS出力端5までと、1系の方向性結合器14からBTS出力端15までとの遅延時間偏差が無いように同じ特性の伝送線で接続する。同様に0系の方向性結合器4からCPU23入力までと、1系の方向性結合器14からCPU23入力までの遅延時間偏差が無いように同じ特性の伝送線及び検波器6,16で接続する。
【0022】
送信ダイバーシチで0系の送信信号(Sig2)と1系の送信信号(Sig12)の遅延時間偏差を無くさなければならない理由は、時間偏差があると送信ダイバーシチの効果が無くなってしまうためである(公知技術)。携帯電話機などの移動通信端末装置がフェージングの環境下で受信レベルの高いBTSの0系のアンテナ出力と1系のアンテナ出力を選択し復調する事により常時高い通信品質を保つ事を目的として送信ダイバーシチを行っている。にもかかわらず、移動通信端末装置に入力される受信信号に遅延時間偏差があると高いレベルのBTSの送信信号を選ぶと高品質な復調が出来なくなってしまう。
【0023】
次に、本発明の他の実施形態について説明する。図5を参照すると、送信機31,32,33,34を4台用いた2キャリアによるダイバーシチ無線基地局において、1キャリアしか使用しない場合、4台の送信機31,32,33,34の遅延時間偏差を調整し、各送信機31,32,33,34を同じ周波数キャリアに設定すると、送信機2台によるダイバーシチ無線基地局よりも、合成器40,41の出力で合成電力が2倍となる。このことによりセル範囲を拡大することが出来る。
【0024】
【発明の効果】
以上説明したように、本発明による第1の効果は、IPDLの無送信状態になる立ち下がりエッジを制御回路で測定し、その測定した0系と1系の立ち下がりエッジの時間差だけ、速く立ち下がった系の遅延調整回路にて早い分だけの時間を遅延させることによって、各送信機での遅延時間が同等になるので、送信ダイバーシチ構成の遅延時間偏差を調整できることである。
【0025】
第2の効果は、送信ダイバーシチ構成の遅延時間偏差を自動調整できるので、RF回路が故障し予備系のRF回路に切り替わったとしても遅延時間偏差が発生しないことである。
【0026】
第3の効果は、本発明による遅延時間偏差自動調整システムが安価な部品で作成でき、遅延時間偏差を計測するための高価な測定器を必要とせず、遅延時間調整を行うための定期的な保守費用が発生しないので、経費を低減できることである。
【0027】
第4の効果は、遅延時間調整機能とIPDL機能とALC機能(Auto Loop Control:送信電力の自動制御機能)を含め、元々ある回路で構成することができるので、本発明のために新たに部品を追加する必要がなく、実装スペースを必要とせず小型化に寄与でき、かつ、装置原価が上がらないことである。
【図面の簡単な説明】
【図1】本発明による実施形態のブロック図
【図2】図1の制御回路の詳細ブロック図
【図3】本発明による遅延時間偏差検出を説明するタイムチャート
【図4】本発明による実施形態の動作を説明するフローチャート
【図5】発明による他の実施形態のブロック図
【図6】従来の技術を説明するブロック図
【符号の説明】
0,10 アンテナ
1,11 アイドル回路
2,12 遅延検出回路
3,13 RF回路
4,14 方向性結合器
5,15 BTS出力端
6,16 検波器
20 制御回路
21,22 A/Dコンバータ
23 CPU
24 メモリー
31,32,33,34 送信機
35,36,37,38 検波器
39 制御回路
40,41 合成器
100,110 送信機
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a W-CDMA radio base station for automatically correcting a delay time deviation of each transmitter having a transmission diversity configuration and a delay time difference correcting method thereof.
[0002]
[Prior art]
A conventional technique will be described with reference to FIG. In a transmission diversity W-CDMA radio base station (hereinafter referred to as BTS), a measuring instrument such as a transmitter tester or a high-frequency oscilloscope is connected to the BTS output terminal 5 and the BTS output terminal 15 to measure delay time deviation. . Based on the measured delay time deviation, the delay adjustment circuits 2 and 12 are controlled to adjust the delay time.
[0003]
In addition, in the Japanese Patent Application 2000-368785, the present applicant detects a delay time deviation based on an SCH (Synchronization Channel) signal by a TSTD (Time Switched Transmit Diversity) circuit and adjusts the delay time. Is disclosed.
[0004]
[Problems to be solved by the invention]
However, in the conventional delay time adjustment method, it is necessary to prepare an expensive measuring instrument when adjusting the delay time deviation, and the measurement time and labor cost of the delay time are required.
[0005]
The conventional WCDMA radio base station is premised on using an SCH signal based on the TSTD scheme.
[0006]
Therefore, an object of the present invention is to provide a W-CDMA radio base station that automatically corrects delay time deviations of transmitters having a transmission diversity configuration with a simple configuration and a delay time difference correction method thereof.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problem, in the present invention, in FIG. 1, the BB (abbreviation of Base Band) input signal (Sig1, Sig11), which is transmission data in the idle circuits 1 and 11, is transmitted in the non-transmission state (BB signal). Are all 0), and each transmission carrier is distributed by the directional couplers 4 and 14 before the BTS output terminals 5 and 15 and detected by the detectors 6 and 16. The control circuit 20 detects a time deviation between the detected falling edge of the 0-system idle period and the detected falling edge of the 1-system idle period. If the 0 system falling edge is faster in the detected time deviation between the 0 system and the 1 system, the 0 system transmitter 100 is delayed by delaying the time by the time deviation advanced in the 0 system delay adjustment circuit 2. A time deviation from the transmitter 110 of the first system is eliminated. When the 1 system falling edge is faster than the detected time difference between the 0 system and the 1 system, the time corresponding to the time deviation advanced by the 1 system delay adjustment circuit 12 is delayed to delay the 0 system transmitters 100 and 1. It is characterized by eliminating the time deviation from the transmitter 110 of the system.
[0008]
With the above configuration, the delay time deviation between the 0-system transmitter 100 and the 1-system transmitter 110 is eliminated.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0010]
Referring to FIG. 1, a portion constituted by an idle circuit 1, a delay adjustment circuit 2, an RF circuit 3, a directional coupler 4, and a BTS output terminal 5 is a 0-system transmitter 100, and the idle circuit 11 and delay adjustment are performed. A portion constituted by the circuit 12, the RF circuit 13, the directional coupler 14, and the BTS output terminal 15 is a 1-system transmitter 110.
[0011]
The 0-system transmitter 100 includes an idle circuit 1 that converts a BB input signal (Sig1), which is transmission data, into all zeros and outputs a 0-system BB transmission signal (Sig2) in order to make a non-transmission state during IPDL, and an idle circuit A delay adjusting circuit 2 for setting a desired delay time of the 0-system transmission signal (Sig2) output from 1 to a desired delay time by the control signal (Sig4), and delaying and outputting the 0-system transmission signal (Sig2); The RF circuit 3 that modulates the carrier wave with the 0-system transmission signal (Sig2) delayed at 2 and amplifies it to a desired power and outputs an RF (radio frequency) signal, and the 0-system that is output from the RF circuit 3 The directional coupler 4 that distributes two RF signals, the BTS output terminal 5 that inputs the 0-system RF signal output from the directional coupler 4 and outputs the RF signal to the antenna 0, and the directional coupler 4 The And a detector 6 which converts the RF signal of the system to the detection to the 0-system BB transmission signal (Sig 3).
[0012]
The 1-system transmitter 110 converts an BB input signal (Sig11), which is transmission data, into all zeros to output a 1-system BB transmission signal (Sig12), and an idle circuit. A delay adjustment circuit 12 for setting a desired transmission delay time of the 1-system transmission signal (Sig12) output from the control signal 11 by a control signal (Sig14) and outputting the 1-system transmission signal (Sig12) by delaying; The RF circuit 13 that modulates the carrier wave with the 1-system transmission signal (Sig12) delayed at 12 and amplifies it to a desired power and outputs an RF (radio frequency) signal, and the 1-system that is output from the RF circuit 13 A directional coupler 14 that distributes two RF signals, and a BTS output terminal 15 that inputs a 1-system RF signal output from the directional coupler 14 and outputs the RF signal to the antenna 10. , And a detector 16 for converting the 1-system BB transmission signal by detecting the RF signal of one system is distributed from the directional coupler 14 (Sig13).
[0013]
The 0-system transmission signal (Sig3) output from the detector 6 of the transmitter 100 and the 1-system transmission signal (Sig13) output from the detector 16 of the transmitter 110 are input, and the delay time deviation is corrected. For this purpose, it further includes a control circuit 20 for outputting the 0-system control signal (Sig4) and the 1-system control signal (Sgi14) to the delay adjustment circuits 2 and 12, respectively.
[0014]
FIG. 2 is a block diagram showing the control circuit 20 in the present invention. The control circuit 20 includes an A / D converter 21 that converts the 0-system analog transmission signal (Sig3) output from the detector 6 into a digital signal, and a 1-system analog transmission signal (Sig13) output from the detector 16. A / D converter 22 for converting the signal into a digital signal, a 0-system digital transmission signal output from A / D converter 21 and a 1-system digital transmission signal output from A / D converter 22 are input and delayed. In order to correct the time deviation, the CPU 23 outputs the 0-system control signal (Sig4) and the 1-system control signal (Sig14) to the delay adjustment circuits 2 and 12, respectively, and is connected to the CPU 23 for delay time deviation control. The memory 24 stores a program in advance.
[0015]
Next, the operation of the above circuit will be described. Note that IPDL temporarily makes transmission from the BTS in a non-transmission state in order to measure the time difference required for the location information service (according to 3GPP specification TS.25.214).
[0016]
The IPDL information is received from a higher-level device such as an RNC (network control device), and the BB input signals (Sig1, Sig11) are set to all zero in the idle circuits 1 and 11 to generate a non-transmission state called an idle period. During normal system operation without IPDL, the idle circuits 1 and 11 output the input BB signals (Sig1, Sig11) as they are. The BB input signals (Sig1, Sig11) are signals obtained by subjecting a signal sent from a higher-level device such as RNC to spreading modulation, error correction coding, framing and the like inside the BTS. The carrier wave (2110 to 2170 MHz) is modulated by the output 0 system transmission signal (Sig2), amplified to a desired power, and output as an RF signal. The output 0-system RF signal is divided into two by the directional coupler 4 and output to the BTS output terminal 5, and the other distributed 0-system RF signal is detected by the detector 6 to be detected by the control circuit 20. Is input. Similarly, the 1-system transmission signal (Sig 12) is also input to the control circuit 20 through the RF circuit 13, the directional coupler 14, and the detector 16. In the control circuit 20, the CPU 23 operates based on a program stored in advance in the memory 24.
[0017]
As shown in FIG. 3, the control circuit 20 detects the delay time deviation based on the falling edges of the 0-system transmission signal (Sig3) and the 1-system transmission signal (Sig13), and corrects the delay time deviation. Therefore, control signals (Sig4, Sig14) are output to the delay adjustment circuits 2 and 12, respectively. The delay adjustment circuits 2 and 12 adjust the delay time based on the control signals (Sig4 and Sig14) output from the control circuit 20. The delay adjustment circuits 2 and 12 can be adjusted with a general shift register circuit.
[0018]
The delay time deviation correction control method will be described with reference to the flowchart of FIG. For example, when the falling edges of the 0-system transmission signal (Sig3) and the 1-system transmission signal (Sig13) are input to the control circuit 20 at the same timing (A = B) (St2), the control circuit 20 It is determined that there is no delay time deviation between the system transmitter 100 and the system 1 transmitter 110 (St12), and the system 0 and system 1 delay adjustment circuits 2 and 12 are controlled to the current delay time (St13). . As a result, there is no delay time deviation between the 0-system transmitter 100 and the 1-system transmitter 110.
[0019]
The falling edge of the 0 system is input to the control circuit 50 ns faster than the falling edge of the 1 system (St2, 3, 4), and the control amounts of the current 0 system and 1 system delay adjusting circuits 2, 12 are In the case of 0 ns (St6), the delay adjustment circuit 2 of the 0 system is controlled to be delayed by 50 ns, and the delay time of the delay adjustment circuit 12 of the 1 system is kept at the current 0 ns (St8). This eliminates the delay time deviation between the 0-system transmitter 100 and the 1-system transmitter 110.
[0020]
The falling edge of the 1st system is input to the control circuit 13 150ns faster than the falling edge of the 0th system (St2, 3, 5), and the current control amount of the delay adjusting circuit 2 of the 0th system is 50ns. When the control amount of the delay adjustment circuit 12 is 0 ns (St7), the delay time of the 0-system delay adjustment circuit 2 is controlled to 0 ns, and the delay time of the 1-system delay adjustment circuit 12 is set to 100 ns (St10). Accordingly, the delay time adjustment is performed for 150 ns, and the delay time deviation between the 0-system transmitter 100 and the 1-system transmitter 110 is eliminated.
[0021]
Since it is an object of the present invention to eliminate delay time deviations of transmission signals output from the 0-system BTS output terminal 5 and the 1-system BTS output terminal 15, the 0-system directional coupler 4 to the BTS output terminal 5 And a transmission line having the same characteristics so that there is no delay time deviation from the directional coupler 14 of the first system to the BTS output terminal 15. Similarly, transmission lines and detectors 6 and 16 having the same characteristics are connected so that there is no delay time deviation from the 0-system directional coupler 4 to the CPU 23 input and from the 1-system directional coupler 14 to the CPU 23 input. .
[0022]
The reason why it is necessary to eliminate the delay time deviation between the 0-system transmission signal (Sig2) and the 1-system transmission signal (Sig12) in transmission diversity is that if there is a time deviation, the effect of transmission diversity is lost (known in the art). Technology). Transmit diversity for the purpose of maintaining high communication quality at all times by selecting and demodulating BTS 0 antenna output and 1 antenna output of a BTS with a high reception level in a fading environment by a mobile communication terminal device such as a cellular phone It is carried out. Nevertheless, if there is a delay time deviation in the received signal input to the mobile communication terminal apparatus, high-quality demodulation cannot be performed if a high-level BTS transmission signal is selected.
[0023]
Next, another embodiment of the present invention will be described. Referring to FIG. 5, when only one carrier is used in a two-carrier diversity radio base station using four transmitters 31, 32, 33, and 34, the delay of four transmitters 31, 32, 33, and 34 is used. When the time deviation is adjusted and each transmitter 31, 32, 33, 34 is set to the same frequency carrier, the combined power is doubled at the output of the combiners 40, 41 than the diversity radio base station with two transmitters. Become. This can expand the cell range.
[0024]
【The invention's effect】
As described above, the first effect of the present invention is that the falling edge where the IPDL is not transmitted is measured by the control circuit, and the rising edge rises faster by the time difference between the measured 0 and 1 falling edges. By delaying the time by an early amount by the delay adjustment circuit of the lowered system, the delay time in each transmitter becomes equal, so that the delay time deviation of the transmission diversity configuration can be adjusted.
[0025]
The second effect is that the delay time deviation of the transmission diversity configuration can be automatically adjusted, so that the delay time deviation does not occur even if the RF circuit fails and is switched to the standby RF circuit.
[0026]
The third effect is that the delay time deviation automatic adjustment system according to the present invention can be created with inexpensive parts, and an expensive measuring instrument for measuring the delay time deviation is not required, and the delay time adjustment is performed periodically. Since no maintenance cost is incurred, the cost can be reduced.
[0027]
The fourth effect is that it can be configured with a circuit originally including a delay time adjustment function, an IPDL function, and an ALC function (Auto Loop Control: automatic transmission power control function). It is possible to contribute to downsizing without requiring a mounting space, and the apparatus cost does not increase.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment according to the present invention. FIG. 2 is a detailed block diagram of a control circuit of FIG. 1. FIG. 3 is a time chart for explaining delay time deviation detection according to the present invention. FIG. 5 is a block diagram of another embodiment according to the invention. FIG. 6 is a block diagram for explaining the prior art.
DESCRIPTION OF SYMBOLS 0,10 Antenna 1,11 Idle circuit 2,12 Delay detection circuit 3,13 RF circuit 4,14 Directional coupler 5,15 BTS output terminal 6,16 Detector 20 Control circuit 21,22 A / D converter 23 CPU
24 Memory 31, 32, 33, 34 Transmitter 35, 36, 37, 38 Detector 39 Control circuit 40, 41 Synthesizer 100, 110 Transmitter

Claims (6)

送信ダイバーシチ構成のW−CDMA無線基地局において、IPDL時に無送信状態にするためにベースバンド入力信号をゼロにしてベースバンド送信信号を出力するアイドル回路と、
このアイドル回路より出力されたベースバンド送信信号を、制御信号により設定された時間遅延させてベースバンド送信信号を出力する遅延調整回路と、
この遅延調整回路にて遅延されたベースバンド送信信号で搬送波を変調してRF信号を出力するRF回路と、
このRF信号を2分配する方向性結合器と、
この分配された一方のRF信号を検波してベースバンド送信信号に変換する検波器とをそれぞれ有する第1及び第2の送信機を備え、
前記第1の送信機の検波器から出力される第1のベースバンド送信信号及び前記第2の送信機の検波器から出力される第2のベースバンド送信信号を入力とし、それらの遅延時間偏差を検出して、前記第1の及び第2の送信機の遅延調整回路にそれぞれ遅延時間偏差を補正するための前記制御信号を出力する制御回路をさらに有することを特徴とするW−CDMA無線基地局。
In a W-CDMA radio base station having a transmission diversity configuration, an idle circuit that outputs a baseband transmission signal with a baseband input signal set to zero in order to make a non-transmission state during IPDL,
A delay adjustment circuit that outputs a baseband transmission signal by delaying the baseband transmission signal output from the idle circuit by a time set by a control signal;
An RF circuit that modulates a carrier wave with a baseband transmission signal delayed by the delay adjustment circuit and outputs an RF signal;
A directional coupler for distributing the RF signal into two parts;
A first transmitter and a second transmitter each having a detector that detects one of the distributed RF signals and converts the detected RF signal into a baseband transmission signal;
The first baseband transmission signal output from the detector of the first transmitter and the second baseband transmission signal output from the detector of the second transmitter are input, and a delay time deviation between them is input. And a control circuit that outputs the control signal for correcting the delay time deviation to the delay adjustment circuits of the first and second transmitters, respectively. Bureau.
前記制御回路は、前記第1のベースバンド送信信号のアイドル期間の立ち下がりエッジと、前記第2のベースバンド送信信号のアイドル期間の立ち下がりエッジとの時間偏差を検出して、遅延時間偏差を補正するための制御信号を出力することを特徴とする請求項1記載のW−CDMA無線基地局。The control circuit detects a time deviation between a falling edge of the idle period of the first baseband transmission signal and a falling edge of the idle period of the second baseband transmission signal, and calculates a delay time deviation. The W-CDMA radio base station according to claim 1, wherein a control signal for correction is output. 前記制御回路は、前記第1及び第2のベースバンド送信信号の時間偏差検出結果が、前記第1のベースバンド送信信号の立ち下がりエッジの方が早い場合、前記第1の送信機の遅延調整回路に進んでいる時間偏差分の時間を遅延させる制御信号を出力し、
前記第2のベースバンド送信信号の立ち下がりエッジの方が早い場合、前記第2の送信機の遅延調整回路に進んでいる時間偏差分の時間を遅延させる制御信号を出力することを特徴とする請求項2記載のW−CDMA無線基地局。
The control circuit adjusts the delay of the first transmitter when a time deviation detection result of the first and second baseband transmission signals is earlier than a falling edge of the first baseband transmission signal. Outputs a control signal that delays the time for the time deviation going to the circuit,
When a falling edge of the second baseband transmission signal is earlier, a control signal for delaying a time corresponding to a time deviation going to the delay adjustment circuit of the second transmitter is output. The W-CDMA radio base station according to claim 2.
前記第1及び第2の送信機が、それぞれ複数の送信機によって構成され、その構成する送信機の出力を合成してそれぞれのダイバーシチ・アンテナから送信することを特徴とする請求項1〜3のいずれかに記載のW−CDMA無線基地局。The said 1st and 2nd transmitter is respectively comprised by several transmitters, The output of the transmitter which comprises the said is combined, and it transmits from each diversity antenna, The characterized by the above-mentioned. The W-CDMA radio base station according to any one of the above. 送信ダイバーシチ構成の第1及び第2の送信機を有するW−CDMA無線基地局における遅延時間差補正方法であって、
前記第1及び第2の送信機にて、上位装置からIPDL信号を受け取りアイドル期間に対応してベースバンド入力信号をゼロにしてベースバンド送信信号を出力するステップと、
前記第1及び第2の送信機にて、出力されたベースバンド送信信号で搬送波を変調してRF信号を出力するステップと、
前記第1及び第2の送信機にて、前記RF信号を2分配して、その一方を検波してベースバンド送信信号に変換するステップと、
前記第1の送信機から出力される第1のベースバンド送信信号と前記第2の送信機から出力される第2のベースバンド送信信号との遅延時間偏差を検出して、前記第1の及び第2の送信機にそれぞれ遅延時間偏差を補正するための制御信号を出力するステップと、
前記第1及び第2の送信機にて、前記制御信号により設定された時間ベースバンド送信信号を遅延させるステップとを含むことを特徴とするW−CDMA無線基地局の遅延時間差補正方法。
A method for correcting a delay time difference in a W-CDMA radio base station having first and second transmitters having a transmission diversity configuration,
In the first and second transmitters, receiving an IPDL signal from a host device and setting a baseband input signal to zero corresponding to an idle period, and outputting a baseband transmission signal;
Modulating the carrier wave with the output baseband transmission signal at the first and second transmitters and outputting an RF signal;
In the first and second transmitters, the RF signal is divided into two, one of them is detected and converted into a baseband transmission signal;
Detecting a delay time deviation between a first baseband transmission signal output from the first transmitter and a second baseband transmission signal output from the second transmitter; Outputting a control signal for correcting the delay time deviation to each of the second transmitters;
Delaying a time baseband transmission signal set by the control signal at the first and second transmitters, and a delay time difference correction method for a W-CDMA radio base station.
前記第1のベースバンド送信信号のアイドル期間の立ち下がりエッジと、前記第2のベースバンド送信信号のアイドル期間の立ち下がりエッジとの時間偏差を検出して、遅延時間偏差を補正するための制御信号を出力することを特徴とする請求項5記載のW−CDMA無線基地局の遅延時間差補正方法。Control for correcting a delay time deviation by detecting a time deviation between a falling edge of an idle period of the first baseband transmission signal and a falling edge of an idle period of the second baseband transmission signal 6. The delay time difference correction method for a W-CDMA radio base station according to claim 5, wherein a signal is output.
JP2001357670A 2001-11-22 2001-11-22 W-CDMA radio base station and delay time difference correction method thereof Expired - Fee Related JP3631716B2 (en)

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