JP3629693B2 - Signal processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing apparatus suitable for use in, for example, a sound source of an electronic musical instrument.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, dedicated signal processing devices aiming at high performance or distribution of host CPU functions are known. This type of processing device has a built-in multiplier that performs high-speed product-sum operations in order to efficiently perform processing such as digital filtering and FFT (Fast Fourier Transform) on digital signals obtained by digitally converting analog waveforms. Is called a digital signal processor (DSP).
[0003]
Such a signal processing apparatus often takes a form in which data to be processed is stored in an external memory and is sequentially fetched to perform signal processing. For example, when used as a sound source for an electronic musical instrument, waveform data stored in an external memory is sequentially read at predetermined sampling periods, and delayed feedback calculation and filter calculation (for example, FIR filter) are performed on the read waveform data. Is used to form musical tones with various overtone structures, or various sound effects are added to the formed musical sounds for output.
[0004]
[Problems to be solved by the invention]
By the way, in the conventional signal processing apparatus described above, the access time to the external memory is generally later than that to the internal memory. That is, referring to the case of reading data from the external memory based on the example of pipeline processing timing shown in FIG. 9, first, when the program counter PC is “n”, the external memory read instruction Ex_read is set as an operation code. Then, it is sequentially interpreted by decodes 1 and 2 and executed in the next cycle.
[0005]
In other words, after two stages of decoding, it takes 2 clocks to access the external memory, 1 clock to decode the read data, and an access time of 3 clocks, which is a time lag. The command for processing the data has the program counter PC after n + 3.
[0006]
Similarly, when writing data in the external memory, as an example shown in FIG. 10, an addition instruction ADD, and an external memory write instruction Ex_write is set the program counter PC = n, at n + 1 as the operation code Then, it is written in the external memory for 3 clocks. Therefore, the program counter PC becomes “n + 3” or later in order to be able to start the next memory access instruction.
[0007]
Thus, in the conventional signal processing apparatus, if the process of frequently accessing the external memory is performed, the above-mentioned time lag becomes a “dead time”, which causes a decrease in the processing speed of the entire apparatus. There is.
Accordingly, the present invention has been made in view of such circumstances, and an object thereof is to provide a signal processing device capable of improving processing speed by omitting dead time when accessing an external memory. Yes.
[0008]
[Means for Solving the Problems]
To achieve the above object, according to the invention of claim 1 has an internal storage means provided in the apparatus, against the internal storage unit, a first signal processing that proceeds in synchronization with the predetermined sampling rate Thus, the first processing unit that performs at least one of reading and writing of data and the second signal processing that proceeds at the timing between the first signal processing, the first processing unit is transferred to the internal storage unit. In addition to generating an access request, in response to access permission generated from the first processing unit in response to the access request, writing of data read from the external storage unit provided outside the apparatus to the internal storage unit, and internal storage and second processing means for performing at least one of writing to the external storage unit of the read data from the unit, the predetermined the start timing of the first signal processing By the time of adding the offset to initiate the second signal processing is characterized by comprising a processing schedule adjustment means to avoid conflicts between the first signal processing and the second signal processing, the.
[0009]
According to the second aspect of the present invention that is dependent on the first aspect, the processing schedule adjustment means starts the second signal processing from the time when the predetermined offset is added to the start timing of the first signal processing. When the second signal processing competes with the first signal processing, the progress of the second signal processing is temporarily stopped .
[0012]
In the present invention, in synchronization with a time slot in which the first processing means does not occupy the internal storage means, the data read by the second processing means from the external storage means is written to the internal storage means or from the internal storage means. Since the read data is written into the external storage means, the external storage means can be regarded as a part of the internal storage means when viewed from the first processing means, so that the time wasted when accessing the external storage means is omitted. This improves the processing speed of the entire apparatus.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The signal processing device according to the present invention performs signal processing based on data or parameters stored in an external memory, such as a sound synthesis device, a speech recognition device, an image processing device, etc. It can be applied to various devices. Below, the signal processing apparatus which is embodiment of this invention is demonstrated with reference to drawings as an Example.
[0014]
A. Configuration (1) Overview of Embodiment FIG. 1 is a block diagram showing a configuration of a signal processing apparatus 1 according to an embodiment of the present invention. The signal processing apparatus 1 shown in FIG. 1 reads / writes data from / to the external memory 3 separately from the first processing unit 4 that performs signal processing under the control of the host CPU 2. It comprises a second processing unit 5 that performs processing.
[0015]
The signal processing apparatus 1 is different from the conventional one in that the second processing unit 5 can read / write the external memory 3 separately from the first processing unit 4.
By doing so, the first processing unit 4 can access the external memory 3 as if it is a part of the internal memory, and therefore omits the “dead time” when accessing the external memory 3. To improve processing speed.
[0016]
(2) Configuration of first processing unit 4 The first processing unit 4 includes components 4a to 4e. 4a is a main program memory (ROM) for storing the main program MP, and 4b is a CPU interface for exchanging data between the host CPU 2 and an arithmetic processing control unit 4e described later. Reference numeral 4c denotes an arithmetic unit including an arithmetic logic unit (ALU), a multiplier (MUL), and the like, and performs various arithmetic operations according to instructions from the arithmetic processing control unit 4e. Reference numeral 4d denotes a work memory (RAM) used as a work area for the calculation unit 4c and the calculation processing control unit 4e, and includes a plurality of register areas for temporarily storing various calculation results and control flags.
[0017]
The arithmetic processing control unit 4 e controls each of the above elements 4 a to 4 d and performs data exchange with the second processing unit 5. That is, the arithmetic processing control unit 4e reads the corresponding main program MP from the main program memory 4a based on the operation instruction supplied via the CPU interface 4b, and instructs the arithmetic unit 4c to perform various operations according to the program MP. To do. In addition, the arithmetic processing control unit 4 e instructs the second processing unit 5 to write data to the external memory 3 or instructs the second processing unit 5 to read data from the external memory 3. In addition, the arithmetic processing control unit 4e includes a schedule adjustment circuit 4e-1 (described later) that avoids processing competition with the second processing unit 5 side.
[0018]
(3) Configuration of the second processing unit 5 The second processing unit 5 includes components 5a to 5c. Reference numeral 5a denotes a subprogram memory (ROM), which stores a subprogram SP describing processing related to data writing or data reading with respect to the external memory 3. Reference numeral 5b denotes an external memory interface that exchanges data between the external memory 3 and the external memory control unit 5c. The external memory control unit 5c reads the corresponding subprogram SP from the subprogram memory 5a based on the write request Wreq or the read request Rreq to the arithmetic processing control unit 4e described above, and via the external memory interface 5b according to the program SP. The external memory 3 is accessed.
[0019]
(4) Relationship between Main Program MP and Subprogram SP Next, referring to FIG. 2, the main program MP executed by the first processing unit 4 (arithmetic processing control unit 4e) and the second processing unit 5 and the relationship with the subprogram SP executed by the external memory control unit 5c will be described.
[0020]
First, the data written in the work memory 4d by the arithmetic processing control unit 4e in accordance with the main program MP is written in the external memory 3 by the external memory control unit 5c in accordance with the subprogram SP immediately after the writing.
Further, the data read out from the work memory 4d by the arithmetic processing control unit 4e according to the main program MP is read out from the external memory 3 by the external memory control unit 5c according to the subprogram SP immediately before the reading.
[0021]
Therefore, for example, when used as a sound source of an electronic musical instrument, the operation of the first processing unit 4 is synchronized with a time slot fixed at a predetermined sampling rate, so that as shown in FIG. 2, the main program counter MPC Although the address value changes linearly, the stepping speed of the sub program counter sPC changes according to the degree to which the arithmetic processing control unit 4e occupies the work memory 4d. That is, the access to the external memory 3 by the subprogram SP is accompanied by a delay of at least one sampling period.
[0022]
For example, in the external memory control unit 5c, an instruction set of subprogram A: WRD M; (external memory write instruction by offset address M) and an instruction set of B: RED N; (external memory read instruction by offset address N) Is executed so that there is a delay of M−N + 1 (M> N) between the address A and the address B.
[0023]
The subprogram counter sPC has a stepping speed that changes according to the degree to which the arithmetic processing control unit 4e occupies the work memory 4d. Therefore, the execution schedule of the subprogram SP is always within the shaded area shown in FIG. There is a need.
When the address value of the sub program counter sPC deviates from the hatched area and intersects with the address value of the main program counter PC, the execution schedule of the main program MP and that of the sub program SP interfere (compete). The signal generated by one processing unit 4 becomes discontinuous, and this becomes a noise factor at the time of waveform generation.
[0024]
That is, as in the example illustrated in FIG. 3, if the use frequency of the work memory 4d by the main program MP is low, the execution schedule of the subprogram SP is relatively advanced, and the execution schedules of both programs may cross each other. . In such a case, it is necessary that the main program MP and the subprogram SP do not conflict with each other in execution schedules.
[0025]
For this reason, in the present embodiment, a schedule adjustment circuit 4e-1 is provided in the arithmetic processing control unit 4e, and the execution schedule of the subprogram SP is started with a certain delay from the execution schedule of the main program MP by the circuit 4e-1. I have to.
Specifically, the sub program counter SPC is incremented from the time when a predetermined offset is added to the address value of the main program counter MPC . The offset amount is determined in consideration of the processing contents of the main program MP and the access time of the external memory 3. Hereinafter, the configuration of the schedule adjustment circuit 4e-1 will be described.
[0026]
(5) Configuration of Schedule Adjustment Circuit 4e-1 FIG. 4 is a block diagram showing the configuration of the schedule adjustment circuit 4e-1. In this figure, 41 is a start register that temporarily stores the start address value of the subprogram counter sPC supplied from the host CPU 2 (see FIG. 1). 42, when the start address value stored in the value and the start register 41 of the main program counter MPC matches a comparator for inputting a reset signal S _R to the sub program counter SPC.
[0027]
According to such a configuration, when the address value of the main program counter MPC advanced in accordance with the clock CK matches the start address value of the sub program counter sPC, the sub program counter sPC is reset and restarted. The progress of the sub program SP can be offset with respect to the progress of the main program MP. As a result, the execution schedule of the subprogram SP can be started with a certain delay from the execution schedule of the main program MP, thereby avoiding conflict between both programs.
[0028]
Further, the schedule adjustment circuit 4e-1 having the configuration shown in FIG. 5 may be used instead of the configuration shown in FIG. In this case, further to the configuration shown in FIG. 4, the comparator 43 and the AND circuit 44 is provided, when both the address value of the main program counter MPC and subprograms counter sPC matches by the comparator 43, the enable signal of the AND circuit 44 E _N Is set to “L” to temporarily stop the advancement of the subprogram counter sPC.
[0029]
That is, as shown in FIG. 6, when the value of the sub program counter sPC approaches the main program MPC, the step of the sub program counter sPC is temporarily stopped, and both the sub program SP and the main program MP are stopped. Stop progress from competing.
In the case of the schedule adjustment circuit 4e-1 shown in FIG. 5, even if the offset stored in the start register 41 (start value of the sub program counter sPC) is set to a sufficiently small value, the conflict between both programs is avoided. To get.
[0030]
B. Next, the operation of the embodiment having the above-described configuration will be described with reference to FIGS. Here, a data read process for reading data from the external memory 3 and a data write process for writing data to the external memory 3 will be particularly referred to.
[0031]
(1) Data Read Process In this process, as shown in FIG. 7, when the value of the sub program counter sPC is “n”, a sub program SP for reading data from the external memory 3 is first read from the sub program memory 5a. It is assumed that the data is read and loaded into the external memory control unit 5c. Then, when the value of the sub program counter sPC is “n + 1”, the external memory control unit 5 c calculates the read address of the external memory 3 after decoding the contents of the sub program SP.
[0032]
When the read address of the external memory 3 is thus determined, the external memory control unit 5c accesses the external memory 3. In this case, a memory access period MAD for two clock cycles is required.
During this period MAD, when the read request Rreq is set to “active” for the arithmetic processing control unit 4e, the external memory control unit 5c sets the data read from the external memory 3 in the transfer register, and then accepts it. Wait.
[0033]
Subsequently, when the arithmetic processing control unit 4e sets the accept Accept to “active” and notifies the external memory control unit 5c that the preparation for acceptance is complete, the external memory control unit 5c causes the external memory 3 set in the transfer register to be set. The read data from is transferred to the arithmetic processing control unit 4e side.
Thus, the arithmetic processing control unit 4e stores the transferred read data from the external memory 3 in the work memory 4d. That is, when viewed from the arithmetic processing control unit 4e side, the external memory 3 can be read as if it were an internal memory.
[0034]
(2) Data Write Process On the other hand, in the data write process, as shown in FIG. 8, when the value of the sub program counter sPC is “n”, a sub program SP for writing data to the external memory 3 is displayed as the sub program memory 5a. Is read from and loaded into the external memory control unit 5c.
Then, when the sub program counter sPC is “n + 1”, the external memory control unit 5 c decodes the content of the sub program SP and calculates the write address of the external memory 3.
[0035]
When the write request Wreq of “active” is supplied to the arithmetic processing control unit 4e while the write address for the external memory 3 is being calculated, the external memory control unit 5c waits for an acceptance Accept.
Then, when the “Accept” accept Accept is given from the arithmetic processing control unit 4e, the external memory control unit 5c temporarily stores the data transferred from the work memory 4d in the transfer register, and then calculates the calculated write The external memory 3 is accessed according to the address, and the data stored in the transfer register is written.
[0036]
Thus, according to the present embodiment, in the second processing unit 5, both the data read and data write processes are time slots different from the time slot on the first processing unit 4 side (arithmetic processing control unit 4e). Since the first processing unit 4 processes the operation of the main program MP in preference to the operation of the subprogram SP, the second processing unit 5 is viewed from the first processing unit 4. Since the external memory 3 including the memory can be regarded as a part of the internal memory, the dead time for accessing the external memory 3 is omitted, and the processing speed of the entire apparatus is improved.
[0037]
In the embodiment described above, an example in which only the external memory 3 is accessed has been described. However, the present invention is not limited to this, and the same effect can be obtained even when a plurality of external memories are provided. That is, when viewed from the first processing unit 4 side, even when there are a plurality of external memories, the second processing unit 5 side handles both data read and data write processes, so that it can be handled as one internal memory. It has become.
[0038]
【The invention's effect】
According to the present invention, in synchronization with a time slot in which the first processing means does not occupy the internal storage means, the data read from the external storage means by the second processing means is written to the internal storage means, or the internal storage Since the data read from the means is written to the external storage means, the external storage means can be regarded as a part of the internal storage means when viewed from the first processing means. For this reason, the dead time when accessing the external storage means can be omitted, and the processing speed of the entire apparatus can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment according to the present invention.
FIG. 2 shows a relationship between a main program MP executed by the first processing unit 4 (arithmetic processing control unit 4e) and a subprogram SP executed by the second processing unit 5 (external memory control unit 5c). It is a figure for demonstrating.
FIG. 3 is a diagram exemplifying a case where an execution schedule of a main program MP interferes with that of a sub program SP.
FIG. 4 is a block diagram showing a configuration of a schedule adjustment circuit 4e-1.
FIG. 5 is a block diagram showing another configuration of the schedule adjustment circuit 4e-1.
6 is a diagram for explaining an operation example of a schedule adjustment circuit 4e-1 configured as shown in FIG. 5; FIG.
FIG. 7 is a timing chart for explaining a data read process according to the embodiment.
FIG. 8 is a timing chart for explaining a data write process according to an embodiment.
FIG. 9 is a timing chart for explaining a conventional example.
FIG. 10 is a timing chart for explaining a conventional example.
[Explanation of symbols]
1 Signal processor 2 Host CPU
3 External memory (external storage means)
4 1st process part (1st process means)
4a main program memory 4b CPU interface 4c arithmetic unit 4d work memory (internal storage means)
4e Arithmetic processing control unit 5 Second processing unit (second processing means)
5a Subprogram memory 5b External memory interface 5c External memory controller

Claims (2)

Has an internal storage means provided in the apparatus, against the internal storage unit, the first signal processing that proceeds in synchronization with the predetermined sampling rate, a first process for performing at least one of reading and writing data Means,
By the second signal processing that proceeds at the timing between the first signal processing, an access request to the internal storage means is generated for the first processing means, and the first request is made in response to the access request. In accordance with the access permission generated from the processing means, the data read from the external storage means provided outside the apparatus is written to the internal storage means, and the data read from the internal storage means is written to the external storage means Second processing means for performing at least one of writing ;
A processing schedule for avoiding competition between the first signal processing and the second signal processing by starting the second signal processing from the time when a predetermined offset is added to the start timing of the first signal processing. Adjusting means;
A signal processing apparatus comprising: The processing schedule adjustment means starts the second signal processing from a time point when a predetermined offset is added to the start timing of the first signal processing, while the second signal processing is changed to the first signal processing. 2. The signal processing apparatus according to claim 1, wherein when the contention occurs, the progress of the second signal processing is temporarily stopped .

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