JP3623756B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an EEPROM (Electrically Erasable and Programmable Read Only Memory) which is a memory capable of electrically rewriting data.
[0002]
[Prior art]
In recent years, nonvolatile semiconductor memory devices, particularly flash memories, have been used in various fields because data can be electrically rewritten and data can be retained even when the power is turned off. It is used for data storage in portable terminals such as mobile phones, digital cameras, and silicon audio players. In addition, a flash memory is embedded as a rewritable program storage area in a system LSI such as a microcomputer, and the development period of a set device is shortened. This flash memory is strongly required to realize a high-speed and low power consumption read operation.
[0003]
FIG. 10 shows the distribution of the threshold voltage Vth in the flash memory and the state of the selected word line voltage Vcg during the read operation. In the program operation, the threshold voltage is set to a high state by injecting electrons into the floating gate of the memory cell by CHE (Channel Hot Electron) injection or FN (Fowler Nordheim) tunnel current (hereinafter, in this state). Memory cells are called program cells). In the erase operation, the threshold voltage is set to a low state by drawing out electrons in the floating gate by an FN (Fowler Nordheim) tunnel current (hereinafter, the memory cell in this state is referred to as an erase cell).
[0004]
In the read operation, the bit line connected to the drain of the memory cell to be read is precharged to a predetermined voltage Vpre, and after completion of the precharge, the positive voltage Vcgh is applied to the word line connected to the gate. To the selected state. FIG. 11 shows a change in the bit line potential after the memory cell is selected. When the memory cell is a program cell, the memory cell current does not flow, so the bit line maintains the precharge voltage Vpre. On the other hand, in the case of an erase cell, since a current flows through the memory cell, the bit line potential is lowered from the precharge voltage Vpre with time. Thus, since the bit line potential differs between the case where the memory cell is a program cell and the erase cell, the voltage of the reference bit line to be compared with this bit line potential is set to an intermediate level between the two, and the difference between both bit lines is set. Data of the memory cell can be determined by amplifying the voltage with a differential sense amplifier. Here, the differential sense amplifier needs to be activated when the difference voltage between the two bit lines becomes sufficiently large in order to output stable and correct data.
[0005]
In order to realize high-speed reading by the reading operation of the flash memory, it is necessary to increase the bit line potential difference between the program cell and the erase cell in a short time and start the sense amplifier in a fast time. For this purpose, it is necessary to increase the memory cell current when the erase cell is activated. Conventionally, as a method of increasing the memory cell current, a word line boosting method in which the voltage of a selected word line is boosted to a higher voltage is generally used.
[0006]
[Problems to be solved by the invention]
However, the word line boosting method that has been performed to realize high-speed reading in the conventional nonvolatile semiconductor memory device has the following problems.
[0007]
First, since it is necessary to apply a high boosted voltage to the word line, there is a problem that the power consumption increases in the booster circuit that generates the high boosted voltage, and the power consumption of the entire chip increases.
[0008]
Second, since the program cell needs to be in the off state even when a high word line boosted voltage is applied, the threshold voltage must be set to a high value. For this reason, there is a problem that the writing time of the memory cell increases. Further, when the threshold voltage of the program cell is high, the electric field applied to the floating gate is increased, so that there is a problem that the retention characteristics of electrons in the floating gate are lowered when the power is turned off.
[0009]
The present invention solves the above-mentioned conventional problems, and can perform a high-speed and low-power consumption read operation, and can freely switch each block area constituting the memory cell array to a high-speed read area, a low-power consumption read area, or the like. An object of the present invention is to provide a non-volatile semiconductor memory device that can be made available.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, in the first nonvolatile semiconductor memory device according to the present invention, the control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, Memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of bit lines, and a plurality of memory cells in which memory cell units for storing data are connected to the same bit line and connected to different word lines And a word line selection unit that selects a plurality of word lines connected to the memory cell unit and selects a plurality of memory cells constituting the memory cell unit during a data read operation. WhenThe dummy cell control gate is connected to the dummy word line, the drain is connected to the dummy bit line, the source is connected to the dummy source line, and the dummy cell unit that generates the reference voltage on the dummy bit line is connected to the same dummy bit line In addition, a dummy cell array composed of a plurality of dummy cells connected to different dummy word lines and a plurality of dummy word lines connected to the dummy cell unit are selected at the time of data read operation to activate the plurality of dummy cells. Dummy word line selection sectionIt is characterized by comprising.
[0011]
According to this configuration, since the read current is the sum of the plurality of memory cell currents, a large read current can be obtained even with the same word line boosted voltage as in the past, and high-speed reading can be realized. Further, by dividing the memory cell unit into a plurality of memory cells having a small transistor size, that is, having a small gate load capacity, and simultaneously selecting the memory cells, it becomes easy to realize a high selection time of the memory cell unit portion. On the other hand, even if the boosted voltage of the word line is lowered, a read current equivalent to or higher than that of the conventional one can be obtained, so that a low power consumption read operation can be realized without reducing the access speed. Further, this high-speed and low-power consumption reading can be performed by changing only the peripheral circuits of the decoder unit and the control unit without changing the existing memory cell array.In addition, the dummy cell unit is divided into a plurality of dummy cells having a small transistor size, that is, a small gate load capacity, and simultaneously activated, so that the activation time of the dummy cell unit can be increased and an accurate reference can be realized. A voltage can be generated.
[0016]
In order to achieve the above object, in the second nonvolatile semiconductor memory device according to the present invention, the control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, Memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of bit lines, and a plurality of memory cells in which memory cell units for storing data are connected to the same bit line and connected to different word lines And a word line selection unit that selects a plurality of word lines connected to the memory cell unit and selects a plurality of memory cells constituting the memory cell unit during a data read operation. AndA memory cell array is a flash memory having a plurality of erase blocks that can perform an erase operation collectively in units of a plurality of memory cells, and each of a plurality of memory cells constituting a memory cell unit belongs to a different erase block. The word line selection unit performs multiple selection of the corresponding word line during the data read operation based on the control signal, and switches between single selection and multiple selection of the word line during the program / program verify and erase verify operations. During erase operation, single erase and multiple erase of the corresponding erase block are switched, and the number of target memory cells for program / program verify and erase / erase verify operations to the plurality of memory cells constituting the memory cell unit Single or multiple selection of word lines, and erasing Switching on the basis of a single erase or multiple erase locksCharacterized by.
[0017]
According to this configuration, since the plurality of memory cells constituting the memory cell unit belong to different erase blocks, only the program, program verify, and erase verify operations can be performed even in a flash memory capable of batch erase for each block. In addition, the erase operation can be performed for each memory cell constituting the memory cell unit, and the write threshold voltage distribution and the erase threshold voltage distribution of each memory cell can be set with high accuracy. It becomes possible.
[0018]
In order to achieve the above object, in the third nonvolatile semiconductor memory device according to the present invention, the control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, Memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of bit lines, and a plurality of memory cells in which memory cell units for storing data are connected to the same bit line and connected to different word lines And a word line selection unit that selects a plurality of word lines connected to the memory cell unit and selects a plurality of memory cells constituting the memory cell unit during a data read operation. When,Sense unit for determining read data from memory cell arrayAndA first read mode in which a first boosted voltage is applied to the word line to select multiple memory cells, and the activation timing of the sense unit is set to a first predetermined value; Second read mode in which a second boosted voltage lower than the boosted voltage is applied to select multiple memory cells, and the activation timing of the sense unit is set to a second predetermined value that is slower than the first predetermined value In the semiconductor manufacturing process or the inspection process, either the first reading mode or the second reading mode can be used, or any reading mode can be freely selected when the apparatus is used. aboutCharacterized by.
[0019]
According to this configuration, high-speed reading can be realized by using the first read mode, and low-power consumption reading can be realized by using the second read mode. Two different read operations called read modes can be realized.
[0020]
In this case, the memory cell takes an erase state having a low threshold voltage and a program state having a threshold voltage higher than the erase state, and the first nonvolatile semiconductor memory device is used in the first read mode. Read with the first boost voltage used in the first program verify mode and the second read mode for determining the first write threshold voltage necessary for determining the read data with the first boost voltage after programming A second program verify mode for determining, after programming, a second write threshold voltage lower than the first write threshold voltage necessary for determining data, and is used during a data read operation It is preferable to change the threshold voltage for writing to the memory cell in accordance with the boosted voltage of the word line.
[0021]
According to this configuration, if the second program verify mode is used, the write threshold voltage to the memory cell block read in the second read mode can be set low, and the program time in this block can be increased. It becomes possible to do. In addition, by setting the write threshold voltage low, the electric field applied to the floating gate of the memory cell is reduced, improving the retention characteristics of electrons in the floating gate when the power is turned off, and improving device reliability. Can be achieved.
[0022]
In this case, the memory cell array preferably includes a block that can be read in the first read mode and a block that can be read in the second read mode.
[0023]
According to this configuration, a single flash memory can have both a high-speed read area and a low power consumption read area.
[0024]
To achieve the above object, according to the present invention.4thIn the nonvolatile semiconductor memory device, the control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, and the memory cell intersects the plurality of word lines and the plurality of bit lines. A plurality of memories arranged in a matrix at a location where a memory cell unit storing data is connected to the same bit line and to a different word line, and a first block composed of a single memory cell When a memory cell unit having one or more second blocks each composed of cells and a memory cell unit belonging to the first block is selected based on an input address during a data read operation, the corresponding word line When a memory cell unit belonging to the second block is selected, the selection is switched to multiple selection of the corresponding word line. A word line selection unit, a sense unit for determining read data from the memory cell array, and a memory cell unit by controlling the word line selection unit during a data read operation so that the corresponding word line is single-selected or multiple-selected. The single or a plurality of memory cells constituting the memory cell are set in a selected state, and the sense unit is controlled so that the activation timing of the sense unit during the read operation of the second block is faster than that during the read operation of the first block. And a control unit.
[0025]
According to this configuration, the first block is a memory cell block area equivalent to the conventional one, and high-speed and low-power consumption reading cannot be realized. However, since the memory cell unit is configured by one memory cell, the first block has a large capacity. The memory cell area can be configured, and the second block can realize the high-speed and low-power consumption read operation as described above. It is possible to have both areas where priority is given.
[0026]
To achieve the above object, according to the present invention.5thIn the nonvolatile semiconductor memory device, the control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, and the memory cell intersects the plurality of word lines and the plurality of bit lines. A plurality of memories arranged in a matrix at a location where a memory cell unit storing data is connected to the same bit line and to a different word line, and a first block composed of a single memory cell A memory cell array provided with one or more blocks that can take any one of the second blocks composed of cells, and information on whether each block is the first block or the second block is stored. The memory cell of the selected memory cell unit to be read is a single memory based on the data storage unit to be read and the information and input address of the data storage unit. A determination unit that determines whether the cell is a plurality of memory cells, and based on the determination result of the determination unit, the word line of the selected memory cell unit is switched to single selection of the corresponding word line for the first block; For the second block, a word line selection unit that switches to multiple selection of the corresponding word line, a sense unit that determines read data from the memory cell array, and a data read operation based on the determination result of the determination unit, The word line selection unit is controlled to select a single or multiple selection of the word line to select one or more memory cells constituting the memory cell unit, and the sense unit is controlled to control the second block. The timing of starting the sense unit during the read operation is faster than that during the read operation of the first block, and the information stored in the data storage unit is changed. Characterized by comprising a control unit.
[0027]
According to this configuration, since the number of memory cells constituting the memory cell unit in each block of the memory cell array is determined based on the data stored in the data storage unit (register), the data in the data storage unit can be changed. Thus, the configuration of the memory cell array can be freely set and used as a memory capacity priority area, a high-speed read area, and a low power consumption read area.
[0028]
4th and 5thIn the nonvolatile semiconductor memory device, a dummy cell unit is connected to a dummy word line, a drain is connected to a dummy bit line, a source is connected to a dummy source line, and a dummy cell unit that generates a reference voltage is provided on the dummy bit line. A dummy cell array composed of a plurality of dummy cells connected to the same dummy bit line and connected to different dummy word lines, and a single dummy word line when selecting the first block during the data read operation A single dummy cell is selected by selection, and when selecting the second block, a plurality of dummy cells are selected by selecting a plurality of dummy word lines, and the dummy word that activates a single dummy cell or a plurality of dummy cells is selected. It is preferable to include a line selection unit.
[0029]
According to this configuration, as described above, the activation time of the dummy cell unit portion can be increased, and an accurate reference voltage can be generated. Further, since the load capacity per dummy word line at the time of single selection and multiple selection of dummy word lines does not change, the difference in dummy cell activation time between single selection and multiple selection of dummy word lines is eliminated. It becomes possible.
[0030]
In this case, the word line selection unit switches between single selection and multiple selection of the word line based on the control signal from the control unit at the time of program / program verify and erase / erase verify operations for the second block. Accordingly, it is preferable to switch the number of target memory cells for program / program verify and erase / erase verify operations to a plurality of memory cells constituting the memory cell unit.
[0031]
According to this configuration, since the program / program verify and erase / erase verify operations can be performed for each of the plurality of memory cells constituting the memory cell unit, the write threshold value of each memory cell can be set. The value voltage distribution and the erase threshold voltage distribution can be set with high accuracy.
[0032]
The memory cell array is a flash memory having a plurality of erase blocks that can collectively perform an erase operation in units of a plurality of memory cells, and each of the plurality of memory cells constituting the memory cell unit belonging to the second block is Each word line selection unit belongs to a different erase block, and the word line selection unit performs single selection or multiple selection of the corresponding word line during the data read operation based on the control signal from the control unit, and the program in the second block・ Switching between single selection and multiple selection of word lines during program verify and erase verify operations, and switching between single erase and multiple erase of the corresponding erase block during erase operations Program / verify and erase / erase Single or select multiple selection of the word line number target memory cell's verify operation, and it is preferable to switch on the basis of a single erase or multiple erase operation.
[0033]
According to this configuration, since the plurality of memory cells constituting the memory cell unit belong to different erase blocks, only the program, program verify, and erase verify operations can be performed even in a flash memory capable of batch erase for each block. In addition, the erase operation can be performed for each memory cell constituting the memory cell unit, and the write threshold voltage distribution and the erase threshold voltage distribution of each memory cell can be set with high accuracy. It becomes possible.
[0034]
4th and 5thThe nonvolatile semiconductor memory device includes a first read mode in which a first boosted voltage is applied to the word line to select multiple memory cells, and the activation timing of the sense unit is set to a first predetermined value; A second boosted voltage lower than the first boosted voltage is applied to the word line to select multiple memory cells, and the activation timing of the sense unit is set to a second predetermined value that is later than the first predetermined value. A second read mode, the first block performs a read operation in the first read mode, and the second block has a first read mode during a semiconductor manufacturing process or an inspection process. It is preferable that either the reading mode or the second reading mode can be used, or any of the reading modes can be freely selected when the apparatus is used.
[0035]
According to this configuration, high-speed reading can be realized by using the first reading mode, and low power consumption reading can be realized by using the second reading mode. Different read operations such as power consumption can be realized.
[0036]
In this case, the memory cell takes an erase state having a low threshold voltage and a program state having a threshold voltage higher than the erase state,4th and 5thThe non-volatile semiconductor memory device includes a first program verify mode for determining a first write threshold voltage necessary for determining read data with a first boosted voltage used in the first read mode after programming. The second write threshold voltage lower than the first write threshold voltage necessary for determining the read data with the second boosted voltage used in the second read mode is determined after programming. It is preferable to change the threshold voltage for writing to the memory cell in accordance with the boosted voltage of the word line used during the data read operation.
[0037]
According to this configuration, if the second program verify mode is used, the write threshold voltage to the memory cell block read in the second read mode can be set low. It is possible to increase the program time and improve the reliability of the device.
[0038]
The second block preferably includes a block that can be read in the first read mode and a block that can be read in the second read mode.
[0039]
According to this configuration, it is possible to have a normal memory capacity priority area, a high-speed read area, and a low power consumption read area in a single flash memory.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0041]
(First embodiment)
FIG. 1 is a configuration diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, a memory cell array 50 is a NOR flash memory, and a memory cell unit for storing data is composed of two memory cells connected to the same bit line and connected to different word lines. Features. In the following description, the memory cell unit is described as being composed of two memory cells, but may be composed of three or more memory cells.
[0042]
More specifically, the memory cell unit MU111 includes M111a and M111b which are memory cells connected to the same bit line BL1 and memory cells connected to different word lines WL11a and WL11b. Similarly, the memory cell unit MU112 includes memory cells connected to the same bit line BL2 and memory cells connected to different word lines WL11a and WL11b. The memory cell is connected to the line BLk and is composed of M11ka and M11kb which are memory cells connected to different word lines WL11a and WL11b.
[0043]
The memory cell unit MU121 includes memory cells connected to the same bit line BL1 and memory cells connected to different word lines WL12a and WL12b. From the memory cells M121a and M121b, the memory cell unit MU122 includes the same bit line. From M122a and M122b which are memory cells connected to BL2 and connected to different word lines WL12a and WL12b, the memory cell unit MU12k is a memory cell connected to the same bit line BLk and different word lines. It consists of M12ka and M12kb which are memory cells connected to WL12a and WL12b. A plurality of these memory cell units are connected to form a first block (Block 1) 50a.
[0044]
Here, the source lines of the memory cells belonging to the first block 50a are all connected in common, and are connected to the source line driver 10 as the source line SL1. In the memory cell array 50, there are a total of m blocks configured as described above, from the first block 50a, the second block (Block 2) 50b,... To the m-th block (Block m) 50c. Since the source line of the memory cell is connected in common to each block, a negative high voltage is applied to all word lines and a positive high voltage is applied to the source line in the block during the erase operation. Batch erase operation can be performed.
[0045]
The input address is composed of a row address and a column address, and the row address buffer / decoder 8 drives the word line multiplexing / single selection driver 9 and the source line driver 10 in response to the input of the row address. Here, the word line multiplexing / single selection driver 9 is characterized in that a plurality of word lines are selected at a time during a read operation. This word line multiple selection operation is controlled by a control signal MULTITIWL. Thereby, two memory cells constituting the memory cell unit can be selected simultaneously.
[0046]
The column address buffer / decoder 6 drives the column selector 7 in response to the input of the column address. The column selector 7 serves to select one bit line from the k bit lines from the bit line BL1 to the bit line BLk and connect it to the first input terminal 3 of the sense amplifier (SA) 2. More specifically, the column gate Y1 selects the bit line BL1 by the column gate signal YG1, the column gate Y2 selects the bit line BL2 by the column gate signal YG2, and the column gate Yk is selected by the column gate signal YGk. The line BLk is selected. The column selector 7 also serves to connect the dummy bit line DBL to the second input terminal 4 of the sense amplifier 2, and the column gate YD connects the dummy bit line DBL to the sense amplifier 2 by the column gate signal YGD. .
[0047]
The dummy word line multiplexing / single selection driver 11 is characterized in that the dummy word lines DWLa and DWLb are simultaneously selected at the time of a read operation. This dummy word line multiple selection operation is controlled by a control signal MULTIWIL. The dummy cell array 12 is connected to the dummy bit line DBL and serves to generate a reference voltage for the dummy bit line DBL to be compared with the voltage of the bit line to which the memory cell is connected during a read operation. Here, the dummy cell array 12 is composed of two dummy cells DCa and DCb. During the read operation, the dummy word lines DWLa and DWLb are multiple-selected by the dummy word line multiplexing / single selection driver 11 so that the dummy cell DCa. And DCb are activated simultaneously. Here, the transistor sizes of the dummy cells DCa and DCb are set so as to be half the amount of current that flows when the memory cell is an erase cell, and the transistor sizes of the dummy cells DCa and DCb are exactly the same. Set to size.
[0048]
The sense amplifier 2 is a differential amplifier circuit that compares the voltage at the first input terminal 3 and the voltage at the second input terminal 4, and the activation timing of the sense amplifier is controlled by the control signal SAE. The latch circuit 1 is a circuit that latches the output data of the sense amplifier 2, and the latch timing of the output data is controlled by the control signal DL. The precharge circuit 5 is a circuit for precharging the bit line and the dummy bit line selected by the column selector 7 to a predetermined voltage Vpre, and the precharge operation is controlled by the control signal NPRE. Further, an equalize operation between the selected bit line and the dummy bit line is also performed. The reset transistor 13 serves to reset the voltages of all bit lines and dummy bit lines to the ground potential, and the activation state of the reset transistor 13 is controlled by the control signal BLRST.
[0049]
The control circuit 14 plays a role of controlling various operations such as a read operation, a program operation, and an erase operation by inputting the mode signal MODE and the trigger signal NTRG. Specifically, the control signals DL, SAE, NPRE, BLRST, and MULTIWIL described above are control signals output from the control circuit 14. The control circuit 14 also controls the operation of the booster circuit 15. Further, although not shown as a control signal, the control circuit 14 also controls word line selection timing, column selector 7 opening / closing timing, and the like.
[0050]
The booster circuit 15 is a circuit that generates a voltage necessary for a read operation, a program operation, and an erase operation, and the output voltage Vcg is input to the word line multiplex / single selection driver 9 from which a necessary word line is necessary. Voltage is supplied. The output voltage Vdcg is input to the dummy word line multiplex / single selection driver 11, from which a necessary voltage is supplied to the selected dummy word line. The output voltage Vsl is input to the source line driver 10, from which a necessary voltage is supplied to the selected source line. These output voltages are controlled by the control circuit 14.
[0051]
Hereinafter, a read operation of the nonvolatile semiconductor memory device configured as described above will be described in detail. The read operation in the present embodiment realizes a first read mode in which a read operation can be performed at a higher speed than the conventional one, and a second read mode in which a low power consumption read can be performed with an access speed equal to or higher than that of the conventional one. be able to.
[0052]
First, the first reading mode that can realize high-speed reading will be described in detail. FIG. 5A is a timing chart during the first read mode operation. Here, a case where data is read from the memory cell unit MU111 including the memory cells M111a and M111b will be described.
[0053]
Prior to time T0, all the column gates Y1 to YD are closed (the column gate signals YG1 to YGD are at the ground potential level), and the BLRST signal is at the logic “H” level, so that the reset transistor 13 is activated. The voltages of all the bit lines are at the ground potential. All word lines and all source lines are also at the ground potential, and all terminals of the memory cells are fixed at the ground potential.
[0054]
Here, the read operation is started by inputting the read address and setting the NTRG signal to the logic “L” level at time T0. At this timing, the BLRST signal becomes a logic “L” level, and the reset transistor 13 is inactivated. Further, the column gate signals YG1 and YGD become positive voltage levels, and the selected bit line BL1 and dummy bit line DBL are connected to the first input terminal 3 and the second input terminal 4 of the sense amplifier 2, respectively. The Further, since the NPRE signal is at the logic “L” level, the selected bit line BL 1 and dummy bit line DBL are precharged to a predetermined bit line voltage Vpre by the precharge circuit 5. Here, since the precharge circuit 5 also performs an equalizing operation between both bit lines, the bit line precharge voltages of the bit line BL1 and the dummy bit line DBL are equal to the voltage Vpre.
[0055]
When the precharge operation to the bit line is completed, a read operation is performed from time T1. At time T1, the NPRE signal becomes a logic “H” level, and the precharge operation and the equalize operation by the precharge circuit 5 are stopped. At the same time, the word lines WL11a and WL11b connected to the memory cell unit MU111 are multiple-selected, and the boosted voltage Vcgh generated by the booster circuit 15 is applied to the word lines. In addition, the dummy word lines DWLa and DWLb connected to the dummy cell array 12 are also multiple-selected. As a result, the memory cells M111a and M111b constituting the memory cell unit MU111 and the dummy cells DCa and DCb constituting the dummy cell array 12 are activated.
[0056]
Here, the activation time of the memory cell unit is relatively fast. This is because a plurality of memory cells are selected by different word lines, so that the load capacity seen from one word line is not increased at all compared to the conventional case. Therefore, the dummy cell array is also composed of a plurality of dummy cells and activated simultaneously with different dummy word lines. By doing so, the load capacity driven by one dummy word line can be reduced, so that the activation time of the dummy cell array can be increased.
[0057]
FIG. 6A shows the threshold voltage distribution of the memory cell and the state of the voltage applied to the selected word line at this time. If the memory cell unit MU111 is an erase cell, a current flows through the memory cell, so that the voltage of the bit line drops from the precharge voltage Vpre toward the ground potential. In the case of a program cell, no current flows through the memory cell, so that the voltage of the bit line maintains the precharge voltage Vpre. On the other hand, the voltage of the dummy bit line DBL drops from the precharge voltage Vpre toward the ground potential by the dummy cells DCa and DCb regardless of the state of the memory cell unit. Here, as described above, the amount of current flowing through the dummy cells DCa and DCb is set to be half the amount of current flowing when the memory cell is an erase cell, so that the dummy bit line DBL is set to the ground potential. The descending speed is slower than when the memory cell is an erase cell.
[0058]
FIG. 7 is a diagram showing potential changes of the bit lines and dummy bit lines during the read operation. FIG. 7 shows potential changes from time T1 (FIG. 5) at which the read operation starts. FIG. 7A shows the potential change of the bit line / dummy bit line of the word line single selection method when the conventional memory cell unit is composed of one memory cell (same as FIG. 11). FIG. 7B shows potential changes of the bit line / dummy bit line of the word line multiple selection method when the memory cell unit is composed of a plurality of memory cells.
[0059]
Since the potential change of the dummy bit line changes while taking the intermediate potential of the bit line potential that can be taken when the memory cell unit is a program cell and an erase cell, the voltage of the dummy bit line DBL is used as a reference voltage. The data of the memory cell can be determined by comparing the voltages with the sense amplifier 2. Here, in order for the sense amplifier 2 to correctly determine the data in the memory cell, the difference voltage between the bit line and the dummy bit line is required to be large to some extent.
[0060]
Therefore, in the word line single selection method in the case where the conventional memory cell unit is composed of one memory cell, the time for starting up the sense amplifier 2 is set at time T2a as shown in FIG. However, in the word line multiple selection method in which the memory cell unit is composed of a plurality of memory cells, since the read current is the sum of the plurality of memory cell currents, the bit line drop speed of the erase cell is increased, and FIG. ), The activation time of the sense amplifier 2 can be set quickly from the conventional T2a to T2b. Accordingly, since the activation time of the sense amplifier 2 can be set faster, it is possible to read at a higher speed than before.
[0061]
Furthermore, since the plurality of memory cells constituting the memory cell unit are connected to the same bit line, there is no increase in the bit line load capacity due to the word line multiple selection method. This is one of the factors that realizes further increase in the reading speed. That is, since the read current can be increased with the same bit line load capacitance, the increase in the read current directly increases the bit line voltage drop speed, and high-speed reading can be realized.
[0062]
Here, the activation time Tsa of the sense amplifier 2 is the time from the time T0 when the NTRG signal becomes the logic “L” level to the time T2 at which the sense amplifier 2 is activated, as described with reference to the timing chart of FIG. Yes, Tsa = T2-T0.
[0063]
After the sense amplifier 2 is activated at time T2, read data (DataOut) is determined, and the read data is determined at time T3. Here, the read data access time Tacc is the time from the time T0 when the NTRG signal becomes the logic “L” level to the time T3 when the data is determined, and Tacc = T3−T0. Since the sense amplifier activation time Tsa is increased, naturally the access time Tacc is also increased.
[0064]
Thereafter, at time T 4, the DL signal rises to a logic “H” level, and the output data of the sense amplifier 2 is latched by the latch circuit 1. At the same time, the SAE signal becomes a logic “L” level, and the operation of the sense amplifier 2 is stopped. The word lines WL11a and WL11b and the dummy word lines DWLa and DWLb are also returned to the ground potential, and the memory cells M111a and M111b and the dummy cells DCa and DCb are deactivated. The column gate signals YG1 and YGD are also returned to the ground potential, and the connection between the bit line BL1, the dummy bit line DBL and the sense amplifier 2 is cut off. Further, since the BLRST signal becomes a logic “H” level and the reset transistor 13 is activated, the voltages of all the bit lines and the dummy bit lines become the ground potential again. Thereafter, at time T5, the NTRG signal is set to a logic “H” level to complete the read operation.
[0065]
Next, the operation in the second read mode in which low power consumption reading can be realized will be described in detail. Here, a case where data is read from the memory cell unit MU111 including the memory cells M111a and M111b will be described. FIG. 5B shows a timing chart during a read operation, and FIG. 6B shows a threshold voltage distribution of a memory cell and a state of a voltage applied to a selected word line (low power consumption read mode 1). The read operation in the second read mode is almost the same as that in the first read mode, and only a portion in which the operation is different will be described here.
[0066]
In the second read mode, the control circuit 14 controls the booster circuit 15 to output Vcgl that is lower than the output voltage Vcgh in the first read mode as the output voltage Vcg. Since the booster circuit 15 only needs to output a voltage lower than that of the prior art, the power consumption of the booster circuit 15 can be reduced, thereby realizing the low power consumption operation of the entire chip.
[0067]
Since the value of the output voltage Vcg of the booster circuit is Vcgl, Vcgl, which is a voltage lower than that in the first read mode, is applied to the selected word line during the read operation. Here, the read current that flows when the memory cell unit is an erase cell is smaller than when the voltage applied to the selected word line is Vcgh. However, since the memory cell unit is composed of a plurality of memory cells, it is possible to obtain a memory cell current equivalent to or higher than that in which the conventional memory cell unit is composed of one memory cell.
[0068]
In the second read mode, when the memory cell unit is an erase cell, the speed at which the bit line voltage is lowered is slower than that in the first read mode. It is controlled so as to start at a certain start timing.
[0069]
Also, the reference voltage of the dummy bit line needs to be generated differently from that in the first read mode. Here, as shown in FIG. 5B, it is applied to the dummy word lines DWLa and DWLb. The necessary reference voltage is generated by lowering the voltage. As a result, it is possible to realize a read operation with lower power consumption than the conventional one while realizing an access speed equal to or higher than the conventional one.
[0070]
In this embodiment, the reference voltage necessary for the second read mode is generated by changing the voltage applied to the dummy word line. However, the voltages applied to the dummy word line are the same, and the dummy cells DCa and DCb are the same. A reference voltage necessary for the second read mode may be generated by separately providing a dummy cell having a transistor size different from the above and selecting a dummy word line connected to the dummy cell.
[0071]
Here, the threshold voltage of the program cell at the time of reading in the second read mode may be a threshold voltage at which the memory cell current does not flow when the selected word line application voltage Vcgl is applied. A threshold voltage lower than that in the first read mode is sufficient. FIG. 6C shows the threshold voltage distribution of the memory cell and the voltage applied to the selected word line at this time (low power consumption read mode 2). As described above, when the read operation is performed in the second read mode, the threshold voltage of the program cell can be set to a low value, so that the write time to the memory cell can be increased. In addition, by setting the threshold voltage of the program cell low, the electric field applied to the floating gate of the memory cell is reduced, which improves the retention characteristics of electrons in the floating gate when the power is turned off, and improves device reliability. It is possible to improve the performance.
[0072]
As described above, a memory cell unit for storing data is composed of memory cells connected to the same bit line and a plurality of memory cells connected to different word lines. If the line application voltage Vcgh is applied, a high-speed read operation can be realized, and if the selected word line application voltage Vcgl lower than the conventional one is applied, the access speed can be reduced while realizing an access speed equivalent to or higher than the conventional one. Read operation can be realized with power consumption.
[0073]
Next, the program operation / program verify operation will be described in detail. In the program operation, a positive high voltage is applied to the selected word line, a ground potential is applied to the source line, a positive high voltage is applied to the selected bit line, and a hot electron generated at the drain end of the memory cell is applied to the gate. A program operation is performed by a CHE (Channel Hot Electron) method in which a high voltage is injected into the floating gate. After the program ends, a program verify operation is performed to detect the threshold voltage of the memory cell and determine whether the threshold voltage is sufficient. Although not shown in FIG. 1, these operations are performed by a program circuit and a verify circuit. Here, the program operation and program verify operation for the memory cell unit MU111 including the memory cells M111a and M111b will be described in detail.
[0074]
The program operation according to the present embodiment can perform the first and second program operations depending on the difference in the number of memory cells to be operated. The program verify operation includes the number of memory cells to be operated and the determination threshold voltage. From the difference, the first to fourth program verify operations can be performed.
[0075]
FIG. 8A shows a voltage application state in the selected word lines WL11a and WL11b during the first program operation and the first program verify operation. By setting the first program mode Program1 and setting the NTRG signal to a logic “L” level at time T10, the first program operation is started. The first program mode is a mode in which a program operation is simultaneously performed on a plurality of memory cells constituting the memory cell unit. Therefore, the two selected word lines WL11a and WL11b rise from the ground potential to the positive high voltage Vpp necessary for the program operation at time T10. A program operation is performed for a predetermined time, and the NTRG signal is set to a logic “H” level at time T11 to stop the program operation, and the selected word lines WL11a and WL11b are returned to the ground potential again.
[0076]
Next, the first program verify operation is started by setting the first program verify mode Program Verify1 at time T12 and setting the NTRG signal to the logic “L” level at time T13. The first program verify mode is a mode in which a program verify operation is simultaneously performed on a plurality of memory cells constituting the memory cell unit. Therefore, the two selected word lines WL11a and WL11b rise from the ground potential to the positive voltage Vpvh necessary for the program verify operation at time T13. Further, in the first program verify mode, as shown in FIG. 6A, it is determined that the threshold voltage of the program cell is a threshold voltage necessary for realizing the first high-speed read operation. It is a mode to do. Here, a positive voltage Vpvh is applied to the two selected word lines WL11a and WL11b, and it is detected that the current value flowing at this time is below a certain value, and the verify operation of the program cell is performed. A program verify operation is performed for a predetermined time, and the NTRG signal is set to a logic “H” level at time T14 to complete the program verify operation and return the selected word line to the ground potential again.
[0077]
FIG. 8B shows a voltage application state in the selected word lines WL11a and WL11b during the second program operation and the second program verify operation. The second program operation is started by setting the second program mode Program2 and setting the NTRG signal to the logic “L” level at time T10. The second program mode is a mode in which a program operation is performed only on one memory cell among a plurality of memory cells constituting the memory cell unit. FIG. 8B shows a state when the program operation is performed only on the memory cell M111a, and only the selected word line WL11a has a positive high voltage necessary for the program operation from the ground potential at time T10. The voltage rises to Vpp, and the program operation to the memory cell M111a is performed. At this time, the word line WL11b remains at the ground potential, and the program operation to the memory cell M111b is not performed. A program operation is performed for a predetermined time, and the NTRG signal is set to a logic “H” level at time T11, whereby the program operation is stopped and the selected word line WL11a is returned to the ground potential again.
[0078]
Next, the second program verify operation is started by setting the second program verify mode Program Verify2 at time T12 and setting the NTRG signal to the logic “L” level at time T13. The second program verify mode is a mode in which the program verify operation is performed only on one memory cell among the plurality of memory cells constituting the memory cell unit. FIG. 8B shows a state when the program verify operation is performed only on the memory cell M111a. Only the selected word line WL11a is positive at the time T13 required for the program verify operation from the ground potential. The voltage rises to the voltage Vpvh, and the program verify operation for the memory cell M111a is performed. At this time, the word line WL11b remains at the ground potential, and the program verify operation for the memory cell M111b is not performed. Further, in the second program verify mode, as in the first program verify mode, it is determined that the threshold voltage of the program cell is a threshold voltage necessary for realizing the first high-speed read operation. It is a mode to do. A program verify operation is performed for a predetermined time, and the NTRG signal is set to a logic “H” level at time T14, whereby the program verify operation is completed and the selected word line WL11a is returned to the ground potential again.
[0079]
Here, in the second program mode and the second program verify mode, the number of target memory cells needs to be specified not for each memory cell unit but for individual memory cells. More bits are required than are necessary. In this embodiment, since the memory cell unit is composed of two memory cells, only one bit is required to specify each memory cell, compared to the number of address bits necessary for the read operation.
[0080]
As described above, in the first program mode and the first program verify mode, a program and program verify operation can be performed simultaneously on a plurality of memory cells constituting the memory cell unit. Verify operation can be realized. On the other hand, in the second program mode and the second program verify mode, the program and program verify operations can be performed on the individual memory cells. Therefore, the threshold voltage in each memory cell is accurately set. It becomes possible.
[0081]
By providing these modes, for example, in the initial stage of the program operation, the program operation is performed at high speed in the first program mode and the first program verify mode, and the threshold voltage of the memory cell is set to the target threshold value. When the voltage approaches, the program operation is performed on each memory cell using the second program mode and the second program verify mode, and each memory cell is set to an accurate threshold voltage. It is possible to perform a program operation such as
[0082]
FIG. 8C shows a voltage application state in the selected word lines WL11a and WL11b during the first program operation and the third program verify operation. The first program operation is the same as that described above, and the program operation is simultaneously performed on a plurality of memory cells constituting the memory cell unit.
[0083]
Next, the program verify operation is started third by setting the third program verify mode Program Verify3 at time T12 and setting the NTRG signal to the logic “L” level at time T13. The third program verify mode is the same as the first program verify mode, in which the program verify operation is simultaneously performed on a plurality of memory cells constituting the memory cell unit. Value voltage is different. In the third program verify mode, as shown in FIG. 6C, it is determined that the threshold voltage of the program cell is a threshold voltage necessary for realizing the second low power consumption read operation. It is a mode to do. Here, Vpvl, which is lower than the voltage Vpvh applied to the word line during the first program verify operation, is applied to the two selected word lines WL11a and WL11b, and the value of the current flowing at this time is below a certain value And verify operation of the program cell.
[0084]
FIG. 8D shows a voltage application state in the selected word lines WL11a and WL11b during the second program operation and the fourth program verify operation. The second program operation is the same as that described above, and the program operation is performed on the individual memory cells constituting the memory cell unit.
[0085]
Next, the fourth program verify operation is started by setting the fourth program verify mode Program Verify4 at time T12 and setting the NTRG signal to the logic “L” level at time T13. The fourth program verify mode is the same as the second program verify mode, and performs a program verify operation on each memory cell constituting the memory cell unit. Further, the fourth program verify mode is the same as the third program verify mode. In this mode, the threshold voltage of the program cell is determined to be a threshold voltage necessary for realizing the second low power consumption read operation.
[0086]
As described above, by providing the third and fourth program verify modes, it is determined that the threshold voltage of the program cell is a threshold voltage necessary for realizing the second low power consumption read mode. Since the program operation can be terminated at a threshold voltage lower than the threshold voltage determined by the first and second program verify operations, as described above, a high-speed program operation can be realized. In addition, the reliability of the device can be improved.
[0087]
The operations of the first and second read modes, the first and second program modes, and the first to fourth program verify modes have been described above. By providing these modes, one flash memory is provided. In the chip, flash memories with various performances can be realized.
[0088]
For example, all the memory cell units are programmed using the first and second program verify modes, and read in the first high-speed read mode during the read operation, so that a flash memory that realizes a high-speed read operation is obtained ( FIG. 6 (a) state). Further, by reading in the second low power consumption read mode, the flash memory can achieve a low power consumption read operation although the access speed is comparable to the conventional one (state of FIG. 6B). That is, if the program operation is performed using the first and second program verify modes, the first or second read mode is selected at the time of the read operation, so that high-speed read or low power consumption read can be freely performed. Can be realized. Further, if the read operation is performed only by the second low power consumption read operation, the program time can be increased by performing the program operation using the third and fourth program verify modes. (State of FIG. 6C). Furthermore, by mixing the area read in the first high-speed read mode and the area read in the second low power consumption read mode in one flash memory, it is possible to have areas with different performance for each block.
[0089]
Here, the selection of the first and second read modes, the selection of the first and second program modes, and the selection of the first to fourth program verify modes can be determined by a mode signal input from the outside. Then, the user can freely select the use mode. Here, the user needs to input the mode he / she wants to use from the outside.
[0090]
On the other hand, if the specifications of the flash memory are determined in advance, it is controlled so that various detailed modes are selected inside the chip only by designating one of the read, program, and program verify modes from the outside. You can also. For example, when the entire area of the flash memory array is used in the first high-speed read area, the first and second program modes and the first and second program verify modes are selected. 1 high-speed read mode is selected. Further, when the entire area of the flash memory array is used in the second low power consumption read area, the first and second program modes and the third and fourth program verify modes are selected. The second low power consumption read mode is selected. Furthermore, when the area used in the high-speed read mode and the area used in the low power consumption read mode are mixed in the flash memory array, various modes are selected in the chip based on the input address. If these controls can be determined in the semiconductor manufacturing process or the inspection process, flash memories having various performances can be shipped with one flash memory chip.
[0091]
(Second Embodiment)
FIG. 2 is a configuration diagram of a nonvolatile semiconductor memory device according to the second embodiment of the present invention. Since the second embodiment is different from the first embodiment shown in FIG. 1 only in the configuration of the memory cell array 60, only the configuration of the memory cell array 60 will be described here. Other configurations are the same as those in FIG. 1, and the read operation, the program operation, and the program verify operation are also the same.
[0092]
In this embodiment, the memory cell units for storing data are composed of a plurality of memory cells connected to the same bit line and connected to different word lines, and each of the plurality of memory cells constituting the memory cell unit is It is characterized by being arranged in different erase blocks.
[0093]
More specifically, the memory cell unit MU111 includes memory cells M111a and M111b which are memory cells connected to the same bit line BL1 and memory cells connected to different word lines WL11a and WL11b. The memory cell M111a belongs to the first block 60a, and the memory cell M111b belongs to the lth block 60c. Since the same applies to other memory cell units, the description thereof is omitted. As described above, by configuring the plurality of memory cells constituting the memory cell unit with memory cells belonging to different blocks, not only the program operation but also the erase operation can be performed individually.
[0094]
The erase operation is performed by applying a positive high voltage to the selected source line and a negative high voltage to the selected word line. In the erase verify operation, a positive voltage is applied to the selection gate, and it is determined by a verify circuit that the value of the current flowing through the memory cell is not less than a predetermined value, although not shown in FIG. Hereinafter, the erase operation and the operation during the erase verify operation will be described in detail. Here, the erase operation and the erase verify operation for the memory cell unit MU111 including the memory cells M111a and M111b will be described. In the erase operation and the erase verify operation in the present embodiment, the first and second erase operations and the first and second erase verify operations can be performed depending on the difference in the number of memory cells to be operated.
[0095]
FIG. 9A shows a voltage application state in the selected word lines WL11a and WL11b during the first erase operation and the first erase verify operation. The first erase operation is started by setting the first erase mode Erase1 and setting the NTRG signal to the logic “L” level at time T20. The first erase mode is a mode in which an erase operation is simultaneously performed on a plurality of blocks to which a plurality of memory cells constituting a memory cell unit belong. Therefore, at time T20, the source lines SL1 and SLl have a positive high voltage, and all the word lines connected to the first block 60a and the lth block 60c including the selected word lines WL11a and WL11b have a negative high voltage Vnn. Set to By performing the erase operation for a predetermined time and setting the NTRG signal to the logic “H” level at time T21, the erase operation is stopped, and the source lines SL1 and SLl and the selected word lines WL11a and WL11b are returned to the ground potential again.
[0096]
Next, at time T22, the first erase verify mode Erase Verify1 is set, and at time T23, the NTRG signal is set to the logic “L” level to start the first erase verify operation. The first erase verify mode is a mode in which an erase verify operation is simultaneously performed on a plurality of memory cells constituting the memory cell unit. Therefore, the two selected word lines WL11a and WL11b rise from the ground potential to the positive voltage Vev necessary for the erase verify operation at time T23. An erase verify operation is performed for a predetermined time, and the NTRG signal is set to a logic “H” level at time T24, whereby the erase verify operation is completed and the selected word line is returned to the ground potential.
[0097]
FIG. 9B shows a voltage application state in the selected word lines WL11a and WL11b during the second erase operation and the second erase verify operation. The second erase operation is started by setting the second erase mode Erase2 and setting the NTRG signal to the logic "L" level at time T20. The second erase mode is a mode in which an erase operation is individually performed on a plurality of blocks to which a plurality of memory cells constituting a memory cell unit belong. FIG. 9B shows a state when the memory cell unit MU111 performs an erase operation only on the memory cell M111a. At time T20, the source line SL1 is set to a positive high voltage, and the selected word line WL11a is selected. All word lines connected to the first block 60a including are set to the negative high voltage Vnn, and the erase operation of the first block 60a including the memory cell M111a is performed. At this time, all word lines connected to the source line SLl and the l-th block remain at the ground potential, and the erase operation of the l-th block 60c including the memory cell M111b is not performed. By performing the erase operation for a predetermined time and setting the NTRG signal to logic “H” level at time T21, the erase operation is stopped and the selected word line WL11a is returned to the ground potential again.
[0098]
Next, at time T22, the second erase verify mode Erase Verify2 is set, and at time T23, the NTRG signal is set to the logic “L” level to start the second erase verify operation. The second erase verify mode is a mode in which the erase verify operation is performed only on one memory cell among the plurality of memory cells constituting the memory cell unit. FIG. 9B shows a state when the memory cell unit MU111 performs an erase verify operation only on the memory cell M111a. Only the selected word line WL11a performs an erase verify operation from the ground potential at time T23. Rise to the positive voltage Vev required for the above operation, and an erase verify operation is performed on the memory cell M111a. At this time, the word line WL11b remains at the ground potential, and the erase verify operation for the memory cell M111b is not performed. An erase verify operation is performed for a predetermined time, and the NTRG signal is set to a logic “H” level at time T24, whereby the erase verify operation is completed and the selected word line WL11a is returned to the ground potential again.
[0099]
As described above, in the first erase mode and the first erase verify mode, the erase and erase verify operations can be simultaneously performed on a plurality of memory cells constituting the memory cell unit, so that high speed erase and erase can be performed. Verify operation can be realized. On the other hand, in the second erase mode and the second erase verify mode, erase and erase verify operations can be performed on individual memory cells, so that the threshold voltage in each memory cell is set accurately. It becomes possible.
[0100]
By providing these modes, for example, in the initial stage of the erase operation, the erase operation is performed at high speed in the first erase mode and the first erase verify mode, and the threshold voltage of the memory cell is set to the target threshold value. When the voltage approaches, the erase operation is performed on each memory cell using the second erase mode and the second erase verify mode, and each memory cell is set to an accurate threshold voltage. An erasing operation such as performing is enabled.
[0101]
(Third embodiment)
FIG. 3 is a configuration diagram of a nonvolatile semiconductor memory device according to the third embodiment of the present invention. Since the third embodiment differs from the first and second embodiments only in the configuration of the memory cell array 70, only the configuration of the memory cell array 70 will be described. Other configurations are the same as those in FIGS. The main feature of the present embodiment is that the memory cell array 70 has a block in which the memory cell unit is composed of a plurality of memory cells and a block composed of one memory cell.
[0102]
In FIG. 3, a block composed of a plurality of memory cells is a first block 70a and an mth block 70d, and a memory cell unit is composed of memory cells belonging to the respective blocks. Also, the blocks composed of one memory cell are from the second block 70b to the (m−1) th block 70c. In the present embodiment, the above-described memory array configuration will be described, but actually, the number of memory cells constituting the memory cell unit in each block can take various combinations.
[0103]
Here, the read operation, program / program verify operation, and erase / erase verify operation for the block in which the memory cell unit is composed of a plurality of memory cells are the same as those described in the first and second embodiments. Therefore, explanation is omitted. Hereinafter, a case where the memory cell unit MU211 including the memory cell M211 is read as a block including one memory cell as a memory cell unit will be described.
[0104]
FIG. 5C is a timing chart during the read operation of the memory cell unit MU211. Since the read principle is the same as that described with reference to FIGS. 5A and 5B, only the portions with different operations will be described.
[0105]
In FIG. 5C, when the read operation starts at time T1, the voltage of the selected word line WL21 changes from the ground potential to the positive voltage Vcgh. Here, the selected word line is a single selection. In addition, since the number of selected memory cells is one, the read current is halved compared to the word line multiple selection method, and only one DWLa is selected as the dummy word line for generating the reference voltage. The sense amplifier activation time is the same as that of the conventional one, and is set so as to be activated at a later timing than that in which the memory cell unit is composed of a plurality of memory cells.
[0106]
As described above, when the memory cell unit is composed of one memory cell, it is difficult to perform high-speed and low power consumption reading compared to the case where the memory cell unit is composed of a plurality of memory cells. Since the cell unit is composed of one memory cell, a large-capacity memory cell array block region can be realized. Therefore, the memory cell unit is provided with a block composed of a plurality of memory cells, so that an area where priority is given to high speed and low power consumption reading is provided, and a block composed of a single memory cell is provided to increase the memory capacity. It is possible to place a priority area.
[0107]
In the read operation of these different areas, the row address buffer / decoder 8 determines whether the read target area is a multiple selection block or a single selection block based on the input row address, and the determination result JRESULT controls it. Input to the circuit 14, the control circuit 14 controls whether to select multiple or single word lines and dummy word lines, and controls the activation timing of the sense amplifier 2. These controls are performed not only for the read operation but also for the program operation and the erase operation.
[0108]
(Fourth embodiment)
FIG. 4 is a configuration diagram of a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. Hereinafter, only parts different from the first to third embodiments will be described.
[0109]
In FIG. 4, the memory cell array 80 has a total of m blocks from the first block 80a to the mth block 80d, and each block is a block in which the memory cell unit is composed of one memory cell. The memory cell unit can be a block composed of a plurality of memory cells. The configuration of the memory cell unit is determined by the data stored in the register 21. Further, the selected word line voltage during the read operation, the sense amplifier activation timing, the program cell threshold voltage during programming, and the like are also determined by the data stored in the register 21. Here, the first block and the mth block are paired to form a block in which the memory cell unit is composed of two memory cells, and this block can be read at high speed in the first read mode. It is assumed that the area is an area, and the description will proceed assuming that the conventional memory cell unit is composed of one memory cell from the second block to the (m−1) th block. When performing a read operation, a program operation, and an erase operation, it is necessary to store block configuration information of the memory cell array 80 in the register 21 in advance, and this block configuration information may be set in the register 21 from the outside. Alternatively, it may be set by performing an operation of transferring information stored in this area to a register 21 stored in a certain area of the flash memory.
[0110]
Here, a case where a memory cell unit MU111 composed of two memory cells and a memory cell unit MU211 composed of one memory cell are read will be described. The read operation is the same as that described in the previous embodiment.
[0111]
FIG. 5A shows a timing chart when reading the memory cell unit MU111, and FIG. 5C shows a timing chart when reading the memory cell unit MU211. When the address of the memory cell unit MU111 is input, the data stored in the register 21 storing the block configuration information of the memory cell array 80 and the row address are compared by the comparison circuit 22. At this time, the register 21 contains two memory cell units MU111. Since information indicating that the memory cell is composed of memory cells of the first block 80a and the m-th block 80d is stored, the comparison circuit 22 sends the word line / dummy to the control circuit 14. Multiple selection of the word line is performed, and further, the high-speed read mode is instructed. The control circuit 14 receives the determination result JRESULT from the comparison circuit 22 so as to perform multiple selection of the word line / dummy word line, and for the booster circuit 15, a positive high voltage applied to the selected word line. Various control signals are sent to generate the voltage Vcgh. Further, the control circuit 14 controls the SAE signal so that the sense amplifier 2 is activated in a faster time than in the past. Thereby, a high-speed read operation is realized.
[0112]
When the memory cell unit MU211 is read, the block configuration information of the register 21 and the row address are compared by the comparison circuit 22, and the comparison circuit 22 performs the single selection of the word line / dummy word line. To order. The control circuit 14 receives the determination result JRESULT from the comparison circuit 22 so as to perform a single selection of the word line / dummy word line, and for the booster circuit 15, a positive high voltage applied to the selected word line. Various control signals are sent to generate the voltage Vcgh. Further, the control circuit 14 controls the SAE signal so that the sense amplifier 2 is activated with a conventional activation time. As a result, the conventional read operation is executed. The details of the subsequent read operation are the same as those described in the previous embodiment, and a description thereof will be omitted.
[0113]
In addition, in the program operation, the program verify operation, the erase operation, and the erase verify operation, the block configuration information stored in the register 21 and the row address are compared by the comparison circuit 22, and based on this determination result JRESULT, the control circuit 14 Multiple selection or single selection of word lines is performed, and the output voltage of the booster circuit 15 is switched. The details of the subsequent program operation, program verify operation, erase operation, and erase verify operation are the same as those described above, and thus the description thereof is omitted.
[0114]
As described above, according to the data stored in the register 21, the number of memory cells constituting the memory cell unit in each block of the memory cell array, the selected word line voltage during the read operation, the sense amplifier activation timing, and the threshold value of the program cell Since the voltage and the like can be changed, flash memories having various performances can be shipped with a single flash memory chip if data to be stored in the register 21 is determined in the semiconductor manufacturing process or the inspection process.
[0115]
For example, a high-speed read chip in which the memory cell units in all blocks are composed of a plurality of memory cells, a low power consumption read chip in which the memory cell units in all blocks are composed of a plurality of memory cells, and a memory cell unit in all blocks Chips with high-speed read areas and low-power-consumption read areas composed of cells, and blocks with memory cell units composed of multiple memory cells and blocks composed of one memory cell Realization of chips with various performances such as chips with low-consumption read areas and conventional read areas where large memory capacity can be obtained, and chips with large memory capacity in which memory cell units of all blocks are composed of one memory cell be able to.
[0116]
Also, by performing these register settings on the user side, the user side can freely determine the read performance (high-speed access, low power consumption, memory capacity) in each block of the memory cell array.
[0117]
Note that the nonvolatile semiconductor memory device of the present invention is not limited to the above-described examples, and various modifications and the like are included in the present invention without departing from the gist of the present invention. Of course.
[0118]
【The invention's effect】
As described above, the nonvolatile semiconductor memory device of the present invention includes a plurality of memory cells in which memory cell units for storing data are memory cells connected to the same bit line and connected to different word lines. In the read operation of this block, a plurality of memory cells are selected by multiple selection of the corresponding word lines. At this time, since a large cell current can be obtained, high-speed reading can be realized. Furthermore, since a sufficient cell current can be obtained for this block even if the boosted voltage of the selected word line is lowered, a low power consumption read operation can be realized.
[0119]
In addition, the program operation of the memory cell unit in this block, the program verify operation, the erase operation, and the number of target memory cells for the erase verify operation can be changed to one or more, thereby enabling high-speed and high-precision programming. Operation and erase operation can be realized.
[0120]
Furthermore, the performance of the memory cell array can be freely changed by controlling the single selection / multiple selection of the word lines and the boosted voltage by the data stored in the data storage unit.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a nonvolatile semiconductor memory device according to a second embodiment of the invention.
FIG. 3 is a configuration diagram of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.
FIG. 4 is a configuration diagram of a nonvolatile semiconductor memory device according to a fourth embodiment of the invention.
FIG. 5 is a timing chart showing a voltage change of each part during a read operation in the embodiment of the present invention.
FIG. 6 is a view showing a threshold voltage distribution of a memory cell in an embodiment of the present invention.
FIG. 7 is a diagram showing a change in the bit line potential during a read operation in the embodiment of the present invention.
FIG. 8 is a timing chart showing a voltage change of a word line during a program and program verify operation in the embodiment of the present invention.
FIG. 9 is a timing chart showing a voltage change of a word line during erase and erase verify operation in the embodiment of the present invention.
FIG. 10 is a diagram showing a threshold voltage distribution of a memory cell in a conventional nonvolatile memory device.
FIG. 11 is a diagram showing a change in bit line potential during a read operation in a conventional nonvolatile semiconductor memory device.
[Explanation of symbols]
1 Latch circuit
2 sense amplifiers
3 First input terminal of the sense amplifier 2
4 Second input terminal of the sense amplifier 2
5 Precharge circuit
6 Column address buffer decoder
7 Column selector
8 Row address buffer decoder
9 Word line multiplexing / single selection driver
10 Source line driver
11 Dummy word line multiple / single selection driver
12 Dummy cell array
13 Reset transistor
14 Control circuit
15 Booster circuit
21 register (data storage)
22 Comparison circuit
50, 60, 70, 80 Memory cell array
50a-50c, 60a-60d, 70a-70d, 80a-80d Memory cell block
YG1 to YGk, YGD Column gate signal
Y1-Yk, YD Column gate
BL1 to BLk bit lines
DBL dummy bit line
WL11a, WL11b, WL12a, WL12b, WL21, WL22 Word line
DWLa, DWLb Dummy word line
SL1 to SLm source line
MU111 to MU12k, MU211 to MU22k Memory cell unit
M111a to M12kb, M211 to M22k, M111 to M12k, Mm11 to Mm2k Memory cells
DCa, DCb dummy cell
MODE mode signal
NTRG operation control signal
DL data latch control signal
SAE sense amplifier start control signal
NPRE precharge control signal
BLRST Bit line reset control signal
MULTIWIWL Word line single / multiple selection control signal
JRESULT judgment result signal

Claims (13)

The control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, and the memory cells are arranged in a matrix at intersections of the plurality of word lines and the plurality of bit lines. A memory cell array comprising a plurality of memory cells in which memory cell units for storing data are connected to the same bit line and connected to different word lines;
A word line selection unit that multiple-selects the plurality of word lines connected to the memory cell unit and sets the plurality of memory cells constituting the memory cell unit in a selected state during the data read operation;
The dummy cell control gate is connected to the dummy word line, the drain is connected to the dummy bit line, the source is connected to the dummy source line, and the dummy cell unit for generating the reference voltage is connected to the dummy bit line to the same dummy bit line And a dummy cell array composed of a plurality of the dummy cells connected to different dummy word lines,
And a dummy word line selection unit that multiplex-selects the plurality of dummy word lines connected to the dummy cell unit and activates the plurality of dummy cells during the data read operation. that nonvolatile semiconductor memory device. The control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, and the memory cells are arranged in a matrix at intersections of the plurality of word lines and the plurality of bit lines. A memory cell array comprising a plurality of memory cells in which memory cell units for storing data are connected to the same bit line and connected to different word lines;
A word line selection unit that multiple-selects the plurality of word lines connected to the memory cell unit and selects the plurality of memory cells constituting the memory cell unit during the data read operation; ,
The memory cell array is a flash memory having a plurality of erase blocks that can collectively perform an erase operation in units of the plurality of memory cells, and each of the plurality of memory cells constituting the memory cell unit is different from each other. Belongs to the block,
The word line selection unit performs multiple selection of the corresponding word line during the data read operation based on the control signal, and single selection and multiple selection of the word line during the program / program verify and erase verify operations. In the erase operation, single erase and multiple erase of the corresponding erase block are switched, and the program / program verify to the plurality of memory cells constituting the memory cell unit and the erase / erase verify are performed. single or select multiple selection of the word line number target memory cell operation, and nonvolatile semiconductor memory device you characterized in that switching on the basis of a single erase or more erasure of the erase blocks. The control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, and the memory cells are arranged in a matrix at intersections of the plurality of word lines and the plurality of bit lines. A memory cell array comprising a plurality of memory cells in which memory cell units for storing data are connected to the same bit line and connected to different word lines;
A word line selection unit that multiple-selects the plurality of word lines connected to the memory cell unit and sets the plurality of memory cells constituting the memory cell unit in a selected state during the data read operation;
And a sense unit for determining read data from said memory cell array,
A first read mode in which a first boosted voltage is applied to the word line to multiple-select the memory cells, and the activation timing of the sense unit is set to a first predetermined value;
A second boosted voltage lower than the first boosted voltage is applied to the word line to multiple-select the memory cells, and a second activation timing of the sense unit is later than the first predetermined value A second readout mode set to a predetermined value,
Either the first readout mode or the second readout mode can be used during a semiconductor manufacturing process or an inspection process, or any one of the readout modes can be freely selected when the apparatus is used. It shall be the nonvolatile semiconductor memory device. The memory cell has an erase state having a low threshold voltage and a program state having a threshold voltage higher than the erase state,
The nonvolatile semiconductor memory device is
A first program verify mode for determining, after programming, a first write threshold voltage required to determine read data with the first boosted voltage used in the first read mode;
A second write threshold voltage lower than the first write threshold voltage necessary for determining read data with the second boosted voltage used in the second read mode is determined after programming. A second program verify mode;
4. The nonvolatile semiconductor memory device according to claim 3 , wherein a write threshold voltage to the memory cell is changed according to a boosted voltage of the word line used during the data read operation. 5. The nonvolatile semiconductor memory device according to claim 4 , wherein the memory cell array includes blocks that can be read in the first read mode and blocks that can be read in the second read mode. The control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, and the memory cells are arranged in a matrix at intersections of the plurality of word lines and the plurality of bit lines. A memory cell unit for storing data is composed of a first block composed of a single memory cell and a plurality of memory cells connected to the same bit line and connected to different word lines A memory cell array having at least one second block;
When the memory cell unit belonging to the first block is selected based on the input address during the data read operation, the memory cell unit belonging to the second block is switched to single selection of the corresponding word line. When selected, a word line selection unit that switches to multiple selection of the corresponding word line;
A sense unit for determining read data from the memory cell array;
At the time of the data read operation, the word line selection unit is controlled so that the corresponding word line is single-selected or multiple-selected, and the single or plural memory cells constituting the memory cell unit are selected, and And a control unit configured to control the sense unit to make the activation timing of the sense unit during the read operation of the second block faster than that during the read operation of the first block. Semiconductor memory device. The control gate of the memory cell is connected to the word line, the drain is connected to the bit line, the source is connected to the source line, and the memory cells are arranged in a matrix at intersections of the plurality of word lines and the plurality of bit lines. A memory cell unit for storing data includes a first block including a single memory cell and a plurality of memory cells connected to the same bit line and connected to different word lines. A memory cell array provided with one or more blocks that can be in any one of the second blocks;
A data storage unit for storing information as to whether each block is the first block or the second block;
A determination unit for determining whether a memory cell of a selected memory cell unit to be read is the single memory cell or the plurality of memory cells based on the information of the data storage unit and an input address;
Based on the determination result of the determination unit, the word line of the selected memory cell unit is switched to the single selection of the corresponding word line for the first block, and the corresponding word line for the second block. A word line selector that switches to multiple selection of
A sense unit for determining read data from the memory cell array;
During the data read operation, the word line selection unit is controlled based on the determination result of the determination unit, and the single or multiple selection of the word line is performed to configure the single or the cell cell unit. A plurality of memory cells are selected, and the sense unit is controlled so that the activation timing of the sense unit during the read operation of the second block is faster than that during the read operation of the first block; A non-volatile semiconductor memory device comprising: a control unit that changes information stored in the data storage unit. The nonvolatile semiconductor memory device is
The dummy cell control gate is connected to the dummy word line, the drain is connected to the dummy bit line, the source is connected to the dummy source line, and the dummy cell unit for generating the reference voltage is connected to the dummy bit line to the same dummy bit line And a dummy cell array composed of a plurality of the dummy cells connected to different dummy word lines,
During the data read operation, when the first block is selected, the single dummy cell is selected by a single selection of the dummy word line, and when the second block is selected, the dummy word line is selected. 8. The nonvolatile memory according to claim 6 , further comprising: a dummy word line selection unit that selects the plurality of dummy cells by a plurality of selections and activates the single dummy cell or the plurality of dummy cells. Semiconductor memory device. The word line selection unit switches between single selection and multiple selection of the word line based on a control signal from the control unit during program / program verify and erase / erase verify operations for the second block. by performing the program program verify to the plurality of memory cells constituting the memory cell units, and according to claim 6 or 7, wherein the switching the target number of memory cells of the erase erase verify operation Nonvolatile semiconductor memory device. The memory cell array is a flash memory having a plurality of erase blocks that can collectively perform an erase operation in units of the plurality of memory cells, and the plurality of memory cells constituting the memory cell unit belonging to the second block Each belong to a different erase block,
The word line selection unit performs a single selection or multiple selection of the corresponding word line during the data read operation based on a control signal from the control unit, and performs program / program verify in the second block, and During the erase verify operation, switching between single selection and multiple selection of the word line is performed, and during the erase operation, switching between single erase and multiple erase of the corresponding erase block is performed, and the plurality of memories constituting the memory cell unit Switching the number of target memory cells for the program / program verify and erase / erase verify operations to a cell based on single selection or multiple selection of the word line and single erase or multiple erase of the erase block. The nonvolatile semiconductor memory device according to claim 6 or 7, characterized in that: The nonvolatile semiconductor memory device is
A first read mode in which a first boosted voltage is applied to the word line to multiple-select the memory cells, and the activation timing of the sense unit is set to a first predetermined value;
A second boosted voltage lower than the first boosted voltage is applied to the word line to multiple-select the memory cells, and the activation timing of the sense unit is a second predetermined delay later than the first predetermined value A second readout mode set to the value,
For the first block, a read operation is performed in the first read mode, and for the second block, the first read mode and the second read are performed during a semiconductor manufacturing process or an inspection process. 13. The nonvolatile semiconductor memory device according to claim 6 , wherein any one of the modes can be used, or any one of the reading modes can be freely selected when the device is used. The memory cell has an erase state having a low threshold voltage and a program state having a threshold voltage higher than the erase state,
The nonvolatile semiconductor memory device is
A first program verify mode for determining, after programming, a first write threshold voltage required to determine read data with the first boosted voltage used in the first read mode;
A second write threshold voltage lower than the first write threshold voltage necessary for determining read data with the second boosted voltage used in the second read mode is determined after programming. A second program verify mode;
12. The nonvolatile semiconductor memory device according to claim 11 , wherein a write threshold voltage to the memory cell is changed in accordance with a boosted voltage of the word line used during the data read operation. 13. The nonvolatile semiconductor memory device according to claim 12, wherein the second block includes a block that can be read in the first read mode and a block that can be read in the second read mode.

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